1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Cadence CDNSP DRD Driver.
4 *
5 * Copyright (C) 2020 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 *
9 * Code based on Linux XHCI driver.
10 * Origin: Copyright (C) 2008 Intel Corp.
11 */
12 #ifndef __LINUX_CDNSP_GADGET_H
13 #define __LINUX_CDNSP_GADGET_H
14
15 #include <linux/io-64-nonatomic-lo-hi.h>
16 #include <linux/usb/gadget.h>
17 #include <linux/irq.h>
18
19 /* Max number slots - only 1 is allowed. */
20 #define CDNSP_DEV_MAX_SLOTS 1
21
22 #define CDNSP_EP0_SETUP_SIZE 512
23
24 /* One control and 15 for in and 15 for out endpoints. */
25 #define CDNSP_ENDPOINTS_NUM 31
26
27 /* Best Effort Service Latency. */
28 #define CDNSP_DEFAULT_BESL 0
29
30 /* Device Controller command default timeout value in us */
31 #define CDNSP_CMD_TIMEOUT (15 * 1000)
32
33 /* Up to 16 ms to halt an device controller */
34 #define CDNSP_MAX_HALT_USEC (16 * 1000)
35
36 #define CDNSP_CTX_SIZE 2112
37
38 /*
39 * Controller register interface.
40 */
41
42 /**
43 * struct cdnsp_cap_regs - CDNSP Registers.
44 * @hc_capbase: Length of the capabilities register and controller
45 * version number
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
52 * @hcc_params2: HCCPARAMS2 Capability Parameters 2,
53 */
54 struct cdnsp_cap_regs {
55 __le32 hc_capbase;
56 __le32 hcs_params1;
57 __le32 hcs_params2;
58 __le32 hcs_params3;
59 __le32 hcc_params;
60 __le32 db_off;
61 __le32 run_regs_off;
62 __le32 hcc_params2;
63 /* Reserved up to (CAPLENGTH - 0x1C) */
64 };
65
66 /* hc_capbase bitmasks. */
67 /* bits 7:0 - how long is the Capabilities register. */
68 #define HC_LENGTH(p) (((p) >> 00) & GENMASK(7, 0))
69 /* bits 31:16 */
70 #define HC_VERSION(p) (((p) >> 16) & GENMASK(15, 1))
71
72 /* HCSPARAMS1 - hcs_params1 - bitmasks */
73 /* bits 0:7, Max Device Endpoints */
74 #define HCS_ENDPOINTS_MASK GENMASK(7, 0)
75 #define HCS_ENDPOINTS(p) (((p) & HCS_ENDPOINTS_MASK) >> 0)
76
77 /* HCCPARAMS offset from PCI base address */
78 #define HCC_PARAMS_OFFSET 0x10
79
80 /* HCCPARAMS - hcc_params - bitmasks */
81 /* 1: device controller can use 64-bit address pointers. */
82 #define HCC_64BIT_ADDR(p) ((p) & BIT(0))
83 /* 1: device controller uses 64-byte Device Context structures. */
84 #define HCC_64BYTE_CONTEXT(p) ((p) & BIT(2))
85 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
86 #define HCC_MAX_PSA(p) ((((p) >> 12) & 0xf) + 1)
87 /* Extended Capabilities pointer from PCI base. */
88 #define HCC_EXT_CAPS(p) (((p) & GENMASK(31, 16)) >> 16)
89
90 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
91
92 /* db_off bitmask - bits 0:1 reserved. */
93 #define DBOFF_MASK GENMASK(31, 2)
94
95 /* run_regs_off bitmask - bits 0:4 reserved. */
96 #define RTSOFF_MASK GENMASK(31, 5)
97
98 /**
99 * struct cdnsp_op_regs - Device Controller Operational Registers.
100 * @command: USBCMD - Controller command register.
101 * @status: USBSTS - Controller status register.
102 * @page_size: This indicates the page size that the device controller supports.
103 * If bit n is set, the controller supports a page size of 2^(n+12),
104 * up to a 128MB page size. 4K is the minimum page size.
105 * @dnctrl: DNCTRL - Device notification control register.
106 * @cmd_ring: CRP - 64-bit Command Ring Pointer.
107 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
108 * @config_reg: CONFIG - Configure Register
109 * @port_reg_base: PORTSCn - base address for Port Status and Control
110 * Each port has a Port Status and Control register,
111 * followed by a Port Power Management Status and Control
112 * register, a Port Link Info register, and a reserved
113 * register.
114 */
115 struct cdnsp_op_regs {
116 __le32 command;
117 __le32 status;
118 __le32 page_size;
119 __le32 reserved1;
120 __le32 reserved2;
121 __le32 dnctrl;
122 __le64 cmd_ring;
123 /* rsvd: offset 0x20-2F. */
124 __le32 reserved3[4];
125 __le64 dcbaa_ptr;
126 __le32 config_reg;
127 /* rsvd: offset 0x3C-3FF. */
128 __le32 reserved4[241];
129 /* port 1 registers, which serve as a base address for other ports. */
130 __le32 port_reg_base;
131 };
132
133 /* Number of registers per port. */
134 #define NUM_PORT_REGS 4
135
136 /**
137 * struct cdnsp_port_regs - Port Registers.
138 * @portsc: PORTSC - Port Status and Control Register.
139 * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
140 * @portli: PORTLI - Port Link Info register.
141 */
142 struct cdnsp_port_regs {
143 __le32 portsc;
144 __le32 portpmsc;
145 __le32 portli;
146 __le32 reserved;
147 };
148
149 /*
150 * These bits are Read Only (RO) and should be saved and written to the
151 * registers: 0 (connect status) and 10:13 (port speed).
152 * These bits are also sticky - meaning they're in the AUX well and they aren't
153 * changed by a hot and warm.
154 */
155 #define CDNSP_PORT_RO (PORT_CONNECT | DEV_SPEED_MASK)
156
157 /*
158 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
159 * bits 5:8 (link state), 25:26 ("wake on" enable state)
160 */
161 #define CDNSP_PORT_RWS (PORT_PLS_MASK | PORT_WKCONN_E | PORT_WKDISC_E)
162
163 /*
164 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
165 * bits 1 (port enable/disable), 17 ( connect changed),
166 * 21 (port reset changed) , 22 (Port Link State Change),
167 */
168 #define CDNSP_PORT_RW1CS (PORT_PED | PORT_CSC | PORT_RC | PORT_PLC)
169
170 /* USBCMD - USB command - bitmasks. */
171 /* Run/Stop, controller execution - do not write unless controller is halted.*/
172 #define CMD_R_S BIT(0)
173 /*
174 * Reset device controller - resets internal controller state machine and all
175 * registers (except PCI config regs).
176 */
177 #define CMD_RESET BIT(1)
178 /* Event Interrupt Enable - a '1' allows interrupts from the controller. */
179 #define CMD_INTE BIT(2)
180 /*
181 * Device System Error Interrupt Enable - get out-of-band signal for
182 * controller errors.
183 */
184 #define CMD_DSEIE BIT(3)
185 /* device controller save/restore state. */
186 #define CMD_CSS BIT(8)
187 #define CMD_CRS BIT(9)
188 /*
189 * Enable Wrap Event - '1' means device controller generates an event
190 * when MFINDEX wraps.
191 */
192 #define CMD_EWE BIT(10)
193 /* 1: device enabled */
194 #define CMD_DEVEN BIT(17)
195 /* bits 18:31 are reserved (and should be preserved on writes). */
196
197 /* Command register values to disable interrupts. */
198 #define CDNSP_IRQS (CMD_INTE | CMD_DSEIE | CMD_EWE)
199
200 /* USBSTS - USB status - bitmasks */
201 /* controller not running - set to 1 when run/stop bit is cleared. */
202 #define STS_HALT BIT(0)
203 /*
204 * serious error, e.g. PCI parity error. The controller will clear
205 * the run/stop bit.
206 */
207 #define STS_FATAL BIT(2)
208 /* event interrupt - clear this prior to clearing any IP flags in IR set.*/
209 #define STS_EINT BIT(3)
210 /* port change detect */
211 #define STS_PCD BIT(4)
212 /* save state status - '1' means device controller is saving state. */
213 #define STS_SSS BIT(8)
214 /* restore state status - '1' means controllers is restoring state. */
215 #define STS_RSS BIT(9)
216 /* 1: save or restore error */
217 #define STS_SRE BIT(10)
218 /* 1: device Not Ready to accept doorbell or op reg writes after reset. */
219 #define STS_CNR BIT(11)
220 /* 1: internal Device Controller Error.*/
221 #define STS_HCE BIT(12)
222
223 /* CRCR - Command Ring Control Register - cmd_ring bitmasks. */
224 /* bit 0 is the command ring cycle state. */
225 #define CMD_RING_CS BIT(0)
226 /* stop ring immediately - abort the currently executing command. */
227 #define CMD_RING_ABORT BIT(2)
228 /*
229 * Command Ring Busy.
230 * Set when Doorbell register is written with DB for command and cleared when
231 * the controller reached end of CR.
232 */
233 #define CMD_RING_BUSY(p) ((p) & BIT(4))
234 /* 1: command ring is running */
235 #define CMD_RING_RUNNING BIT(3)
236 /* Command Ring pointer - bit mask for the lower 32 bits. */
237 #define CMD_RING_RSVD_BITS GENMASK(5, 0)
238
239 /* CONFIG - Configure Register - config_reg bitmasks. */
240 /* bits 0:7 - maximum number of device slots enabled. */
241 #define MAX_DEVS GENMASK(7, 0)
242 /* bit 8: U3 Entry Enabled, assert PLC when controller enters U3. */
243 #define CONFIG_U3E BIT(8)
244
245 /* PORTSC - Port Status and Control Register - port_reg_base bitmasks */
246 /* 1: device connected. */
247 #define PORT_CONNECT BIT(0)
248 /* 1: port enabled. */
249 #define PORT_PED BIT(1)
250 /* 1: port reset signaling asserted. */
251 #define PORT_RESET BIT(4)
252 /*
253 * Port Link State - bits 5:8
254 * A read gives the current link PM state of the port,
255 * a write with Link State Write Strobe sets the link state.
256 */
257 #define PORT_PLS_MASK GENMASK(8, 5)
258 #define XDEV_U0 (0x0 << 5)
259 #define XDEV_U1 (0x1 << 5)
260 #define XDEV_U2 (0x2 << 5)
261 #define XDEV_U3 (0x3 << 5)
262 #define XDEV_DISABLED (0x4 << 5)
263 #define XDEV_RXDETECT (0x5 << 5)
264 #define XDEV_INACTIVE (0x6 << 5)
265 #define XDEV_POLLING (0x7 << 5)
266 #define XDEV_RECOVERY (0x8 << 5)
267 #define XDEV_HOT_RESET (0x9 << 5)
268 #define XDEV_COMP_MODE (0xa << 5)
269 #define XDEV_TEST_MODE (0xb << 5)
270 #define XDEV_RESUME (0xf << 5)
271 /* 1: port has power. */
272 #define PORT_POWER BIT(9)
273 /*
274 * bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - Reserved (Low Speed not supported
278 * 3 - high speed
279 * 4 - super speed
280 * 5 - super speed
281 * 6-15 reserved
282 */
283 #define DEV_SPEED_MASK GENMASK(13, 10)
284 #define XDEV_FS (0x1 << 10)
285 #define XDEV_HS (0x3 << 10)
286 #define XDEV_SS (0x4 << 10)
287 #define XDEV_SSP (0x5 << 10)
288 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0 << 10))
289 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
290 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
293 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
294 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
295 /* Port Link State Write Strobe - set this when changing link state */
296 #define PORT_LINK_STROBE BIT(16)
297 /* 1: connect status change */
298 #define PORT_CSC BIT(17)
299 /* 1: warm reset for a USB 3.0 device is done. */
300 #define PORT_WRC BIT(19)
301 /* 1: reset change - 1 to 0 transition of PORT_RESET */
302 #define PORT_RC BIT(21)
303 /*
304 * port link status change - set on some port link state transitions:
305 * Transition Reason
306 * ----------------------------------------------------------------------------
307 * - U3 to Resume Wakeup signaling from a device
308 * - Resume to Recovery to U0 USB 3.0 device resume
309 * - Resume to U0 USB 2.0 device resume
310 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
311 * - U3 to U0 Software resume of USB 2.0 device complete
312 * - U2 to U0 L1 resume of USB 2.1 device complete
313 * - U0 to U0 L1 entry rejection by USB 2.1 device
314 * - U0 to disabled L1 entry error with USB 2.1 device
315 * - Any state to inactive Error on USB 3.0 port
316 */
317 #define PORT_PLC BIT(22)
318 /* Port configure error change - port failed to configure its link partner. */
319 #define PORT_CEC BIT(23)
320 /* Wake on connect (enable). */
321 #define PORT_WKCONN_E BIT(25)
322 /* Wake on disconnect (enable). */
323 #define PORT_WKDISC_E BIT(26)
324 /* Indicates if Warm Reset is being received. */
325 #define PORT_WR BIT(31)
326
327 #define PORT_CHANGE_BITS (PORT_CSC | PORT_WRC | PORT_RC | PORT_PLC | PORT_CEC)
328
329 /* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */
330 /* Enables U1 entry. */
331 #define PORT_U1_TIMEOUT_MASK GENMASK(7, 0)
332 #define PORT_U1_TIMEOUT(p) ((p) & PORT_U1_TIMEOUT_MASK)
333 /* Enables U2 entry .*/
334 #define PORT_U2_TIMEOUT_MASK GENMASK(14, 8)
335 #define PORT_U2_TIMEOUT(p) (((p) << 8) & PORT_U2_TIMEOUT_MASK)
336
337 /* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */
338 #define PORT_L1S_MASK GENMASK(2, 0)
339 #define PORT_L1S(p) ((p) & PORT_L1S_MASK)
340 #define PORT_L1S_ACK PORT_L1S(1)
341 #define PORT_L1S_NYET PORT_L1S(2)
342 #define PORT_L1S_STALL PORT_L1S(3)
343 #define PORT_L1S_TIMEOUT PORT_L1S(4)
344 /* Remote Wake Enable. */
345 #define PORT_RWE BIT(3)
346 /* Best Effort Service Latency (BESL). */
347 #define PORT_BESL(p) (((p) << 4) & GENMASK(7, 4))
348 /* Hardware LPM Enable (HLE). */
349 #define PORT_HLE BIT(16)
350 /* Received Best Effort Service Latency (BESL). */
351 #define PORT_RRBESL(p) (((p) & GENMASK(20, 17)) >> 17)
352 /* Port Test Control. */
353 #define PORT_TEST_MODE_MASK GENMASK(31, 28)
354 #define PORT_TEST_MODE(p) (((p) << 28) & PORT_TEST_MODE_MASK)
355
356 /**
357 * struct cdnsp_intr_reg - Interrupt Register Set.
358 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
359 * interrupts and check for pending interrupts.
360 * @irq_control: IMOD - Interrupt Moderation Register.
361 * Used to throttle interrupts.
362 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
363 * @erst_base: ERST base address.
364 * @erst_dequeue: Event ring dequeue pointer.
365 *
366 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
367 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
368 * multiple segments of the same size. The controller places events on the ring
369 * and "updates the Cycle bit in the TRBs to indicate to software the current
370 * position of the Enqueue Pointer." The driver processes those events and
371 * updates the dequeue pointer.
372 */
373 struct cdnsp_intr_reg {
374 __le32 irq_pending;
375 __le32 irq_control;
376 __le32 erst_size;
377 __le32 rsvd;
378 __le64 erst_base;
379 __le64 erst_dequeue;
380 };
381
382 /* IMAN - Interrupt Management Register - irq_pending bitmasks l. */
383 #define IMAN_IE BIT(1)
384 #define IMAN_IP BIT(0)
385 /* bits 2:31 need to be preserved */
386 #define IMAN_IE_SET(p) ((p) | IMAN_IE)
387 #define IMAN_IE_CLEAR(p) ((p) & ~IMAN_IE)
388
389 /* IMOD - Interrupter Moderation Register - irq_control bitmasks. */
390 /*
391 * Minimum interval between interrupts (in 250ns intervals). The interval
392 * between interrupts will be longer if there are no events on the event ring.
393 * Default is 4000 (1 ms).
394 */
395 #define IMOD_INTERVAL_MASK GENMASK(15, 0)
396 /* Counter used to count down the time to the next interrupt - HW use only */
397 #define IMOD_COUNTER_MASK GENMASK(31, 16)
398 #define IMOD_DEFAULT_INTERVAL 0
399
400 /* erst_size bitmasks. */
401 /* Preserve bits 16:31 of erst_size. */
402 #define ERST_SIZE_MASK GENMASK(31, 16)
403
404 /* erst_dequeue bitmasks. */
405 /*
406 * Dequeue ERST Segment Index (DESI) - Segment number (or alias)
407 * where the current dequeue pointer lies. This is an optional HW hint.
408 */
409 #define ERST_DESI_MASK GENMASK(2, 0)
410 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */
411 #define ERST_EHB BIT(3)
412 #define ERST_PTR_MASK GENMASK(3, 0)
413
414 /**
415 * struct cdnsp_run_regs
416 * @microframe_index: MFINDEX - current microframe number.
417 * @ir_set: Array of Interrupter registers.
418 *
419 * Device Controller Runtime Registers:
420 * "Software should read and write these registers using only Dword (32 bit)
421 * or larger accesses"
422 */
423 struct cdnsp_run_regs {
424 __le32 microframe_index;
425 __le32 rsvd[7];
426 struct cdnsp_intr_reg ir_set[128];
427 };
428
429 /**
430 * USB2.0 Port Peripheral Configuration Registers.
431 * @ext_cap: Header register for Extended Capability.
432 * @port_reg1: Timer Configuration Register.
433 * @port_reg2: Timer Configuration Register.
434 * @port_reg3: Timer Configuration Register.
435 * @port_reg4: Timer Configuration Register.
436 * @port_reg5: Timer Configuration Register.
437 * @port_reg6: Chicken bits for USB20PPP.
438 */
439 struct cdnsp_20port_cap {
440 __le32 ext_cap;
441 __le32 port_reg1;
442 __le32 port_reg2;
443 __le32 port_reg3;
444 __le32 port_reg4;
445 __le32 port_reg5;
446 __le32 port_reg6;
447 };
448
449 /* Extended capability register fields */
450 #define EXT_CAPS_ID(p) (((p) >> 0) & GENMASK(7, 0))
451 #define EXT_CAPS_NEXT(p) (((p) >> 8) & GENMASK(7, 0))
452 /* Extended capability IDs - ID 0 reserved */
453 #define EXT_CAPS_PROTOCOL 2
454
455 /* USB 2.0 Port Peripheral Configuration Extended Capability */
456 #define EXT_CAP_CFG_DEV_20PORT_CAP_ID 0xC1
457 /*
458 * Setting this bit to '1' enables automatic wakeup from L1 state on transfer
459 * TRB prepared when USBSSP operates in USB2.0 mode.
460 */
461 #define PORT_REG6_L1_L0_HW_EN BIT(1)
462 /*
463 * Setting this bit to '1' forces Full Speed when USBSSP operates in USB2.0
464 * mode (disables High Speed).
465 */
466 #define PORT_REG6_FORCE_FS BIT(0)
467
468 /**
469 * USB3.x Port Peripheral Configuration Registers.
470 * @ext_cap: Header register for Extended Capability.
471 * @mode_addr: Miscellaneous 3xPORT operation mode configuration register.
472 * @mode_2: 3x Port Control Register 2.
473 */
474 struct cdnsp_3xport_cap {
475 __le32 ext_cap;
476 __le32 mode_addr;
477 __le32 reserved[52];
478 __le32 mode_2;
479 };
480
481 /* Extended Capability Header for 3XPort Configuration Registers. */
482 #define D_XEC_CFG_3XPORT_CAP 0xC0
483 #define CFG_3XPORT_SSP_SUPPORT BIT(31)
484 #define CFG_3XPORT_U1_PIPE_CLK_GATE_EN BIT(0)
485
486 /* Revision Extended Capability ID */
487 #define RTL_REV_CAP 0xC4
488 #define RTL_REV_CAP_RX_BUFF_CMD_SIZE BITMASK(31, 24)
489 #define RTL_REV_CAP_RX_BUFF_SIZE BITMASK(15, 0)
490 #define RTL_REV_CAP_TX_BUFF_CMD_SIZE BITMASK(31, 24)
491 #define RTL_REV_CAP_TX_BUFF_SIZE BITMASK(15, 0)
492
493 #define CDNSP_VER_1 0x00000000
494 #define CDNSP_VER_2 0x10000000
495
496 #define CDNSP_IF_EP_EXIST(pdev, ep_num, dir) \
497 (readl(&(pdev)->rev_cap->ep_supported) & \
498 (BIT(ep_num) << ((dir) ? 0 : 16)))
499
500 /**
501 * struct cdnsp_rev_cap - controller capabilities.
502 * @ext_cap: Header for RTL Revision Extended Capability.
503 * @rtl_revision: RTL revision.
504 * @rx_buff_size: Rx buffer sizes.
505 * @tx_buff_size: Tx buffer sizes.
506 * @ep_supported: Supported endpoints.
507 * @ctrl_revision: Controller revision ID.
508 */
509 struct cdnsp_rev_cap {
510 __le32 ext_cap;
511 __le32 rtl_revision;
512 __le32 rx_buff_size;
513 __le32 tx_buff_size;
514 __le32 ep_supported;
515 __le32 ctrl_revision;
516 };
517
518 /* USB2.0 Port Peripheral Configuration Registers. */
519 #define D_XEC_PRE_REGS_CAP 0xC8
520 #define REG_CHICKEN_BITS_2_OFFSET 0x48
521 #define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28)
522
523 /* XBUF Extended Capability ID. */
524 #define XBUF_CAP_ID 0xCB
525 #define XBUF_RX_TAG_MASK_0_OFFSET 0x1C
526 #define XBUF_RX_TAG_MASK_1_OFFSET 0x24
527 #define XBUF_TX_CMD_OFFSET 0x2C
528
529 /**
530 * struct cdnsp_doorbell_array.
531 * @cmd_db: Command ring doorbell register.
532 * @ep_db: Endpoint ring doorbell register.
533 * Bits 0 - 7: Endpoint target.
534 * Bits 8 - 15: RsvdZ.
535 * Bits 16 - 31: Stream ID.
536 */
537 struct cdnsp_doorbell_array {
538 __le32 cmd_db;
539 __le32 ep_db;
540 };
541
542 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
543 #define DB_VALUE_EP0_OUT(ep, stream) ((ep) & 0xff)
544 #define DB_VALUE_CMD 0x00000000
545
546 /**
547 * struct cdnsp_container_ctx.
548 * @type: Type of context. Used to calculated offsets to contained contexts.
549 * @size: Size of the context data.
550 * @ctx_size: context data structure size - 64 or 32 bits.
551 * @dma: dma address of the bytes.
552 * @bytes: The raw context data given to HW.
553 *
554 * Represents either a Device or Input context. Holds a pointer to the raw
555 * memory used for the context (bytes) and dma address of it (dma).
556 */
557 struct cdnsp_container_ctx {
558 unsigned int type;
559 #define CDNSP_CTX_TYPE_DEVICE 0x1
560 #define CDNSP_CTX_TYPE_INPUT 0x2
561 int size;
562 int ctx_size;
563 dma_addr_t dma;
564 u8 *bytes;
565 };
566
567 /**
568 * struct cdnsp_slot_ctx
569 * @dev_info: Device speed, and last valid endpoint.
570 * @dev_port: Device port number that is needed to access the USB device.
571 * @int_target: Interrupter target number.
572 * @dev_state: Slot state and device address.
573 *
574 * Slot Context - This assumes the controller uses 32-byte context
575 * structures. If the controller uses 64-byte contexts, there is an additional
576 * 32 bytes reserved at the end of the slot context for controller internal use.
577 */
578 struct cdnsp_slot_ctx {
579 __le32 dev_info;
580 __le32 dev_port;
581 __le32 int_target;
582 __le32 dev_state;
583 /* offset 0x10 to 0x1f reserved for controller internal use. */
584 __le32 reserved[4];
585 };
586
587 /* Bits 20:23 in the Slot Context are the speed for the device. */
588 #define SLOT_SPEED_FS (XDEV_FS << 10)
589 #define SLOT_SPEED_HS (XDEV_HS << 10)
590 #define SLOT_SPEED_SS (XDEV_SS << 10)
591 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
592
593 /* dev_info bitmasks. */
594 /* Device speed - values defined by PORTSC Device Speed field - 20:23. */
595 #define DEV_SPEED GENMASK(23, 20)
596 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
597 /* Index of the last valid endpoint context in this device context - 27:31. */
598 #define LAST_CTX_MASK ((unsigned int)GENMASK(31, 27))
599 #define LAST_CTX(p) ((p) << 27)
600 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
601 #define SLOT_FLAG BIT(0)
602 #define EP0_FLAG BIT(1)
603
604 /* dev_port bitmasks */
605 /* Device port number that is needed to access the USB device. */
606 #define DEV_PORT(p) (((p) & 0xff) << 16)
607
608 /* dev_state bitmasks */
609 /* USB device address - assigned by the controller. */
610 #define DEV_ADDR_MASK GENMASK(7, 0)
611 /* Slot state */
612 #define SLOT_STATE GENMASK(31, 27)
613 #define GET_SLOT_STATE(p) (((p) & SLOT_STATE) >> 27)
614
615 #define SLOT_STATE_DISABLED 0
616 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
617 #define SLOT_STATE_DEFAULT 1
618 #define SLOT_STATE_ADDRESSED 2
619 #define SLOT_STATE_CONFIGURED 3
620
621 /**
622 * struct cdnsp_ep_ctx.
623 * @ep_info: Endpoint state, streams, mult, and interval information.
624 * @ep_info2: Information on endpoint type, max packet size, max burst size,
625 * error count, and whether the controller will force an event for
626 * all transactions.
627 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
628 * defines one stream, this points to the endpoint transfer ring.
629 * Otherwise, it points to a stream context array, which has a
630 * ring pointer for each flow.
631 * @tx_info: Average TRB lengths for the endpoint ring and
632 * max payload within an Endpoint Service Interval Time (ESIT).
633 *
634 * Endpoint Context - This assumes the controller uses 32-byte context
635 * structures. If the controller uses 64-byte contexts, there is an additional
636 * 32 bytes reserved at the end of the endpoint context for controller internal
637 * use.
638 */
639 struct cdnsp_ep_ctx {
640 __le32 ep_info;
641 __le32 ep_info2;
642 __le64 deq;
643 __le32 tx_info;
644 /* offset 0x14 - 0x1f reserved for controller internal use. */
645 __le32 reserved[3];
646 };
647
648 /* ep_info bitmasks. */
649 /*
650 * Endpoint State - bits 0:2:
651 * 0 - disabled
652 * 1 - running
653 * 2 - halted due to halt condition
654 * 3 - stopped
655 * 4 - TRB error
656 * 5-7 - reserved
657 */
658 #define EP_STATE_MASK GENMASK(3, 0)
659 #define EP_STATE_DISABLED 0
660 #define EP_STATE_RUNNING 1
661 #define EP_STATE_HALTED 2
662 #define EP_STATE_STOPPED 3
663 #define EP_STATE_ERROR 4
664 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
665
666 /* Mult - Max number of burst within an interval, in EP companion desc. */
667 #define EP_MULT(p) (((p) << 8) & GENMASK(9, 8))
668 #define CTX_TO_EP_MULT(p) (((p) & GENMASK(9, 8)) >> 8)
669 /* bits 10:14 are Max Primary Streams. */
670 /* bit 15 is Linear Stream Array. */
671 /* Interval - period between requests to an endpoint - 125u increments. */
672 #define EP_INTERVAL(p) (((p) << 16) & GENMASK(23, 16))
673 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) & GENMASK(23, 16)) >> 16))
674 #define CTX_TO_EP_INTERVAL(p) (((p) & GENMASK(23, 16)) >> 16)
675 #define EP_MAXPSTREAMS_MASK GENMASK(14, 10)
676 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
677 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
678 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
679 #define EP_HAS_LSA BIT(15)
680
681 /* ep_info2 bitmasks */
682 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
683 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
684 #define EP_TYPE(p) ((p) << 3)
685 #define ISOC_OUT_EP 1
686 #define BULK_OUT_EP 2
687 #define INT_OUT_EP 3
688 #define CTRL_EP 4
689 #define ISOC_IN_EP 5
690 #define BULK_IN_EP 6
691 #define INT_IN_EP 7
692 /* bit 6 reserved. */
693 /* bit 7 is Device Initiate Disable - for disabling stream selection. */
694 #define MAX_BURST(p) (((p) << 8) & GENMASK(15, 8))
695 #define CTX_TO_MAX_BURST(p) (((p) & GENMASK(15, 8)) >> 8)
696 #define MAX_PACKET(p) (((p) << 16) & GENMASK(31, 16))
697 #define MAX_PACKET_MASK GENMASK(31, 16)
698 #define MAX_PACKET_DECODED(p) (((p) & GENMASK(31, 16)) >> 16)
699
700 /* tx_info bitmasks. */
701 #define EP_AVG_TRB_LENGTH(p) ((p) & GENMASK(15, 0))
702 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) << 16) & GENMASK(31, 16))
703 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) & GENMASK(23, 16)) >> 16) << 24)
704 #define CTX_TO_MAX_ESIT_PAYLOAD_LO(p) (((p) & GENMASK(31, 16)) >> 16)
705 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) & GENMASK(31, 24)) >> 24)
706
707 /* deq bitmasks. */
708 #define EP_CTX_CYCLE_MASK BIT(0)
709 #define CTX_DEQ_MASK (~0xfL)
710
711 /**
712 * struct cdnsp_input_control_context
713 * Input control context;
714 *
715 * @drop_context: Set the bit of the endpoint context you want to disable.
716 * @add_context: Set the bit of the endpoint context you want to enable.
717 */
718 struct cdnsp_input_control_ctx {
719 __le32 drop_flags;
720 __le32 add_flags;
721 __le32 rsvd2[6];
722 };
723
724 /**
725 * Represents everything that is needed to issue a command on the command ring.
726 *
727 * @in_ctx: Pointer to input context structure.
728 * @status: Command Completion Code for last command.
729 * @command_trb: Pointer to command TRB.
730 */
731 struct cdnsp_command {
732 /* Input context for changing device state. */
733 struct cdnsp_container_ctx *in_ctx;
734 u32 status;
735 union cdnsp_trb *command_trb;
736 };
737
738 /**
739 * Stream context structure.
740 *
741 * @stream_ring: 64-bit stream ring address, cycle state, and stream type.
742 * @reserved: offset 0x14 - 0x1f reserved for controller internal use.
743 */
744 struct cdnsp_stream_ctx {
745 __le64 stream_ring;
746 __le32 reserved[2];
747 };
748
749 /* Stream Context Types - bits 3:1 of stream ctx deq ptr. */
750 #define SCT_FOR_CTX(p) (((p) << 1) & GENMASK(3, 1))
751 /* Secondary stream array type, dequeue pointer is to a transfer ring. */
752 #define SCT_SEC_TR 0
753 /* Primary stream array type, dequeue pointer is to a transfer ring. */
754 #define SCT_PRI_TR 1
755
756 /**
757 * struct cdnsp_stream_info: Representing everything that is needed to
758 * supports stream capable endpoints.
759 * @stream_rings: Array of pointers containing Transfer rings for all
760 * supported streams.
761 * @num_streams: Number of streams, including stream 0.
762 * @stream_ctx_array: The stream context array may be bigger than the number
763 * of streams the driver asked for.
764 * @num_stream_ctxs: Number of streams.
765 * @ctx_array_dma: Dma address of Context Stream Array.
766 * @trb_address_map: For mapping physical TRB addresses to segments in
767 * stream rings.
768 * @td_count: Number of TDs associated with endpoint.
769 * @first_prime_det: First PRIME packet detected.
770 * @drbls_count: Number of allowed doorbells.
771 */
772 struct cdnsp_stream_info {
773 struct cdnsp_ring **stream_rings;
774 unsigned int num_streams;
775 struct cdnsp_stream_ctx *stream_ctx_array;
776 unsigned int num_stream_ctxs;
777 dma_addr_t ctx_array_dma;
778 struct radix_tree_root trb_address_map;
779 int td_count;
780 u8 first_prime_det;
781 #define STREAM_DRBL_FIFO_DEPTH 2
782 u8 drbls_count;
783 };
784
785 #define STREAM_LOG_STREAMS 4
786 #define STREAM_NUM_STREAMS BIT(STREAM_LOG_STREAMS)
787
788 #if STREAM_LOG_STREAMS > 16 && STREAM_LOG_STREAMS < 1
789 #error "Not suupported stream value"
790 #endif
791
792 /**
793 * struct cdnsp_ep - extended device side representation of USB endpoint.
794 * @endpoint: usb endpoint
795 * @pending_req_list: List of requests queuing on transfer ring.
796 * @pdev: Device associated with this endpoint.
797 * @number: Endpoint number (1 - 15).
798 * idx: The device context index (DCI).
799 * interval: Interval between packets used for ISOC endpoint.
800 * @name: A human readable name e.g. ep1out.
801 * @direction: Endpoint direction.
802 * @buffering: Number of on-chip buffers related to endpoint.
803 * @buffering_period; Number of on-chip buffers related to periodic endpoint.
804 * @in_ctx: Pointer to input endpoint context structure.
805 * @out_ctx: Pointer to output endpoint context structure.
806 * @ring: Pointer to transfer ring.
807 * @stream_info: Hold stream information.
808 * @ep_state: Current state of endpoint.
809 * @skip: Sometimes the controller can not process isochronous endpoint ring
810 * quickly enough, and it will miss some isoc tds on the ring and
811 * generate Missed Service Error Event.
812 * Set skip flag when receive a Missed Service Error Event and
813 * process the missed tds on the endpoint ring.
814 */
815 struct cdnsp_ep {
816 struct usb_ep endpoint;
817 struct list_head pending_list;
818 struct cdnsp_device *pdev;
819 u8 number;
820 u8 idx;
821 u32 interval;
822 char name[20];
823 u8 direction;
824 u8 buffering;
825 u8 buffering_period;
826 struct cdnsp_ep_ctx *in_ctx;
827 struct cdnsp_ep_ctx *out_ctx;
828 struct cdnsp_ring *ring;
829 struct cdnsp_stream_info stream_info;
830 unsigned int ep_state;
831 #define EP_ENABLED BIT(0)
832 #define EP_DIS_IN_RROGRESS BIT(1)
833 #define EP_HALTED BIT(2)
834 #define EP_STOPPED BIT(3)
835 #define EP_WEDGE BIT(4)
836 #define EP0_HALTED_STATUS BIT(5)
837 #define EP_HAS_STREAMS BIT(6)
838 #define EP_UNCONFIGURED BIT(7)
839
840 bool skip;
841 };
842
843 /**
844 * struct cdnsp_device_context_array
845 * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts.
846 * @dma: DMA address for device contexts structure.
847 */
848 struct cdnsp_device_context_array {
849 __le64 dev_context_ptrs[CDNSP_DEV_MAX_SLOTS + 1];
850 dma_addr_t dma;
851 };
852
853 /**
854 * struct cdnsp_transfer_event.
855 * @buffer: 64-bit buffer address, or immediate data.
856 * @transfer_len: Data length transferred.
857 * @flags: Field is interpreted differently based on the type of TRB.
858 */
859 struct cdnsp_transfer_event {
860 __le64 buffer;
861 __le32 transfer_len;
862 __le32 flags;
863 };
864
865 /* Invalidate event after disabling endpoint. */
866 #define TRB_EVENT_INVALIDATE 8
867
868 /* Transfer event TRB length bit mask. */
869 /* bits 0:23 */
870 #define EVENT_TRB_LEN(p) ((p) & GENMASK(23, 0))
871 /* Completion Code - only applicable for some types of TRBs */
872 #define COMP_CODE_MASK (0xff << 24)
873 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
874 #define COMP_INVALID 0
875 #define COMP_SUCCESS 1
876 #define COMP_DATA_BUFFER_ERROR 2
877 #define COMP_BABBLE_DETECTED_ERROR 3
878 #define COMP_TRB_ERROR 5
879 #define COMP_RESOURCE_ERROR 7
880 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
881 #define COMP_INVALID_STREAM_TYPE_ERROR 10
882 #define COMP_SLOT_NOT_ENABLED_ERROR 11
883 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
884 #define COMP_SHORT_PACKET 13
885 #define COMP_RING_UNDERRUN 14
886 #define COMP_RING_OVERRUN 15
887 #define COMP_VF_EVENT_RING_FULL_ERROR 16
888 #define COMP_PARAMETER_ERROR 17
889 #define COMP_CONTEXT_STATE_ERROR 19
890 #define COMP_EVENT_RING_FULL_ERROR 21
891 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
892 #define COMP_MISSED_SERVICE_ERROR 23
893 #define COMP_COMMAND_RING_STOPPED 24
894 #define COMP_COMMAND_ABORTED 25
895 #define COMP_STOPPED 26
896 #define COMP_STOPPED_LENGTH_INVALID 27
897 #define COMP_STOPPED_SHORT_PACKET 28
898 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
899 #define COMP_ISOCH_BUFFER_OVERRUN 31
900 #define COMP_EVENT_LOST_ERROR 32
901 #define COMP_UNDEFINED_ERROR 33
902 #define COMP_INVALID_STREAM_ID_ERROR 34
903
904 /*Transfer Event NRDY bit fields */
905 #define TRB_TO_DEV_STREAM(p) ((p) & GENMASK(16, 0))
906 #define TRB_TO_HOST_STREAM(p) ((p) & GENMASK(16, 0))
907 #define STREAM_PRIME_ACK 0xFFFE
908 #define STREAM_REJECTED 0xFFFF
909
910 /** Transfer Event bit fields **/
911 #define TRB_TO_EP_ID(p) (((p) & GENMASK(20, 16)) >> 16)
912
913 /**
914 * struct cdnsp_link_trb
915 * @segment_ptr: 64-bit segment pointer.
916 * @intr_target: Interrupter target.
917 * @control: Flags.
918 */
919 struct cdnsp_link_trb {
920 __le64 segment_ptr;
921 __le32 intr_target;
922 __le32 control;
923 };
924
925 /* control bitfields */
926 #define LINK_TOGGLE BIT(1)
927
928 /**
929 * struct cdnsp_event_cmd - Command completion event TRB.
930 * cmd_trb: Pointer to command TRB, or the value passed by the event data trb
931 * status: Command completion parameters and error code.
932 * flags: Flags.
933 */
934 struct cdnsp_event_cmd {
935 __le64 cmd_trb;
936 __le32 status;
937 __le32 flags;
938 };
939
940 /* flags bitmasks */
941
942 /* Address device - disable SetAddress. */
943 #define TRB_BSR BIT(9)
944
945 /* Configure Endpoint - Deconfigure. */
946 #define TRB_DC BIT(9)
947
948 /* Force Header */
949 #define TRB_FH_TO_PACKET_TYPE(p) ((p) & GENMASK(4, 0))
950 #define TRB_FH_TR_PACKET 0x4
951 #define TRB_FH_TO_DEVICE_ADDRESS(p) (((p) << 25) & GENMASK(31, 25))
952 #define TRB_FH_TR_PACKET_DEV_NOT 0x6
953 #define TRB_FH_TO_NOT_TYPE(p) (((p) << 4) & GENMASK(7, 4))
954 #define TRB_FH_TR_PACKET_FUNCTION_WAKE 0x1
955 #define TRB_FH_TO_INTERFACE(p) (((p) << 8) & GENMASK(15, 8))
956
957 enum cdnsp_setup_dev {
958 SETUP_CONTEXT_ONLY,
959 SETUP_CONTEXT_ADDRESS,
960 };
961
962 /* bits 24:31 are the slot ID. */
963 #define TRB_TO_SLOT_ID(p) (((p) & GENMASK(31, 24)) >> 24)
964 #define SLOT_ID_FOR_TRB(p) (((p) << 24) & GENMASK(31, 24))
965
966 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */
967 #define TRB_TO_EP_INDEX(p) (((p) >> 16) & 0x1f)
968
969 #define EP_ID_FOR_TRB(p) ((((p) + 1) << 16) & GENMASK(20, 16))
970
971 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
972 #define TRB_TO_SUSPEND_PORT(p) (((p) >> 23) & 0x1)
973 #define LAST_EP_INDEX 30
974
975 /* Set TR Dequeue Pointer command TRB fields. */
976 #define TRB_TO_STREAM_ID(p) ((((p) & GENMASK(31, 16)) >> 16))
977 #define STREAM_ID_FOR_TRB(p) ((((p)) << 16) & GENMASK(31, 16))
978 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
979
980 /* Link TRB specific fields. */
981 #define TRB_TC BIT(1)
982
983 /* Port Status Change Event TRB fields. */
984 /* Port ID - bits 31:24. */
985 #define GET_PORT_ID(p) (((p) & GENMASK(31, 24)) >> 24)
986 #define SET_PORT_ID(p) (((p) << 24) & GENMASK(31, 24))
987 #define EVENT_DATA BIT(2)
988
989 /* Normal TRB fields. */
990 /* transfer_len bitmasks - bits 0:16. */
991 #define TRB_LEN(p) ((p) & GENMASK(16, 0))
992 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31). */
993 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
994 #define GET_TD_SIZE(p) (((p) & GENMASK(21, 17)) >> 17)
995 /*
996 * Controller uses the TD_SIZE field for TBC if Extended TBC
997 * is enabled (ETE).
998 */
999 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1000 /* Interrupter Target - which MSI-X vector to target the completion event at. */
1001 #define TRB_INTR_TARGET(p) (((p) << 22) & GENMASK(31, 22))
1002 #define GET_INTR_TARGET(p) (((p) & GENMASK(31, 22)) >> 22)
1003 /*
1004 * Total burst count field, Rsvdz on controller with Extended TBC
1005 * enabled (ETE).
1006 */
1007 #define TRB_TBC(p) (((p) & 0x3) << 7)
1008 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1009
1010 /* Cycle bit - indicates TRB ownership by driver or driver.*/
1011 #define TRB_CYCLE BIT(0)
1012 /*
1013 * Force next event data TRB to be evaluated before task switch.
1014 * Used to pass OS data back after a TD completes.
1015 */
1016 #define TRB_ENT BIT(1)
1017 /* Interrupt on short packet. */
1018 #define TRB_ISP BIT(2)
1019 /* Set PCIe no snoop attribute. */
1020 #define TRB_NO_SNOOP BIT(3)
1021 /* Chain multiple TRBs into a TD. */
1022 #define TRB_CHAIN BIT(4)
1023 /* Interrupt on completion. */
1024 #define TRB_IOC BIT(5)
1025 /* The buffer pointer contains immediate data. */
1026 #define TRB_IDT BIT(6)
1027 /* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */
1028 #define TRB_STAT BIT(7)
1029 /* Block Event Interrupt. */
1030 #define TRB_BEI BIT(9)
1031
1032 /* Control transfer TRB specific fields. */
1033 #define TRB_DIR_IN BIT(16)
1034
1035 /* TRB bit mask in Data Stage TRB */
1036 #define TRB_SETUPID_BITMASK GENMASK(9, 8)
1037 #define TRB_SETUPID(p) ((p) << 8)
1038 #define TRB_SETUPID_TO_TYPE(p) (((p) & TRB_SETUPID_BITMASK) >> 8)
1039
1040 #define TRB_SETUP_SPEEDID_USB3 0x1
1041 #define TRB_SETUP_SPEEDID_USB2 0x0
1042 #define TRB_SETUP_SPEEDID(p) ((p) & (1 << 7))
1043
1044 #define TRB_SETUPSTAT_ACK 0x1
1045 #define TRB_SETUPSTAT_STALL 0x0
1046 #define TRB_SETUPSTAT(p) ((p) << 6)
1047
1048 /* Isochronous TRB specific fields */
1049 #define TRB_SIA BIT(31)
1050 #define TRB_FRAME_ID(p) (((p) << 20) & GENMASK(30, 20))
1051
1052 struct cdnsp_generic_trb {
1053 __le32 field[4];
1054 };
1055
1056 union cdnsp_trb {
1057 struct cdnsp_link_trb link;
1058 struct cdnsp_transfer_event trans_event;
1059 struct cdnsp_event_cmd event_cmd;
1060 struct cdnsp_generic_trb generic;
1061 };
1062
1063 /* TRB bit mask. */
1064 #define TRB_TYPE_BITMASK GENMASK(15, 10)
1065 #define TRB_TYPE(p) ((p) << 10)
1066 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1067
1068 /* TRB type IDs. */
1069 /* bulk, interrupt, isoc scatter/gather, and control data stage. */
1070 #define TRB_NORMAL 1
1071 /* Setup Stage for control transfers. */
1072 #define TRB_SETUP 2
1073 /* Data Stage for control transfers. */
1074 #define TRB_DATA 3
1075 /* Status Stage for control transfers. */
1076 #define TRB_STATUS 4
1077 /* ISOC transfers. */
1078 #define TRB_ISOC 5
1079 /* TRB for linking ring segments. */
1080 #define TRB_LINK 6
1081 #define TRB_EVENT_DATA 7
1082 /* Transfer Ring No-op (not for the command ring). */
1083 #define TRB_TR_NOOP 8
1084
1085 /* Command TRBs */
1086 /* Enable Slot Command. */
1087 #define TRB_ENABLE_SLOT 9
1088 /* Disable Slot Command. */
1089 #define TRB_DISABLE_SLOT 10
1090 /* Address Device Command. */
1091 #define TRB_ADDR_DEV 11
1092 /* Configure Endpoint Command. */
1093 #define TRB_CONFIG_EP 12
1094 /* Evaluate Context Command. */
1095 #define TRB_EVAL_CONTEXT 13
1096 /* Reset Endpoint Command. */
1097 #define TRB_RESET_EP 14
1098 /* Stop Transfer Ring Command. */
1099 #define TRB_STOP_RING 15
1100 /* Set Transfer Ring Dequeue Pointer Command. */
1101 #define TRB_SET_DEQ 16
1102 /* Reset Device Command. */
1103 #define TRB_RESET_DEV 17
1104 /* Force Event Command (opt). */
1105 #define TRB_FORCE_EVENT 18
1106 /* Force Header Command - generate a transaction or link management packet. */
1107 #define TRB_FORCE_HEADER 22
1108 /* No-op Command - not for transfer rings. */
1109 #define TRB_CMD_NOOP 23
1110 /* TRB IDs 24-31 reserved. */
1111
1112 /* Event TRBS. */
1113 /* Transfer Event. */
1114 #define TRB_TRANSFER 32
1115 /* Command Completion Event. */
1116 #define TRB_COMPLETION 33
1117 /* Port Status Change Event. */
1118 #define TRB_PORT_STATUS 34
1119 /* Device Controller Event. */
1120 #define TRB_HC_EVENT 37
1121 /* MFINDEX Wrap Event - microframe counter wrapped. */
1122 #define TRB_MFINDEX_WRAP 39
1123 /* TRB IDs 40-47 reserved. */
1124 /* Endpoint Not Ready Event. */
1125 #define TRB_ENDPOINT_NRDY 48
1126 /* TRB IDs 49-53 reserved. */
1127 /* Halt Endpoint Command. */
1128 #define TRB_HALT_ENDPOINT 54
1129 /* Doorbell Overflow Event. */
1130 #define TRB_DRB_OVERFLOW 57
1131
1132 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1133 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1134 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1135 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1136 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1137
1138 /*
1139 * TRBS_PER_SEGMENT must be a multiple of 4.
1140 * The command ring is 64-byte aligned, so it must also be greater than 16.
1141 */
1142 #define TRBS_PER_SEGMENT 256
1143 #define TRBS_PER_EVENT_SEGMENT 256
1144 #define TRBS_PER_EV_DEQ_UPDATE 100
1145 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT * 16)
1146 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1147 /* TRB buffer pointers can't cross 64KB boundaries. */
1148 #define TRB_MAX_BUFF_SHIFT 16
1149 #define TRB_MAX_BUFF_SIZE BIT(TRB_MAX_BUFF_SHIFT)
1150 /* How much data is left before the 64KB boundary? */
1151 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1152 ((addr) & (TRB_MAX_BUFF_SIZE - 1)))
1153
1154 /**
1155 * struct cdnsp_segment - segment related data.
1156 * @trbs: Array of Transfer Request Blocks.
1157 * @next: Pointer to the next segment.
1158 * @dma: DMA address of current segment.
1159 * @bounce_dma: Bounce buffer DMA address .
1160 * @bounce_buf: Bounce buffer virtual address.
1161 * bounce_offs: Bounce buffer offset.
1162 * bounce_len: Bounce buffer length.
1163 */
1164 struct cdnsp_segment {
1165 union cdnsp_trb *trbs;
1166 struct cdnsp_segment *next;
1167 dma_addr_t dma;
1168 /* Max packet sized bounce buffer for td-fragmant alignment */
1169 dma_addr_t bounce_dma;
1170 void *bounce_buf;
1171 unsigned int bounce_offs;
1172 unsigned int bounce_len;
1173 };
1174
1175 /**
1176 * struct cdnsp_td - Transfer Descriptor object.
1177 * @td_list: Used for binding TD with ep_ring->td_list.
1178 * @preq: Request associated with this TD
1179 * @start_seg: Segment containing the first_trb in TD.
1180 * @first_trb: First TRB for this TD.
1181 * @last_trb: Last TRB related with TD.
1182 * @bounce_seg: Bounce segment for this TD.
1183 * @request_length_set: actual_length of the request has already been set.
1184 * @drbl - TD has been added to HW scheduler - only for stream capable
1185 * endpoints.
1186 */
1187 struct cdnsp_td {
1188 struct list_head td_list;
1189 struct cdnsp_request *preq;
1190 struct cdnsp_segment *start_seg;
1191 union cdnsp_trb *first_trb;
1192 union cdnsp_trb *last_trb;
1193 struct cdnsp_segment *bounce_seg;
1194 bool request_length_set;
1195 bool drbl;
1196 };
1197
1198 /**
1199 * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring.
1200 * @new_deq_seg: New dequeue segment.
1201 * @new_deq_ptr: New dequeue pointer.
1202 * @new_cycle_state: New cycle state.
1203 * @stream_id: stream id for which new dequeue pointer has been selected.
1204 */
1205 struct cdnsp_dequeue_state {
1206 struct cdnsp_segment *new_deq_seg;
1207 union cdnsp_trb *new_deq_ptr;
1208 int new_cycle_state;
1209 unsigned int stream_id;
1210 };
1211
1212 enum cdnsp_ring_type {
1213 TYPE_CTRL = 0,
1214 TYPE_ISOC,
1215 TYPE_BULK,
1216 TYPE_INTR,
1217 TYPE_STREAM,
1218 TYPE_COMMAND,
1219 TYPE_EVENT,
1220 };
1221
1222 /**
1223 * struct cdnsp_ring - information describing transfer, command or event ring.
1224 * @first_seg: First segment on transfer ring.
1225 * @last_seg: Last segment on transfer ring.
1226 * @enqueue: SW enqueue pointer address.
1227 * @enq_seg: SW enqueue segment address.
1228 * @dequeue: SW dequeue pointer address.
1229 * @deq_seg: SW dequeue segment address.
1230 * @td_list: transfer descriptor list associated with this ring.
1231 * @cycle_state: Current cycle bit. Write the cycle state into the TRB cycle
1232 * field to give ownership of the TRB to the device controller
1233 * (if we are the producer) or to check if we own the TRB
1234 * (if we are the consumer).
1235 * @stream_id: Stream id
1236 * @stream_active: Stream is active - PRIME packet has been detected.
1237 * @stream_rejected: This ring has been rejected by host.
1238 * @num_tds: Number of TDs associated with ring.
1239 * @num_segs: Number of segments.
1240 * @num_trbs_free: Number of free TRBs on the ring.
1241 * @bounce_buf_len: Length of bounce buffer.
1242 * @type: Ring type - event, transfer, or command ring.
1243 * @last_td_was_short - TD is short TD.
1244 * @trb_address_map: For mapping physical TRB addresses to segments in
1245 * stream rings.
1246 */
1247 struct cdnsp_ring {
1248 struct cdnsp_segment *first_seg;
1249 struct cdnsp_segment *last_seg;
1250 union cdnsp_trb *enqueue;
1251 struct cdnsp_segment *enq_seg;
1252 union cdnsp_trb *dequeue;
1253 struct cdnsp_segment *deq_seg;
1254 struct list_head td_list;
1255 u32 cycle_state;
1256 unsigned int stream_id;
1257 unsigned int stream_active;
1258 unsigned int stream_rejected;
1259 int num_tds;
1260 unsigned int num_segs;
1261 unsigned int num_trbs_free;
1262 unsigned int bounce_buf_len;
1263 enum cdnsp_ring_type type;
1264 bool last_td_was_short;
1265 struct radix_tree_root *trb_address_map;
1266 };
1267
1268 /**
1269 * struct cdnsp_erst_entry - even ring segment table entry object.
1270 * @seg_addr: 64-bit event ring segment address.
1271 * seg_size: Number of TRBs in segment.;
1272 */
1273 struct cdnsp_erst_entry {
1274 __le64 seg_addr;
1275 __le32 seg_size;
1276 /* Set to zero */
1277 __le32 rsvd;
1278 };
1279
1280 /**
1281 * struct cdnsp_erst - even ring segment table for event ring.
1282 * @entries: Array of event ring segments
1283 * @num_entries: Number of segments in entries array.
1284 * @erst_dma_addr: DMA address for entries array.
1285 */
1286 struct cdnsp_erst {
1287 struct cdnsp_erst_entry *entries;
1288 unsigned int num_entries;
1289 dma_addr_t erst_dma_addr;
1290 };
1291
1292 /**
1293 * struct cdnsp_request - extended device side representation of usb_request
1294 * object .
1295 * @td: Transfer descriptor associated with this request.
1296 * @request: Generic usb_request object describing single I/O request.
1297 * @list: Used to adding request to endpoint pending_list.
1298 * @pep: Extended representation of usb_ep object
1299 * @epnum: Endpoint number associated with usb request.
1300 * @direction: Endpoint direction for usb request.
1301 */
1302 struct cdnsp_request {
1303 struct cdnsp_td td;
1304 struct usb_request request;
1305 struct list_head list;
1306 struct cdnsp_ep *pep;
1307 u8 epnum;
1308 unsigned direction:1;
1309 };
1310
1311 #define ERST_NUM_SEGS 1
1312
1313 /* Stages used during enumeration process.*/
1314 enum cdnsp_ep0_stage {
1315 CDNSP_SETUP_STAGE,
1316 CDNSP_DATA_STAGE,
1317 CDNSP_STATUS_STAGE,
1318 };
1319
1320 /**
1321 * struct cdnsp_port - holds information about detected ports.
1322 * @port_num: Port number.
1323 * @exist: Indicate if port exist.
1324 * maj_rev: Major revision.
1325 * min_rev: Minor revision.
1326 */
1327 struct cdnsp_port {
1328 struct cdnsp_port_regs __iomem *regs;
1329 u8 port_num;
1330 u8 exist;
1331 u8 maj_rev;
1332 u8 min_rev;
1333 };
1334
1335 #define CDNSP_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
1336 #define CDNSP_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
1337 #define CDNSP_EXT_PORT_OFF(x) ((x) & 0xff)
1338 #define CDNSP_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
1339
1340 /**
1341 * struct cdnsp_device - represent USB device.
1342 * @dev: Pointer to device structure associated whit this controller.
1343 * @gadget: Device side representation of the peripheral controller.
1344 * @gadget_driver: Pointer to the gadget driver.
1345 * @irq: IRQ line number used by device side.
1346 * @regs:IO device memory.
1347 * @cap_regs: Capability registers.
1348 * @op_regs: Operational registers.
1349 * @run_regs: Runtime registers.
1350 * @dba: Device base address register.
1351 * @ir_set: Current interrupter register set.
1352 * @port20_regs: Port 2.0 Peripheral Configuration Registers.
1353 * @port3x_regs: USB3.x Port Peripheral Configuration Registers.
1354 * @rev_cap: Controller Capabilities Registers.
1355 * @hcs_params1: Cached register copies of read-only HCSPARAMS1
1356 * @hcc_params: Cached register copies of read-only HCCPARAMS1
1357 * @setup: Temporary buffer for setup packet.
1358 * @ep0_preq: Internal allocated request used during enumeration.
1359 * @ep0_stage: ep0 stage during enumeration process.
1360 * @three_stage_setup: Three state or two state setup.
1361 * @ep0_expect_in: Data IN expected for control transfer.
1362 * @setup_id: Setup identifier.
1363 * @setup_speed - Speed detected for current SETUP packet.
1364 * @setup_buf: Buffer for SETUP packet.
1365 * @device_address: Current device address.
1366 * @may_wakeup: remote wakeup enabled/disabled.
1367 * @lock: Lock used in interrupt thread context.
1368 * @hci_version: device controller version.
1369 * @dcbaa: Device context base address array.
1370 * @cmd_ring: Command ring.
1371 * @cmd: Represent all what is needed to issue command on Command Ring.
1372 * @event_ring: Event ring.
1373 * @erst: Event Ring Segment table
1374 * @slot_id: Current Slot ID. Should be 0 or 1.
1375 * @out_ctx: Output context.
1376 * @in_ctx: Input context.
1377 * @eps: array of endpoints object associated with device.
1378 * @usb2_hw_lpm_capable: hardware lpm is enabled;
1379 * @u1_allowed: Allow device transition to U1 state.
1380 * @u2_allowed: Allow device transition to U2 state
1381 * @device_pool: DMA pool for allocating input and output context.
1382 * @segment_pool: DMA pool for allocating new segments.
1383 * @cdnsp_state: Current state of controller.
1384 * @link_state: Current link state.
1385 * @usb2_port - Port USB 2.0.
1386 * @usb3_port - Port USB 3.0.
1387 * @active_port - Current selected Port.
1388 * @test_mode: selected Test Mode.
1389 */
1390 struct cdnsp_device {
1391 struct device *dev;
1392 struct usb_gadget gadget;
1393 struct usb_gadget_driver *gadget_driver;
1394 unsigned int irq;
1395 void __iomem *regs;
1396
1397 /* Registers map */
1398 struct cdnsp_cap_regs __iomem *cap_regs;
1399 struct cdnsp_op_regs __iomem *op_regs;
1400 struct cdnsp_run_regs __iomem *run_regs;
1401 struct cdnsp_doorbell_array __iomem *dba;
1402 struct cdnsp_intr_reg __iomem *ir_set;
1403 struct cdnsp_20port_cap __iomem *port20_regs;
1404 struct cdnsp_3xport_cap __iomem *port3x_regs;
1405 struct cdnsp_rev_cap __iomem *rev_cap;
1406
1407 /* Cached register copies of read-only CDNSP data */
1408 __u32 hcs_params1;
1409 __u32 hcs_params3;
1410 __u32 hcc_params;
1411 /* Lock used in interrupt thread context. */
1412 spinlock_t lock;
1413 struct usb_ctrlrequest setup;
1414 struct cdnsp_request ep0_preq;
1415 enum cdnsp_ep0_stage ep0_stage;
1416 u8 three_stage_setup;
1417 u8 ep0_expect_in;
1418 u8 setup_id;
1419 u8 setup_speed;
1420 void *setup_buf;
1421 u8 device_address;
1422 int may_wakeup;
1423 u16 hci_version;
1424
1425 /* data structures */
1426 struct cdnsp_device_context_array *dcbaa;
1427 struct cdnsp_ring *cmd_ring;
1428 struct cdnsp_command cmd;
1429 struct cdnsp_ring *event_ring;
1430 struct cdnsp_erst erst;
1431 int slot_id;
1432
1433 /*
1434 * Commands to the hardware are passed an "input context" that
1435 * tells the hardware what to change in its data structures.
1436 * The hardware will return changes in an "output context" that
1437 * software must allocate for the hardware. .
1438 */
1439 struct cdnsp_container_ctx out_ctx;
1440 struct cdnsp_container_ctx in_ctx;
1441 struct cdnsp_ep eps[CDNSP_ENDPOINTS_NUM];
1442 u8 usb2_hw_lpm_capable:1;
1443 u8 u1_allowed:1;
1444 u8 u2_allowed:1;
1445
1446 /* DMA pools */
1447 struct dma_pool *device_pool;
1448 struct dma_pool *segment_pool;
1449
1450 #define CDNSP_STATE_HALTED BIT(1)
1451 #define CDNSP_STATE_DYING BIT(2)
1452 #define CDNSP_STATE_DISCONNECT_PENDING BIT(3)
1453 #define CDNSP_WAKEUP_PENDING BIT(4)
1454 unsigned int cdnsp_state;
1455 unsigned int link_state;
1456
1457 struct cdnsp_port usb2_port;
1458 struct cdnsp_port usb3_port;
1459 struct cdnsp_port *active_port;
1460 u16 test_mode;
1461 };
1462
1463 /*
1464 * Registers should always be accessed with double word or quad word accesses.
1465 *
1466 * Registers with 64-bit address pointers should be written to with
1467 * dword accesses by writing the low dword first (ptr[0]), then the high dword
1468 * (ptr[1]) second. controller implementations that do not support 64-bit
1469 * address pointers will ignore the high dword, and write order is irrelevant.
1470 */
cdnsp_read_64(__le64 __iomem * regs)1471 static inline u64 cdnsp_read_64(__le64 __iomem *regs)
1472 {
1473 return lo_hi_readq(regs);
1474 }
1475
cdnsp_write_64(const u64 val,__le64 __iomem * regs)1476 static inline void cdnsp_write_64(const u64 val, __le64 __iomem *regs)
1477 {
1478 lo_hi_writeq(val, regs);
1479 }
1480
1481 /* CDNSP memory management functions. */
1482 void cdnsp_mem_cleanup(struct cdnsp_device *pdev);
1483 int cdnsp_mem_init(struct cdnsp_device *pdev);
1484 int cdnsp_setup_addressable_priv_dev(struct cdnsp_device *pdev);
1485 void cdnsp_copy_ep0_dequeue_into_input_ctx(struct cdnsp_device *pdev);
1486 void cdnsp_endpoint_zero(struct cdnsp_device *pdev, struct cdnsp_ep *ep);
1487 int cdnsp_endpoint_init(struct cdnsp_device *pdev,
1488 struct cdnsp_ep *pep,
1489 gfp_t mem_flags);
1490 int cdnsp_ring_expansion(struct cdnsp_device *pdev,
1491 struct cdnsp_ring *ring,
1492 unsigned int num_trbs, gfp_t flags);
1493 struct cdnsp_ring *cdnsp_dma_to_transfer_ring(struct cdnsp_ep *ep, u64 address);
1494 int cdnsp_alloc_stream_info(struct cdnsp_device *pdev,
1495 struct cdnsp_ep *pep,
1496 unsigned int num_stream_ctxs,
1497 unsigned int num_streams);
1498 int cdnsp_alloc_streams(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1499 void cdnsp_free_endpoint_rings(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1500
1501 /* Device controller glue. */
1502 int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id);
1503 int cdnsp_halt(struct cdnsp_device *pdev);
1504 void cdnsp_died(struct cdnsp_device *pdev);
1505 int cdnsp_reset(struct cdnsp_device *pdev);
1506 irqreturn_t cdnsp_irq_handler(int irq, void *priv);
1507 int cdnsp_setup_device(struct cdnsp_device *pdev, enum cdnsp_setup_dev setup);
1508 void cdnsp_set_usb2_hardware_lpm(struct cdnsp_device *usbsssp_data,
1509 struct usb_request *req, int enable);
1510 irqreturn_t cdnsp_thread_irq_handler(int irq, void *data);
1511
1512 /* Ring, segment, TRB, and TD functions. */
1513 dma_addr_t cdnsp_trb_virt_to_dma(struct cdnsp_segment *seg,
1514 union cdnsp_trb *trb);
1515 bool cdnsp_last_trb_on_seg(struct cdnsp_segment *seg, union cdnsp_trb *trb);
1516 bool cdnsp_last_trb_on_ring(struct cdnsp_ring *ring,
1517 struct cdnsp_segment *seg,
1518 union cdnsp_trb *trb);
1519 int cdnsp_wait_for_cmd_compl(struct cdnsp_device *pdev);
1520 void cdnsp_update_erst_dequeue(struct cdnsp_device *pdev,
1521 union cdnsp_trb *event_ring_deq,
1522 u8 clear_ehb);
1523 void cdnsp_initialize_ring_info(struct cdnsp_ring *ring);
1524 void cdnsp_ring_cmd_db(struct cdnsp_device *pdev);
1525 void cdnsp_queue_slot_control(struct cdnsp_device *pdev, u32 trb_type);
1526 void cdnsp_queue_address_device(struct cdnsp_device *pdev,
1527 dma_addr_t in_ctx_ptr,
1528 enum cdnsp_setup_dev setup);
1529 void cdnsp_queue_stop_endpoint(struct cdnsp_device *pdev,
1530 unsigned int ep_index);
1531 int cdnsp_queue_ctrl_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq);
1532 int cdnsp_queue_bulk_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq);
1533 int cdnsp_queue_isoc_tx(struct cdnsp_device *pdev,
1534 struct cdnsp_request *preq);
1535 void cdnsp_queue_configure_endpoint(struct cdnsp_device *pdev,
1536 dma_addr_t in_ctx_ptr);
1537 void cdnsp_queue_reset_ep(struct cdnsp_device *pdev, unsigned int ep_index);
1538 void cdnsp_queue_halt_endpoint(struct cdnsp_device *pdev,
1539 unsigned int ep_index);
1540 void cdnsp_force_header_wakeup(struct cdnsp_device *pdev, int intf_num);
1541 void cdnsp_queue_reset_device(struct cdnsp_device *pdev);
1542 void cdnsp_queue_new_dequeue_state(struct cdnsp_device *pdev,
1543 struct cdnsp_ep *pep,
1544 struct cdnsp_dequeue_state *deq_state);
1545 void cdnsp_ring_doorbell_for_active_rings(struct cdnsp_device *pdev,
1546 struct cdnsp_ep *pep);
1547 void cdnsp_inc_deq(struct cdnsp_device *pdev, struct cdnsp_ring *ring);
1548 void cdnsp_set_link_state(struct cdnsp_device *pdev,
1549 __le32 __iomem *port_regs, u32 link_state);
1550 u32 cdnsp_port_state_to_neutral(u32 state);
1551
1552 /* CDNSP device controller contexts. */
1553 int cdnsp_enable_slot(struct cdnsp_device *pdev);
1554 int cdnsp_disable_slot(struct cdnsp_device *pdev);
1555 struct cdnsp_input_control_ctx
1556 *cdnsp_get_input_control_ctx(struct cdnsp_container_ctx *ctx);
1557 struct cdnsp_slot_ctx *cdnsp_get_slot_ctx(struct cdnsp_container_ctx *ctx);
1558 struct cdnsp_ep_ctx *cdnsp_get_ep_ctx(struct cdnsp_container_ctx *ctx,
1559 unsigned int ep_index);
1560 /* CDNSP gadget interface. */
1561 void cdnsp_suspend_gadget(struct cdnsp_device *pdev);
1562 void cdnsp_resume_gadget(struct cdnsp_device *pdev);
1563 void cdnsp_disconnect_gadget(struct cdnsp_device *pdev);
1564 void cdnsp_gadget_giveback(struct cdnsp_ep *pep, struct cdnsp_request *preq,
1565 int status);
1566 int cdnsp_ep_enqueue(struct cdnsp_ep *pep, struct cdnsp_request *preq);
1567 int cdnsp_ep_dequeue(struct cdnsp_ep *pep, struct cdnsp_request *preq);
1568 unsigned int cdnsp_port_speed(unsigned int port_status);
1569 void cdnsp_irq_reset(struct cdnsp_device *pdev);
1570 int cdnsp_halt_endpoint(struct cdnsp_device *pdev,
1571 struct cdnsp_ep *pep, int value);
1572 int cdnsp_cmd_stop_ep(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1573 void cdnsp_setup_analyze(struct cdnsp_device *pdev);
1574 int cdnsp_status_stage(struct cdnsp_device *pdev);
1575 int cdnsp_reset_device(struct cdnsp_device *pdev);
1576
1577 /**
1578 * next_request - gets the next request on the given list
1579 * @list: the request list to operate on
1580 *
1581 * Caller should take care of locking. This function return NULL or the first
1582 * request available on list.
1583 */
next_request(struct list_head * list)1584 static inline struct cdnsp_request *next_request(struct list_head *list)
1585 {
1586 return list_first_entry_or_null(list, struct cdnsp_request, list);
1587 }
1588
1589 #define to_cdnsp_ep(ep) (container_of(ep, struct cdnsp_ep, endpoint))
1590 #define gadget_to_cdnsp(g) (container_of(g, struct cdnsp_device, gadget))
1591 #define request_to_cdnsp_request(r) (container_of(r, struct cdnsp_request, \
1592 request))
1593 #define to_cdnsp_request(r) (container_of(r, struct cdnsp_request, request))
1594 int cdnsp_remove_request(struct cdnsp_device *pdev, struct cdnsp_request *preq,
1595 struct cdnsp_ep *pep);
1596
1597 #endif /* __LINUX_CDNSP_GADGET_H */
1598