1 /* 2 * Copyright 2005-2009 Freescale Semiconductor, Inc. 3 * 4 * The code contained herein is licensed under the GNU Lesser General 5 * Public License. You may obtain a copy of the GNU Lesser General 6 * Public License Version 2.1 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/lgpl-license.html 9 * http://www.gnu.org/copyleft/lgpl.html 10 */ 11 12 #ifndef __DRM_IPU_H__ 13 #define __DRM_IPU_H__ 14 15 #include <linux/types.h> 16 #include <linux/videodev2.h> 17 #include <linux/bitmap.h> 18 #include <linux/fb.h> 19 #include <linux/of.h> 20 #include <media/v4l2-mediabus.h> 21 #include <video/videomode.h> 22 23 struct ipu_soc; 24 25 enum ipuv3_type { 26 IPUV3EX, 27 IPUV3M, 28 IPUV3H, 29 }; 30 31 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') 32 33 /* 34 * Bitfield of Display Interface signal polarities. 35 */ 36 struct ipu_di_signal_cfg { 37 unsigned data_pol:1; /* true = inverted */ 38 unsigned clk_pol:1; /* true = rising edge */ 39 unsigned enable_pol:1; 40 41 struct videomode mode; 42 43 u32 bus_format; 44 u32 v_to_h_sync; 45 46 #define IPU_DI_CLKMODE_SYNC (1 << 0) 47 #define IPU_DI_CLKMODE_EXT (1 << 1) 48 unsigned long clkflags; 49 50 u8 hsync_pin; 51 u8 vsync_pin; 52 }; 53 54 /* 55 * Enumeration of CSI destinations 56 */ 57 enum ipu_csi_dest { 58 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */ 59 IPU_CSI_DEST_IC, /* to Image Converter */ 60 IPU_CSI_DEST_VDIC, /* to VDIC */ 61 }; 62 63 /* 64 * Enumeration of IPU rotation modes 65 */ 66 enum ipu_rotate_mode { 67 IPU_ROTATE_NONE = 0, 68 IPU_ROTATE_VERT_FLIP, 69 IPU_ROTATE_HORIZ_FLIP, 70 IPU_ROTATE_180, 71 IPU_ROTATE_90_RIGHT, 72 IPU_ROTATE_90_RIGHT_VFLIP, 73 IPU_ROTATE_90_RIGHT_HFLIP, 74 IPU_ROTATE_90_LEFT, 75 }; 76 77 enum ipu_color_space { 78 IPUV3_COLORSPACE_RGB, 79 IPUV3_COLORSPACE_YUV, 80 IPUV3_COLORSPACE_UNKNOWN, 81 }; 82 83 /* 84 * Enumeration of VDI MOTION select 85 */ 86 enum ipu_motion_sel { 87 MOTION_NONE = 0, 88 LOW_MOTION, 89 MED_MOTION, 90 HIGH_MOTION, 91 }; 92 93 struct ipuv3_channel; 94 95 enum ipu_channel_irq { 96 IPU_IRQ_EOF = 0, 97 IPU_IRQ_NFACK = 64, 98 IPU_IRQ_NFB4EOF = 128, 99 IPU_IRQ_EOS = 192, 100 }; 101 102 /* 103 * Enumeration of IDMAC channels 104 */ 105 #define IPUV3_CHANNEL_CSI0 0 106 #define IPUV3_CHANNEL_CSI1 1 107 #define IPUV3_CHANNEL_CSI2 2 108 #define IPUV3_CHANNEL_CSI3 3 109 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5 110 /* 111 * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels, 112 * but the direct CSI->VDI linking is handled the same way as IDMAC 113 * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so 114 * these channel names are used to support the direct CSI->VDI link. 115 */ 116 #define IPUV3_CHANNEL_CSI_DIRECT 6 117 #define IPUV3_CHANNEL_CSI_VDI_PREV 7 118 #define IPUV3_CHANNEL_MEM_VDI_PREV 8 119 #define IPUV3_CHANNEL_MEM_VDI_CUR 9 120 #define IPUV3_CHANNEL_MEM_VDI_NEXT 10 121 #define IPUV3_CHANNEL_MEM_IC_PP 11 122 #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12 123 #define IPUV3_CHANNEL_VDI_MEM_RECENT 13 124 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14 125 #define IPUV3_CHANNEL_G_MEM_IC_PP 15 126 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17 127 #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18 128 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19 129 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20 130 #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21 131 #define IPUV3_CHANNEL_IC_PP_MEM 22 132 #define IPUV3_CHANNEL_MEM_BG_SYNC 23 133 #define IPUV3_CHANNEL_MEM_BG_ASYNC 24 134 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25 135 #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26 136 #define IPUV3_CHANNEL_MEM_FG_SYNC 27 137 #define IPUV3_CHANNEL_MEM_DC_SYNC 28 138 #define IPUV3_CHANNEL_MEM_FG_ASYNC 29 139 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31 140 #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33 141 #define IPUV3_CHANNEL_DC_MEM_READ 40 142 #define IPUV3_CHANNEL_MEM_DC_ASYNC 41 143 #define IPUV3_CHANNEL_MEM_DC_COMMAND 42 144 #define IPUV3_CHANNEL_MEM_DC_COMMAND2 43 145 #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44 146 #define IPUV3_CHANNEL_MEM_ROT_ENC 45 147 #define IPUV3_CHANNEL_MEM_ROT_VF 46 148 #define IPUV3_CHANNEL_MEM_ROT_PP 47 149 #define IPUV3_CHANNEL_ROT_ENC_MEM 48 150 #define IPUV3_CHANNEL_ROT_VF_MEM 49 151 #define IPUV3_CHANNEL_ROT_PP_MEM 50 152 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51 153 #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52 154 #define IPUV3_NUM_CHANNELS 64 155 156 int ipu_map_irq(struct ipu_soc *ipu, int irq); 157 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 158 enum ipu_channel_irq irq); 159 160 #define IPU_IRQ_DP_SF_START (448 + 2) 161 #define IPU_IRQ_DP_SF_END (448 + 3) 162 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, 163 #define IPU_IRQ_DC_FC_0 (448 + 8) 164 #define IPU_IRQ_DC_FC_1 (448 + 9) 165 #define IPU_IRQ_DC_FC_2 (448 + 10) 166 #define IPU_IRQ_DC_FC_3 (448 + 11) 167 #define IPU_IRQ_DC_FC_4 (448 + 12) 168 #define IPU_IRQ_DC_FC_6 (448 + 13) 169 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14) 170 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15) 171 172 /* 173 * IPU Common functions 174 */ 175 int ipu_get_num(struct ipu_soc *ipu); 176 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2); 177 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi); 178 void ipu_dump(struct ipu_soc *ipu); 179 180 /* 181 * IPU Image DMA Controller (idmac) functions 182 */ 183 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); 184 void ipu_idmac_put(struct ipuv3_channel *); 185 186 int ipu_idmac_enable_channel(struct ipuv3_channel *channel); 187 int ipu_idmac_disable_channel(struct ipuv3_channel *channel); 188 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable); 189 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts); 190 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); 191 192 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 193 bool doublebuffer); 194 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); 195 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num); 196 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); 197 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num); 198 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); 199 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch); 200 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink); 201 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink); 202 203 /* 204 * IPU Channel Parameter Memory (cpmem) functions 205 */ 206 struct ipu_rgb { 207 struct fb_bitfield red; 208 struct fb_bitfield green; 209 struct fb_bitfield blue; 210 struct fb_bitfield transp; 211 int bits_per_pixel; 212 }; 213 214 struct ipu_image { 215 struct v4l2_pix_format pix; 216 struct v4l2_rect rect; 217 dma_addr_t phys0; 218 dma_addr_t phys1; 219 }; 220 221 void ipu_cpmem_zero(struct ipuv3_channel *ch); 222 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres); 223 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride); 224 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch); 225 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf); 226 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off); 227 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride); 228 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id); 229 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch); 230 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize); 231 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch); 232 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, 233 enum ipu_rotate_mode rot); 234 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, 235 const struct ipu_rgb *rgb); 236 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); 237 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); 238 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 239 unsigned int uv_stride, 240 unsigned int u_offset, 241 unsigned int v_offset); 242 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 243 u32 pixel_format, int stride, int height); 244 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); 245 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image); 246 void ipu_cpmem_dump(struct ipuv3_channel *ch); 247 248 /* 249 * IPU Display Controller (dc) functions 250 */ 251 struct ipu_dc; 252 struct ipu_di; 253 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); 254 void ipu_dc_put(struct ipu_dc *dc); 255 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, 256 u32 pixel_fmt, u32 width); 257 void ipu_dc_enable(struct ipu_soc *ipu); 258 void ipu_dc_enable_channel(struct ipu_dc *dc); 259 void ipu_dc_disable_channel(struct ipu_dc *dc); 260 void ipu_dc_disable(struct ipu_soc *ipu); 261 262 /* 263 * IPU Display Interface (di) functions 264 */ 265 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); 266 void ipu_di_put(struct ipu_di *); 267 int ipu_di_disable(struct ipu_di *); 268 int ipu_di_enable(struct ipu_di *); 269 int ipu_di_get_num(struct ipu_di *); 270 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode); 271 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); 272 273 /* 274 * IPU Display Multi FIFO Controller (dmfc) functions 275 */ 276 struct dmfc_channel; 277 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); 278 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); 279 void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width); 280 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); 281 void ipu_dmfc_put(struct dmfc_channel *dmfc); 282 283 /* 284 * IPU Display Processor (dp) functions 285 */ 286 #define IPU_DP_FLOW_SYNC_BG 0 287 #define IPU_DP_FLOW_SYNC_FG 1 288 #define IPU_DP_FLOW_ASYNC0_BG 2 289 #define IPU_DP_FLOW_ASYNC0_FG 3 290 #define IPU_DP_FLOW_ASYNC1_BG 4 291 #define IPU_DP_FLOW_ASYNC1_FG 5 292 293 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); 294 void ipu_dp_put(struct ipu_dp *); 295 int ipu_dp_enable(struct ipu_soc *ipu); 296 int ipu_dp_enable_channel(struct ipu_dp *dp); 297 void ipu_dp_disable_channel(struct ipu_dp *dp); 298 void ipu_dp_disable(struct ipu_soc *ipu); 299 int ipu_dp_setup_channel(struct ipu_dp *dp, 300 enum ipu_color_space in, enum ipu_color_space out); 301 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); 302 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, 303 bool bg_chan); 304 305 /* 306 * IPU CMOS Sensor Interface (csi) functions 307 */ 308 struct ipu_csi; 309 int ipu_csi_init_interface(struct ipu_csi *csi, 310 struct v4l2_mbus_config *mbus_cfg, 311 struct v4l2_mbus_framefmt *mbus_fmt); 312 bool ipu_csi_is_interlaced(struct ipu_csi *csi); 313 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); 314 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); 315 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active, 316 u32 r_value, u32 g_value, u32 b_value, 317 u32 pix_clk); 318 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, 319 struct v4l2_mbus_framefmt *mbus_fmt); 320 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip, 321 u32 max_ratio, u32 id); 322 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest); 323 int ipu_csi_enable(struct ipu_csi *csi); 324 int ipu_csi_disable(struct ipu_csi *csi); 325 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id); 326 void ipu_csi_put(struct ipu_csi *csi); 327 void ipu_csi_dump(struct ipu_csi *csi); 328 329 /* 330 * IPU Image Converter (ic) functions 331 */ 332 enum ipu_ic_task { 333 IC_TASK_ENCODER, 334 IC_TASK_VIEWFINDER, 335 IC_TASK_POST_PROCESSOR, 336 IC_NUM_TASKS, 337 }; 338 339 struct ipu_ic; 340 int ipu_ic_task_init(struct ipu_ic *ic, 341 int in_width, int in_height, 342 int out_width, int out_height, 343 enum ipu_color_space in_cs, 344 enum ipu_color_space out_cs); 345 int ipu_ic_task_graphics_init(struct ipu_ic *ic, 346 enum ipu_color_space in_g_cs, 347 bool galpha_en, u32 galpha, 348 bool colorkey_en, u32 colorkey); 349 void ipu_ic_task_enable(struct ipu_ic *ic); 350 void ipu_ic_task_disable(struct ipu_ic *ic); 351 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, 352 u32 width, u32 height, int burst_size, 353 enum ipu_rotate_mode rot); 354 int ipu_ic_enable(struct ipu_ic *ic); 355 int ipu_ic_disable(struct ipu_ic *ic); 356 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task); 357 void ipu_ic_put(struct ipu_ic *ic); 358 void ipu_ic_dump(struct ipu_ic *ic); 359 360 /* 361 * IPU Video De-Interlacer (vdi) functions 362 */ 363 struct ipu_vdi; 364 void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field); 365 void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel); 366 void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres); 367 void ipu_vdi_unsetup(struct ipu_vdi *vdi); 368 int ipu_vdi_enable(struct ipu_vdi *vdi); 369 int ipu_vdi_disable(struct ipu_vdi *vdi); 370 struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu); 371 void ipu_vdi_put(struct ipu_vdi *vdi); 372 373 /* 374 * IPU Sensor Multiple FIFO Controller (SMFC) functions 375 */ 376 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno); 377 void ipu_smfc_put(struct ipu_smfc *smfc); 378 int ipu_smfc_enable(struct ipu_smfc *smfc); 379 int ipu_smfc_disable(struct ipu_smfc *smfc); 380 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id); 381 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize); 382 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level); 383 384 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); 385 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); 386 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code); 387 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat); 388 bool ipu_pixelformat_is_planar(u32 pixelformat); 389 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 390 bool hflip, bool vflip); 391 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 392 bool hflip, bool vflip); 393 394 struct ipu_client_platformdata { 395 int csi; 396 int di; 397 int dc; 398 int dp; 399 int dma[2]; 400 struct device_node *of_node; 401 }; 402 403 #endif /* __DRM_IPU_H__ */ 404