Revision tags: v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6, v5.11-rc5, v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7 |
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#
4618cb79 |
| 21-Jul-2020 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: Add Rec.709 limited range support to DP
Add YCbCr encoding and quantization range parameters to ipu_dp_setup_channel() and configure the CSC DP matrix accordingly.
Signed-off-by: Phili
gpu: ipu-v3: Add Rec.709 limited range support to DP
Add YCbCr encoding and quantization range parameters to ipu_dp_setup_channel() and configure the CSC DP matrix accordingly.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Revision tags: v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4, v5.6-rc3, v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6, v5.4-rc5, v5.4-rc4, v5.4-rc3, v5.4-rc2, v5.4-rc1, v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3 |
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#
58b24a38 |
| 29-Jul-2019 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: remove unused functions
ipu_mbus_code_to_colorspace, ipu_stride_to_bytes, and ipu_pixelformat_is_planar are unused. Remove them.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> R
gpu: ipu-v3: remove unused functions
ipu_mbus_code_to_colorspace, ipu_stride_to_bytes, and ipu_pixelformat_is_planar are unused. Remove them.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
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Revision tags: v5.3-rc2, v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5, v5.2-rc4, v5.2-rc3, v5.2-rc2 |
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#
f208b26e |
| 22-May-2019 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: ipu-ic: Fully describe colorspace conversions
Only providing the input and output RGB/YUV space to the IC task init functions is not sufficient. To fully characterize a colorspace conve
gpu: ipu-v3: ipu-ic: Fully describe colorspace conversions
Only providing the input and output RGB/YUV space to the IC task init functions is not sufficient. To fully characterize a colorspace conversion, the Y'CbCr encoding standard, and quantization also need to be specified.
Define a 'struct ipu_ic_colorspace' that includes all the above.
This allows to actually enforce the fact that the IC:
- can only encode to/from YUV and RGB full range. A follow-up patch will remove this restriction. - can only encode using BT.601 standard. A follow-up patch will add Rec.709 encoding support.
The determination of the CSC coefficients based on the input/output 'struct ipu_ic_colorspace' are moved to a new exported function ipu_ic_calc_csc(), and 'struct ic_csc_params' is exported as 'struct ipu_ic_csc_params'. ipu_ic_calc_csc() fills a 'struct ipu_ic_csc' with the input/output 'struct ipu_ic_colorspace' and the calculated 'struct ic_csc_params' from those input/output colorspaces.
The functions ipu_ic_task_init(_rsc)() now take a filled 'struct ipu_ic_csc'.
The existing CSC coefficient tables and ipu_ic_calc_csc() are moved to a new module ipu-ic-csc.c. This is in preparation for adding more coefficient tables for limited range quantization and more encoding standards.
The existing ycbcr2rgb and inverse rgb2ycbcr tables defined the BT.601 Y'CbCr encoding coefficients. The rgb2ycbcr table specifically described the BT.601 encoding from full range RGB to full range YUV. Table comments have been added in ipu-ic-csc.c to make this more clear.
The ycbcr2rgb inverse table described encoding YUV limited range to RGB full range. To be consistent with the rgb2ycbcr table, this table is converted to YUV full range to RGB full range, and the comments are expanded in ipu-ic-csc.c.
The ic_csc_rgb2rgb table was just an identity matrix, so it is renamed 'identity' in ipu-ic-csc.c.
Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> [p.zabel@pengutronix.de: removed a superfluous blank line] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Revision tags: v5.2-rc1, v5.1, v5.1-rc7, v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1, v5.0, v5.0-rc8, v5.0-rc7, v5.0-rc6, v5.0-rc5, v5.0-rc4, v5.0-rc3, v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7, v4.20-rc6, v4.20-rc5, v4.20-rc4, v4.20-rc3, v4.20-rc2, v4.20-rc1, v4.19, v4.19-rc8, v4.19-rc7, v4.19-rc6, v4.19-rc5, v4.19-rc4 |
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#
4bfbd561 |
| 11-Sep-2018 |
Lucas Stach <l.stach@pengutronix.de> |
gpu: ipu-v3: prg: add function to get channel configure status
This allows channels using the PRG to check if a requested configuration update has been applied or is still pending.
Signed-off-by: L
gpu: ipu-v3: prg: add function to get channel configure status
This allows channels using the PRG to check if a requested configuration update has been applied or is still pending.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> [p.zabel@pengutronix.de: inverted logic: done -> pending] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
9b5c8d5f |
| 09-Jan-2019 |
Steve Longerbeam <slongerbeam@gmail.com> |
media: gpu: ipu-v3: Add planar support to interlaced scan
To support interlaced scan with planar formats, cpmem SLUV must be programmed with the correct chroma line stride. For full and partial plan
media: gpu: ipu-v3: Add planar support to interlaced scan
To support interlaced scan with planar formats, cpmem SLUV must be programmed with the correct chroma line stride. For full and partial planar 4:2:2 (YUV422P, NV16), chroma line stride must be doubled. For full and partial planar 4:2:0 (YUV420, YVU420, NV12), chroma line stride must _not_ be doubled, since a single chroma line is shared by two luma lines.
Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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#
fc8c7238 |
| 09-Jan-2019 |
Steve Longerbeam <slongerbeam@gmail.com> |
media: gpu: ipu-csi: Swap fields according to input/output field types
The function ipu_csi_init_interface() was inverting the F-bit for NTSC case, in the CCIR_CODE_1/2 registers. The result being t
media: gpu: ipu-csi: Swap fields according to input/output field types
The function ipu_csi_init_interface() was inverting the F-bit for NTSC case, in the CCIR_CODE_1/2 registers. The result being that for NTSC bottom-top field order, the CSI would swap fields and capture in top-bottom order.
Instead, base field swap on the field order of the input to the CSI, and the field order of the requested output. If the input/output fields are sequential but different, swap fields, otherwise do not swap. This requires passing both the input and output mbus frame formats to ipu_csi_init_interface().
Move this code to a new private function ipu_csi_set_bt_interlaced_codes() that programs the CCIR_CODE_1/2 registers for interlaced BT.656 (and possibly interlaced BT.1120 in the future).
When detecting input video standard from the input frame width/height, make sure to double height if input field type is alternate, since in that case input height only includes lines for one field.
Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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#
d0cbc93a |
| 18-Sep-2018 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: ipu-ic: allow to manually set resize coefficients
For tiled scaling, we want to compute the scaling coefficients externally in such a way that the interpolation overshoots tile boundari
gpu: ipu-v3: ipu-ic: allow to manually set resize coefficients
For tiled scaling, we want to compute the scaling coefficients externally in such a way that the interpolation overshoots tile boundaries and samples up to the first pixel of the next tile. Prepare to override the resizing coefficients from the image conversion code.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
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#
dec408fd |
| 06-Oct-2018 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: Add chroma plane offset overrides to ipu_cpmem_set_image()
Allow the caller of ipu_cpmem_set_image() to override the latters calculation of the chroma plane offsets, by adding override
gpu: ipu-v3: Add chroma plane offset overrides to ipu_cpmem_set_image()
Allow the caller of ipu_cpmem_set_image() to override the latters calculation of the chroma plane offsets, by adding override U/V plane offsets to 'struct ipu_image'.
Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Revision tags: v4.19-rc3, v4.19-rc2, v4.19-rc1, v4.18, v4.18-rc8, v4.18-rc7, v4.18-rc6, v4.18-rc5, v4.18-rc4, v4.18-rc3, v4.18-rc2, v4.18-rc1, v4.17, v4.17-rc7, v4.17-rc6, v4.17-rc5, v4.17-rc4, v4.17-rc3, v4.17-rc2, v4.17-rc1, v4.16, v4.16-rc7, v4.16-rc6, v4.16-rc5, v4.16-rc4, v4.16-rc3, v4.16-rc2, v4.16-rc1, v4.15, v4.15-rc9, v4.15-rc8, v4.15-rc7, v4.15-rc6, v4.15-rc5, v4.15-rc4, v4.15-rc3, v4.15-rc2, v4.15-rc1, v4.14 |
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#
a2ceec52 |
| 10-Nov-2017 |
Lucas Stach <l.stach@pengutronix.de> |
gpu: ipu-v3: prg: add modifier support
Allow to pass through the modifier to the PRE unit and extend the format check with the supported modifiers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.d
gpu: ipu-v3: prg: add modifier support
Allow to pass through the modifier to the PRE unit and extend the format check with the supported modifiers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Revision tags: v4.14-rc8, v4.14-rc7, v4.14-rc6, v4.14-rc5, v4.14-rc4, v4.14-rc3, v4.14-rc2, v4.14-rc1, v4.13, v4.13-rc7, v4.13-rc6, v4.13-rc5, v4.13-rc4, v4.13-rc3, v4.13-rc2, v4.13-rc1, v4.12, v4.12-rc7, v4.12-rc6, v4.12-rc5, v4.12-rc4, v4.12-rc3, v4.12-rc2, v4.12-rc1, v4.11, v4.11-rc8, v4.11-rc7, v4.11-rc6, v4.11-rc5, v4.11-rc4, v4.11-rc3, v4.11-rc2, v4.11-rc1, v4.10, v4.10-rc8, v4.10-rc7, v4.10-rc6, v4.10-rc5, v4.10-rc4, v4.10-rc3, v4.10-rc2, v4.10-rc1, v4.9, v4.9-rc8, v4.9-rc7, v4.9-rc6, v4.9-rc5, v4.9-rc4, v4.9-rc3, v4.9-rc2, v4.9-rc1, v4.8, v4.8-rc8, v4.8-rc7, v4.8-rc6, v4.8-rc5, v4.8-rc4, v4.8-rc3, v4.8-rc2, v4.8-rc1, v4.7, v4.7-rc7, v4.7-rc6, v4.7-rc5, v4.7-rc4, v4.7-rc3, v4.7-rc2, v4.7-rc1, v4.6, v4.6-rc7, v4.6-rc6, v4.6-rc5, v4.6-rc4, v4.6-rc3, v4.6-rc2, v4.6-rc1, v4.5, v4.5-rc7, v4.5-rc6, v4.5-rc5, v4.5-rc4, v4.5-rc3, v4.5-rc2, v4.5-rc1, v4.4, v4.4-rc8, v4.4-rc7, v4.4-rc6, v4.4-rc5, v4.4-rc4, v4.4-rc3, v4.4-rc2, v4.4-rc1, v4.3, v4.3-rc7, v4.3-rc6, v4.3-rc5, v4.3-rc4, v4.3-rc3, v4.3-rc2, v4.3-rc1, v4.2, v4.2-rc8, v4.2-rc7, v4.2-rc6, v4.2-rc5, v4.2-rc4, v4.2-rc3, v4.2-rc2, v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0, v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4, v4.0-rc3, v4.0-rc2, v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1, v3.18, v3.18-rc7, v3.18-rc6, v3.18-rc5, v3.18-rc4, v3.18-rc3, v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6 |
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#
e1e9733c |
| 17-Sep-2014 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: Add support for double read/write reduction
Allow to skip writing odd chroma rows by setting the RDRW bit for 4:2:0 chroma subsampled formats for any IDMAC write channel. This also allo
gpu: ipu-v3: Add support for double read/write reduction
Allow to skip writing odd chroma rows by setting the RDRW bit for 4:2:0 chroma subsampled formats for any IDMAC write channel. This also allows to skip reading odd rows for the VDIC read channel.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
ea9c2605 |
| 08-Mar-2017 |
Lucas Stach <l.stach@pengutronix.de> |
gpu: ipu-v3: add driver for Prefetch Resolve Gasket
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the IPU and the PRE units.
Signed-off-by: Lucas Stach <l.stach@pengutronix.d
gpu: ipu-v3: add driver for Prefetch Resolve Gasket
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the IPU and the PRE units.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- v4: add missing ipu_soc->prg_priv
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#
e72db3b1 |
| 09-Jan-2015 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: add support for separate alpha channels
The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven by the Alpha Transparency Controller (ATC) for the graphics IDMAC chan
gpu: ipu-v3: add support for separate alpha channels
The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven by the Alpha Transparency Controller (ATC) for the graphics IDMAC channels. This allows to reduce memory bandwidth via a conditional read mechanism or to support planar YUV formats with alpha transparency.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
f9bb7acb |
| 24-Feb-2017 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: add unsynchronised DP channel disabling
When disabling the foreground DP channel during a modeset, the DC is already disabled without waiting for end of frame. There is no reason to wai
gpu: ipu-v3: add unsynchronised DP channel disabling
When disabling the foreground DP channel during a modeset, the DC is already disabled without waiting for end of frame. There is no reason to wait for a frame boundary before updating the DP registers in that case. Add support to apply updates immediately. No functional changes, yet.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
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#
867341b9 |
| 05-Oct-2016 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: add ipu_csi_set_downsize
Support downsizing to 1/2 width and/or height in the CSI.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
9c24d680 |
| 18-Oct-2016 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar function
ipu_cpmem_set_yuv_planar_full is only used directly, remove the wrapper.
Suggested-by: Liu Ying <gnuiyl@gmail.com> Signed-off-by: Phi
gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar function
ipu_cpmem_set_yuv_planar_full is only used directly, remove the wrapper.
Suggested-by: Liu Ying <gnuiyl@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Liu Ying <gnuiyl@gmail.com>
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#
8b9c3d50 |
| 17-Sep-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: Add ipu_rot_mode_is_irt()
Add a macro that returns boolean true if the given ipu_rotate_mode requires the use of the Image Rotator.
Signed-off-by: Steve Longerbeam <steve_longerbeam@me
gpu: ipu-v3: Add ipu_rot_mode_is_irt()
Add a macro that returns boolean true if the given ipu_rotate_mode requires the use of the Image Rotator.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
ac4708fa |
| 18-Aug-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: Add FSU channel linking support
Adds functions to link and unlink source channels to sink channels in the FSU:
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); int ipu_f
gpu: ipu-v3: Add FSU channel linking support
Adds functions to link and unlink source channels to sink channels in the FSU:
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
The channels numbers are usually IDMAC channels, but they can also be channels that do not transfer data to or from memory. The following convenience functions can be used in place of ipu_fsu_link/unlink() when both source and sink channels are IDMAC channels:
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink); int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
So far the following links are supported:
IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC PUV3_CHANNEL_IC_PRP_VF_MEM -> IPUV3_CHANNEL_MEM_ROT_VF IPUV3_CHANNEL_IC_PP_MEM -> IPUV3_CHANNEL_MEM_ROT_PP IPUV3_CHANNEL_CSI_DIRECT -> IPUV3_CHANNEL_CSI_VDI_PREV
More links can be added to the fsu_link_info[] array.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
2d2ead45 |
| 18-Aug-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: Add Video Deinterlacer unit
Adds the Video Deinterlacer (VDIC) unit.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Revision tags: v3.17-rc5, v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1, v3.16 |
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#
bc0a3387 |
| 30-Jul-2014 |
Philipp Zabel <p.zabel@pengutronix.de> |
gpu: ipu-v3: Add missing IDMAC channel names
This patch adds the remaining missing IDMAC channel names: VDIC channels for combining, the separate alpha channels for the MEM->IC and MEM->DC ASYNC cha
gpu: ipu-v3: Add missing IDMAC channel names
This patch adds the remaining missing IDMAC channel names: VDIC channels for combining, the separate alpha channels for the MEM->IC and MEM->DC ASYNC channels, and the DC read, command, and output mask channels.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
97afc25c |
| 20-Jul-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: Add VDI input IDMAC channels
Adds the VDIC field input IDMAC channels. These channels transfer fields F(n-1), F(n), and F(N+1) from memory to the VDIC (channels 8, 9, 10 respectively).
gpu: ipu-v3: Add VDI input IDMAC channels
Adds the VDIC field input IDMAC channels. These channels transfer fields F(n-1), F(n), and F(N+1) from memory to the VDIC (channels 8, 9, 10 respectively).
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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#
572a7615 |
| 20-Jul-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-v3: Add ipu_get_num()
Adds of-alias id to ipu_soc and retrieve with ipu_get_num().
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengu
gpu: ipu-v3: Add ipu_get_num()
Adds of-alias id to ipu_soc and retrieve with ipu_get_num().
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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03085911 |
| 20-Jul-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
Adds ipu_cpmem_get_burstsize().
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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e5e8690f |
| 20-Jul-2016 |
Steve Longerbeam <slongerbeam@gmail.com> |
gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <
gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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d7868cb7 |
| 08-Jul-2016 |
Liu Ying <gnuiyl@gmail.com> |
gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanism
For all video modes we support currently, we always get 2 slots for a plane by using the current existing dynamic DMFC FIFO allocatio
gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanism
For all video modes we support currently, we always get 2 slots for a plane by using the current existing dynamic DMFC FIFO allocation mechanism. So, let's change to use the static one to simplify the code. This also makes it easier to implement the atomic mode setting as we don't need to handle allocation failure cases then.
Signed-off-by: Liu Ying <gnuiyl@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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310944d1 |
| 12-May-2016 |
Philipp Zabel <p.zabel@pengutronix.de> |
drm/imx: Match imx-ipuv3-crtc components using device node in platform data
The component master driver imx-drm-core matches component devices using their of_node. Since commit 950b410dd1ab ("gpu: i
drm/imx: Match imx-ipuv3-crtc components using device node in platform data
The component master driver imx-drm-core matches component devices using their of_node. Since commit 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading"), the imx-ipuv3-crtc dev->of_node is not set during probing. Before that, of_node was set and caused an of: modalias to be used instead of the platform: modalias, which broke module autoloading.
On the other hand, if dev->of_node is not set yet when the imx-ipuv3-crtc probe function calls component_add, component matching in imx-drm-core fails. While dev->of_node will be set once the next component tries to bring up the component master, imx-drm-core component binding will never succeed if one of the crtc devices is probed last.
Add of_node to the component platform data and match against the pdata->of_node instead of dev->of_node in imx-drm-core to work around this problem.
Cc: <stable@vger.kernel.org> # 4.4.x Fixes: 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Lothar Waßmann <LW@KARO-electronics.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
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