1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for SIRegisterInfo 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H 17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H 18 19 #include "AMDGPURegisterInfo.h" 20 #include "AMDGPUSubtarget.h" 21 #include "llvm/Support/Debug.h" 22 23 namespace llvm { 24 25 struct SIRegisterInfo : public AMDGPURegisterInfo { 26 27 SIRegisterInfo(const AMDGPUSubtarget &st); 28 29 BitVector getReservedRegs(const MachineFunction &MF) const override; 30 31 unsigned getRegPressureSetLimit(unsigned Idx) const override; 32 33 bool requiresRegisterScavenging(const MachineFunction &Fn) const override; 34 35 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 36 unsigned FIOperandNum, 37 RegScavenger *RS) const override; 38 39 /// \brief get the register class of the specified type to use in the 40 /// CFGStructurizer 41 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override; 42 43 unsigned getHWRegIndex(unsigned Reg) const override; 44 45 /// \brief Return the 'base' register class for this register. 46 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc. 47 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const; 48 49 /// \returns true if this class contains only SGPR registers isSGPRClassSIRegisterInfo50 bool isSGPRClass(const TargetRegisterClass *RC) const { 51 if (!RC) 52 return false; 53 54 return !hasVGPRs(RC); 55 } 56 57 /// \returns true if this class ID contains only SGPR registers isSGPRClassIDSIRegisterInfo58 bool isSGPRClassID(unsigned RCID) const { 59 if (static_cast<int>(RCID) == -1) 60 return false; 61 62 return isSGPRClass(getRegClass(RCID)); 63 } 64 65 /// \returns true if this class contains VGPR registers. 66 bool hasVGPRs(const TargetRegisterClass *RC) const; 67 68 /// \returns A VGPR reg class with the same width as \p SRC 69 const TargetRegisterClass *getEquivalentVGPRClass( 70 const TargetRegisterClass *SRC) const; 71 72 /// \returns The register class that is used for a sub-register of \p RC for 73 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will 74 /// be returned. 75 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC, 76 unsigned SubIdx) const; 77 78 /// \p Channel This is the register channel (e.g. a value from 0-16), not the 79 /// SubReg index. 80 /// \returns The sub-register of Reg that is in Channel. 81 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, 82 unsigned Channel) const; 83 84 /// \returns True if operands defined with this operand type can accept 85 /// a literal constant (i.e. any 32-bit immediate). 86 bool opCanUseLiteralConstant(unsigned OpType) const; 87 88 /// \returns True if operands defined with this operand type can accept 89 /// an inline constant. i.e. An integer value in the range (-16, 64) or 90 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f. 91 bool opCanUseInlineConstant(unsigned OpType) const; 92 93 enum PreloadedValue { 94 TGID_X, 95 TGID_Y, 96 TGID_Z, 97 SCRATCH_WAVE_OFFSET, 98 SCRATCH_PTR, 99 INPUT_PTR, 100 TIDIG_X, 101 TIDIG_Y, 102 TIDIG_Z 103 }; 104 105 /// \brief Returns the physical register that \p Value is stored in. 106 unsigned getPreloadedValue(const MachineFunction &MF, 107 enum PreloadedValue Value) const; 108 109 /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount 110 /// concurrent waves. 111 unsigned getNumVGPRsAllowed(unsigned WaveCount) const; 112 113 /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount 114 /// concurrent waves. 115 unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, 116 unsigned WaveCount) const; 117 118 unsigned findUnusedRegister(const MachineRegisterInfo &MRI, 119 const TargetRegisterClass *RC) const; 120 121 private: 122 void buildScratchLoadStore(MachineBasicBlock::iterator MI, 123 unsigned LoadStoreOp, unsigned Value, 124 unsigned ScratchRsrcReg, unsigned ScratchOffset, 125 int64_t Offset, RegScavenger *RS) const; 126 }; 127 128 } // End namespace llvm 129 130 #endif 131