1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// SI Instruction format definitions.
10//
11//===----------------------------------------------------------------------===//
12
13class InstSI <dag outs, dag ins, string asm = "",
14              list<dag> pattern = []> :
15  AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
16  // Low bits - basic encoding information.
17  field bit SALU = 0;
18  field bit VALU = 0;
19
20  // SALU instruction formats.
21  field bit SOP1 = 0;
22  field bit SOP2 = 0;
23  field bit SOPC = 0;
24  field bit SOPK = 0;
25  field bit SOPP = 0;
26
27  // VALU instruction formats.
28  field bit VOP1 = 0;
29  field bit VOP2 = 0;
30  field bit VOPC = 0;
31  field bit VOP3 = 0;
32  field bit VOP3P = 0;
33  field bit VINTRP = 0;
34  field bit SDWA = 0;
35  field bit DPP = 0;
36  field bit TRANS = 0;
37
38  // Memory instruction formats.
39  field bit MUBUF = 0;
40  field bit MTBUF = 0;
41  field bit SMRD = 0;
42  field bit MIMG = 0;
43  field bit EXP = 0;
44  field bit FLAT = 0;
45  field bit DS = 0;
46
47  // Pseudo instruction formats.
48  field bit VGPRSpill = 0;
49  field bit SGPRSpill = 0;
50
51  // High bits - other information.
52  field bit VM_CNT = 0;
53  field bit EXP_CNT = 0;
54  field bit LGKM_CNT = 0;
55
56  // Whether WQM _must_ be enabled for this instruction.
57  field bit WQM = 0;
58
59  // Whether WQM _must_ be disabled for this instruction.
60  field bit DisableWQM = 0;
61
62  field bit Gather4 = 0;
63
64  // Most sopk treat the immediate as a signed 16-bit, however some
65  // use it as unsigned.
66  field bit SOPKZext = 0;
67
68  // This is an s_store_dword* instruction that requires a cache flush
69  // on wave termination. It is necessary to distinguish from mayStore
70  // SMEM instructions like the cache flush ones.
71  field bit ScalarStore = 0;
72
73  // Whether the operands can be ignored when computing the
74  // instruction size.
75  field bit FixedSize = 0;
76
77  // This bit tells the assembler to use the 32-bit encoding in case it
78  // is unable to infer the encoding from the operands.
79  field bit VOPAsmPrefer32Bit = 0;
80
81  // This bit indicates that this is a VOP3 opcode which supports op_sel
82  // modifier (gfx9 only).
83  field bit VOP3_OPSEL = 0;
84
85  // Is it possible for this instruction to be atomic?
86  field bit maybeAtomic = 0;
87
88  // This bit indicates that this is a VI instruction which is renamed
89  // in GFX9. Required for correct mapping from pseudo to MC.
90  field bit renamedInGFX9 = 0;
91
92  // This bit indicates that this has a floating point result type, so
93  // the clamp modifier has floating point semantics.
94  field bit FPClamp = 0;
95
96  // This bit indicates that instruction may support integer clamping
97  // which depends on GPU features.
98  field bit IntClamp = 0;
99
100  // This field indicates that the clamp applies to the low component
101  // of a packed output register.
102  field bit ClampLo = 0;
103
104  // This field indicates that the clamp applies to the high component
105  // of a packed output register.
106  field bit ClampHi = 0;
107
108  // This bit indicates that this is a packed VOP3P instruction
109  field bit IsPacked = 0;
110
111  // This bit indicates that this is a D16 buffer instruction.
112  field bit D16Buf = 0;
113
114  // This field indicates that FLAT instruction accesses FLAT_GLBL segment.
115  // Must be 0 for non-FLAT instructions.
116  field bit FlatGlobal = 0;
117
118  // Reads the mode register, usually for FP environment.
119  field bit ReadsModeReg = 0;
120
121  // This bit indicates that this uses the floating point double precision
122  // rounding mode flags
123  field bit FPDPRounding = 0;
124
125  // Instruction is FP atomic.
126  field bit FPAtomic = 0;
127
128  // This bit indicates that this is one of MFMA instructions.
129  field bit IsMAI = 0;
130
131  // This bit indicates that this is one of DOT instructions.
132  field bit IsDOT = 0;
133
134  // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment.
135  // Must be 0 for non-FLAT instructions.
136  field bit FlatScratch = 0;
137
138  // Atomic without a return.
139  field bit IsAtomicNoRet = 0;
140
141  // Atomic with return.
142  field bit IsAtomicRet = 0;
143
144  // These need to be kept in sync with the enum in SIInstrFlags.
145  let TSFlags{0} = SALU;
146  let TSFlags{1} = VALU;
147
148  let TSFlags{2} = SOP1;
149  let TSFlags{3} = SOP2;
150  let TSFlags{4} = SOPC;
151  let TSFlags{5} = SOPK;
152  let TSFlags{6} = SOPP;
153
154  let TSFlags{7} = VOP1;
155  let TSFlags{8} = VOP2;
156  let TSFlags{9} = VOPC;
157  let TSFlags{10} = VOP3;
158  let TSFlags{12} = VOP3P;
159
160  let TSFlags{13} = VINTRP;
161  let TSFlags{14} = SDWA;
162  let TSFlags{15} = DPP;
163  let TSFlags{16} = TRANS;
164
165  let TSFlags{17} = MUBUF;
166  let TSFlags{18} = MTBUF;
167  let TSFlags{19} = SMRD;
168  let TSFlags{20} = MIMG;
169  let TSFlags{21} = EXP;
170  let TSFlags{22} = FLAT;
171  let TSFlags{23} = DS;
172
173  let TSFlags{24} = VGPRSpill;
174  let TSFlags{25} = SGPRSpill;
175
176  let TSFlags{32} = VM_CNT;
177  let TSFlags{33} = EXP_CNT;
178  let TSFlags{34} = LGKM_CNT;
179
180  let TSFlags{35} = WQM;
181  let TSFlags{36} = DisableWQM;
182  let TSFlags{37} = Gather4;
183
184  let TSFlags{38} = SOPKZext;
185  let TSFlags{39} = ScalarStore;
186  let TSFlags{40} = FixedSize;
187  let TSFlags{41} = VOPAsmPrefer32Bit;
188  let TSFlags{42} = VOP3_OPSEL;
189
190  let TSFlags{43} = maybeAtomic;
191  let TSFlags{44} = renamedInGFX9;
192
193  let TSFlags{45} = FPClamp;
194  let TSFlags{46} = IntClamp;
195  let TSFlags{47} = ClampLo;
196  let TSFlags{48} = ClampHi;
197
198  let TSFlags{49} = IsPacked;
199
200  let TSFlags{50} = D16Buf;
201
202  let TSFlags{51} = FlatGlobal;
203
204  let TSFlags{52} = FPDPRounding;
205
206  let TSFlags{53} = FPAtomic;
207
208  let TSFlags{54} = IsMAI;
209
210  let TSFlags{55} = IsDOT;
211
212  let TSFlags{56} = FlatScratch;
213
214  let TSFlags{57} = IsAtomicNoRet;
215
216  let TSFlags{58} = IsAtomicRet;
217
218  let SchedRW = [Write32Bit];
219
220  let AsmVariantName = AMDGPUAsmVariants.Default;
221
222  // Avoid changing source registers in a way that violates constant bus read limitations.
223  let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
224}
225
226class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
227  : InstSI<outs, ins, asm, pattern> {
228  let isPseudo = 1;
229  let isCodeGenOnly = 1;
230}
231
232class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
233  : PseudoInstSI<outs, ins, pattern, asm> {
234  let SALU = 1;
235}
236
237class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
238  : PseudoInstSI<outs, ins, pattern, asm> {
239  let VALU = 1;
240  let Uses = [EXEC];
241}
242
243class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
244  bit UseExec = 0, bit DefExec = 0> :
245  SPseudoInstSI<outs, ins, pattern> {
246
247  let Uses = !if(UseExec, [EXEC], []);
248  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
249  let mayLoad = 0;
250  let mayStore = 0;
251  let hasSideEffects = 0;
252}
253
254class Enc32 {
255  field bits<32> Inst;
256  int Size = 4;
257}
258
259class Enc64 {
260  field bits<64> Inst;
261  int Size = 8;
262}
263
264def CPolBit {
265  int GLC = 0;
266  int SLC = 1;
267  int DLC = 2;
268  int SCC = 4;
269}
270
271class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
272
273class VINTRPe <bits<2> op> : Enc32 {
274  bits<8> vdst;
275  bits<8> vsrc;
276  bits<2> attrchan;
277  bits<6> attr;
278
279  let Inst{7-0} = vsrc;
280  let Inst{9-8} = attrchan;
281  let Inst{15-10} = attr;
282  let Inst{17-16} = op;
283  let Inst{25-18} = vdst;
284  let Inst{31-26} = 0x32; // encoding
285}
286
287class MIMGe : Enc64 {
288  bits<10> vdata;
289  bits<4> dmask;
290  bits<1> unorm;
291  bits<5> cpol;
292  bits<1> r128;
293  bits<1> tfe;
294  bits<1> lwe;
295  bit d16;
296  bits<7> srsrc;
297  bits<7> ssamp;
298
299  let Inst{11-8} = dmask;
300  let Inst{12} = unorm;
301  let Inst{13} = cpol{CPolBit.GLC};
302  let Inst{15} = r128;
303  let Inst{17} = lwe;
304  let Inst{25} = cpol{CPolBit.SLC};
305  let Inst{31-26} = 0x3c;
306  let Inst{47-40} = vdata{7-0};
307  let Inst{52-48} = srsrc{6-2};
308  let Inst{57-53} = ssamp{6-2};
309  let Inst{63} = d16;
310}
311
312class MIMGe_gfx6789 <bits<8> op> : MIMGe {
313  bits<8> vaddr;
314  bits<1> da;
315
316  let Inst{0} = op{7};
317  let Inst{7} = cpol{CPolBit.SCC};
318  let Inst{14} = da;
319  let Inst{16} = tfe;
320  let Inst{24-18} = op{6-0};
321  let Inst{39-32} = vaddr;
322}
323
324class MIMGe_gfx90a <bits<8> op> : MIMGe {
325  bits<8> vaddr;
326  bits<1> da;
327
328  let Inst{0} = op{7};
329  let Inst{7} = cpol{CPolBit.SCC};
330  let Inst{14} = da;
331  let Inst{16} = vdata{9}; // ACC bit
332  let Inst{24-18} = op{6-0};
333  let Inst{39-32} = vaddr;
334}
335
336class MIMGe_gfx10 <bits<8> op> : MIMGe {
337  bits<8> vaddr0;
338  bits<3> dim;
339  bits<2> nsa;
340  bits<1> a16;
341
342  let Inst{0} = op{7};
343  let Inst{2-1} = nsa;
344  let Inst{5-3} = dim;
345  let Inst{7} = cpol{CPolBit.DLC};
346  let Inst{16} = tfe;
347  let Inst{24-18} = op{6-0};
348  let Inst{39-32} = vaddr0;
349  let Inst{62} = a16;
350}
351
352class EXPe : Enc64 {
353  bits<4> en;
354  bits<6> tgt;
355  bits<1> compr;
356  bits<1> done;
357  bits<1> vm;
358  bits<8> src0;
359  bits<8> src1;
360  bits<8> src2;
361  bits<8> src3;
362
363  let Inst{3-0} = en;
364  let Inst{9-4} = tgt;
365  let Inst{10} = compr;
366  let Inst{11} = done;
367  let Inst{12} = vm;
368  let Inst{31-26} = 0x3e;
369  let Inst{39-32} = src0;
370  let Inst{47-40} = src1;
371  let Inst{55-48} = src2;
372  let Inst{63-56} = src3;
373}
374
375let Uses = [EXEC] in {
376
377class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
378    InstSI <outs, ins, asm, pattern> {
379  let VINTRP = 1;
380  // VINTRP instructions read parameter values from LDS, but these parameter
381  // values are stored outside of the LDS memory that is allocated to the
382  // shader for general purpose use.
383  //
384  // While it may be possible for ds_read/ds_write instructions to access
385  // the parameter values in LDS, this would essentially be an out-of-bounds
386  // memory access which we consider to be undefined behavior.
387  //
388  // So even though these instructions read memory, this memory is outside the
389  // addressable memory space for the shader, and we consider these instructions
390  // to be readnone.
391  let mayLoad = 0;
392  let mayStore = 0;
393  let hasSideEffects = 0;
394  let VALU = 1;
395}
396
397} // End Uses = [EXEC]
398