1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 x87 FPU instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// FPStack specific DAG Nodes. 17//===----------------------------------------------------------------------===// 18 19def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20 SDTCisPtrTy<1>]>; 21def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22 SDTCisPtrTy<1>]>; 23def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25 26def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 27def SDTX86CwdLoad : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 28 29def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 30 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 31def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 32 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 33def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 34 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 35def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 36 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 37def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 38 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 39def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 40 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 41 SDNPMemOperand]>; 42def X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m", SDTX86CwdLoad, 43 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 44 SDNPMemOperand]>; 45 46def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 47 (X86fst node:$val, node:$ptr), [{ 48 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 49}]>; 50def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 51 (X86fst node:$val, node:$ptr), [{ 52 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 53}]>; 54def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 55 (X86fst node:$val, node:$ptr), [{ 56 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 57}]>; 58 59def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 60 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 61}]>; 62def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 63 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 64}]>; 65def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 66 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 67}]>; 68 69def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 70 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 71}]>; 72def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 73 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 74}]>; 75def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 76 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 77}]>; 78 79def X86fist32 : PatFrag<(ops node:$val, node:$ptr), 80 (X86fist node:$val, node:$ptr), [{ 81 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 82}]>; 83 84def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 85 (X86fist node:$val, node:$ptr), [{ 86 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 87}]>; 88 89def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 90 (X86fp_to_mem node:$val, node:$ptr), [{ 91 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 92}]>; 93def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 94 (X86fp_to_mem node:$val, node:$ptr), [{ 95 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 96}]>; 97def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 98 (X86fp_to_mem node:$val, node:$ptr), [{ 99 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 100}]>; 101 102//===----------------------------------------------------------------------===// 103// FPStack pattern fragments 104//===----------------------------------------------------------------------===// 105 106def fpimm0 : FPImmLeaf<fAny, [{ 107 return Imm.isExactlyValue(+0.0); 108}]>; 109 110def fpimmneg0 : FPImmLeaf<fAny, [{ 111 return Imm.isExactlyValue(-0.0); 112}]>; 113 114def fpimm1 : FPImmLeaf<fAny, [{ 115 return Imm.isExactlyValue(+1.0); 116}]>; 117 118def fpimmneg1 : FPImmLeaf<fAny, [{ 119 return Imm.isExactlyValue(-1.0); 120}]>; 121 122// Some 'special' instructions - expanded after instruction selection. 123// Clobbers EFLAGS due to OR instruction used internally. 124// FIXME: Can we model this in SelectionDAG? 125let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 126 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 127 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 128 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 129 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 130 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 131 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 132 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 133 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 134 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 135 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 136 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 137 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 138 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 139 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 140 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 141 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 142 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 143 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 144} 145 146// All FP Stack operations are represented with four instructions here. The 147// first three instructions, generated by the instruction selector, use "RFP32" 148// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 149// 64-bit or 80-bit floating point values. These sizes apply to the values, 150// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 151// copied to each other without losing information. These instructions are all 152// pseudo instructions and use the "_Fp" suffix. 153// In some cases there are additional variants with a mixture of different 154// register sizes. 155// The second instruction is defined with FPI, which is the actual instruction 156// emitted by the assembler. These use "RST" registers, although frequently 157// the actual register(s) used are implicit. These are always 80 bits. 158// The FP stackifier pass converts one to the other after register allocation 159// occurs. 160// 161// Note that the FpI instruction should have instruction selection info (e.g. 162// a pattern) and the FPI instruction should have emission info (e.g. opcode 163// encoding and asm printing info). 164 165// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 166// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 167// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 168// f80 instructions cannot use SSE and use neither of these. 169class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 170 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 171class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 172 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 173 174// Factoring for arithmetic. 175multiclass FPBinary_rr<SDPatternOperator OpNode> { 176// Register op register -> register 177// These are separated out because they have no reversed form. 178def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 179 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 180def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 181 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 182def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 183 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 184} 185// The FopST0 series are not included here because of the irregularities 186// in where the 'r' goes in assembly output. 187// These instructions cannot address 80-bit memory. 188multiclass FPBinary<SDPatternOperator OpNode, Format fp, string asmstring, 189 bit Forward = 1> { 190// ST(0) = ST(0) + [mem] 191def _Fp32m : FpIf32<(outs RFP32:$dst), 192 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 193 [!if(Forward, 194 (set RFP32:$dst, 195 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 196 (set RFP32:$dst, 197 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 198def _Fp64m : FpIf64<(outs RFP64:$dst), 199 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 200 [!if(Forward, 201 (set RFP64:$dst, 202 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 203 (set RFP64:$dst, 204 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 205def _Fp64m32: FpIf64<(outs RFP64:$dst), 206 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 207 [!if(Forward, 208 (set RFP64:$dst, 209 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 210 (set RFP64:$dst, 211 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 212def _Fp80m32: FpI_<(outs RFP80:$dst), 213 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 214 [!if(Forward, 215 (set RFP80:$dst, 216 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 217 (set RFP80:$dst, 218 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 219def _Fp80m64: FpI_<(outs RFP80:$dst), 220 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 221 [!if(Forward, 222 (set RFP80:$dst, 223 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 224 (set RFP80:$dst, 225 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 226let mayLoad = 1 in 227def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 228 !strconcat("f", asmstring, "{s}\t$src")>; 229let mayLoad = 1 in 230def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 231 !strconcat("f", asmstring, "{l}\t$src")>; 232// ST(0) = ST(0) + [memint] 233def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 234 OneArgFPRW, 235 [!if(Forward, 236 (set RFP32:$dst, 237 (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 238 (set RFP32:$dst, 239 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 240def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 241 OneArgFPRW, 242 [!if(Forward, 243 (set RFP32:$dst, 244 (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 245 (set RFP32:$dst, 246 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 247def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 248 OneArgFPRW, 249 [!if(Forward, 250 (set RFP64:$dst, 251 (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 252 (set RFP64:$dst, 253 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 254def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 255 OneArgFPRW, 256 [!if(Forward, 257 (set RFP64:$dst, 258 (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 259 (set RFP64:$dst, 260 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 261def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 262 OneArgFPRW, 263 [!if(Forward, 264 (set RFP80:$dst, 265 (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 266 (set RFP80:$dst, 267 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 268def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 269 OneArgFPRW, 270 [!if(Forward, 271 (set RFP80:$dst, 272 (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 273 (set RFP80:$dst, 274 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 275let mayLoad = 1 in 276def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 277 !strconcat("fi", asmstring, "{s}\t$src")>; 278let mayLoad = 1 in 279def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 280 !strconcat("fi", asmstring, "{l}\t$src")>; 281} 282 283let Uses = [FPCW], mayRaiseFPException = 1 in { 284// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 285// resources. 286let hasNoSchedulingInfo = 1 in { 287defm ADD : FPBinary_rr<any_fadd>; 288defm SUB : FPBinary_rr<any_fsub>; 289defm MUL : FPBinary_rr<any_fmul>; 290defm DIV : FPBinary_rr<any_fdiv>; 291} 292 293// Sets the scheduling resources for the actual NAME#_F<size>m definitions. 294let SchedRW = [WriteFAddLd] in { 295defm ADD : FPBinary<any_fadd, MRM0m, "add">; 296defm SUB : FPBinary<any_fsub, MRM4m, "sub">; 297defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>; 298} 299 300let SchedRW = [WriteFMulLd] in { 301defm MUL : FPBinary<any_fmul, MRM1m, "mul">; 302} 303 304let SchedRW = [WriteFDivLd] in { 305defm DIV : FPBinary<any_fdiv, MRM6m, "div">; 306defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>; 307} 308} // Uses = [FPCW], mayRaiseFPException = 1 309 310class FPST0rInst<Format fp, string asm> 311 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 312class FPrST0Inst<Format fp, string asm> 313 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 314class FPrST0PInst<Format fp, string asm> 315 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 316 317// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 318// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 319// we have to put some 'r's in and take them out of weird places. 320let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in { 321def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 322def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 323def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 324def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 325def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 326def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 327def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 328def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 329def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 330} // SchedRW 331let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in { 332def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 333def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 334} // SchedRW 335let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in { 336def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 337def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 338def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 339} // SchedRW 340let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in { 341def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 342def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 343def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 344def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 345def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 346def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 347} // SchedRW 348 349// Unary operations. 350multiclass FPUnary<SDPatternOperator OpNode, Format fp, string asmstring> { 351def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 352 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 353def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 354 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 355def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 356 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 357def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 358} 359 360let SchedRW = [WriteFSign] in { 361defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 362defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 363} 364 365let Uses = [FPCW], mayRaiseFPException = 1 in { 366let SchedRW = [WriteFSqrt80] in 367defm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">; 368 369let SchedRW = [WriteFCom] in { 370let hasSideEffects = 0 in { 371def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 372def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 373def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 374} // hasSideEffects 375 376def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 377} // SchedRW 378} // Uses = [FPCW], mayRaiseFPException = 1 379 380// Versions of FP instructions that take a single memory operand. Added for the 381// disassembler; remove as they are included with patterns elsewhere. 382let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1, 383 mayLoad = 1 in { 384def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 385def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 386 387def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 388def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 389 390def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 391def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 392 393def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 394def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 395} // SchedRW 396 397let SchedRW = [WriteMicrocoded] in { 398let Defs = [FPSW, FPCW], mayLoad = 1 in { 399def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins anymem:$src), "fldenv\t$src">; 400def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins anymem:$src), "frstor\t$src">; 401} 402 403let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW], mayStore = 1 in { 404def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins anymem:$dst), "fnstenv\t$dst">; 405def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins anymem:$dst), "fnsave\t$dst">; 406} 407 408let Uses = [FPSW], mayStore = 1 in 409def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 410 411let mayLoad = 1 in 412def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 413let Uses = [FPCW] ,mayRaiseFPException = 1, mayStore = 1 in 414def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 415} // SchedRW 416 417// Floating point cmovs. 418class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 419 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 420class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 421 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 422 423multiclass FPCMov<PatLeaf cc> { 424 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 425 CondMovFP, 426 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 427 cc, EFLAGS))]>; 428 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 429 CondMovFP, 430 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 431 cc, EFLAGS))]>; 432 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 433 CondMovFP, 434 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 435 cc, EFLAGS))]>, 436 Requires<[HasCMov]>; 437} 438 439let SchedRW = [WriteFCMOV] in { 440let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 441defm CMOVB : FPCMov<X86_COND_B>; 442defm CMOVBE : FPCMov<X86_COND_BE>; 443defm CMOVE : FPCMov<X86_COND_E>; 444defm CMOVP : FPCMov<X86_COND_P>; 445defm CMOVNB : FPCMov<X86_COND_AE>; 446defm CMOVNBE: FPCMov<X86_COND_A>; 447defm CMOVNE : FPCMov<X86_COND_NE>; 448defm CMOVNP : FPCMov<X86_COND_NP>; 449} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 450 451let Predicates = [HasCMov] in { 452// These are not factored because there's no clean way to pass DA/DB. 453def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 454 "fcmovb\t{$op, %st|st, $op}">; 455def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 456 "fcmovbe\t{$op, %st|st, $op}">; 457def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 458 "fcmove\t{$op, %st|st, $op}">; 459def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 460 "fcmovu\t{$op, %st|st, $op}">; 461def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 462 "fcmovnb\t{$op, %st|st, $op}">; 463def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 464 "fcmovnbe\t{$op, %st|st, $op}">; 465def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 466 "fcmovne\t{$op, %st|st, $op}">; 467def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 468 "fcmovnu\t{$op, %st|st, $op}">; 469} // Predicates = [HasCMov] 470} // SchedRW 471 472let mayRaiseFPException = 1 in { 473// Floating point loads & stores. 474let SchedRW = [WriteLoad], Uses = [FPCW] in { 475let canFoldAsLoad = 1 in { 476def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 477 [(set RFP32:$dst, (loadf32 addr:$src))]>; 478def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 479 [(set RFP64:$dst, (loadf64 addr:$src))]>; 480def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 481 [(set RFP80:$dst, (loadf80 addr:$src))]>; 482} // canFoldAsLoad 483def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 484 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 485def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 486 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 487def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 488 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 489let mayRaiseFPException = 0 in { 490def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 491 [(set RFP32:$dst, (X86fild16 addr:$src))]>; 492def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 493 [(set RFP32:$dst, (X86fild32 addr:$src))]>; 494def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 495 [(set RFP32:$dst, (X86fild64 addr:$src))]>; 496def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 497 [(set RFP64:$dst, (X86fild16 addr:$src))]>; 498def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 499 [(set RFP64:$dst, (X86fild32 addr:$src))]>; 500def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 501 [(set RFP64:$dst, (X86fild64 addr:$src))]>; 502def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 503 [(set RFP80:$dst, (X86fild16 addr:$src))]>; 504def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 505 [(set RFP80:$dst, (X86fild32 addr:$src))]>; 506def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 507 [(set RFP80:$dst, (X86fild64 addr:$src))]>; 508} // mayRaiseFPException = 0 509} // SchedRW 510 511let SchedRW = [WriteStore], Uses = [FPCW] in { 512def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 513 [(store RFP32:$src, addr:$op)]>; 514def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 515 [(truncstoref32 RFP64:$src, addr:$op)]>; 516def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 517 [(store RFP64:$src, addr:$op)]>; 518def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 519 [(truncstoref32 RFP80:$src, addr:$op)]>; 520def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 521 [(truncstoref64 RFP80:$src, addr:$op)]>; 522// FST does not support 80-bit memory target; FSTP must be used. 523 524let mayStore = 1, hasSideEffects = 0 in { 525def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 526def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 527def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 528def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 529def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 530} // mayStore 531 532def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 533 [(store RFP80:$src, addr:$op)]>; 534 535let mayStore = 1, hasSideEffects = 0 in { 536def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 537def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 538 [(X86fist32 RFP32:$src, addr:$op)]>; 539def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 540 [(X86fist64 RFP32:$src, addr:$op)]>; 541def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 542def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 543 [(X86fist32 RFP64:$src, addr:$op)]>; 544def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 545 [(X86fist64 RFP64:$src, addr:$op)]>; 546def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 547def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 548 [(X86fist32 RFP80:$src, addr:$op)]>; 549def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 550 [(X86fist64 RFP80:$src, addr:$op)]>; 551} // mayStore 552} // SchedRW, Uses = [FPCW] 553 554let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 555def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 556def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 557def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 558let mayRaiseFPException = 0 in { 559def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 560def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 561def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 562} 563} 564let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 565def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 566def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 567def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 568def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 569def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 570def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 571def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 572def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 573def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 574def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 575} 576 577// FISTTP requires SSE3 even though it's a FPStack op. 578let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 579def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 580 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 581def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 582 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 583def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 584 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 585def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 586 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 587def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 588 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 589def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 590 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 591def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 592 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 593def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 594 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 595def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 596 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 597} // Predicates = [HasSSE3] 598 599let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 600def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 601def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 602def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 603} 604 605// FP Stack manipulation instructions. 606let SchedRW = [WriteMove], Uses = [FPCW] in { 607def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 608def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 609def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 610let mayRaiseFPException = 0 in 611def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 612} 613 614// Floating point constant loads. 615let SchedRW = [WriteZero], Uses = [FPCW] in { 616def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 617 [(set RFP32:$dst, fpimm0)]>; 618def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 619 [(set RFP32:$dst, fpimm1)]>; 620def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 621 [(set RFP64:$dst, fpimm0)]>; 622def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 623 [(set RFP64:$dst, fpimm1)]>; 624def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 625 [(set RFP80:$dst, fpimm0)]>; 626def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 627 [(set RFP80:$dst, fpimm1)]>; 628} 629 630let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in 631def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 632 633let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in 634def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 635 636let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in { 637def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 638def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 639def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 640def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 641def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 642} // SchedRW 643 644// Floating point compares. 645let SchedRW = [WriteFCom], Uses = [FPCW], hasSideEffects = 0 in { 646def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 647def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 648def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 649def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 650def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 651def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 652} // SchedRW 653} // mayRaiseFPException = 1 654 655let SchedRW = [WriteFCom], mayRaiseFPException = 1 in { 656// CC = ST(0) cmp ST(i) 657let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 658def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 659 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>, 660 Requires<[FPStackf32, HasCMov]>; 661def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 662 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>, 663 Requires<[FPStackf64, HasCMov]>; 664def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 665 [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>, 666 Requires<[HasCMov]>; 667def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 668 [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>, 669 Requires<[FPStackf32, HasCMov]>; 670def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 671 [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>, 672 Requires<[FPStackf64, HasCMov]>; 673def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 674 [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>, 675 Requires<[HasCMov]>; 676} 677 678let Uses = [ST0, FPCW] in { 679def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 680 (outs), (ins RSTi:$reg), "fucom\t$reg">; 681def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 682 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 683def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 684 (outs), (ins), "fucompp">; 685} 686 687let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 688def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 689 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 690def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 691 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 692 693def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 694 "fcomi\t{$reg, %st|st, $reg}">; 695def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 696 "fcompi\t{$reg, %st|st, $reg}">; 697} 698} // SchedRW 699 700// Floating point flag ops. 701let SchedRW = [WriteALU] in { 702let Defs = [AX, FPSW], Uses = [FPSW], hasSideEffects = 0 in 703def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 704 (outs), (ins), "fnstsw\t{%ax|ax}", []>; 705let Defs = [FPSW], Uses = [FPCW] in 706def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 707 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 708 [(X86fp_cwd_get16 addr:$dst)]>; 709} // SchedRW 710let Defs = [FPSW,FPCW], mayLoad = 1 in 711def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 712 (outs), (ins i16mem:$dst), "fldcw\t$dst", 713 [(X86fp_cwd_set16 addr:$dst)]>, 714 Sched<[WriteLoad]>; 715 716// FPU control instructions 717let SchedRW = [WriteMicrocoded] in { 718def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 719def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 720 721let Defs = [FPSW, FPCW] in 722def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 723// Clear exceptions 724let Defs = [FPSW] in 725def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 726} // SchedRW 727 728// Operand-less floating-point instructions for the disassembler. 729let Defs = [FPSW] in 730def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 731 732let SchedRW = [WriteMicrocoded] in { 733let Defs = [FPSW] in { 734def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 735def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 736def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 737def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 738let Uses = [FPCW], mayRaiseFPException = 1 in { 739def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 740def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 741def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 742def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 743def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 744def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 745def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 746def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 747def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 748def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 749def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 750def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 751def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 752def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 753} // Uses = [FPCW], mayRaiseFPException = 1 754} // Defs = [FPSW] 755 756let Uses = [FPSW, FPCW] in { 757def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 758 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, PS, 759 Requires<[HasFXSR]>; 760def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 761 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 762 PS, Requires<[HasFXSR, In64BitMode]>; 763} // Uses = [FPSW, FPCW] 764 765let Defs = [FPSW, FPCW] in { 766def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 767 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 768 PS, Requires<[HasFXSR]>; 769def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 770 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 771 PS, Requires<[HasFXSR, In64BitMode]>; 772} // Defs = [FPSW, FPCW] 773} // SchedRW 774 775//===----------------------------------------------------------------------===// 776// Non-Instruction Patterns 777//===----------------------------------------------------------------------===// 778 779// Required for RET of f32 / f64 / f80 values. 780def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 781def : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>; 782def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 783def : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>; 784def : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>; 785def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 786 787// Required for CALL which return f32 / f64 / f80 values. 788def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 789def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 790def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 791def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 792def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 793def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 794 795// Floating point constant -0.0 and -1.0 796def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 797def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 798def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 799def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 800def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 801def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 802 803// FP extensions map onto simple pseudo-value conversions if they are to/from 804// the FP stack. 805def : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 806 Requires<[FPStackf32]>; 807def : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 808 Requires<[FPStackf32]>; 809def : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 810 Requires<[FPStackf64]>; 811 812// FP truncations map onto simple pseudo-value conversions if they are to/from 813// the FP stack. We have validated that only value-preserving truncations make 814// it through isel. 815def : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 816 Requires<[FPStackf32]>; 817def : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 818 Requires<[FPStackf32]>; 819def : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 820 Requires<[FPStackf64]>; 821