106f32e7eSjoerg//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 206f32e7eSjoerg// 306f32e7eSjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406f32e7eSjoerg// See https://llvm.org/LICENSE.txt for license information. 506f32e7eSjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606f32e7eSjoerg// 706f32e7eSjoerg//===----------------------------------------------------------------------===// 806f32e7eSjoerg// 906f32e7eSjoerg// This file describes the X86 x87 FPU instruction set, defining the 1006f32e7eSjoerg// instructions, and properties of the instructions which are needed for code 1106f32e7eSjoerg// generation, machine code emission, and analysis. 1206f32e7eSjoerg// 1306f32e7eSjoerg//===----------------------------------------------------------------------===// 1406f32e7eSjoerg 1506f32e7eSjoerg//===----------------------------------------------------------------------===// 1606f32e7eSjoerg// FPStack specific DAG Nodes. 1706f32e7eSjoerg//===----------------------------------------------------------------------===// 1806f32e7eSjoerg 1906f32e7eSjoergdef SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 2006f32e7eSjoerg SDTCisPtrTy<1>]>; 2106f32e7eSjoergdef SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 2206f32e7eSjoerg SDTCisPtrTy<1>]>; 2306f32e7eSjoergdef SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 2406f32e7eSjoergdef SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 2506f32e7eSjoerg 2606f32e7eSjoergdef SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 27*da58b97aSjoergdef SDTX86CwdLoad : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 2806f32e7eSjoerg 2906f32e7eSjoergdef X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 3006f32e7eSjoerg [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 3106f32e7eSjoergdef X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 32*da58b97aSjoerg [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 3306f32e7eSjoergdef X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 3406f32e7eSjoerg [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 3506f32e7eSjoergdef X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 36*da58b97aSjoerg [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 3706f32e7eSjoergdef X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 3806f32e7eSjoerg [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 3906f32e7eSjoergdef X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 4006f32e7eSjoerg [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 4106f32e7eSjoerg SDNPMemOperand]>; 42*da58b97aSjoergdef X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m", SDTX86CwdLoad, 43*da58b97aSjoerg [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 44*da58b97aSjoerg SDNPMemOperand]>; 4506f32e7eSjoerg 4606f32e7eSjoergdef X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 4706f32e7eSjoerg (X86fst node:$val, node:$ptr), [{ 4806f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 4906f32e7eSjoerg}]>; 5006f32e7eSjoergdef X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 5106f32e7eSjoerg (X86fst node:$val, node:$ptr), [{ 5206f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 5306f32e7eSjoerg}]>; 5406f32e7eSjoergdef X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 5506f32e7eSjoerg (X86fst node:$val, node:$ptr), [{ 5606f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 5706f32e7eSjoerg}]>; 5806f32e7eSjoerg 5906f32e7eSjoergdef X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 6006f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 6106f32e7eSjoerg}]>; 6206f32e7eSjoergdef X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 6306f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 6406f32e7eSjoerg}]>; 6506f32e7eSjoergdef X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 6606f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 6706f32e7eSjoerg}]>; 6806f32e7eSjoerg 6906f32e7eSjoergdef X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 7006f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 7106f32e7eSjoerg}]>; 7206f32e7eSjoergdef X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 7306f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 7406f32e7eSjoerg}]>; 7506f32e7eSjoergdef X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 7606f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 7706f32e7eSjoerg}]>; 7806f32e7eSjoerg 79*da58b97aSjoergdef X86fist32 : PatFrag<(ops node:$val, node:$ptr), 80*da58b97aSjoerg (X86fist node:$val, node:$ptr), [{ 81*da58b97aSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 8206f32e7eSjoerg}]>; 8306f32e7eSjoerg 8406f32e7eSjoergdef X86fist64 : PatFrag<(ops node:$val, node:$ptr), 8506f32e7eSjoerg (X86fist node:$val, node:$ptr), [{ 8606f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 8706f32e7eSjoerg}]>; 8806f32e7eSjoerg 8906f32e7eSjoergdef X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 9006f32e7eSjoerg (X86fp_to_mem node:$val, node:$ptr), [{ 9106f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 9206f32e7eSjoerg}]>; 9306f32e7eSjoergdef X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 9406f32e7eSjoerg (X86fp_to_mem node:$val, node:$ptr), [{ 9506f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 9606f32e7eSjoerg}]>; 9706f32e7eSjoergdef X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 9806f32e7eSjoerg (X86fp_to_mem node:$val, node:$ptr), [{ 9906f32e7eSjoerg return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 10006f32e7eSjoerg}]>; 10106f32e7eSjoerg 10206f32e7eSjoerg//===----------------------------------------------------------------------===// 10306f32e7eSjoerg// FPStack pattern fragments 10406f32e7eSjoerg//===----------------------------------------------------------------------===// 10506f32e7eSjoerg 10606f32e7eSjoergdef fpimm0 : FPImmLeaf<fAny, [{ 10706f32e7eSjoerg return Imm.isExactlyValue(+0.0); 10806f32e7eSjoerg}]>; 10906f32e7eSjoerg 11006f32e7eSjoergdef fpimmneg0 : FPImmLeaf<fAny, [{ 11106f32e7eSjoerg return Imm.isExactlyValue(-0.0); 11206f32e7eSjoerg}]>; 11306f32e7eSjoerg 11406f32e7eSjoergdef fpimm1 : FPImmLeaf<fAny, [{ 11506f32e7eSjoerg return Imm.isExactlyValue(+1.0); 11606f32e7eSjoerg}]>; 11706f32e7eSjoerg 11806f32e7eSjoergdef fpimmneg1 : FPImmLeaf<fAny, [{ 11906f32e7eSjoerg return Imm.isExactlyValue(-1.0); 12006f32e7eSjoerg}]>; 12106f32e7eSjoerg 12206f32e7eSjoerg// Some 'special' instructions - expanded after instruction selection. 12306f32e7eSjoerg// Clobbers EFLAGS due to OR instruction used internally. 12406f32e7eSjoerg// FIXME: Can we model this in SelectionDAG? 12506f32e7eSjoerglet usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 12606f32e7eSjoerg def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 12706f32e7eSjoerg [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 12806f32e7eSjoerg def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 12906f32e7eSjoerg [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 13006f32e7eSjoerg def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 13106f32e7eSjoerg [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 13206f32e7eSjoerg def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 13306f32e7eSjoerg [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 13406f32e7eSjoerg def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 13506f32e7eSjoerg [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 13606f32e7eSjoerg def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 13706f32e7eSjoerg [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 13806f32e7eSjoerg def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 13906f32e7eSjoerg [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 14006f32e7eSjoerg def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 14106f32e7eSjoerg [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 14206f32e7eSjoerg def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 14306f32e7eSjoerg [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 14406f32e7eSjoerg} 14506f32e7eSjoerg 14606f32e7eSjoerg// All FP Stack operations are represented with four instructions here. The 14706f32e7eSjoerg// first three instructions, generated by the instruction selector, use "RFP32" 14806f32e7eSjoerg// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 14906f32e7eSjoerg// 64-bit or 80-bit floating point values. These sizes apply to the values, 15006f32e7eSjoerg// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 15106f32e7eSjoerg// copied to each other without losing information. These instructions are all 15206f32e7eSjoerg// pseudo instructions and use the "_Fp" suffix. 15306f32e7eSjoerg// In some cases there are additional variants with a mixture of different 15406f32e7eSjoerg// register sizes. 15506f32e7eSjoerg// The second instruction is defined with FPI, which is the actual instruction 15606f32e7eSjoerg// emitted by the assembler. These use "RST" registers, although frequently 15706f32e7eSjoerg// the actual register(s) used are implicit. These are always 80 bits. 15806f32e7eSjoerg// The FP stackifier pass converts one to the other after register allocation 15906f32e7eSjoerg// occurs. 16006f32e7eSjoerg// 16106f32e7eSjoerg// Note that the FpI instruction should have instruction selection info (e.g. 16206f32e7eSjoerg// a pattern) and the FPI instruction should have emission info (e.g. opcode 16306f32e7eSjoerg// encoding and asm printing info). 16406f32e7eSjoerg 16506f32e7eSjoerg// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 16606f32e7eSjoerg// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 16706f32e7eSjoerg// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 16806f32e7eSjoerg// f80 instructions cannot use SSE and use neither of these. 16906f32e7eSjoergclass FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 17006f32e7eSjoerg FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 17106f32e7eSjoergclass FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 17206f32e7eSjoerg FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 17306f32e7eSjoerg 17406f32e7eSjoerg// Factoring for arithmetic. 175*da58b97aSjoergmulticlass FPBinary_rr<SDPatternOperator OpNode> { 17606f32e7eSjoerg// Register op register -> register 17706f32e7eSjoerg// These are separated out because they have no reversed form. 17806f32e7eSjoergdef _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 17906f32e7eSjoerg [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 18006f32e7eSjoergdef _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 18106f32e7eSjoerg [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 18206f32e7eSjoergdef _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 18306f32e7eSjoerg [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 18406f32e7eSjoerg} 18506f32e7eSjoerg// The FopST0 series are not included here because of the irregularities 18606f32e7eSjoerg// in where the 'r' goes in assembly output. 18706f32e7eSjoerg// These instructions cannot address 80-bit memory. 188*da58b97aSjoergmulticlass FPBinary<SDPatternOperator OpNode, Format fp, string asmstring, 18906f32e7eSjoerg bit Forward = 1> { 19006f32e7eSjoerg// ST(0) = ST(0) + [mem] 19106f32e7eSjoergdef _Fp32m : FpIf32<(outs RFP32:$dst), 19206f32e7eSjoerg (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 19306f32e7eSjoerg [!if(Forward, 19406f32e7eSjoerg (set RFP32:$dst, 19506f32e7eSjoerg (OpNode RFP32:$src1, (loadf32 addr:$src2))), 19606f32e7eSjoerg (set RFP32:$dst, 19706f32e7eSjoerg (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 19806f32e7eSjoergdef _Fp64m : FpIf64<(outs RFP64:$dst), 19906f32e7eSjoerg (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 20006f32e7eSjoerg [!if(Forward, 20106f32e7eSjoerg (set RFP64:$dst, 20206f32e7eSjoerg (OpNode RFP64:$src1, (loadf64 addr:$src2))), 20306f32e7eSjoerg (set RFP64:$dst, 20406f32e7eSjoerg (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 20506f32e7eSjoergdef _Fp64m32: FpIf64<(outs RFP64:$dst), 20606f32e7eSjoerg (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 20706f32e7eSjoerg [!if(Forward, 20806f32e7eSjoerg (set RFP64:$dst, 20906f32e7eSjoerg (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 21006f32e7eSjoerg (set RFP64:$dst, 21106f32e7eSjoerg (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 21206f32e7eSjoergdef _Fp80m32: FpI_<(outs RFP80:$dst), 21306f32e7eSjoerg (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 21406f32e7eSjoerg [!if(Forward, 21506f32e7eSjoerg (set RFP80:$dst, 21606f32e7eSjoerg (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 21706f32e7eSjoerg (set RFP80:$dst, 21806f32e7eSjoerg (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 21906f32e7eSjoergdef _Fp80m64: FpI_<(outs RFP80:$dst), 22006f32e7eSjoerg (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 22106f32e7eSjoerg [!if(Forward, 22206f32e7eSjoerg (set RFP80:$dst, 22306f32e7eSjoerg (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 22406f32e7eSjoerg (set RFP80:$dst, 22506f32e7eSjoerg (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 22606f32e7eSjoerglet mayLoad = 1 in 22706f32e7eSjoergdef _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 22806f32e7eSjoerg !strconcat("f", asmstring, "{s}\t$src")>; 22906f32e7eSjoerglet mayLoad = 1 in 23006f32e7eSjoergdef _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 23106f32e7eSjoerg !strconcat("f", asmstring, "{l}\t$src")>; 23206f32e7eSjoerg// ST(0) = ST(0) + [memint] 23306f32e7eSjoergdef _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 23406f32e7eSjoerg OneArgFPRW, 23506f32e7eSjoerg [!if(Forward, 23606f32e7eSjoerg (set RFP32:$dst, 23706f32e7eSjoerg (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 23806f32e7eSjoerg (set RFP32:$dst, 23906f32e7eSjoerg (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 24006f32e7eSjoergdef _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 24106f32e7eSjoerg OneArgFPRW, 24206f32e7eSjoerg [!if(Forward, 24306f32e7eSjoerg (set RFP32:$dst, 24406f32e7eSjoerg (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 24506f32e7eSjoerg (set RFP32:$dst, 24606f32e7eSjoerg (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 24706f32e7eSjoergdef _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 24806f32e7eSjoerg OneArgFPRW, 24906f32e7eSjoerg [!if(Forward, 25006f32e7eSjoerg (set RFP64:$dst, 25106f32e7eSjoerg (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 25206f32e7eSjoerg (set RFP64:$dst, 25306f32e7eSjoerg (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 25406f32e7eSjoergdef _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 25506f32e7eSjoerg OneArgFPRW, 25606f32e7eSjoerg [!if(Forward, 25706f32e7eSjoerg (set RFP64:$dst, 25806f32e7eSjoerg (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 25906f32e7eSjoerg (set RFP64:$dst, 26006f32e7eSjoerg (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 26106f32e7eSjoergdef _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 26206f32e7eSjoerg OneArgFPRW, 26306f32e7eSjoerg [!if(Forward, 26406f32e7eSjoerg (set RFP80:$dst, 26506f32e7eSjoerg (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 26606f32e7eSjoerg (set RFP80:$dst, 26706f32e7eSjoerg (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 26806f32e7eSjoergdef _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 26906f32e7eSjoerg OneArgFPRW, 27006f32e7eSjoerg [!if(Forward, 27106f32e7eSjoerg (set RFP80:$dst, 27206f32e7eSjoerg (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 27306f32e7eSjoerg (set RFP80:$dst, 27406f32e7eSjoerg (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 27506f32e7eSjoerglet mayLoad = 1 in 27606f32e7eSjoergdef _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 27706f32e7eSjoerg !strconcat("fi", asmstring, "{s}\t$src")>; 27806f32e7eSjoerglet mayLoad = 1 in 27906f32e7eSjoergdef _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 28006f32e7eSjoerg !strconcat("fi", asmstring, "{l}\t$src")>; 28106f32e7eSjoerg} 28206f32e7eSjoerg 283*da58b97aSjoerglet Uses = [FPCW], mayRaiseFPException = 1 in { 28406f32e7eSjoerg// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 28506f32e7eSjoerg// resources. 28606f32e7eSjoerglet hasNoSchedulingInfo = 1 in { 287*da58b97aSjoergdefm ADD : FPBinary_rr<any_fadd>; 288*da58b97aSjoergdefm SUB : FPBinary_rr<any_fsub>; 289*da58b97aSjoergdefm MUL : FPBinary_rr<any_fmul>; 290*da58b97aSjoergdefm DIV : FPBinary_rr<any_fdiv>; 29106f32e7eSjoerg} 29206f32e7eSjoerg 293*da58b97aSjoerg// Sets the scheduling resources for the actual NAME#_F<size>m definitions. 29406f32e7eSjoerglet SchedRW = [WriteFAddLd] in { 295*da58b97aSjoergdefm ADD : FPBinary<any_fadd, MRM0m, "add">; 296*da58b97aSjoergdefm SUB : FPBinary<any_fsub, MRM4m, "sub">; 297*da58b97aSjoergdefm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>; 29806f32e7eSjoerg} 29906f32e7eSjoerg 30006f32e7eSjoerglet SchedRW = [WriteFMulLd] in { 301*da58b97aSjoergdefm MUL : FPBinary<any_fmul, MRM1m, "mul">; 30206f32e7eSjoerg} 30306f32e7eSjoerg 30406f32e7eSjoerglet SchedRW = [WriteFDivLd] in { 305*da58b97aSjoergdefm DIV : FPBinary<any_fdiv, MRM6m, "div">; 306*da58b97aSjoergdefm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>; 30706f32e7eSjoerg} 308*da58b97aSjoerg} // Uses = [FPCW], mayRaiseFPException = 1 30906f32e7eSjoerg 31006f32e7eSjoergclass FPST0rInst<Format fp, string asm> 31106f32e7eSjoerg : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 31206f32e7eSjoergclass FPrST0Inst<Format fp, string asm> 31306f32e7eSjoerg : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 31406f32e7eSjoergclass FPrST0PInst<Format fp, string asm> 31506f32e7eSjoerg : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 31606f32e7eSjoerg 31706f32e7eSjoerg// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 31806f32e7eSjoerg// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 31906f32e7eSjoerg// we have to put some 'r's in and take them out of weird places. 320*da58b97aSjoerglet SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in { 32106f32e7eSjoergdef ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 32206f32e7eSjoergdef ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 32306f32e7eSjoergdef ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 32406f32e7eSjoergdef SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 32506f32e7eSjoergdef SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 32606f32e7eSjoergdef SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 32706f32e7eSjoergdef SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 32806f32e7eSjoergdef SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 32906f32e7eSjoergdef SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 33006f32e7eSjoerg} // SchedRW 331*da58b97aSjoerglet SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in { 33206f32e7eSjoergdef COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 33306f32e7eSjoergdef COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 33406f32e7eSjoerg} // SchedRW 335*da58b97aSjoerglet SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in { 33606f32e7eSjoergdef MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 33706f32e7eSjoergdef MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 33806f32e7eSjoergdef MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 33906f32e7eSjoerg} // SchedRW 340*da58b97aSjoerglet SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in { 34106f32e7eSjoergdef DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 34206f32e7eSjoergdef DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 34306f32e7eSjoergdef DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 34406f32e7eSjoergdef DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 34506f32e7eSjoergdef DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 34606f32e7eSjoergdef DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 34706f32e7eSjoerg} // SchedRW 34806f32e7eSjoerg 34906f32e7eSjoerg// Unary operations. 350*da58b97aSjoergmulticlass FPUnary<SDPatternOperator OpNode, Format fp, string asmstring> { 35106f32e7eSjoergdef _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 35206f32e7eSjoerg [(set RFP32:$dst, (OpNode RFP32:$src))]>; 35306f32e7eSjoergdef _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 35406f32e7eSjoerg [(set RFP64:$dst, (OpNode RFP64:$src))]>; 35506f32e7eSjoergdef _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 35606f32e7eSjoerg [(set RFP80:$dst, (OpNode RFP80:$src))]>; 35706f32e7eSjoergdef _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 35806f32e7eSjoerg} 35906f32e7eSjoerg 36006f32e7eSjoerglet SchedRW = [WriteFSign] in { 36106f32e7eSjoergdefm CHS : FPUnary<fneg, MRM_E0, "fchs">; 36206f32e7eSjoergdefm ABS : FPUnary<fabs, MRM_E1, "fabs">; 36306f32e7eSjoerg} 36406f32e7eSjoerg 365*da58b97aSjoerglet Uses = [FPCW], mayRaiseFPException = 1 in { 36606f32e7eSjoerglet SchedRW = [WriteFSqrt80] in 367*da58b97aSjoergdefm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">; 36806f32e7eSjoerg 36906f32e7eSjoerglet SchedRW = [WriteFCom] in { 37006f32e7eSjoerglet hasSideEffects = 0 in { 37106f32e7eSjoergdef TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 37206f32e7eSjoergdef TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 37306f32e7eSjoergdef TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 37406f32e7eSjoerg} // hasSideEffects 37506f32e7eSjoerg 37606f32e7eSjoergdef TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 37706f32e7eSjoerg} // SchedRW 378*da58b97aSjoerg} // Uses = [FPCW], mayRaiseFPException = 1 37906f32e7eSjoerg 38006f32e7eSjoerg// Versions of FP instructions that take a single memory operand. Added for the 38106f32e7eSjoerg// disassembler; remove as they are included with patterns elsewhere. 382*da58b97aSjoerglet SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1, 383*da58b97aSjoerg mayLoad = 1 in { 38406f32e7eSjoergdef FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 38506f32e7eSjoergdef FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 38606f32e7eSjoerg 38706f32e7eSjoergdef FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 38806f32e7eSjoergdef FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 38906f32e7eSjoerg 39006f32e7eSjoergdef FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 39106f32e7eSjoergdef FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 39206f32e7eSjoerg 39306f32e7eSjoergdef FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 39406f32e7eSjoergdef FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 39506f32e7eSjoerg} // SchedRW 39606f32e7eSjoerg 39706f32e7eSjoerglet SchedRW = [WriteMicrocoded] in { 398*da58b97aSjoerglet Defs = [FPSW, FPCW], mayLoad = 1 in { 399*da58b97aSjoergdef FLDENVm : FPI<0xD9, MRM4m, (outs), (ins anymem:$src), "fldenv\t$src">; 400*da58b97aSjoergdef FRSTORm : FPI<0xDD, MRM4m, (outs), (ins anymem:$src), "frstor\t$src">; 401*da58b97aSjoerg} 40206f32e7eSjoerg 403*da58b97aSjoerglet Defs = [FPSW, FPCW], Uses = [FPSW, FPCW], mayStore = 1 in { 404*da58b97aSjoergdef FSTENVm : FPI<0xD9, MRM6m, (outs), (ins anymem:$dst), "fnstenv\t$dst">; 405*da58b97aSjoergdef FSAVEm : FPI<0xDD, MRM6m, (outs), (ins anymem:$dst), "fnsave\t$dst">; 406*da58b97aSjoerg} 407*da58b97aSjoerg 408*da58b97aSjoerglet Uses = [FPSW], mayStore = 1 in 40906f32e7eSjoergdef FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 41006f32e7eSjoerg 411*da58b97aSjoerglet mayLoad = 1 in 41206f32e7eSjoergdef FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 413*da58b97aSjoerglet Uses = [FPCW] ,mayRaiseFPException = 1, mayStore = 1 in 41406f32e7eSjoergdef FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 41506f32e7eSjoerg} // SchedRW 41606f32e7eSjoerg 41706f32e7eSjoerg// Floating point cmovs. 41806f32e7eSjoergclass FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 41906f32e7eSjoerg FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 42006f32e7eSjoergclass FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 42106f32e7eSjoerg FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 42206f32e7eSjoerg 42306f32e7eSjoergmulticlass FPCMov<PatLeaf cc> { 42406f32e7eSjoerg def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 42506f32e7eSjoerg CondMovFP, 42606f32e7eSjoerg [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 42706f32e7eSjoerg cc, EFLAGS))]>; 42806f32e7eSjoerg def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 42906f32e7eSjoerg CondMovFP, 43006f32e7eSjoerg [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 43106f32e7eSjoerg cc, EFLAGS))]>; 43206f32e7eSjoerg def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 43306f32e7eSjoerg CondMovFP, 43406f32e7eSjoerg [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 43506f32e7eSjoerg cc, EFLAGS))]>, 43606f32e7eSjoerg Requires<[HasCMov]>; 43706f32e7eSjoerg} 43806f32e7eSjoerg 43906f32e7eSjoerglet SchedRW = [WriteFCMOV] in { 44006f32e7eSjoerglet Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 44106f32e7eSjoergdefm CMOVB : FPCMov<X86_COND_B>; 44206f32e7eSjoergdefm CMOVBE : FPCMov<X86_COND_BE>; 44306f32e7eSjoergdefm CMOVE : FPCMov<X86_COND_E>; 44406f32e7eSjoergdefm CMOVP : FPCMov<X86_COND_P>; 44506f32e7eSjoergdefm CMOVNB : FPCMov<X86_COND_AE>; 44606f32e7eSjoergdefm CMOVNBE: FPCMov<X86_COND_A>; 44706f32e7eSjoergdefm CMOVNE : FPCMov<X86_COND_NE>; 44806f32e7eSjoergdefm CMOVNP : FPCMov<X86_COND_NP>; 44906f32e7eSjoerg} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 45006f32e7eSjoerg 45106f32e7eSjoerglet Predicates = [HasCMov] in { 45206f32e7eSjoerg// These are not factored because there's no clean way to pass DA/DB. 45306f32e7eSjoergdef CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 45406f32e7eSjoerg "fcmovb\t{$op, %st|st, $op}">; 45506f32e7eSjoergdef CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 45606f32e7eSjoerg "fcmovbe\t{$op, %st|st, $op}">; 45706f32e7eSjoergdef CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 45806f32e7eSjoerg "fcmove\t{$op, %st|st, $op}">; 45906f32e7eSjoergdef CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 46006f32e7eSjoerg "fcmovu\t{$op, %st|st, $op}">; 46106f32e7eSjoergdef CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 46206f32e7eSjoerg "fcmovnb\t{$op, %st|st, $op}">; 46306f32e7eSjoergdef CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 46406f32e7eSjoerg "fcmovnbe\t{$op, %st|st, $op}">; 46506f32e7eSjoergdef CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 46606f32e7eSjoerg "fcmovne\t{$op, %st|st, $op}">; 46706f32e7eSjoergdef CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 46806f32e7eSjoerg "fcmovnu\t{$op, %st|st, $op}">; 46906f32e7eSjoerg} // Predicates = [HasCMov] 47006f32e7eSjoerg} // SchedRW 47106f32e7eSjoerg 472*da58b97aSjoerglet mayRaiseFPException = 1 in { 47306f32e7eSjoerg// Floating point loads & stores. 47406f32e7eSjoerglet SchedRW = [WriteLoad], Uses = [FPCW] in { 47506f32e7eSjoerglet canFoldAsLoad = 1 in { 47606f32e7eSjoergdef LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 47706f32e7eSjoerg [(set RFP32:$dst, (loadf32 addr:$src))]>; 47806f32e7eSjoergdef LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 47906f32e7eSjoerg [(set RFP64:$dst, (loadf64 addr:$src))]>; 48006f32e7eSjoergdef LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 48106f32e7eSjoerg [(set RFP80:$dst, (loadf80 addr:$src))]>; 48206f32e7eSjoerg} // canFoldAsLoad 48306f32e7eSjoergdef LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 48406f32e7eSjoerg [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 48506f32e7eSjoergdef LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 48606f32e7eSjoerg [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 48706f32e7eSjoergdef LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 48806f32e7eSjoerg [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 489*da58b97aSjoerglet mayRaiseFPException = 0 in { 49006f32e7eSjoergdef ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 49106f32e7eSjoerg [(set RFP32:$dst, (X86fild16 addr:$src))]>; 49206f32e7eSjoergdef ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 49306f32e7eSjoerg [(set RFP32:$dst, (X86fild32 addr:$src))]>; 49406f32e7eSjoergdef ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 49506f32e7eSjoerg [(set RFP32:$dst, (X86fild64 addr:$src))]>; 49606f32e7eSjoergdef ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 49706f32e7eSjoerg [(set RFP64:$dst, (X86fild16 addr:$src))]>; 49806f32e7eSjoergdef ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 49906f32e7eSjoerg [(set RFP64:$dst, (X86fild32 addr:$src))]>; 50006f32e7eSjoergdef ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 50106f32e7eSjoerg [(set RFP64:$dst, (X86fild64 addr:$src))]>; 50206f32e7eSjoergdef ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 50306f32e7eSjoerg [(set RFP80:$dst, (X86fild16 addr:$src))]>; 50406f32e7eSjoergdef ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 50506f32e7eSjoerg [(set RFP80:$dst, (X86fild32 addr:$src))]>; 50606f32e7eSjoergdef ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 50706f32e7eSjoerg [(set RFP80:$dst, (X86fild64 addr:$src))]>; 508*da58b97aSjoerg} // mayRaiseFPException = 0 50906f32e7eSjoerg} // SchedRW 51006f32e7eSjoerg 51106f32e7eSjoerglet SchedRW = [WriteStore], Uses = [FPCW] in { 51206f32e7eSjoergdef ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 51306f32e7eSjoerg [(store RFP32:$src, addr:$op)]>; 51406f32e7eSjoergdef ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 51506f32e7eSjoerg [(truncstoref32 RFP64:$src, addr:$op)]>; 51606f32e7eSjoergdef ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 51706f32e7eSjoerg [(store RFP64:$src, addr:$op)]>; 51806f32e7eSjoergdef ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 51906f32e7eSjoerg [(truncstoref32 RFP80:$src, addr:$op)]>; 52006f32e7eSjoergdef ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 52106f32e7eSjoerg [(truncstoref64 RFP80:$src, addr:$op)]>; 52206f32e7eSjoerg// FST does not support 80-bit memory target; FSTP must be used. 52306f32e7eSjoerg 52406f32e7eSjoerglet mayStore = 1, hasSideEffects = 0 in { 52506f32e7eSjoergdef ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 52606f32e7eSjoergdef ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 52706f32e7eSjoergdef ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 52806f32e7eSjoergdef ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 52906f32e7eSjoergdef ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 53006f32e7eSjoerg} // mayStore 53106f32e7eSjoerg 53206f32e7eSjoergdef ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 53306f32e7eSjoerg [(store RFP80:$src, addr:$op)]>; 53406f32e7eSjoerg 53506f32e7eSjoerglet mayStore = 1, hasSideEffects = 0 in { 53606f32e7eSjoergdef IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 537*da58b97aSjoergdef IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 538*da58b97aSjoerg [(X86fist32 RFP32:$src, addr:$op)]>; 539*da58b97aSjoergdef IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 540*da58b97aSjoerg [(X86fist64 RFP32:$src, addr:$op)]>; 54106f32e7eSjoergdef IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 542*da58b97aSjoergdef IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 543*da58b97aSjoerg [(X86fist32 RFP64:$src, addr:$op)]>; 544*da58b97aSjoergdef IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 545*da58b97aSjoerg [(X86fist64 RFP64:$src, addr:$op)]>; 54606f32e7eSjoergdef IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 547*da58b97aSjoergdef IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 548*da58b97aSjoerg [(X86fist32 RFP80:$src, addr:$op)]>; 549*da58b97aSjoergdef IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 550*da58b97aSjoerg [(X86fist64 RFP80:$src, addr:$op)]>; 55106f32e7eSjoerg} // mayStore 55206f32e7eSjoerg} // SchedRW, Uses = [FPCW] 55306f32e7eSjoerg 55406f32e7eSjoerglet mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 55506f32e7eSjoergdef LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 55606f32e7eSjoergdef LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 55706f32e7eSjoergdef LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 558*da58b97aSjoerglet mayRaiseFPException = 0 in { 55906f32e7eSjoergdef ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 56006f32e7eSjoergdef ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 56106f32e7eSjoergdef ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 56206f32e7eSjoerg} 563*da58b97aSjoerg} 56406f32e7eSjoerglet mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 56506f32e7eSjoergdef ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 56606f32e7eSjoergdef ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 56706f32e7eSjoergdef ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 56806f32e7eSjoergdef ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 56906f32e7eSjoergdef ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 57006f32e7eSjoergdef IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 57106f32e7eSjoergdef IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 57206f32e7eSjoergdef IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 57306f32e7eSjoergdef IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 57406f32e7eSjoergdef IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 57506f32e7eSjoerg} 57606f32e7eSjoerg 57706f32e7eSjoerg// FISTTP requires SSE3 even though it's a FPStack op. 57806f32e7eSjoerglet Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 57906f32e7eSjoergdef ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 58006f32e7eSjoerg [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 58106f32e7eSjoergdef ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 58206f32e7eSjoerg [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 58306f32e7eSjoergdef ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 58406f32e7eSjoerg [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 58506f32e7eSjoergdef ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 58606f32e7eSjoerg [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 58706f32e7eSjoergdef ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 58806f32e7eSjoerg [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 58906f32e7eSjoergdef ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 59006f32e7eSjoerg [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 59106f32e7eSjoergdef ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 59206f32e7eSjoerg [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 59306f32e7eSjoergdef ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 59406f32e7eSjoerg [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 59506f32e7eSjoergdef ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 59606f32e7eSjoerg [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 59706f32e7eSjoerg} // Predicates = [HasSSE3] 59806f32e7eSjoerg 59906f32e7eSjoerglet mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 60006f32e7eSjoergdef ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 60106f32e7eSjoergdef ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 60206f32e7eSjoergdef ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 60306f32e7eSjoerg} 60406f32e7eSjoerg 60506f32e7eSjoerg// FP Stack manipulation instructions. 60606f32e7eSjoerglet SchedRW = [WriteMove], Uses = [FPCW] in { 60706f32e7eSjoergdef LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 60806f32e7eSjoergdef ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 60906f32e7eSjoergdef ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 610*da58b97aSjoerglet mayRaiseFPException = 0 in 61106f32e7eSjoergdef XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 61206f32e7eSjoerg} 61306f32e7eSjoerg 61406f32e7eSjoerg// Floating point constant loads. 61506f32e7eSjoerglet SchedRW = [WriteZero], Uses = [FPCW] in { 61606f32e7eSjoergdef LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 61706f32e7eSjoerg [(set RFP32:$dst, fpimm0)]>; 61806f32e7eSjoergdef LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 61906f32e7eSjoerg [(set RFP32:$dst, fpimm1)]>; 62006f32e7eSjoergdef LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 62106f32e7eSjoerg [(set RFP64:$dst, fpimm0)]>; 62206f32e7eSjoergdef LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 62306f32e7eSjoerg [(set RFP64:$dst, fpimm1)]>; 62406f32e7eSjoergdef LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 62506f32e7eSjoerg [(set RFP80:$dst, fpimm0)]>; 62606f32e7eSjoergdef LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 62706f32e7eSjoerg [(set RFP80:$dst, fpimm1)]>; 62806f32e7eSjoerg} 62906f32e7eSjoerg 630*da58b97aSjoerglet SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in 63106f32e7eSjoergdef LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 63206f32e7eSjoerg 633*da58b97aSjoerglet SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in 63406f32e7eSjoergdef LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 63506f32e7eSjoerg 636*da58b97aSjoerglet SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in { 63706f32e7eSjoergdef FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 63806f32e7eSjoergdef FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 63906f32e7eSjoergdef FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 64006f32e7eSjoergdef FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 64106f32e7eSjoergdef FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 64206f32e7eSjoerg} // SchedRW 64306f32e7eSjoerg 64406f32e7eSjoerg// Floating point compares. 645*da58b97aSjoerglet SchedRW = [WriteFCom], Uses = [FPCW], hasSideEffects = 0 in { 646*da58b97aSjoergdef UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 647*da58b97aSjoergdef UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 648*da58b97aSjoergdef UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 649*da58b97aSjoergdef COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 650*da58b97aSjoergdef COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 651*da58b97aSjoergdef COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 65206f32e7eSjoerg} // SchedRW 653*da58b97aSjoerg} // mayRaiseFPException = 1 65406f32e7eSjoerg 655*da58b97aSjoerglet SchedRW = [WriteFCom], mayRaiseFPException = 1 in { 65606f32e7eSjoerg// CC = ST(0) cmp ST(i) 65706f32e7eSjoerglet Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 65806f32e7eSjoergdef UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 659*da58b97aSjoerg [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>, 66006f32e7eSjoerg Requires<[FPStackf32, HasCMov]>; 66106f32e7eSjoergdef UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 662*da58b97aSjoerg [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>, 66306f32e7eSjoerg Requires<[FPStackf64, HasCMov]>; 66406f32e7eSjoergdef UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 665*da58b97aSjoerg [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>, 666*da58b97aSjoerg Requires<[HasCMov]>; 667*da58b97aSjoergdef COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 668*da58b97aSjoerg [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>, 669*da58b97aSjoerg Requires<[FPStackf32, HasCMov]>; 670*da58b97aSjoergdef COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 671*da58b97aSjoerg [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>, 672*da58b97aSjoerg Requires<[FPStackf64, HasCMov]>; 673*da58b97aSjoergdef COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 674*da58b97aSjoerg [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>, 67506f32e7eSjoerg Requires<[HasCMov]>; 67606f32e7eSjoerg} 67706f32e7eSjoerg 678*da58b97aSjoerglet Uses = [ST0, FPCW] in { 67906f32e7eSjoergdef UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 68006f32e7eSjoerg (outs), (ins RSTi:$reg), "fucom\t$reg">; 68106f32e7eSjoergdef UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 68206f32e7eSjoerg (outs), (ins RSTi:$reg), "fucomp\t$reg">; 68306f32e7eSjoergdef UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 68406f32e7eSjoerg (outs), (ins), "fucompp">; 68506f32e7eSjoerg} 68606f32e7eSjoerg 68706f32e7eSjoerglet Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 68806f32e7eSjoergdef UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 68906f32e7eSjoerg (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 69006f32e7eSjoergdef UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 69106f32e7eSjoerg (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 69206f32e7eSjoerg 69306f32e7eSjoergdef COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 69406f32e7eSjoerg "fcomi\t{$reg, %st|st, $reg}">; 69506f32e7eSjoergdef COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 69606f32e7eSjoerg "fcompi\t{$reg, %st|st, $reg}">; 69706f32e7eSjoerg} 69806f32e7eSjoerg} // SchedRW 69906f32e7eSjoerg 70006f32e7eSjoerg// Floating point flag ops. 70106f32e7eSjoerglet SchedRW = [WriteALU] in { 702*da58b97aSjoerglet Defs = [AX, FPSW], Uses = [FPSW], hasSideEffects = 0 in 70306f32e7eSjoergdef FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 704*da58b97aSjoerg (outs), (ins), "fnstsw\t{%ax|ax}", []>; 70506f32e7eSjoerglet Defs = [FPSW], Uses = [FPCW] in 70606f32e7eSjoergdef FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 70706f32e7eSjoerg (outs), (ins i16mem:$dst), "fnstcw\t$dst", 70806f32e7eSjoerg [(X86fp_cwd_get16 addr:$dst)]>; 70906f32e7eSjoerg} // SchedRW 71006f32e7eSjoerglet Defs = [FPSW,FPCW], mayLoad = 1 in 71106f32e7eSjoergdef FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 712*da58b97aSjoerg (outs), (ins i16mem:$dst), "fldcw\t$dst", 713*da58b97aSjoerg [(X86fp_cwd_set16 addr:$dst)]>, 71406f32e7eSjoerg Sched<[WriteLoad]>; 71506f32e7eSjoerg 71606f32e7eSjoerg// FPU control instructions 71706f32e7eSjoerglet SchedRW = [WriteMicrocoded] in { 71806f32e7eSjoergdef FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 71906f32e7eSjoergdef FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 72006f32e7eSjoerg 721*da58b97aSjoerglet Defs = [FPSW, FPCW] in 722*da58b97aSjoergdef FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 72306f32e7eSjoerg// Clear exceptions 724*da58b97aSjoerglet Defs = [FPSW] in 72506f32e7eSjoergdef FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 72606f32e7eSjoerg} // SchedRW 72706f32e7eSjoerg 72806f32e7eSjoerg// Operand-less floating-point instructions for the disassembler. 729*da58b97aSjoerglet Defs = [FPSW] in 73006f32e7eSjoergdef FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 73106f32e7eSjoerg 73206f32e7eSjoerglet SchedRW = [WriteMicrocoded] in { 73306f32e7eSjoerglet Defs = [FPSW] in { 73406f32e7eSjoergdef WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 73506f32e7eSjoergdef FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 736*da58b97aSjoergdef FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 737*da58b97aSjoergdef FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 738*da58b97aSjoerglet Uses = [FPCW], mayRaiseFPException = 1 in { 73906f32e7eSjoergdef F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 74006f32e7eSjoergdef FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 74106f32e7eSjoergdef FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 74206f32e7eSjoergdef FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 74306f32e7eSjoergdef FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 74406f32e7eSjoergdef FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 74506f32e7eSjoergdef FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 74606f32e7eSjoergdef FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 747*da58b97aSjoergdef FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 748*da58b97aSjoergdef FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 74906f32e7eSjoergdef FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 75006f32e7eSjoergdef FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 75106f32e7eSjoergdef FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 75206f32e7eSjoergdef FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 753*da58b97aSjoerg} // Uses = [FPCW], mayRaiseFPException = 1 75406f32e7eSjoerg} // Defs = [FPSW] 75506f32e7eSjoerg 756*da58b97aSjoerglet Uses = [FPSW, FPCW] in { 75706f32e7eSjoergdef FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 758*da58b97aSjoerg "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, PS, 75906f32e7eSjoerg Requires<[HasFXSR]>; 76006f32e7eSjoergdef FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 76106f32e7eSjoerg "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 762*da58b97aSjoerg PS, Requires<[HasFXSR, In64BitMode]>; 763*da58b97aSjoerg} // Uses = [FPSW, FPCW] 764*da58b97aSjoerg 765*da58b97aSjoerglet Defs = [FPSW, FPCW] in { 76606f32e7eSjoergdef FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 76706f32e7eSjoerg "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 768*da58b97aSjoerg PS, Requires<[HasFXSR]>; 76906f32e7eSjoergdef FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 77006f32e7eSjoerg "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 771*da58b97aSjoerg PS, Requires<[HasFXSR, In64BitMode]>; 772*da58b97aSjoerg} // Defs = [FPSW, FPCW] 77306f32e7eSjoerg} // SchedRW 77406f32e7eSjoerg 77506f32e7eSjoerg//===----------------------------------------------------------------------===// 77606f32e7eSjoerg// Non-Instruction Patterns 77706f32e7eSjoerg//===----------------------------------------------------------------------===// 77806f32e7eSjoerg 77906f32e7eSjoerg// Required for RET of f32 / f64 / f80 values. 78006f32e7eSjoergdef : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 781*da58b97aSjoergdef : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>; 78206f32e7eSjoergdef : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 783*da58b97aSjoergdef : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>; 784*da58b97aSjoergdef : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>; 78506f32e7eSjoergdef : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 78606f32e7eSjoerg 78706f32e7eSjoerg// Required for CALL which return f32 / f64 / f80 values. 78806f32e7eSjoergdef : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 78906f32e7eSjoergdef : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 79006f32e7eSjoergdef : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 79106f32e7eSjoergdef : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 79206f32e7eSjoergdef : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 79306f32e7eSjoergdef : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 79406f32e7eSjoerg 79506f32e7eSjoerg// Floating point constant -0.0 and -1.0 79606f32e7eSjoergdef : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 79706f32e7eSjoergdef : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 79806f32e7eSjoergdef : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 79906f32e7eSjoergdef : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 80006f32e7eSjoergdef : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 80106f32e7eSjoergdef : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 80206f32e7eSjoerg 80306f32e7eSjoerg// FP extensions map onto simple pseudo-value conversions if they are to/from 80406f32e7eSjoerg// the FP stack. 805*da58b97aSjoergdef : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 80606f32e7eSjoerg Requires<[FPStackf32]>; 807*da58b97aSjoergdef : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 80806f32e7eSjoerg Requires<[FPStackf32]>; 809*da58b97aSjoergdef : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 81006f32e7eSjoerg Requires<[FPStackf64]>; 81106f32e7eSjoerg 81206f32e7eSjoerg// FP truncations map onto simple pseudo-value conversions if they are to/from 81306f32e7eSjoerg// the FP stack. We have validated that only value-preserving truncations make 81406f32e7eSjoerg// it through isel. 815*da58b97aSjoergdef : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 81606f32e7eSjoerg Requires<[FPStackf32]>; 817*da58b97aSjoergdef : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 81806f32e7eSjoerg Requires<[FPStackf32]>; 819*da58b97aSjoergdef : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 82006f32e7eSjoerg Requires<[FPStackf64]>; 821