1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the schedule class data for the Intel Atom 10// in order (Saltwell-32nm/Bonnell-45nm) processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from the "Intel 64 and IA32 Architectures 16// Optimization Reference Manual", Chapter 13, Section 4. 17 18// Atom machine model. 19def AtomModel : SchedMachineModel { 20 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 21 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 22 let LoadLatency = 3; // Expected cycles, may be overriden. 23 let HighLatency = 30;// Expected, may be overriden. 24 25 // On the Atom, the throughput for taken branches is 2 cycles. For small 26 // simple loops, expand by a small factor to hide the backedge cost. 27 let LoopMicroOpBufferSize = 10; 28 let PostRAScheduler = 1; 29 let CompleteModel = 0; 30} 31 32let SchedModel = AtomModel in { 33 34// Functional Units 35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store 36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA 38 // SIMD/FP: SIMD ALU, FP Adder 39 40// NOTE: This is for ops that can use EITHER port, not for ops that require BOTH ports. 41def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; 42 43// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 44// cycles after the memory operand. 45def : ReadAdvance<ReadAfterLd, 3>; 46def : ReadAdvance<ReadAfterVecLd, 3>; 47def : ReadAdvance<ReadAfterVecXLd, 3>; 48def : ReadAdvance<ReadAfterVecYLd, 3>; 49 50def : ReadAdvance<ReadInt2Fpu, 0>; 51 52// This multiclass defines the resource usage for variants with and without 53// folded loads. 54multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW, 55 list<ProcResourceKind> RRPorts, 56 list<ProcResourceKind> RMPorts, 57 int RRLat = 1, int RMLat = 1, 58 list<int> RRRes = [1], 59 list<int> RMRes = [1]> { 60 // Register variant. 61 def : WriteRes<SchedRW, RRPorts> { 62 let Latency = RRLat; 63 let ResourceCycles = RRRes; 64 } 65 66 // Memory variant. 67 def : WriteRes<SchedRW.Folded, RMPorts> { 68 let Latency = RMLat; 69 let ResourceCycles = RMRes; 70 } 71} 72 73// A folded store needs a cycle on Port0 for the store data. 74def : WriteRes<WriteRMW, [AtomPort0]>; 75 76//////////////////////////////////////////////////////////////////////////////// 77// Arithmetic. 78//////////////////////////////////////////////////////////////////////////////// 79 80defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>; 81defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>; 82 83defm : AtomWriteResPair<WriteIMul8, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>; 84defm : AtomWriteResPair<WriteIMul16, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 85defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 86defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 87defm : AtomWriteResPair<WriteIMul32, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 88defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 89defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 90defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 91defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>; 92defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 93defm : X86WriteResUnsupported<WriteIMulH>; 94 95defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>; 96defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>; 97defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>; 98defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>; 99defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>; 100 101defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>; 102defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 103defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 104defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 105defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 106defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 107defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 108defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 109 110defm : X86WriteResPairUnsupported<WriteCRC32>; 111 112defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>; 113defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move. 114 115def : WriteRes<WriteSETCC, [AtomPort01]>; 116def : WriteRes<WriteSETCCStore, [AtomPort01]> { 117 let Latency = 2; 118 let ResourceCycles = [2]; 119} 120def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { 121 let Latency = 2; 122 let ResourceCycles = [2]; 123} 124defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>; 125defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>; 126defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>; 127defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>; 128//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>; 129//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>; 130 131// This is for simple LEAs with one or two input operands. 132def : WriteRes<WriteLEA, [AtomPort1]>; 133 134// Bit counts. 135defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 136defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 137defm : X86WriteResPairUnsupported<WritePOPCNT>; 138defm : X86WriteResPairUnsupported<WriteLZCNT>; 139defm : X86WriteResPairUnsupported<WriteTZCNT>; 140 141// BMI1 BEXTR/BLS, BMI2 BZHI 142defm : X86WriteResPairUnsupported<WriteBEXTR>; 143defm : X86WriteResPairUnsupported<WriteBLS>; 144defm : X86WriteResPairUnsupported<WriteBZHI>; 145 146//////////////////////////////////////////////////////////////////////////////// 147// Integer shifts and rotates. 148//////////////////////////////////////////////////////////////////////////////// 149 150defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>; 151defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>; 152defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>; 153defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>; 154 155defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>; 156defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>; 157defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>; 158defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>; 159 160//////////////////////////////////////////////////////////////////////////////// 161// Loads, stores, and moves, not folded with other operations. 162//////////////////////////////////////////////////////////////////////////////// 163 164def : WriteRes<WriteLoad, [AtomPort0]>; 165def : WriteRes<WriteStore, [AtomPort0]>; 166def : WriteRes<WriteStoreNT, [AtomPort0]>; 167def : WriteRes<WriteMove, [AtomPort01]>; 168 169// Treat misc copies as a move. 170def : InstRW<[WriteMove], (instrs COPY)>; 171 172//////////////////////////////////////////////////////////////////////////////// 173// Idioms that clear a register, like xorps %xmm0, %xmm0. 174// These can often bypass execution ports completely. 175//////////////////////////////////////////////////////////////////////////////// 176 177def : WriteRes<WriteZero, []>; 178 179//////////////////////////////////////////////////////////////////////////////// 180// Branches don't produce values, so they have no latency, but they still 181// consume resources. Indirect branches can fold loads. 182//////////////////////////////////////////////////////////////////////////////// 183 184defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>; 185 186//////////////////////////////////////////////////////////////////////////////// 187// Special case scheduling classes. 188//////////////////////////////////////////////////////////////////////////////// 189 190def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; } 191def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; } 192def : WriteRes<WriteFence, [AtomPort0]>; 193 194// Nops don't have dependencies, so there's no actual latency, but we set this 195// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. 196def : WriteRes<WriteNop, [AtomPort01]>; 197 198//////////////////////////////////////////////////////////////////////////////// 199// Floating point. This covers both scalar and vector operations. 200//////////////////////////////////////////////////////////////////////////////// 201 202defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>; 203defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>; 204def : WriteRes<WriteFLoad, [AtomPort0]>; 205def : WriteRes<WriteFLoadX, [AtomPort0]>; 206defm : X86WriteResUnsupported<WriteFLoadY>; 207defm : X86WriteResUnsupported<WriteFMaskedLoad>; 208defm : X86WriteResUnsupported<WriteFMaskedLoadY>; 209 210def : WriteRes<WriteFStore, [AtomPort0]>; 211def : WriteRes<WriteFStoreX, [AtomPort0]>; 212defm : X86WriteResUnsupported<WriteFStoreY>; 213def : WriteRes<WriteFStoreNT, [AtomPort0]>; 214def : WriteRes<WriteFStoreNTX, [AtomPort0]>; 215defm : X86WriteResUnsupported<WriteFStoreNTY>; 216defm : X86WriteResUnsupported<WriteFMaskedStore32>; 217defm : X86WriteResUnsupported<WriteFMaskedStore32Y>; 218defm : X86WriteResUnsupported<WriteFMaskedStore64>; 219defm : X86WriteResUnsupported<WriteFMaskedStore64Y>; 220 221def : WriteRes<WriteFMove, [AtomPort01]>; 222def : WriteRes<WriteFMoveX, [AtomPort01]>; 223defm : X86WriteResUnsupported<WriteFMoveY>; 224 225defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>; 226 227defm : AtomWriteResPair<WriteFAdd, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 228defm : AtomWriteResPair<WriteFAddX, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 229defm : X86WriteResPairUnsupported<WriteFAddY>; 230defm : X86WriteResPairUnsupported<WriteFAddZ>; 231defm : AtomWriteResPair<WriteFAdd64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 232defm : AtomWriteResPair<WriteFAdd64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 233defm : X86WriteResPairUnsupported<WriteFAdd64Y>; 234defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 235defm : AtomWriteResPair<WriteFCmp, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 236defm : AtomWriteResPair<WriteFCmpX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 237defm : X86WriteResPairUnsupported<WriteFCmpY>; 238defm : X86WriteResPairUnsupported<WriteFCmpZ>; 239defm : AtomWriteResPair<WriteFCmp64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 240defm : AtomWriteResPair<WriteFCmp64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 241defm : X86WriteResPairUnsupported<WriteFCmp64Y>; 242defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 243defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 244defm : AtomWriteResPair<WriteFComX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 245defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [2], [2]>; 246defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 247defm : X86WriteResPairUnsupported<WriteFMulY>; 248defm : X86WriteResPairUnsupported<WriteFMulZ>; 249defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 250defm : AtomWriteResPair<WriteFMul64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9], [10,10]>; 251defm : X86WriteResPairUnsupported<WriteFMul64Y>; 252defm : X86WriteResPairUnsupported<WriteFMul64Z>; 253defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 254defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 255defm : X86WriteResPairUnsupported<WriteFRcpY>; 256defm : X86WriteResPairUnsupported<WriteFRcpZ>; 257defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 258defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 259defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 260defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 261defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 262defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 263defm : X86WriteResPairUnsupported<WriteFDivY>; 264defm : X86WriteResPairUnsupported<WriteFDivZ>; 265defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 266defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 267defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 268defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 269defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 270defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 271defm : X86WriteResPairUnsupported<WriteFSqrtY>; 272defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 273defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 274defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 275defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 276defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 277defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>; 278defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>; 279defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 280defm : X86WriteResPairUnsupported<WriteFRndY>; 281defm : X86WriteResPairUnsupported<WriteFRndZ>; 282defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>; 283defm : X86WriteResPairUnsupported<WriteFLogicY>; 284defm : X86WriteResPairUnsupported<WriteFLogicZ>; 285defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>; 286defm : X86WriteResPairUnsupported<WriteFTestY>; 287defm : X86WriteResPairUnsupported<WriteFTestZ>; 288defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>; 289defm : X86WriteResPairUnsupported<WriteFShuffleY>; 290defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 291defm : X86WriteResPairUnsupported<WriteFVarShuffle>; 292defm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 293defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 294defm : X86WriteResPairUnsupported<WriteFMA>; 295defm : X86WriteResPairUnsupported<WriteFMAX>; 296defm : X86WriteResPairUnsupported<WriteFMAY>; 297defm : X86WriteResPairUnsupported<WriteFMAZ>; 298defm : X86WriteResPairUnsupported<WriteDPPD>; 299defm : X86WriteResPairUnsupported<WriteDPPS>; 300defm : X86WriteResPairUnsupported<WriteDPPSY>; 301defm : X86WriteResPairUnsupported<WriteDPPSZ>; 302defm : X86WriteResPairUnsupported<WriteFBlend>; 303defm : X86WriteResPairUnsupported<WriteFBlendY>; 304defm : X86WriteResPairUnsupported<WriteFBlendZ>; 305defm : X86WriteResPairUnsupported<WriteFVarBlend>; 306defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 307defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 308defm : X86WriteResPairUnsupported<WriteFShuffle256>; 309defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 310 311//////////////////////////////////////////////////////////////////////////////// 312// Conversions. 313//////////////////////////////////////////////////////////////////////////////// 314 315defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 316defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 317defm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 318defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 319defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 320defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 321defm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 322defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 323 324defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 325defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 326defm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 327defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 328defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 329defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 330defm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 331defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 332 333defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 334defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 335defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 336defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 337defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 338defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 339defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 340defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 341 342defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 343defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 344defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 345defm : X86WriteResUnsupported<WriteCvtPS2PH>; 346defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 347defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 348defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 349defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 350defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 351 352//////////////////////////////////////////////////////////////////////////////// 353// Vector integer operations. 354//////////////////////////////////////////////////////////////////////////////// 355 356def : WriteRes<WriteVecLoad, [AtomPort0]>; 357def : WriteRes<WriteVecLoadX, [AtomPort0]>; 358defm : X86WriteResUnsupported<WriteVecLoadY>; 359def : WriteRes<WriteVecLoadNT, [AtomPort0]>; 360defm : X86WriteResUnsupported<WriteVecLoadNTY>; 361defm : X86WriteResUnsupported<WriteVecMaskedLoad>; 362defm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 363 364def : WriteRes<WriteVecStore, [AtomPort0]>; 365def : WriteRes<WriteVecStoreX, [AtomPort0]>; 366defm : X86WriteResUnsupported<WriteVecStoreY>; 367def : WriteRes<WriteVecStoreNT, [AtomPort0]>; 368defm : X86WriteResUnsupported<WriteVecStoreNTY>; 369defm : X86WriteResUnsupported<WriteVecMaskedStore32>; 370defm : X86WriteResUnsupported<WriteVecMaskedStore64>; 371defm : X86WriteResUnsupported<WriteVecMaskedStore32Y>; 372defm : X86WriteResUnsupported<WriteVecMaskedStore64Y>; 373 374def : WriteRes<WriteVecMove, [AtomPort0]>; 375def : WriteRes<WriteVecMoveX, [AtomPort01]>; 376defm : X86WriteResUnsupported<WriteVecMoveY>; 377defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>; 378defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>; 379 380defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>; 381defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>; 382defm : X86WriteResPairUnsupported<WriteVecALUY>; 383defm : X86WriteResPairUnsupported<WriteVecALUZ>; 384defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>; 385defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>; 386defm : X86WriteResPairUnsupported<WriteVecLogicY>; 387defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 388defm : X86WriteResPairUnsupported<WriteVecTest>; 389defm : X86WriteResPairUnsupported<WriteVecTestY>; 390defm : X86WriteResPairUnsupported<WriteVecTestZ>; 391defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 392defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 393defm : X86WriteResPairUnsupported<WriteVecShiftY>; 394defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 395defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort0], [AtomPort0], 1, 1>; 396defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort0], [AtomPort0], 1, 1>; 397defm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 398defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 399defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>; 400defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 401defm : X86WriteResPairUnsupported<WriteVecIMulY>; 402defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 403defm : X86WriteResPairUnsupported<WritePMULLD>; 404defm : X86WriteResPairUnsupported<WritePMULLDY>; 405defm : X86WriteResPairUnsupported<WritePMULLDZ>; 406defm : X86WriteResPairUnsupported<WritePHMINPOS>; 407defm : X86WriteResPairUnsupported<WriteMPSAD>; 408defm : X86WriteResPairUnsupported<WriteMPSADY>; 409defm : X86WriteResPairUnsupported<WriteMPSADZ>; 410defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>; 411defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 412defm : X86WriteResPairUnsupported<WritePSADBWY>; 413defm : X86WriteResPairUnsupported<WritePSADBWZ>; 414defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>; 415defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>; 416defm : X86WriteResPairUnsupported<WriteShuffleY>; 417defm : X86WriteResPairUnsupported<WriteShuffleZ>; 418defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>; 419defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>; 420defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 421defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 422defm : X86WriteResPairUnsupported<WriteBlend>; 423defm : X86WriteResPairUnsupported<WriteBlendY>; 424defm : X86WriteResPairUnsupported<WriteBlendZ>; 425defm : X86WriteResPairUnsupported<WriteVarBlend>; 426defm : X86WriteResPairUnsupported<WriteVarBlendY>; 427defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 428defm : X86WriteResPairUnsupported<WriteShuffle256>; 429defm : X86WriteResPairUnsupported<WriteVPMOV256>; 430defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 431defm : X86WriteResPairUnsupported<WriteVarVecShift>; 432defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 433defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 434 435//////////////////////////////////////////////////////////////////////////////// 436// Vector insert/extract operations. 437//////////////////////////////////////////////////////////////////////////////// 438 439defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>; 440def : WriteRes<WriteVecExtract, [AtomPort0]>; 441def : WriteRes<WriteVecExtractSt, [AtomPort0]>; 442 443//////////////////////////////////////////////////////////////////////////////// 444// SSE42 String instructions. 445//////////////////////////////////////////////////////////////////////////////// 446 447defm : X86WriteResPairUnsupported<WritePCmpIStrI>; 448defm : X86WriteResPairUnsupported<WritePCmpIStrM>; 449defm : X86WriteResPairUnsupported<WritePCmpEStrI>; 450defm : X86WriteResPairUnsupported<WritePCmpEStrM>; 451 452//////////////////////////////////////////////////////////////////////////////// 453// MOVMSK Instructions. 454//////////////////////////////////////////////////////////////////////////////// 455 456def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 457def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 458defm : X86WriteResUnsupported<WriteVecMOVMSKY>; 459def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 460 461//////////////////////////////////////////////////////////////////////////////// 462// AES instructions. 463//////////////////////////////////////////////////////////////////////////////// 464 465defm : X86WriteResPairUnsupported<WriteAESIMC>; 466defm : X86WriteResPairUnsupported<WriteAESKeyGen>; 467defm : X86WriteResPairUnsupported<WriteAESDecEnc>; 468 469//////////////////////////////////////////////////////////////////////////////// 470// Horizontal add/sub instructions. 471//////////////////////////////////////////////////////////////////////////////// 472 473defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 474defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 475defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>; 476defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 477defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 478 479//////////////////////////////////////////////////////////////////////////////// 480// Carry-less multiplication instructions. 481//////////////////////////////////////////////////////////////////////////////// 482 483defm : X86WriteResPairUnsupported<WriteCLMul>; 484 485//////////////////////////////////////////////////////////////////////////////// 486// Load/store MXCSR. 487//////////////////////////////////////////////////////////////////////////////// 488 489def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; } 490def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; } 491 492//////////////////////////////////////////////////////////////////////////////// 493// Special Cases. 494//////////////////////////////////////////////////////////////////////////////// 495 496// Port0 497def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { 498 let Latency = 1; 499 let ResourceCycles = [1]; 500} 501def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr, 502 MOVSX64rr32)>; 503def : SchedAlias<WriteALURMW, AtomWrite0_1>; 504def : SchedAlias<WriteADCRMW, AtomWrite0_1>; 505def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", 506 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; 507 508// Port1 509def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { 510 let Latency = 1; 511 let ResourceCycles = [1]; 512} 513def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; 514def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>; 515 516def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { 517 let Latency = 5; 518 let ResourceCycles = [5]; 519} 520def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, 521 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; 522 523// Port0 and Port1 524def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { 525 let Latency = 1; 526 let ResourceCycles = [1, 1]; 527} 528def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, 529 POP16rmr, POP32rmr, POP64rmr, 530 PUSH16r, PUSH32r, PUSH64r, 531 PUSHi16, PUSHi32, 532 PUSH16rmr, PUSH32rmr, PUSH64rmr, 533 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, 534 XCH_F)>; 535def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", 536 "IRET(16|32|64)?")>; 537 538def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { 539 let Latency = 5; 540 let ResourceCycles = [5, 5]; 541} 542def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; 543def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; 544 545// Port0 or Port1 546def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { 547 let Latency = 1; 548 let ResourceCycles = [1]; 549} 550def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, 551 LFENCE, 552 STOSB, STOSL, STOSQ, STOSW, 553 MOVSSrr, MOVSSrr_REV, 554 PSLLDQri, PSRLDQri)>; 555def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", 556 "MMX_PUNPCKH(BW|DQ|WD)irr")>; 557 558def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { 559 let Latency = 2; 560 let ResourceCycles = [2]; 561} 562def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, 563 PUSH16rmm, PUSH32rmm, PUSH64rmm, 564 LODSB, LODSL, LODSQ, LODSW, 565 SCASB, SCASL, SCASQ, SCASW)>; 566def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", 567 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", 568 "MMX_P(ADD|SUB)Qirr", 569 "MOV(S|Z)X16rr8", 570 "MOV(UPS|UPD|DQU)mr", 571 "MASKMOVDQU(64)?", 572 "P(ADD|SUB)Qrr")>; 573def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>; 574 575def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { 576 let Latency = 3; 577 let ResourceCycles = [3]; 578} 579def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, 580 CMPSB, CMPSL, CMPSQ, CMPSW, 581 MOVSB, MOVSL, MOVSQ, MOVSW, 582 POP16rmm, POP32rmm, POP64rmm)>; 583def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", 584 "XCHG(8|16|32|64)rm", 585 "PH(ADD|SUB)Drr", 586 "MOV(S|Z)X16rm8", 587 "MMX_P(ADD|SUB)Qirm", 588 "MOV(UPS|UPD|DQU)rm", 589 "P(ADD|SUB)Qrm")>; 590 591def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { 592 let Latency = 4; 593 let ResourceCycles = [4]; 594} 595def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, 596 JCXZ, JECXZ, JRCXZ, 597 LD_F80m)>; 598def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", 599 "(MMX_)?PEXTRWrr(_REV)?")>; 600 601def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { 602 let Latency = 5; 603 let ResourceCycles = [5]; 604} 605def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; 606def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; 607 608def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { 609 let Latency = 6; 610 let ResourceCycles = [6]; 611} 612def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, 613 SHLD16rrCL, SHRD16rrCL, 614 SHLD16rri8, SHRD16rri8, 615 SHLD16mrCL, SHRD16mrCL, 616 SHLD16mri8, SHRD16mri8)>; 617def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m", 618 "MMX_PH(ADD|SUB)S?Wrm")>; 619 620def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { 621 let Latency = 7; 622 let ResourceCycles = [7]; 623} 624def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; 625 626def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { 627 let Latency = 8; 628 let ResourceCycles = [8]; 629} 630def : InstRW<[AtomWrite01_8], (instrs LOOPE, 631 PUSHA16, PUSHA32, 632 SHLD64rrCL, SHRD64rrCL, 633 FNSTCW16m)>; 634 635def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { 636 let Latency = 9; 637 let ResourceCycles = [9]; 638} 639def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32, 640 PUSHF16, PUSHF32, PUSHF64, 641 SHLD64mrCL, SHRD64mrCL, 642 SHLD64mri8, SHRD64mri8, 643 SHLD64rri8, SHRD64rri8, 644 CMPXCHG8rr)>; 645def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", 646 "(U)?COMIS(D|S)rr", 647 "CVT(T)?SS2SI64rr(_Int)?")>; 648 649def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { 650 let Latency = 10; 651 let ResourceCycles = [10]; 652} 653def : SchedAlias<WriteFLDC, AtomWrite01_10>; 654def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", 655 "CVT(T)?SS2SI64rm(_Int)?")>; 656 657def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { 658 let Latency = 11; 659 let ResourceCycles = [11]; 660} 661def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; 662def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>; 663 664def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { 665 let Latency = 13; 666 let ResourceCycles = [13]; 667} 668def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; 669 670def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { 671 let Latency = 14; 672 let ResourceCycles = [14]; 673} 674def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; 675 676def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { 677 let Latency = 17; 678 let ResourceCycles = [17]; 679} 680def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; 681 682def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { 683 let Latency = 18; 684 let ResourceCycles = [18]; 685} 686def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; 687 688def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { 689 let Latency = 20; 690 let ResourceCycles = [20]; 691} 692def : InstRW<[AtomWrite01_20], (instrs DAS)>; 693 694def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { 695 let Latency = 21; 696 let ResourceCycles = [21]; 697} 698def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; 699 700def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { 701 let Latency = 22; 702 let ResourceCycles = [22]; 703} 704def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; 705 706def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { 707 let Latency = 23; 708 let ResourceCycles = [23]; 709} 710def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; 711 712def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { 713 let Latency = 25; 714 let ResourceCycles = [25]; 715} 716def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; 717 718def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { 719 let Latency = 26; 720 let ResourceCycles = [26]; 721} 722def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; 723 724def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { 725 let Latency = 29; 726 let ResourceCycles = [29]; 727} 728def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; 729 730def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { 731 let Latency = 30; 732 let ResourceCycles = [30]; 733} 734def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; 735 736def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { 737 let Latency = 32; 738 let ResourceCycles = [32]; 739} 740def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; 741 742def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { 743 let Latency = 45; 744 let ResourceCycles = [45]; 745} 746def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>; 747 748def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { 749 let Latency = 46; 750 let ResourceCycles = [46]; 751} 752def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; 753 754def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { 755 let Latency = 48; 756 let ResourceCycles = [48]; 757} 758def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; 759 760def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { 761 let Latency = 55; 762 let ResourceCycles = [55]; 763} 764def : InstRW<[AtomWrite01_55], (instrs FPREM)>; 765 766def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { 767 let Latency = 59; 768 let ResourceCycles = [59]; 769} 770def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; 771 772def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { 773 let Latency = 63; 774 let ResourceCycles = [63]; 775} 776def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; 777 778def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { 779 let Latency = 68; 780 let ResourceCycles = [68]; 781} 782def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; 783 784def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { 785 let Latency = 71; 786 let ResourceCycles = [71]; 787} 788def : InstRW<[AtomWrite01_71], (instrs FPREM1, 789 INVLPG, INVLPGA32, INVLPGA64)>; 790 791def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { 792 let Latency = 72; 793 let ResourceCycles = [72]; 794} 795def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; 796 797def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { 798 let Latency = 74; 799 let ResourceCycles = [74]; 800} 801def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; 802 803def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { 804 let Latency = 77; 805 let ResourceCycles = [77]; 806} 807def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; 808 809def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { 810 let Latency = 78; 811 let ResourceCycles = [78]; 812} 813def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; 814 815def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { 816 let Latency = 79; 817 let ResourceCycles = [79]; 818} 819def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", 820 "LRETI?(L|Q|W)")>; 821 822def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { 823 let Latency = 92; 824 let ResourceCycles = [92]; 825} 826def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; 827 828def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { 829 let Latency = 94; 830 let ResourceCycles = [94]; 831} 832def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; 833 834def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { 835 let Latency = 99; 836 let ResourceCycles = [99]; 837} 838def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; 839 840def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { 841 let Latency = 121; 842 let ResourceCycles = [121]; 843} 844def : InstRW<[AtomWrite01_121], (instrs CPUID)>; 845 846def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { 847 let Latency = 127; 848 let ResourceCycles = [127]; 849} 850def : InstRW<[AtomWrite01_127], (instrs INT)>; 851 852def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { 853 let Latency = 130; 854 let ResourceCycles = [130]; 855} 856def : InstRW<[AtomWrite01_130], (instrs INT3)>; 857 858def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { 859 let Latency = 140; 860 let ResourceCycles = [140]; 861} 862def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; 863 864def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { 865 let Latency = 141; 866 let ResourceCycles = [141]; 867} 868def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; 869 870def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { 871 let Latency = 146; 872 let ResourceCycles = [146]; 873} 874def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; 875 876def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { 877 let Latency = 147; 878 let ResourceCycles = [147]; 879} 880def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; 881 882def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { 883 let Latency = 168; 884 let ResourceCycles = [168]; 885} 886def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; 887 888def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { 889 let Latency = 174; 890 let ResourceCycles = [174]; 891} 892def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>; 893 894def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { 895 let Latency = 183; 896 let ResourceCycles = [183]; 897} 898def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; 899 900def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { 901 let Latency = 202; 902 let ResourceCycles = [202]; 903} 904def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; 905 906} // SchedModel 907