1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler Emitter.
10 // It contains the interface of a single recognizable instruction.
11 // Documentation for the disassembler emitter in general can be found in
12 //  X86DisassemblerEmitter.h.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
18 
19 #include "CodeGenTarget.h"
20 #include "X86DisassemblerTables.h"
21 #include "llvm/Support/DataTypes.h"
22 #include "llvm/TableGen/Record.h"
23 
24 namespace llvm {
25 
26 #define X86_INSTR_MRM_MAPPING     \
27   MAP(C0, 64)                     \
28   MAP(C1, 65)                     \
29   MAP(C2, 66)                     \
30   MAP(C3, 67)                     \
31   MAP(C4, 68)                     \
32   MAP(C5, 69)                     \
33   MAP(C6, 70)                     \
34   MAP(C7, 71)                     \
35   MAP(C8, 72)                     \
36   MAP(C9, 73)                     \
37   MAP(CA, 74)                     \
38   MAP(CB, 75)                     \
39   MAP(CC, 76)                     \
40   MAP(CD, 77)                     \
41   MAP(CE, 78)                     \
42   MAP(CF, 79)                     \
43   MAP(D0, 80)                     \
44   MAP(D1, 81)                     \
45   MAP(D2, 82)                     \
46   MAP(D3, 83)                     \
47   MAP(D4, 84)                     \
48   MAP(D5, 85)                     \
49   MAP(D6, 86)                     \
50   MAP(D7, 87)                     \
51   MAP(D8, 88)                     \
52   MAP(D9, 89)                     \
53   MAP(DA, 90)                     \
54   MAP(DB, 91)                     \
55   MAP(DC, 92)                     \
56   MAP(DD, 93)                     \
57   MAP(DE, 94)                     \
58   MAP(DF, 95)                     \
59   MAP(E0, 96)                     \
60   MAP(E1, 97)                     \
61   MAP(E2, 98)                     \
62   MAP(E3, 99)                     \
63   MAP(E4, 100)                    \
64   MAP(E5, 101)                    \
65   MAP(E6, 102)                    \
66   MAP(E7, 103)                    \
67   MAP(E8, 104)                    \
68   MAP(E9, 105)                    \
69   MAP(EA, 106)                    \
70   MAP(EB, 107)                    \
71   MAP(EC, 108)                    \
72   MAP(ED, 109)                    \
73   MAP(EE, 110)                    \
74   MAP(EF, 111)                    \
75   MAP(F0, 112)                    \
76   MAP(F1, 113)                    \
77   MAP(F2, 114)                    \
78   MAP(F3, 115)                    \
79   MAP(F4, 116)                    \
80   MAP(F5, 117)                    \
81   MAP(F6, 118)                    \
82   MAP(F7, 119)                    \
83   MAP(F8, 120)                    \
84   MAP(F9, 121)                    \
85   MAP(FA, 122)                    \
86   MAP(FB, 123)                    \
87   MAP(FC, 124)                    \
88   MAP(FD, 125)                    \
89   MAP(FE, 126)                    \
90   MAP(FF, 127)
91 
92 // A clone of X86 since we can't depend on something that is generated.
93 namespace X86Local {
94   enum {
95     Pseudo        = 0,
96     RawFrm        = 1,
97     AddRegFrm     = 2,
98     RawFrmMemOffs = 3,
99     RawFrmSrc     = 4,
100     RawFrmDst     = 5,
101     RawFrmDstSrc  = 6,
102     RawFrmImm8    = 7,
103     RawFrmImm16   = 8,
104     AddCCFrm      = 9,
105     PrefixByte    = 10,
106     MRMr0          = 21,
107     MRMSrcMemFSIB  = 22,
108     MRMDestMemFSIB = 23,
109     MRMDestMem     = 24,
110     MRMSrcMem      = 25,
111     MRMSrcMem4VOp3 = 26,
112     MRMSrcMemOp4   = 27,
113     MRMSrcMemCC    = 28,
114     MRMXmCC = 30, MRMXm = 31,
115     MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35,
116     MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39,
117     MRMDestReg     = 40,
118     MRMSrcReg      = 41,
119     MRMSrcReg4VOp3 = 42,
120     MRMSrcRegOp4   = 43,
121     MRMSrcRegCC    = 44,
122     MRMXrCC = 46, MRMXr = 47,
123     MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51,
124     MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55,
125     MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59,
126     MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63,
127 #define MAP(from, to) MRM_##from = to,
128     X86_INSTR_MRM_MAPPING
129 #undef MAP
130   };
131 
132   enum {
133     OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7
134   };
135 
136   enum {
137     PD = 1, XS = 2, XD = 3, PS = 4
138   };
139 
140   enum {
141     VEX = 1, XOP = 2, EVEX = 3
142   };
143 
144   enum {
145     OpSize16 = 1, OpSize32 = 2
146   };
147 
148   enum {
149     AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
150   };
151 }
152 
153 namespace X86Disassembler {
154 
155 /// RecognizableInstr - Encapsulates all information required to decode a single
156 ///   instruction, as extracted from the LLVM instruction tables.  Has methods
157 ///   to interpret the information available in the LLVM tables, and to emit the
158 ///   instruction into DisassemblerTables.
159 class RecognizableInstr {
160 private:
161   /// The opcode of the instruction, as used in an MCInst
162   InstrUID UID;
163   /// The record from the .td files corresponding to this instruction
164   const Record* Rec;
165   /// The OpPrefix field from the record
166   uint8_t OpPrefix;
167   /// The OpMap field from the record
168   uint8_t OpMap;
169   /// The opcode field from the record; this is the opcode used in the Intel
170   /// encoding and therefore distinct from the UID
171   uint8_t Opcode;
172   /// The form field from the record
173   uint8_t Form;
174   // The encoding field from the record
175   uint8_t Encoding;
176   /// The OpSize field from the record
177   uint8_t OpSize;
178   /// The AdSize field from the record
179   uint8_t AdSize;
180   /// The hasREX_WPrefix field from the record
181   bool HasREX_WPrefix;
182   /// The hasVEX_4V field from the record
183   bool HasVEX_4V;
184   /// The HasVEX_WPrefix field from the record
185   bool HasVEX_W;
186   /// The IgnoresVEX_W field from the record
187   bool IgnoresVEX_W;
188   /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
189   bool HasVEX_LPrefix;
190   /// The ignoreVEX_L field from the record
191   bool IgnoresVEX_L;
192   /// The hasEVEX_L2Prefix field from the record
193   bool HasEVEX_L2Prefix;
194   /// The hasEVEX_K field from the record
195   bool HasEVEX_K;
196   /// The hasEVEX_KZ field from the record
197   bool HasEVEX_KZ;
198   /// The hasEVEX_B field from the record
199   bool HasEVEX_B;
200   /// Indicates that the instruction uses the L and L' fields for RC.
201   bool EncodeRC;
202   /// The isCodeGenOnly field from the record
203   bool IsCodeGenOnly;
204   /// The ForceDisassemble field from the record
205   bool ForceDisassemble;
206   // The CD8_Scale field from the record
207   uint8_t CD8_Scale;
208   // Whether the instruction has the predicate "In64BitMode"
209   bool Is64Bit;
210   // Whether the instruction has the predicate "In32BitMode"
211   bool Is32Bit;
212 
213   /// The instruction name as listed in the tables
214   std::string Name;
215 
216   /// Indicates whether the instruction should be emitted into the decode
217   /// tables; regardless, it will be emitted into the instruction info table
218   bool ShouldBeEmitted;
219 
220   /// The operands of the instruction, as listed in the CodeGenInstruction.
221   /// They are not one-to-one with operands listed in the MCInst; for example,
222   /// memory operands expand to 5 operands in the MCInst
223   const std::vector<CGIOperandList::OperandInfo>* Operands;
224 
225   /// The description of the instruction that is emitted into the instruction
226   /// info table
227   InstructionSpecifier* Spec;
228 
229   /// insnContext - Returns the primary context in which the instruction is
230   ///   valid.
231   ///
232   /// @return - The context in which the instruction is valid.
233   InstructionContext insnContext() const;
234 
235   /// typeFromString - Translates an operand type from the string provided in
236   ///   the LLVM tables to an OperandType for use in the operand specifier.
237   ///
238   /// @param s              - The string, as extracted by calling Rec->getName()
239   ///                         on a CodeGenInstruction::OperandInfo.
240   /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
241   ///                         prefix.  If it does, 32-bit register operands stay
242   ///                         32-bit regardless of the operand size.
243   /// @param OpSize           Indicates the operand size of the instruction.
244   ///                         If register size does not match OpSize, then
245   ///                         register sizes keep their size.
246   /// @return               - The operand's type.
247   static OperandType typeFromString(const std::string& s,
248                                     bool hasREX_WPrefix, uint8_t OpSize);
249 
250   /// immediateEncodingFromString - Translates an immediate encoding from the
251   ///   string provided in the LLVM tables to an OperandEncoding for use in
252   ///   the operand specifier.
253   ///
254   /// @param s       - See typeFromString().
255   /// @param OpSize  - Indicates whether this is an OpSize16 instruction.
256   ///                  If it is not, then 16-bit immediate operands stay 16-bit.
257   /// @return        - The operand's encoding.
258   static OperandEncoding immediateEncodingFromString(const std::string &s,
259                                                      uint8_t OpSize);
260 
261   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
262   ///   handles operands that are in the REG field of the ModR/M byte.
263   static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
264                                                       uint8_t OpSize);
265 
266   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
267   ///   handles operands that are in the REG field of the ModR/M byte.
268   static OperandEncoding roRegisterEncodingFromString(const std::string &s,
269                                                       uint8_t OpSize);
270   static OperandEncoding memoryEncodingFromString(const std::string &s,
271                                                   uint8_t OpSize);
272   static OperandEncoding relocationEncodingFromString(const std::string &s,
273                                                       uint8_t OpSize);
274   static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
275                                                           uint8_t OpSize);
276   static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
277                                                         uint8_t OpSize);
278   static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
279                                                              uint8_t OpSize);
280 
281   /// Adjust the encoding type for an operand based on the instruction.
282   void adjustOperandEncoding(OperandEncoding &encoding);
283 
284   /// handleOperand - Converts a single operand from the LLVM table format to
285   ///   the emitted table format, handling any duplicate operands it encounters
286   ///   and then one non-duplicate.
287   ///
288   /// @param optional             - Determines whether to assert that the
289   ///                               operand exists.
290   /// @param operandIndex         - The index into the generated operand table.
291   ///                               Incremented by this function one or more
292   ///                               times to reflect possible duplicate
293   ///                               operands).
294   /// @param physicalOperandIndex - The index of the current operand into the
295   ///                               set of non-duplicate ('physical') operands.
296   ///                               Incremented by this function once.
297   /// @param numPhysicalOperands  - The number of non-duplicate operands in the
298   ///                               instructions.
299   /// @param operandMapping       - The operand mapping, which has an entry for
300   ///                               each operand that indicates whether it is a
301   ///                               duplicate, and of what.
302   void handleOperand(bool optional,
303                      unsigned &operandIndex,
304                      unsigned &physicalOperandIndex,
305                      unsigned numPhysicalOperands,
306                      const unsigned *operandMapping,
307                      OperandEncoding (*encodingFromString)
308                        (const std::string&,
309                         uint8_t OpSize));
310 
311   /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
312   ///   filters out many instructions, at various points in decoding we
313   ///   determine that the instruction should not actually be decodable.  In
314   ///   particular, MMX MOV instructions aren't emitted, but they're only
315   ///   identified during operand parsing.
316   ///
317   /// @return - true if at this point we believe the instruction should be
318   ///   emitted; false if not.  This will return false if filter() returns false
319   ///   once emitInstructionSpecifier() has been called.
shouldBeEmitted()320   bool shouldBeEmitted() const {
321     return ShouldBeEmitted;
322   }
323 
324   /// emitInstructionSpecifier - Loads the instruction specifier for the current
325   ///   instruction into a DisassemblerTables.
326   ///
327   void emitInstructionSpecifier();
328 
329   /// emitDecodePath - Populates the proper fields in the decode tables
330   ///   corresponding to the decode paths for this instruction.
331   ///
332   /// \param tables The DisassemblerTables to populate with the decode
333   ///               decode information for the current instruction.
334   void emitDecodePath(DisassemblerTables &tables) const;
335 
336   /// Constructor - Initializes a RecognizableInstr with the appropriate fields
337   ///   from a CodeGenInstruction.
338   ///
339   /// \param tables The DisassemblerTables that the specifier will be added to.
340   /// \param insn   The CodeGenInstruction to extract information from.
341   /// \param uid    The unique ID of the current instruction.
342   RecognizableInstr(DisassemblerTables &tables,
343                     const CodeGenInstruction &insn,
344                     InstrUID uid);
345 public:
346   /// processInstr - Accepts a CodeGenInstruction and loads decode information
347   ///   for it into a DisassemblerTables if appropriate.
348   ///
349   /// \param tables The DiassemblerTables to be populated with decode
350   ///               information.
351   /// \param insn   The CodeGenInstruction to be used as a source for this
352   ///               information.
353   /// \param uid    The unique ID of the instruction.
354   static void processInstr(DisassemblerTables &tables,
355                            const CodeGenInstruction &insn,
356                            InstrUID uid);
357 };
358 
359 } // namespace X86Disassembler
360 
361 } // namespace llvm
362 
363 #endif
364