1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2020 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "as.h"
22 #include <limits.h>
23 #include "sb.h"
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
26 #include "subsegs.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "xtensa-config.h"
31 #include "elf/xtensa.h"
32
33 /* Provide default values for new configuration settings. */
34 #ifndef XSHAL_ABI
35 #define XSHAL_ABI 0
36 #endif
37
38 #ifndef uint32
39 #define uint32 unsigned int
40 #endif
41 #ifndef int32
42 #define int32 signed int
43 #endif
44
45 /* Notes:
46
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
50
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
61
62
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars[] = "#";
65 const char line_comment_chars[] = "#";
66 const char line_separator_chars[] = ";";
67 const char EXP_CHARS[] = "eE";
68 const char FLT_CHARS[] = "rRsSfFdDxXpP";
69
70
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
73
74 bfd_boolean density_supported;
75 bfd_boolean absolute_literals_supported;
76
77 static vliw_insn cur_vinsn;
78
79 unsigned xtensa_num_pipe_stages;
80 unsigned xtensa_fetch_width;
81
82 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
83
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
86 back end. */
87 static bfd_boolean past_xtensa_end = FALSE;
88
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
92
93
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
98
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
103
104
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
111 values are valid. */
112
113 typedef struct lit_state_struct
114 {
115 char *lit_prefix;
116 segT current_text_seg;
117 segT lit_seg;
118 segT lit4_seg;
119 } lit_state;
120
121 static lit_state default_lit_sections;
122
123
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
127
128 typedef struct seg_list_struct
129 {
130 struct seg_list_struct *next;
131 segT seg;
132 } seg_list;
133
134 static seg_list literal_head_h;
135 static seg_list *literal_head = &literal_head_h;
136
137
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
143
144 typedef struct sym_list_struct
145 {
146 struct sym_list_struct *next;
147 symbolS *sym;
148 } sym_list;
149
150 static sym_list *insn_labels = NULL;
151 static sym_list *free_insn_labels = NULL;
152 static sym_list *saved_insn_labels = NULL;
153
154 static sym_list *literal_syms;
155
156
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16 = 0;
160 int prefer_l32r = 0;
161
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals = 0;
164
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
167
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
177
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
191
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
197 Common usage is
198
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
204 */
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
206
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
215
216 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
217 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
218 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
219
220
221 /* Alignment is specified in the block BEFORE the one that needs
222 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
223 get the required alignment specified as a power of 2. Use
224 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
225 alignment. Be careful of side effects since the SET will evaluate
226 flags twice. Also, note that the SIZE of a block in the property
227 table does not include the alignment size, so the alignment fill
228 must be calculated to determine if two blocks are contiguous.
229 TEXT_ALIGN is not currently implemented but is a placeholder for a
230 possible future implementation. */
231
232 #define XTENSA_PROP_ALIGN 0x00000800
233
234 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
235
236 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
237 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
238 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
239
240 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
241
242
243 /* Structure for saving instruction and alignment per-fragment data
244 that will be written to the object file. This structure is
245 equivalent to the actual data that will be written out to the file
246 but is easier to use. We provide a conversion to file flags
247 in frag_flags_to_number. */
248
249 typedef struct frag_flags_struct frag_flags;
250
251 struct frag_flags_struct
252 {
253 /* is_literal should only be used after xtensa_move_literals.
254 If you need to check if you are generating a literal fragment,
255 then use the generating_literals global. */
256
257 unsigned is_literal : 1;
258 unsigned is_insn : 1;
259 unsigned is_data : 1;
260 unsigned is_unreachable : 1;
261
262 /* is_specific_opcode implies no_transform. */
263 unsigned is_no_transform : 1;
264
265 struct
266 {
267 unsigned is_loop_target : 1;
268 unsigned is_branch_target : 1; /* Branch targets have a priority. */
269 unsigned bt_align_priority : 2;
270
271 unsigned is_no_density : 1;
272 /* no_longcalls flag does not need to be placed in the object file. */
273
274 unsigned is_no_reorder : 1;
275
276 /* Uses absolute literal addressing for l32r. */
277 unsigned is_abslit : 1;
278 } insn;
279 unsigned is_align : 1;
280 unsigned alignment : 5;
281 };
282
283
284 /* Structure for saving information about a block of property data
285 for frags that have the same flags. */
286 struct xtensa_block_info_struct
287 {
288 segT sec;
289 bfd_vma offset;
290 size_t size;
291 frag_flags flags;
292 struct xtensa_block_info_struct *next;
293 };
294
295
296 /* Structure for saving the current state before emitting literals. */
297 typedef struct emit_state_struct
298 {
299 const char *name;
300 segT now_seg;
301 subsegT now_subseg;
302 int generating_literals;
303 } emit_state;
304
305
306 /* Opcode placement information */
307
308 typedef unsigned long long bitfield;
309 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
310 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
311 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
312
313 #define MAX_FORMATS 32
314
315 typedef struct op_placement_info_struct
316 {
317 int num_formats;
318 /* A number describing how restrictive the issue is for this
319 opcode. For example, an opcode that fits lots of different
320 formats has a high freedom, as does an opcode that fits
321 only one format but many slots in that format. The most
322 restrictive is the opcode that fits only one slot in one
323 format. */
324 int issuef;
325 xtensa_format narrowest;
326 char narrowest_size;
327 char narrowest_slot;
328
329 /* formats is a bitfield with the Nth bit set
330 if the opcode fits in the Nth xtensa_format. */
331 bitfield formats;
332
333 /* slots[N]'s Mth bit is set if the op fits in the
334 Mth slot of the Nth xtensa_format. */
335 bitfield slots[MAX_FORMATS];
336
337 /* A count of the number of slots in a given format
338 an op can fit (i.e., the bitcount of the slot field above). */
339 char slots_in_format[MAX_FORMATS];
340
341 } op_placement_info, *op_placement_info_table;
342
343 op_placement_info_table op_placement_table;
344
345
346 /* Extra expression types. */
347
348 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
349 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
350 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
351 #define O_pcrel O_md4 /* value is a PC-relative offset */
352 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
353 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
354 #define O_tlscall O_md7 /* TLS_CALL relocation */
355 #define O_tpoff O_md8 /* TPOFF relocation */
356 #define O_dtpoff O_md9 /* DTPOFF relocation */
357
358 struct suffix_reloc_map
359 {
360 const char *suffix;
361 int length;
362 bfd_reloc_code_real_type reloc;
363 operatorT operator;
364 };
365
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
367
368 static struct suffix_reloc_map suffix_relocs[] =
369 {
370 SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel),
373 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel),
374 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc),
375 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg),
376 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall),
377 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff),
378 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff),
379 };
380
381
382 /* Directives. */
383
384 typedef enum
385 {
386 directive_none = 0,
387 directive_literal,
388 directive_density,
389 directive_transform,
390 directive_freeregs,
391 directive_longcalls,
392 directive_literal_prefix,
393 directive_schedule,
394 directive_absolute_literals,
395 directive_last_directive
396 } directiveE;
397
398 typedef struct
399 {
400 const char *name;
401 bfd_boolean can_be_negated;
402 } directive_infoS;
403
404 const directive_infoS directive_info[] =
405 {
406 { "none", FALSE },
407 { "literal", FALSE },
408 { "density", TRUE },
409 { "transform", TRUE },
410 { "freeregs", FALSE },
411 { "longcalls", TRUE },
412 { "literal_prefix", FALSE },
413 { "schedule", TRUE },
414 { "absolute-literals", TRUE }
415 };
416
417 bfd_boolean directive_state[] =
418 {
419 FALSE, /* none */
420 FALSE, /* literal */
421 FALSE, /* density */
422 TRUE, /* transform */
423 FALSE, /* freeregs */
424 FALSE, /* longcalls */
425 FALSE, /* literal_prefix */
426 FALSE, /* schedule */
427 FALSE /* absolute_literals */
428 };
429
430 /* A circular list of all potential and actual literal pool locations
431 in a segment. */
432 struct litpool_frag
433 {
434 struct litpool_frag *next;
435 struct litpool_frag *prev;
436 fragS *fragP;
437 addressT addr;
438 short priority; /* 1, 2, or 3 -- 1 is highest */
439 short original_priority;
440 int literal_count;
441 };
442
443 /* Map a segment to its litpool_frag list. */
444 struct litpool_seg
445 {
446 struct litpool_seg *next;
447 asection *seg;
448 struct litpool_frag frag_list;
449 int frag_count; /* since last litpool location */
450 };
451
452 static struct litpool_seg litpool_seg_list;
453
454 /* Limit maximal size of auto litpool by half of the j range. */
455 #define MAX_AUTO_POOL_LITERALS 16384
456
457 /* Limit maximal size of explicit literal pool by l32r range. */
458 #define MAX_EXPLICIT_POOL_LITERALS 65536
459
460 #define MAX_POOL_LITERALS \
461 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
462
463 /* Directive functions. */
464
465 static void xtensa_begin_directive (int);
466 static void xtensa_end_directive (int);
467 static void xtensa_literal_prefix (void);
468 static void xtensa_literal_position (int);
469 static void xtensa_literal_pseudo (int);
470 static void xtensa_frequency_pseudo (int);
471 static void xtensa_elf_cons (int);
472 static void xtensa_leb128 (int);
473
474 /* Parsing and Idiom Translation. */
475
476 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
477
478 /* Various Other Internal Functions. */
479
480 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
481 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
482 static void xtensa_mark_literal_pool_location (void);
483 static addressT get_expanded_loop_offset (xtensa_opcode);
484 static fragS *get_literal_pool_location (segT);
485 static void set_literal_pool_location (segT, fragS *);
486 static void xtensa_set_frag_assembly_state (fragS *);
487 static void finish_vinsn (vliw_insn *);
488 static bfd_boolean emit_single_op (TInsn *);
489 static int total_frag_text_expansion (fragS *);
490 static bfd_boolean use_trampolines = TRUE;
491 static void xtensa_check_frag_count (void);
492 static void xtensa_create_trampoline_frag (bfd_boolean);
493 static void xtensa_maybe_create_trampoline_frag (void);
494 struct trampoline_frag;
495 static int init_trampoline_frag (fragS *);
496 static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset);
497 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean);
498 static bfd_boolean auto_litpools = FALSE;
499 static int auto_litpool_limit = 0;
500 static bfd_boolean xtensa_is_init_fini (segT seg);
501
502 /* Alignment Functions. */
503
504 static int get_text_align_power (unsigned);
505 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
506 static int branch_align_power (segT);
507
508 /* Helpers for xtensa_relax_frag(). */
509
510 static long relax_frag_add_nop (fragS *);
511
512 /* Accessors for additional per-subsegment information. */
513
514 static unsigned get_last_insn_flags (segT, subsegT);
515 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
516 static float get_subseg_total_freq (segT, subsegT);
517 static float get_subseg_target_freq (segT, subsegT);
518 static void set_subseg_freq (segT, subsegT, float, float);
519
520 /* Segment list functions. */
521
522 static void xtensa_move_literals (void);
523 static void xtensa_reorder_segments (void);
524 static void xtensa_switch_to_literal_fragment (emit_state *);
525 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
526 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
527 static void xtensa_restore_emit_state (emit_state *);
528 static segT cache_literal_section (bfd_boolean);
529
530 /* op_placement_info functions. */
531
532 static void init_op_placement_info_table (void);
533 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
534 static int xg_get_single_size (xtensa_opcode);
535 static xtensa_format xg_get_single_format (xtensa_opcode);
536 static int xg_get_single_slot (xtensa_opcode);
537
538 /* TInsn and IStack functions. */
539
540 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
541 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
542 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
543 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
544 static bfd_boolean tinsn_check_arguments (const TInsn *);
545 static void tinsn_from_chars (TInsn *, char *, int);
546 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
547 static int get_num_stack_text_bytes (IStack *);
548 static int get_num_stack_literal_bytes (IStack *);
549 static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf);
550
551 /* vliw_insn functions. */
552
553 static void xg_init_vinsn (vliw_insn *);
554 static void xg_copy_vinsn (vliw_insn *, vliw_insn *);
555 static void xg_clear_vinsn (vliw_insn *);
556 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
557 static void xg_free_vinsn (vliw_insn *);
558 static bfd_boolean vinsn_to_insnbuf
559 (vliw_insn *, char *, fragS *, bfd_boolean);
560 static void vinsn_from_chars (vliw_insn *, char *);
561
562 /* Expression Utilities. */
563
564 bfd_boolean expr_is_const (const expressionS *);
565 offsetT get_expr_const (const expressionS *);
566 void set_expr_const (expressionS *, offsetT);
567 bfd_boolean expr_is_register (const expressionS *);
568 offsetT get_expr_register (const expressionS *);
569 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
570 bfd_boolean expr_is_equal (expressionS *, expressionS *);
571 static void copy_expr (expressionS *, const expressionS *);
572
573 /* Section renaming. */
574
575 static void build_section_rename (const char *);
576
577
578 /* ISA imported from bfd. */
579 extern xtensa_isa xtensa_default_isa;
580
581 extern int target_big_endian;
582
583 static xtensa_opcode xtensa_addi_opcode;
584 static xtensa_opcode xtensa_addmi_opcode;
585 static xtensa_opcode xtensa_call0_opcode;
586 static xtensa_opcode xtensa_call4_opcode;
587 static xtensa_opcode xtensa_call8_opcode;
588 static xtensa_opcode xtensa_call12_opcode;
589 static xtensa_opcode xtensa_callx0_opcode;
590 static xtensa_opcode xtensa_callx4_opcode;
591 static xtensa_opcode xtensa_callx8_opcode;
592 static xtensa_opcode xtensa_callx12_opcode;
593 static xtensa_opcode xtensa_const16_opcode;
594 static xtensa_opcode xtensa_entry_opcode;
595 static xtensa_opcode xtensa_extui_opcode;
596 static xtensa_opcode xtensa_movi_opcode;
597 static xtensa_opcode xtensa_movi_n_opcode;
598 static xtensa_opcode xtensa_isync_opcode;
599 static xtensa_opcode xtensa_j_opcode;
600 static xtensa_opcode xtensa_jx_opcode;
601 static xtensa_opcode xtensa_l32r_opcode;
602 static xtensa_opcode xtensa_loop_opcode;
603 static xtensa_opcode xtensa_loopnez_opcode;
604 static xtensa_opcode xtensa_loopgtz_opcode;
605 static xtensa_opcode xtensa_nop_opcode;
606 static xtensa_opcode xtensa_nop_n_opcode;
607 static xtensa_opcode xtensa_or_opcode;
608 static xtensa_opcode xtensa_ret_opcode;
609 static xtensa_opcode xtensa_ret_n_opcode;
610 static xtensa_opcode xtensa_retw_opcode;
611 static xtensa_opcode xtensa_retw_n_opcode;
612 static xtensa_opcode xtensa_rsr_lcount_opcode;
613 static xtensa_opcode xtensa_waiti_opcode;
614 static int config_max_slots = 0;
615
616
617 /* Command-line Options. */
618
619 bfd_boolean use_literal_section = TRUE;
620 enum flix_level produce_flix = FLIX_ALL;
621 static bfd_boolean align_targets = TRUE;
622 static bfd_boolean warn_unaligned_branch_targets = FALSE;
623 static bfd_boolean has_a0_b_retw = FALSE;
624 static bfd_boolean workaround_a0_b_retw = FALSE;
625 static bfd_boolean workaround_b_j_loop_end = FALSE;
626 static bfd_boolean workaround_short_loop = FALSE;
627 static bfd_boolean maybe_has_short_loop = FALSE;
628 static bfd_boolean workaround_close_loop_end = FALSE;
629 static bfd_boolean maybe_has_close_loop_end = FALSE;
630 static bfd_boolean enforce_three_byte_loop_align = FALSE;
631 static bfd_boolean opt_linkrelax = TRUE;
632
633 /* When workaround_short_loops is TRUE, all loops with early exits must
634 have at least 3 instructions. workaround_all_short_loops is a modifier
635 to the workaround_short_loop flag. In addition to the
636 workaround_short_loop actions, all straightline loopgtz and loopnez
637 must have at least 3 instructions. */
638
639 static bfd_boolean workaround_all_short_loops = FALSE;
640
641 /* Generate individual property section for every section.
642 This option is defined in BDF library. */
643 extern bfd_boolean elf32xtensa_separate_props;
644
645 static void
xtensa_setup_hw_workarounds(int earliest,int latest)646 xtensa_setup_hw_workarounds (int earliest, int latest)
647 {
648 if (earliest > latest)
649 as_fatal (_("illegal range of target hardware versions"));
650
651 /* Enable all workarounds for pre-T1050.0 hardware. */
652 if (earliest < 105000 || latest < 105000)
653 {
654 workaround_a0_b_retw |= TRUE;
655 workaround_b_j_loop_end |= TRUE;
656 workaround_short_loop |= TRUE;
657 workaround_close_loop_end |= TRUE;
658 workaround_all_short_loops |= TRUE;
659 enforce_three_byte_loop_align = TRUE;
660 }
661 }
662
663
664 enum
665 {
666 option_density = OPTION_MD_BASE,
667 option_no_density,
668
669 option_flix,
670 option_no_generate_flix,
671 option_no_flix,
672
673 option_relax,
674 option_no_relax,
675
676 option_link_relax,
677 option_no_link_relax,
678
679 option_generics,
680 option_no_generics,
681
682 option_transform,
683 option_no_transform,
684
685 option_text_section_literals,
686 option_no_text_section_literals,
687
688 option_absolute_literals,
689 option_no_absolute_literals,
690
691 option_align_targets,
692 option_no_align_targets,
693
694 option_warn_unaligned_targets,
695
696 option_longcalls,
697 option_no_longcalls,
698
699 option_workaround_a0_b_retw,
700 option_no_workaround_a0_b_retw,
701
702 option_workaround_b_j_loop_end,
703 option_no_workaround_b_j_loop_end,
704
705 option_workaround_short_loop,
706 option_no_workaround_short_loop,
707
708 option_workaround_all_short_loops,
709 option_no_workaround_all_short_loops,
710
711 option_workaround_close_loop_end,
712 option_no_workaround_close_loop_end,
713
714 option_no_workarounds,
715
716 option_rename_section_name,
717
718 option_prefer_l32r,
719 option_prefer_const16,
720
721 option_target_hardware,
722
723 option_trampolines,
724 option_no_trampolines,
725
726 option_auto_litpools,
727 option_no_auto_litpools,
728 option_auto_litpool_limit,
729
730 option_separate_props,
731 option_no_separate_props,
732 };
733
734 const char *md_shortopts = "";
735
736 struct option md_longopts[] =
737 {
738 { "density", no_argument, NULL, option_density },
739 { "no-density", no_argument, NULL, option_no_density },
740
741 { "flix", no_argument, NULL, option_flix },
742 { "no-generate-flix", no_argument, NULL, option_no_generate_flix },
743 { "no-allow-flix", no_argument, NULL, option_no_flix },
744
745 /* Both "relax" and "generics" are deprecated and treated as equivalent
746 to the "transform" option. */
747 { "relax", no_argument, NULL, option_relax },
748 { "no-relax", no_argument, NULL, option_no_relax },
749 { "generics", no_argument, NULL, option_generics },
750 { "no-generics", no_argument, NULL, option_no_generics },
751
752 { "transform", no_argument, NULL, option_transform },
753 { "no-transform", no_argument, NULL, option_no_transform },
754 { "text-section-literals", no_argument, NULL, option_text_section_literals },
755 { "no-text-section-literals", no_argument, NULL,
756 option_no_text_section_literals },
757 { "absolute-literals", no_argument, NULL, option_absolute_literals },
758 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
759 /* This option was changed from -align-target to -target-align
760 because it conflicted with the "-al" option. */
761 { "target-align", no_argument, NULL, option_align_targets },
762 { "no-target-align", no_argument, NULL, option_no_align_targets },
763 { "warn-unaligned-targets", no_argument, NULL,
764 option_warn_unaligned_targets },
765 { "longcalls", no_argument, NULL, option_longcalls },
766 { "no-longcalls", no_argument, NULL, option_no_longcalls },
767
768 { "no-workaround-a0-b-retw", no_argument, NULL,
769 option_no_workaround_a0_b_retw },
770 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
771
772 { "no-workaround-b-j-loop-end", no_argument, NULL,
773 option_no_workaround_b_j_loop_end },
774 { "workaround-b-j-loop-end", no_argument, NULL,
775 option_workaround_b_j_loop_end },
776
777 { "no-workaround-short-loops", no_argument, NULL,
778 option_no_workaround_short_loop },
779 { "workaround-short-loops", no_argument, NULL,
780 option_workaround_short_loop },
781
782 { "no-workaround-all-short-loops", no_argument, NULL,
783 option_no_workaround_all_short_loops },
784 { "workaround-all-short-loop", no_argument, NULL,
785 option_workaround_all_short_loops },
786
787 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
788 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
789
790 { "no-workarounds", no_argument, NULL, option_no_workarounds },
791
792 { "no-workaround-close-loop-end", no_argument, NULL,
793 option_no_workaround_close_loop_end },
794 { "workaround-close-loop-end", no_argument, NULL,
795 option_workaround_close_loop_end },
796
797 { "rename-section", required_argument, NULL, option_rename_section_name },
798
799 { "link-relax", no_argument, NULL, option_link_relax },
800 { "no-link-relax", no_argument, NULL, option_no_link_relax },
801
802 { "target-hardware", required_argument, NULL, option_target_hardware },
803
804 { "trampolines", no_argument, NULL, option_trampolines },
805 { "no-trampolines", no_argument, NULL, option_no_trampolines },
806
807 { "auto-litpools", no_argument, NULL, option_auto_litpools },
808 { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools },
809 { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit },
810
811 { "separate-prop-tables", no_argument, NULL, option_separate_props },
812
813 { NULL, no_argument, NULL, 0 }
814 };
815
816 size_t md_longopts_size = sizeof md_longopts;
817
818
819 int
md_parse_option(int c,const char * arg)820 md_parse_option (int c, const char *arg)
821 {
822 switch (c)
823 {
824 case option_density:
825 as_warn (_("--density option is ignored"));
826 return 1;
827 case option_no_density:
828 as_warn (_("--no-density option is ignored"));
829 return 1;
830 case option_link_relax:
831 opt_linkrelax = TRUE;
832 return 1;
833 case option_no_link_relax:
834 opt_linkrelax = FALSE;
835 return 1;
836 case option_flix:
837 produce_flix = FLIX_ALL;
838 return 1;
839 case option_no_generate_flix:
840 produce_flix = FLIX_NO_GENERATE;
841 return 1;
842 case option_no_flix:
843 produce_flix = FLIX_NONE;
844 return 1;
845 case option_generics:
846 as_warn (_("--generics is deprecated; use --transform instead"));
847 return md_parse_option (option_transform, arg);
848 case option_no_generics:
849 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
850 return md_parse_option (option_no_transform, arg);
851 case option_relax:
852 as_warn (_("--relax is deprecated; use --transform instead"));
853 return md_parse_option (option_transform, arg);
854 case option_no_relax:
855 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
856 return md_parse_option (option_no_transform, arg);
857 case option_longcalls:
858 directive_state[directive_longcalls] = TRUE;
859 return 1;
860 case option_no_longcalls:
861 directive_state[directive_longcalls] = FALSE;
862 return 1;
863 case option_text_section_literals:
864 use_literal_section = FALSE;
865 return 1;
866 case option_no_text_section_literals:
867 use_literal_section = TRUE;
868 return 1;
869 case option_absolute_literals:
870 if (!absolute_literals_supported)
871 {
872 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
873 return 0;
874 }
875 directive_state[directive_absolute_literals] = TRUE;
876 return 1;
877 case option_no_absolute_literals:
878 directive_state[directive_absolute_literals] = FALSE;
879 return 1;
880
881 case option_workaround_a0_b_retw:
882 workaround_a0_b_retw = TRUE;
883 return 1;
884 case option_no_workaround_a0_b_retw:
885 workaround_a0_b_retw = FALSE;
886 return 1;
887 case option_workaround_b_j_loop_end:
888 workaround_b_j_loop_end = TRUE;
889 return 1;
890 case option_no_workaround_b_j_loop_end:
891 workaround_b_j_loop_end = FALSE;
892 return 1;
893
894 case option_workaround_short_loop:
895 workaround_short_loop = TRUE;
896 return 1;
897 case option_no_workaround_short_loop:
898 workaround_short_loop = FALSE;
899 return 1;
900
901 case option_workaround_all_short_loops:
902 workaround_all_short_loops = TRUE;
903 return 1;
904 case option_no_workaround_all_short_loops:
905 workaround_all_short_loops = FALSE;
906 return 1;
907
908 case option_workaround_close_loop_end:
909 workaround_close_loop_end = TRUE;
910 return 1;
911 case option_no_workaround_close_loop_end:
912 workaround_close_loop_end = FALSE;
913 return 1;
914
915 case option_no_workarounds:
916 workaround_a0_b_retw = FALSE;
917 workaround_b_j_loop_end = FALSE;
918 workaround_short_loop = FALSE;
919 workaround_all_short_loops = FALSE;
920 workaround_close_loop_end = FALSE;
921 return 1;
922
923 case option_align_targets:
924 align_targets = TRUE;
925 return 1;
926 case option_no_align_targets:
927 align_targets = FALSE;
928 return 1;
929
930 case option_warn_unaligned_targets:
931 warn_unaligned_branch_targets = TRUE;
932 return 1;
933
934 case option_rename_section_name:
935 build_section_rename (arg);
936 return 1;
937
938 case 'Q':
939 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
940 should be emitted or not. FIXME: Not implemented. */
941 return 1;
942
943 case option_prefer_l32r:
944 if (prefer_const16)
945 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
946 prefer_l32r = 1;
947 return 1;
948
949 case option_prefer_const16:
950 if (prefer_l32r)
951 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
952 prefer_const16 = 1;
953 return 1;
954
955 case option_target_hardware:
956 {
957 int earliest, latest = 0;
958 char *end;
959 if (*arg == 0 || *arg == '-')
960 as_fatal (_("invalid target hardware version"));
961
962 earliest = strtol (arg, &end, 0);
963
964 if (*end == 0)
965 latest = earliest;
966 else if (*end == '-')
967 {
968 if (*++end == 0)
969 as_fatal (_("invalid target hardware version"));
970 latest = strtol (end, &end, 0);
971 }
972 if (*end != 0)
973 as_fatal (_("invalid target hardware version"));
974
975 xtensa_setup_hw_workarounds (earliest, latest);
976 return 1;
977 }
978
979 case option_transform:
980 /* This option has no affect other than to use the defaults,
981 which are already set. */
982 return 1;
983
984 case option_no_transform:
985 /* This option turns off all transformations of any kind.
986 However, because we want to preserve the state of other
987 directives, we only change its own field. Thus, before
988 you perform any transformation, always check if transform
989 is available. If you use the functions we provide for this
990 purpose, you will be ok. */
991 directive_state[directive_transform] = FALSE;
992 return 1;
993
994 case option_trampolines:
995 use_trampolines = TRUE;
996 return 1;
997
998 case option_no_trampolines:
999 use_trampolines = FALSE;
1000 return 1;
1001
1002 case option_auto_litpools:
1003 auto_litpools = TRUE;
1004 use_literal_section = FALSE;
1005 if (auto_litpool_limit <= 0)
1006 auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2;
1007 return 1;
1008
1009 case option_no_auto_litpools:
1010 auto_litpools = FALSE;
1011 auto_litpool_limit = -1;
1012 return 1;
1013
1014 case option_auto_litpool_limit:
1015 {
1016 int value = 0;
1017 char *end;
1018 if (auto_litpool_limit < 0)
1019 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1020 if (*arg == 0 || *arg == '-')
1021 as_fatal (_("invalid auto-litpool-limit argument"));
1022 value = strtol (arg, &end, 10);
1023 if (*end != 0)
1024 as_fatal (_("invalid auto-litpool-limit argument"));
1025 if (value < 100 || value > 10000)
1026 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1027 auto_litpool_limit = value;
1028 auto_litpools = TRUE;
1029 use_literal_section = FALSE;
1030 return 1;
1031 }
1032
1033 case option_separate_props:
1034 elf32xtensa_separate_props = TRUE;
1035 return 1;
1036
1037 case option_no_separate_props:
1038 elf32xtensa_separate_props = FALSE;
1039 return 1;
1040
1041 default:
1042 return 0;
1043 }
1044 }
1045
1046
1047 void
md_show_usage(FILE * stream)1048 md_show_usage (FILE *stream)
1049 {
1050 fputs ("\n\
1051 Xtensa options:\n\
1052 --[no-]text-section-literals\n\
1053 [Do not] put literals in the text section\n\
1054 --[no-]absolute-literals\n\
1055 [Do not] default to use non-PC-relative literals\n\
1056 --[no-]target-align [Do not] try to align branch targets\n\
1057 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1058 --[no-]transform [Do not] transform instructions\n\
1059 --flix both allow hand-written and generate flix bundles\n\
1060 --no-generate-flix allow hand-written but do not generate\n\
1061 flix bundles\n\
1062 --no-allow-flix neither allow hand-written nor generate\n\
1063 flix bundles\n\
1064 --rename-section old=new Rename section 'old' to 'new'\n\
1065 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1066 when jumps do not reach their targets\n\
1067 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1068 --auto-litpool-limit=<value>\n\
1069 (range 100-10000) Maximum number of blocks of\n\
1070 instructions to emit between literal pool\n\
1071 locations; implies --auto-litpools flag\n\
1072 --[no-]separate-prop-tables\n\
1073 [Do not] place Xtensa property records into\n\
1074 individual property sections for each section.\n\
1075 Default is to generate single property section.\n", stream);
1076 }
1077
1078
1079 /* Functions related to the list of current label symbols. */
1080
1081 static void
xtensa_add_insn_label(symbolS * sym)1082 xtensa_add_insn_label (symbolS *sym)
1083 {
1084 sym_list *l;
1085
1086 if (!free_insn_labels)
1087 l = XNEW (sym_list);
1088 else
1089 {
1090 l = free_insn_labels;
1091 free_insn_labels = l->next;
1092 }
1093
1094 l->sym = sym;
1095 l->next = insn_labels;
1096 insn_labels = l;
1097 }
1098
1099
1100 static void
xtensa_clear_insn_labels(void)1101 xtensa_clear_insn_labels (void)
1102 {
1103 sym_list **pl;
1104
1105 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1106 ;
1107 *pl = insn_labels;
1108 insn_labels = NULL;
1109 }
1110
1111
1112 static void
xtensa_move_labels(fragS * new_frag,valueT new_offset)1113 xtensa_move_labels (fragS *new_frag, valueT new_offset)
1114 {
1115 sym_list *lit;
1116
1117 for (lit = insn_labels; lit; lit = lit->next)
1118 {
1119 symbolS *lit_sym = lit->sym;
1120 S_SET_VALUE (lit_sym, new_offset);
1121 symbol_set_frag (lit_sym, new_frag);
1122 }
1123 }
1124
1125
1126 /* Directive data and functions. */
1127
1128 typedef struct state_stackS_struct
1129 {
1130 directiveE directive;
1131 bfd_boolean negated;
1132 bfd_boolean old_state;
1133 const char *file;
1134 unsigned int line;
1135 const void *datum;
1136 struct state_stackS_struct *prev;
1137 } state_stackS;
1138
1139 state_stackS *directive_state_stack;
1140
1141 const pseudo_typeS md_pseudo_table[] =
1142 {
1143 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1144 { "literal_position", xtensa_literal_position, 0 },
1145 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1146 { "long", xtensa_elf_cons, 4 },
1147 { "word", xtensa_elf_cons, 4 },
1148 { "4byte", xtensa_elf_cons, 4 },
1149 { "short", xtensa_elf_cons, 2 },
1150 { "2byte", xtensa_elf_cons, 2 },
1151 { "sleb128", xtensa_leb128, 1},
1152 { "uleb128", xtensa_leb128, 0},
1153 { "begin", xtensa_begin_directive, 0 },
1154 { "end", xtensa_end_directive, 0 },
1155 { "literal", xtensa_literal_pseudo, 0 },
1156 { "frequency", xtensa_frequency_pseudo, 0 },
1157 { NULL, 0, 0 },
1158 };
1159
1160
1161 static bfd_boolean
use_transform(void)1162 use_transform (void)
1163 {
1164 /* After md_end, you should be checking frag by frag, rather
1165 than state directives. */
1166 gas_assert (!past_xtensa_end);
1167 return directive_state[directive_transform];
1168 }
1169
1170
1171 static bfd_boolean
do_align_targets(void)1172 do_align_targets (void)
1173 {
1174 /* Do not use this function after md_end; just look at align_targets
1175 instead. There is no target-align directive, so alignment is either
1176 enabled for all frags or not done at all. */
1177 gas_assert (!past_xtensa_end);
1178 return align_targets && use_transform ();
1179 }
1180
1181
1182 static void
directive_push(directiveE directive,bfd_boolean negated,const void * datum)1183 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1184 {
1185 const char *file;
1186 unsigned int line;
1187 state_stackS *stack = XNEW (state_stackS);
1188
1189 file = as_where (&line);
1190
1191 stack->directive = directive;
1192 stack->negated = negated;
1193 stack->old_state = directive_state[directive];
1194 stack->file = file;
1195 stack->line = line;
1196 stack->datum = datum;
1197 stack->prev = directive_state_stack;
1198 directive_state_stack = stack;
1199
1200 directive_state[directive] = !negated;
1201 }
1202
1203
1204 static void
directive_pop(directiveE * directive,bfd_boolean * negated,const char ** file,unsigned int * line,const void ** datum)1205 directive_pop (directiveE *directive,
1206 bfd_boolean *negated,
1207 const char **file,
1208 unsigned int *line,
1209 const void **datum)
1210 {
1211 state_stackS *top = directive_state_stack;
1212
1213 if (!directive_state_stack)
1214 {
1215 as_bad (_("unmatched .end directive"));
1216 *directive = directive_none;
1217 return;
1218 }
1219
1220 directive_state[directive_state_stack->directive] = top->old_state;
1221 *directive = top->directive;
1222 *negated = top->negated;
1223 *file = top->file;
1224 *line = top->line;
1225 *datum = top->datum;
1226 directive_state_stack = top->prev;
1227 free (top);
1228 }
1229
1230
1231 static void
directive_balance(void)1232 directive_balance (void)
1233 {
1234 while (directive_state_stack)
1235 {
1236 directiveE directive;
1237 bfd_boolean negated;
1238 const char *file;
1239 unsigned int line;
1240 const void *datum;
1241
1242 directive_pop (&directive, &negated, &file, &line, &datum);
1243 as_warn_where ((char *) file, line,
1244 _(".begin directive with no matching .end directive"));
1245 }
1246 }
1247
1248
1249 static bfd_boolean
inside_directive(directiveE dir)1250 inside_directive (directiveE dir)
1251 {
1252 state_stackS *top = directive_state_stack;
1253
1254 while (top && top->directive != dir)
1255 top = top->prev;
1256
1257 return (top != NULL);
1258 }
1259
1260
1261 static void
get_directive(directiveE * directive,bfd_boolean * negated)1262 get_directive (directiveE *directive, bfd_boolean *negated)
1263 {
1264 int len;
1265 unsigned i;
1266 const char *directive_string;
1267
1268 if (strncmp (input_line_pointer, "no-", 3) != 0)
1269 *negated = FALSE;
1270 else
1271 {
1272 *negated = TRUE;
1273 input_line_pointer += 3;
1274 }
1275
1276 len = strspn (input_line_pointer,
1277 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1278
1279 /* This code is a hack to make .begin [no-][generics|relax] exactly
1280 equivalent to .begin [no-]transform. We should remove it when
1281 we stop accepting those options. */
1282
1283 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1284 {
1285 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1286 directive_string = "transform";
1287 }
1288 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1289 {
1290 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1291 directive_string = "transform";
1292 }
1293 else
1294 directive_string = input_line_pointer;
1295
1296 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1297 {
1298 if (strncmp (directive_string, directive_info[i].name, len) == 0)
1299 {
1300 input_line_pointer += len;
1301 *directive = (directiveE) i;
1302 if (*negated && !directive_info[i].can_be_negated)
1303 as_bad (_("directive %s cannot be negated"),
1304 directive_info[i].name);
1305 return;
1306 }
1307 }
1308
1309 as_bad (_("unknown directive"));
1310 *directive = (directiveE) XTENSA_UNDEFINED;
1311 }
1312
1313
1314 static void
xtensa_begin_directive(int ignore ATTRIBUTE_UNUSED)1315 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1316 {
1317 directiveE directive;
1318 bfd_boolean negated;
1319 emit_state *state;
1320 lit_state *ls;
1321
1322 get_directive (&directive, &negated);
1323 if (directive == (directiveE) XTENSA_UNDEFINED)
1324 {
1325 discard_rest_of_line ();
1326 return;
1327 }
1328
1329 if (cur_vinsn.inside_bundle)
1330 as_bad (_("directives are not valid inside bundles"));
1331
1332 switch (directive)
1333 {
1334 case directive_literal:
1335 if (!inside_directive (directive_literal))
1336 {
1337 /* Previous labels go with whatever follows this directive, not with
1338 the literal, so save them now. */
1339 saved_insn_labels = insn_labels;
1340 insn_labels = NULL;
1341 }
1342 as_warn (_(".begin literal is deprecated; use .literal instead"));
1343 state = XNEW (emit_state);
1344 xtensa_switch_to_literal_fragment (state);
1345 directive_push (directive_literal, negated, state);
1346 break;
1347
1348 case directive_literal_prefix:
1349 /* Have to flush pending output because a movi relaxed to an l32r
1350 might produce a literal. */
1351 md_flush_pending_output ();
1352 /* Check to see if the current fragment is a literal
1353 fragment. If it is, then this operation is not allowed. */
1354 if (generating_literals)
1355 {
1356 as_bad (_("cannot set literal_prefix inside literal fragment"));
1357 return;
1358 }
1359
1360 /* Allocate the literal state for this section and push
1361 onto the directive stack. */
1362 ls = XNEW (lit_state);
1363 gas_assert (ls);
1364
1365 *ls = default_lit_sections;
1366 directive_push (directive_literal_prefix, negated, ls);
1367
1368 /* Process the new prefix. */
1369 xtensa_literal_prefix ();
1370 break;
1371
1372 case directive_freeregs:
1373 /* This information is currently unused, but we'll accept the statement
1374 and just discard the rest of the line. This won't check the syntax,
1375 but it will accept every correct freeregs directive. */
1376 input_line_pointer += strcspn (input_line_pointer, "\n");
1377 directive_push (directive_freeregs, negated, 0);
1378 break;
1379
1380 case directive_schedule:
1381 md_flush_pending_output ();
1382 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1383 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1384 directive_push (directive_schedule, negated, 0);
1385 xtensa_set_frag_assembly_state (frag_now);
1386 break;
1387
1388 case directive_density:
1389 as_warn (_(".begin [no-]density is ignored"));
1390 break;
1391
1392 case directive_absolute_literals:
1393 md_flush_pending_output ();
1394 if (!absolute_literals_supported && !negated)
1395 {
1396 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1397 break;
1398 }
1399 xtensa_set_frag_assembly_state (frag_now);
1400 directive_push (directive, negated, 0);
1401 break;
1402
1403 default:
1404 md_flush_pending_output ();
1405 xtensa_set_frag_assembly_state (frag_now);
1406 directive_push (directive, negated, 0);
1407 break;
1408 }
1409
1410 demand_empty_rest_of_line ();
1411 }
1412
1413
1414 static void
xtensa_end_directive(int ignore ATTRIBUTE_UNUSED)1415 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1416 {
1417 directiveE begin_directive, end_directive;
1418 bfd_boolean begin_negated, end_negated;
1419 const char *file;
1420 unsigned int line;
1421 emit_state *state;
1422 emit_state **state_ptr;
1423 lit_state *s;
1424
1425 if (cur_vinsn.inside_bundle)
1426 as_bad (_("directives are not valid inside bundles"));
1427
1428 get_directive (&end_directive, &end_negated);
1429
1430 md_flush_pending_output ();
1431
1432 switch ((int) end_directive)
1433 {
1434 case XTENSA_UNDEFINED:
1435 discard_rest_of_line ();
1436 return;
1437
1438 case (int) directive_density:
1439 as_warn (_(".end [no-]density is ignored"));
1440 demand_empty_rest_of_line ();
1441 break;
1442
1443 case (int) directive_absolute_literals:
1444 if (!absolute_literals_supported && !end_negated)
1445 {
1446 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1447 demand_empty_rest_of_line ();
1448 return;
1449 }
1450 break;
1451
1452 default:
1453 break;
1454 }
1455
1456 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1457 directive_pop (&begin_directive, &begin_negated, &file, &line,
1458 (const void **) state_ptr);
1459
1460 if (begin_directive != directive_none)
1461 {
1462 if (begin_directive != end_directive || begin_negated != end_negated)
1463 {
1464 as_bad (_("does not match begin %s%s at %s:%d"),
1465 begin_negated ? "no-" : "",
1466 directive_info[begin_directive].name, file, line);
1467 }
1468 else
1469 {
1470 switch (end_directive)
1471 {
1472 case directive_literal:
1473 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1474 xtensa_restore_emit_state (state);
1475 xtensa_set_frag_assembly_state (frag_now);
1476 free (state);
1477 if (!inside_directive (directive_literal))
1478 {
1479 /* Restore the list of current labels. */
1480 xtensa_clear_insn_labels ();
1481 insn_labels = saved_insn_labels;
1482 }
1483 break;
1484
1485 case directive_literal_prefix:
1486 /* Restore the default collection sections from saved state. */
1487 s = (lit_state *) state;
1488 gas_assert (s);
1489 default_lit_sections = *s;
1490
1491 /* Free the state storage. */
1492 free (s->lit_prefix);
1493 free (s);
1494 break;
1495
1496 case directive_schedule:
1497 case directive_freeregs:
1498 break;
1499
1500 default:
1501 xtensa_set_frag_assembly_state (frag_now);
1502 break;
1503 }
1504 }
1505 }
1506
1507 demand_empty_rest_of_line ();
1508 }
1509
1510
1511 /* Place an aligned literal fragment at the current location. */
1512
1513 static void
xtensa_literal_position(int ignore ATTRIBUTE_UNUSED)1514 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1515 {
1516 md_flush_pending_output ();
1517
1518 if (inside_directive (directive_literal))
1519 as_warn (_(".literal_position inside literal directive; ignoring"));
1520 xtensa_mark_literal_pool_location ();
1521
1522 demand_empty_rest_of_line ();
1523 xtensa_clear_insn_labels ();
1524 }
1525
1526
1527 /* Support .literal label, expr, ... */
1528
1529 static void
xtensa_literal_pseudo(int ignored ATTRIBUTE_UNUSED)1530 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1531 {
1532 emit_state state;
1533 char *p, *base_name;
1534 char c;
1535
1536 if (inside_directive (directive_literal))
1537 {
1538 as_bad (_(".literal not allowed inside .begin literal region"));
1539 ignore_rest_of_line ();
1540 return;
1541 }
1542
1543 md_flush_pending_output ();
1544
1545 /* Previous labels go with whatever follows this directive, not with
1546 the literal, so save them now. */
1547 saved_insn_labels = insn_labels;
1548 insn_labels = NULL;
1549
1550 base_name = input_line_pointer;
1551
1552 xtensa_switch_to_literal_fragment (&state);
1553
1554 /* All literals are aligned to four-byte boundaries. */
1555 frag_align (2, 0, 0);
1556 record_alignment (now_seg, 2);
1557
1558 c = get_symbol_name (&base_name);
1559 /* Just after name is now '\0'. */
1560 p = input_line_pointer;
1561 *p = c;
1562 SKIP_WHITESPACE_AFTER_NAME ();
1563
1564 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1565 {
1566 as_bad (_("expected comma or colon after symbol name; "
1567 "rest of line ignored"));
1568 ignore_rest_of_line ();
1569 xtensa_restore_emit_state (&state);
1570 return;
1571 }
1572
1573 *p = 0;
1574 colon (base_name);
1575 *p = c;
1576
1577 input_line_pointer++; /* skip ',' or ':' */
1578
1579 xtensa_elf_cons (4);
1580
1581 xtensa_restore_emit_state (&state);
1582
1583 /* Restore the list of current labels. */
1584 xtensa_clear_insn_labels ();
1585 insn_labels = saved_insn_labels;
1586 }
1587
1588
1589 static void
xtensa_literal_prefix(void)1590 xtensa_literal_prefix (void)
1591 {
1592 char *name;
1593 int len;
1594
1595 /* Parse the new prefix from the input_line_pointer. */
1596 SKIP_WHITESPACE ();
1597 len = strspn (input_line_pointer,
1598 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1599 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1600
1601 /* Get a null-terminated copy of the name. */
1602 name = xmemdup0 (input_line_pointer, len);
1603
1604 /* Skip the name in the input line. */
1605 input_line_pointer += len;
1606
1607 default_lit_sections.lit_prefix = name;
1608
1609 /* Clear cached literal sections, since the prefix has changed. */
1610 default_lit_sections.lit_seg = NULL;
1611 default_lit_sections.lit4_seg = NULL;
1612 }
1613
1614
1615 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1616
1617 static void
xtensa_frequency_pseudo(int ignored ATTRIBUTE_UNUSED)1618 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1619 {
1620 float fall_through_f, target_f;
1621
1622 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1623 if (fall_through_f < 0)
1624 {
1625 as_bad (_("fall through frequency must be greater than 0"));
1626 ignore_rest_of_line ();
1627 return;
1628 }
1629
1630 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1631 if (target_f < 0)
1632 {
1633 as_bad (_("branch target frequency must be greater than 0"));
1634 ignore_rest_of_line ();
1635 return;
1636 }
1637
1638 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1639
1640 demand_empty_rest_of_line ();
1641 }
1642
1643
1644 /* Like normal .long/.short/.word, except support @plt, etc.
1645 Clobbers input_line_pointer, checks end-of-line. */
1646
1647 static void
xtensa_elf_cons(int nbytes)1648 xtensa_elf_cons (int nbytes)
1649 {
1650 expressionS exp;
1651 bfd_reloc_code_real_type reloc;
1652
1653 md_flush_pending_output ();
1654
1655 if (cur_vinsn.inside_bundle)
1656 as_bad (_("directives are not valid inside bundles"));
1657
1658 if (is_it_end_of_statement ())
1659 {
1660 demand_empty_rest_of_line ();
1661 return;
1662 }
1663
1664 do
1665 {
1666 expression (&exp);
1667 if (exp.X_op == O_symbol
1668 && *input_line_pointer == '@'
1669 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1670 != BFD_RELOC_NONE))
1671 {
1672 reloc_howto_type *reloc_howto =
1673 bfd_reloc_type_lookup (stdoutput, reloc);
1674
1675 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1676 as_bad (_("unsupported relocation"));
1677 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1678 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1679 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1680 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1681 as_bad (_("opcode-specific %s relocation used outside "
1682 "an instruction"), reloc_howto->name);
1683 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1684 as_bad (ngettext ("%s relocations do not fit in %d byte",
1685 "%s relocations do not fit in %d bytes",
1686 nbytes),
1687 reloc_howto->name, nbytes);
1688 else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC
1689 || reloc == BFD_RELOC_XTENSA_TLS_ARG
1690 || reloc == BFD_RELOC_XTENSA_TLS_CALL)
1691 as_bad (_("invalid use of %s relocation"), reloc_howto->name);
1692 else
1693 {
1694 char *p = frag_more ((int) nbytes);
1695 xtensa_set_frag_assembly_state (frag_now);
1696 fix_new_exp (frag_now, p - frag_now->fr_literal,
1697 nbytes, &exp, reloc_howto->pc_relative, reloc);
1698 }
1699 }
1700 else
1701 {
1702 xtensa_set_frag_assembly_state (frag_now);
1703 emit_expr (&exp, (unsigned int) nbytes);
1704 }
1705 }
1706 while (*input_line_pointer++ == ',');
1707
1708 input_line_pointer--; /* Put terminator back into stream. */
1709 demand_empty_rest_of_line ();
1710 }
1711
1712 static bfd_boolean is_leb128_expr;
1713
1714 static void
xtensa_leb128(int sign)1715 xtensa_leb128 (int sign)
1716 {
1717 is_leb128_expr = TRUE;
1718 s_leb128 (sign);
1719 is_leb128_expr = FALSE;
1720 }
1721
1722
1723 /* Parsing and Idiom Translation. */
1724
1725 /* Parse @plt, etc. and return the desired relocation. */
1726 static bfd_reloc_code_real_type
xtensa_elf_suffix(char ** str_p,expressionS * exp_p)1727 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1728 {
1729 char ident[20];
1730 char *str = *str_p;
1731 char *str2;
1732 int ch;
1733 int len;
1734 unsigned int i;
1735
1736 if (*str++ != '@')
1737 return BFD_RELOC_NONE;
1738
1739 for (ch = *str, str2 = ident;
1740 (str2 < ident + sizeof (ident) - 1
1741 && (ISALNUM (ch) || ch == '@'));
1742 ch = *++str)
1743 {
1744 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1745 }
1746
1747 *str2 = '\0';
1748 len = str2 - ident;
1749
1750 ch = ident[0];
1751 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1752 if (ch == suffix_relocs[i].suffix[0]
1753 && len == suffix_relocs[i].length
1754 && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0)
1755 {
1756 /* Now check for "identifier@suffix+constant". */
1757 if (*str == '-' || *str == '+')
1758 {
1759 char *orig_line = input_line_pointer;
1760 expressionS new_exp;
1761
1762 input_line_pointer = str;
1763 expression (&new_exp);
1764 if (new_exp.X_op == O_constant)
1765 {
1766 exp_p->X_add_number += new_exp.X_add_number;
1767 str = input_line_pointer;
1768 }
1769
1770 if (&input_line_pointer != str_p)
1771 input_line_pointer = orig_line;
1772 }
1773
1774 *str_p = str;
1775 return suffix_relocs[i].reloc;
1776 }
1777
1778 return BFD_RELOC_UNUSED;
1779 }
1780
1781
1782 /* Find the matching operator type. */
1783 static operatorT
map_suffix_reloc_to_operator(bfd_reloc_code_real_type reloc)1784 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
1785 {
1786 operatorT operator = O_illegal;
1787 unsigned int i;
1788
1789 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1790 {
1791 if (suffix_relocs[i].reloc == reloc)
1792 {
1793 operator = suffix_relocs[i].operator;
1794 break;
1795 }
1796 }
1797 gas_assert (operator != O_illegal);
1798 return operator;
1799 }
1800
1801
1802 /* Find the matching reloc type. */
1803 static bfd_reloc_code_real_type
map_operator_to_reloc(unsigned char operator,bfd_boolean is_literal)1804 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal)
1805 {
1806 unsigned int i;
1807 bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
1808
1809 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1810 {
1811 if (suffix_relocs[i].operator == operator)
1812 {
1813 reloc = suffix_relocs[i].reloc;
1814 break;
1815 }
1816 }
1817
1818 if (is_literal)
1819 {
1820 if (reloc == BFD_RELOC_XTENSA_TLS_FUNC)
1821 return BFD_RELOC_XTENSA_TLSDESC_FN;
1822 else if (reloc == BFD_RELOC_XTENSA_TLS_ARG)
1823 return BFD_RELOC_XTENSA_TLSDESC_ARG;
1824 }
1825
1826 if (reloc == BFD_RELOC_UNUSED)
1827 return BFD_RELOC_32;
1828
1829 return reloc;
1830 }
1831
1832
1833 static const char *
expression_end(const char * name)1834 expression_end (const char *name)
1835 {
1836 while (1)
1837 {
1838 switch (*name)
1839 {
1840 case '}':
1841 case ';':
1842 case '\0':
1843 case ',':
1844 case ':':
1845 return name;
1846 case ' ':
1847 case '\t':
1848 ++name;
1849 continue;
1850 default:
1851 return 0;
1852 }
1853 }
1854 }
1855
1856
1857 #define ERROR_REG_NUM ((unsigned) -1)
1858
1859 static unsigned
tc_get_register(const char * prefix)1860 tc_get_register (const char *prefix)
1861 {
1862 unsigned reg;
1863 const char *next_expr;
1864 const char *old_line_pointer;
1865
1866 SKIP_WHITESPACE ();
1867 old_line_pointer = input_line_pointer;
1868
1869 if (*input_line_pointer == '$')
1870 ++input_line_pointer;
1871
1872 /* Accept "sp" as a synonym for "a1". */
1873 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1874 && expression_end (input_line_pointer + 2))
1875 {
1876 input_line_pointer += 2;
1877 return 1; /* AR[1] */
1878 }
1879
1880 while (*input_line_pointer++ == *prefix++)
1881 ;
1882 --input_line_pointer;
1883 --prefix;
1884
1885 if (*prefix)
1886 {
1887 as_bad (_("bad register name: %s"), old_line_pointer);
1888 return ERROR_REG_NUM;
1889 }
1890
1891 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1892 {
1893 as_bad (_("bad register number: %s"), input_line_pointer);
1894 return ERROR_REG_NUM;
1895 }
1896
1897 reg = 0;
1898
1899 while (ISDIGIT ((int) *input_line_pointer))
1900 reg = reg * 10 + *input_line_pointer++ - '0';
1901
1902 if (!(next_expr = expression_end (input_line_pointer)))
1903 {
1904 as_bad (_("bad register name: %s"), old_line_pointer);
1905 return ERROR_REG_NUM;
1906 }
1907
1908 input_line_pointer = (char *) next_expr;
1909
1910 return reg;
1911 }
1912
1913
1914 static void
expression_maybe_register(xtensa_opcode opc,int opnd,expressionS * tok)1915 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1916 {
1917 xtensa_isa isa = xtensa_default_isa;
1918
1919 /* Check if this is an immediate operand. */
1920 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1921 {
1922 bfd_reloc_code_real_type reloc;
1923 segT t = expression (tok);
1924
1925 if (t == absolute_section
1926 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1927 {
1928 gas_assert (tok->X_op == O_constant);
1929 tok->X_op = O_symbol;
1930 tok->X_add_symbol = &abs_symbol;
1931 }
1932
1933 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1934 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1935 != BFD_RELOC_NONE))
1936 {
1937 switch (reloc)
1938 {
1939 case BFD_RELOC_LO16:
1940 if (tok->X_op == O_constant)
1941 {
1942 tok->X_add_number &= 0xffff;
1943 return;
1944 }
1945 break;
1946 case BFD_RELOC_HI16:
1947 if (tok->X_op == O_constant)
1948 {
1949 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1950 return;
1951 }
1952 break;
1953 case BFD_RELOC_UNUSED:
1954 as_bad (_("unsupported relocation"));
1955 return;
1956 case BFD_RELOC_32_PCREL:
1957 as_bad (_("pcrel relocation not allowed in an instruction"));
1958 return;
1959 default:
1960 break;
1961 }
1962 tok->X_op = map_suffix_reloc_to_operator (reloc);
1963 }
1964 }
1965 else
1966 {
1967 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1968 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1969
1970 if (reg != ERROR_REG_NUM) /* Already errored */
1971 {
1972 uint32 buf = reg;
1973 if (xtensa_operand_encode (isa, opc, opnd, &buf))
1974 as_bad (_("register number out of range"));
1975 }
1976
1977 tok->X_op = O_register;
1978 tok->X_add_symbol = 0;
1979 tok->X_add_number = reg;
1980 }
1981 }
1982
1983
1984 /* Split up the arguments for an opcode or pseudo-op. */
1985
1986 static int
tokenize_arguments(char ** args,char * str)1987 tokenize_arguments (char **args, char *str)
1988 {
1989 char *old_input_line_pointer;
1990 bfd_boolean saw_comma = FALSE;
1991 bfd_boolean saw_arg = FALSE;
1992 bfd_boolean saw_colon = FALSE;
1993 int num_args = 0;
1994 char *arg_end, *arg;
1995 int arg_len;
1996
1997 /* Save and restore input_line_pointer around this function. */
1998 old_input_line_pointer = input_line_pointer;
1999 input_line_pointer = str;
2000
2001 while (*input_line_pointer)
2002 {
2003 SKIP_WHITESPACE ();
2004 switch (*input_line_pointer)
2005 {
2006 case '\0':
2007 case '}':
2008 goto fini;
2009
2010 case ':':
2011 input_line_pointer++;
2012 if (saw_comma || saw_colon || !saw_arg)
2013 goto err;
2014 saw_colon = TRUE;
2015 break;
2016
2017 case ',':
2018 input_line_pointer++;
2019 if (saw_comma || saw_colon || !saw_arg)
2020 goto err;
2021 saw_comma = TRUE;
2022 break;
2023
2024 default:
2025 if (!saw_comma && !saw_colon && saw_arg)
2026 goto err;
2027
2028 arg_end = input_line_pointer + 1;
2029 while (!expression_end (arg_end))
2030 arg_end += 1;
2031
2032 arg_len = arg_end - input_line_pointer;
2033 arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1);
2034 args[num_args] = arg;
2035
2036 if (saw_colon)
2037 *arg++ = ':';
2038 strncpy (arg, input_line_pointer, arg_len);
2039 arg[arg_len] = '\0';
2040
2041 input_line_pointer = arg_end;
2042 num_args += 1;
2043 saw_comma = FALSE;
2044 saw_colon = FALSE;
2045 saw_arg = TRUE;
2046 break;
2047 }
2048 }
2049
2050 fini:
2051 if (saw_comma || saw_colon)
2052 goto err;
2053 input_line_pointer = old_input_line_pointer;
2054 return num_args;
2055
2056 err:
2057 if (saw_comma)
2058 as_bad (_("extra comma"));
2059 else if (saw_colon)
2060 as_bad (_("extra colon"));
2061 else if (!saw_arg)
2062 as_bad (_("missing argument"));
2063 else
2064 as_bad (_("missing comma or colon"));
2065 input_line_pointer = old_input_line_pointer;
2066 return -1;
2067 }
2068
2069
2070 /* Parse the arguments to an opcode. Return TRUE on error. */
2071
2072 static bfd_boolean
parse_arguments(TInsn * insn,int num_args,char ** arg_strings)2073 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
2074 {
2075 expressionS *tok, *last_tok;
2076 xtensa_opcode opcode = insn->opcode;
2077 bfd_boolean had_error = TRUE;
2078 xtensa_isa isa = xtensa_default_isa;
2079 int n, num_regs = 0;
2080 int opcode_operand_count;
2081 int opnd_cnt, last_opnd_cnt;
2082 unsigned int next_reg = 0;
2083 char *old_input_line_pointer;
2084
2085 if (insn->insn_type == ITYPE_LITERAL)
2086 opcode_operand_count = 1;
2087 else
2088 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
2089
2090 tok = insn->tok;
2091 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
2092
2093 /* Save and restore input_line_pointer around this function. */
2094 old_input_line_pointer = input_line_pointer;
2095
2096 last_tok = 0;
2097 last_opnd_cnt = -1;
2098 opnd_cnt = 0;
2099
2100 /* Skip invisible operands. */
2101 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2102 {
2103 opnd_cnt += 1;
2104 tok++;
2105 }
2106
2107 for (n = 0; n < num_args; n++)
2108 {
2109 input_line_pointer = arg_strings[n];
2110 if (*input_line_pointer == ':')
2111 {
2112 xtensa_regfile opnd_rf;
2113 input_line_pointer++;
2114 if (num_regs == 0)
2115 goto err;
2116 gas_assert (opnd_cnt > 0);
2117 num_regs--;
2118 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2119 if (next_reg
2120 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2121 as_warn (_("incorrect register number, ignoring"));
2122 next_reg++;
2123 }
2124 else
2125 {
2126 if (opnd_cnt >= opcode_operand_count)
2127 {
2128 as_warn (_("too many arguments"));
2129 goto err;
2130 }
2131 gas_assert (opnd_cnt < MAX_INSN_ARGS);
2132
2133 expression_maybe_register (opcode, opnd_cnt, tok);
2134 next_reg = tok->X_add_number + 1;
2135
2136 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2137 goto err;
2138 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2139 {
2140 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2141 /* minus 1 because we are seeing one right now */
2142 }
2143 else
2144 num_regs = 0;
2145
2146 last_tok = tok;
2147 last_opnd_cnt = opnd_cnt;
2148 demand_empty_rest_of_line ();
2149
2150 do
2151 {
2152 opnd_cnt += 1;
2153 tok++;
2154 }
2155 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2156 }
2157 }
2158
2159 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2160 goto err;
2161
2162 insn->ntok = tok - insn->tok;
2163 had_error = FALSE;
2164
2165 err:
2166 input_line_pointer = old_input_line_pointer;
2167 return had_error;
2168 }
2169
2170
2171 static int
get_invisible_operands(TInsn * insn)2172 get_invisible_operands (TInsn *insn)
2173 {
2174 xtensa_isa isa = xtensa_default_isa;
2175 static xtensa_insnbuf slotbuf = NULL;
2176 xtensa_format fmt;
2177 xtensa_opcode opc = insn->opcode;
2178 int slot, opnd, fmt_found;
2179 unsigned val;
2180
2181 if (!slotbuf)
2182 slotbuf = xtensa_insnbuf_alloc (isa);
2183
2184 /* Find format/slot where this can be encoded. */
2185 fmt_found = 0;
2186 slot = 0;
2187 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2188 {
2189 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2190 {
2191 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2192 {
2193 fmt_found = 1;
2194 break;
2195 }
2196 }
2197 if (fmt_found) break;
2198 }
2199
2200 if (!fmt_found)
2201 {
2202 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2203 return -1;
2204 }
2205
2206 /* First encode all the visible operands
2207 (to deal with shared field operands). */
2208 for (opnd = 0; opnd < insn->ntok; opnd++)
2209 {
2210 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2211 && (insn->tok[opnd].X_op == O_register
2212 || insn->tok[opnd].X_op == O_constant))
2213 {
2214 val = insn->tok[opnd].X_add_number;
2215 xtensa_operand_encode (isa, opc, opnd, &val);
2216 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2217 }
2218 }
2219
2220 /* Then pull out the values for the invisible ones. */
2221 for (opnd = 0; opnd < insn->ntok; opnd++)
2222 {
2223 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2224 {
2225 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2226 xtensa_operand_decode (isa, opc, opnd, &val);
2227 insn->tok[opnd].X_add_number = val;
2228 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2229 insn->tok[opnd].X_op = O_register;
2230 else
2231 insn->tok[opnd].X_op = O_constant;
2232 }
2233 }
2234
2235 return 0;
2236 }
2237
2238
2239 static void
xg_reverse_shift_count(char ** cnt_argp)2240 xg_reverse_shift_count (char **cnt_argp)
2241 {
2242 char *cnt_arg, *new_arg;
2243 cnt_arg = *cnt_argp;
2244
2245 /* replace the argument with "31-(argument)" */
2246 new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL);
2247
2248 free (cnt_arg);
2249 *cnt_argp = new_arg;
2250 }
2251
2252
2253 /* If "arg" is a constant expression, return non-zero with the value
2254 in *valp. */
2255
2256 static int
xg_arg_is_constant(char * arg,offsetT * valp)2257 xg_arg_is_constant (char *arg, offsetT *valp)
2258 {
2259 expressionS exp;
2260 char *save_ptr = input_line_pointer;
2261
2262 input_line_pointer = arg;
2263 expression (&exp);
2264 input_line_pointer = save_ptr;
2265
2266 if (exp.X_op == O_constant)
2267 {
2268 *valp = exp.X_add_number;
2269 return 1;
2270 }
2271
2272 return 0;
2273 }
2274
2275
2276 static void
xg_replace_opname(char ** popname,const char * newop)2277 xg_replace_opname (char **popname, const char *newop)
2278 {
2279 free (*popname);
2280 *popname = xstrdup (newop);
2281 }
2282
2283
2284 static int
xg_check_num_args(int * pnum_args,int expected_num,char * opname,char ** arg_strings)2285 xg_check_num_args (int *pnum_args,
2286 int expected_num,
2287 char *opname,
2288 char **arg_strings)
2289 {
2290 int num_args = *pnum_args;
2291
2292 if (num_args < expected_num)
2293 {
2294 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2295 num_args, opname, expected_num);
2296 return -1;
2297 }
2298
2299 if (num_args > expected_num)
2300 {
2301 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2302 num_args, opname, expected_num);
2303 while (num_args-- > expected_num)
2304 {
2305 free (arg_strings[num_args]);
2306 arg_strings[num_args] = 0;
2307 }
2308 *pnum_args = expected_num;
2309 return -1;
2310 }
2311
2312 return 0;
2313 }
2314
2315
2316 /* If the register is not specified as part of the opcode,
2317 then get it from the operand and move it to the opcode. */
2318
2319 static int
xg_translate_sysreg_op(char ** popname,int * pnum_args,char ** arg_strings)2320 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2321 {
2322 xtensa_isa isa = xtensa_default_isa;
2323 xtensa_sysreg sr;
2324 char *opname, *new_opname;
2325 const char *sr_name;
2326 int is_user, is_write;
2327
2328 opname = *popname;
2329 if (*opname == '_')
2330 opname += 1;
2331 is_user = (opname[1] == 'u');
2332 is_write = (opname[0] == 'w');
2333
2334 /* Opname == [rw]ur or [rwx]sr... */
2335
2336 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2337 return -1;
2338
2339 /* Check if the argument is a symbolic register name. */
2340 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2341 /* Handle WSR to "INTSET" as a special case. */
2342 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2343 && !strcasecmp (arg_strings[1], "intset"))
2344 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2345 if (sr == XTENSA_UNDEFINED
2346 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2347 {
2348 /* Maybe it's a register number.... */
2349 offsetT val;
2350 if (!xg_arg_is_constant (arg_strings[1], &val))
2351 {
2352 as_bad (_("invalid register '%s' for '%s' instruction"),
2353 arg_strings[1], opname);
2354 return -1;
2355 }
2356 sr = xtensa_sysreg_lookup (isa, val, is_user);
2357 if (sr == XTENSA_UNDEFINED)
2358 {
2359 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2360 (long) val, opname);
2361 return -1;
2362 }
2363 }
2364
2365 /* Remove the last argument, which is now part of the opcode. */
2366 free (arg_strings[1]);
2367 arg_strings[1] = 0;
2368 *pnum_args = 1;
2369
2370 /* Translate the opcode. */
2371 sr_name = xtensa_sysreg_name (isa, sr);
2372 /* Another special case for "WSR.INTSET".... */
2373 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2374 sr_name = "intset";
2375 new_opname = concat (*popname, ".", sr_name, (char *) NULL);
2376 free (*popname);
2377 *popname = new_opname;
2378
2379 return 0;
2380 }
2381
2382
2383 static int
xtensa_translate_old_userreg_ops(char ** popname)2384 xtensa_translate_old_userreg_ops (char **popname)
2385 {
2386 xtensa_isa isa = xtensa_default_isa;
2387 xtensa_sysreg sr;
2388 char *opname, *new_opname;
2389 const char *sr_name;
2390 bfd_boolean has_underbar = FALSE;
2391
2392 opname = *popname;
2393 if (opname[0] == '_')
2394 {
2395 has_underbar = TRUE;
2396 opname += 1;
2397 }
2398
2399 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2400 if (sr != XTENSA_UNDEFINED)
2401 {
2402 /* The new default name ("nnn") is different from the old default
2403 name ("URnnn"). The old default is handled below, and we don't
2404 want to recognize [RW]nnn, so do nothing if the name is the (new)
2405 default. */
2406 static char namebuf[10];
2407 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2408 if (strcmp (namebuf, opname + 1) == 0)
2409 return 0;
2410 }
2411 else
2412 {
2413 offsetT val;
2414 char *end;
2415
2416 /* Only continue if the reg name is "URnnn". */
2417 if (opname[1] != 'u' || opname[2] != 'r')
2418 return 0;
2419 val = strtoul (opname + 3, &end, 10);
2420 if (*end != '\0')
2421 return 0;
2422
2423 sr = xtensa_sysreg_lookup (isa, val, 1);
2424 if (sr == XTENSA_UNDEFINED)
2425 {
2426 as_bad (_("invalid register number (%ld) for '%s'"),
2427 (long) val, opname);
2428 return -1;
2429 }
2430 }
2431
2432 /* Translate the opcode. */
2433 sr_name = xtensa_sysreg_name (isa, sr);
2434 new_opname = XNEWVEC (char, strlen (sr_name) + 6);
2435 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2436 opname[0], sr_name);
2437 free (*popname);
2438 *popname = new_opname;
2439
2440 return 0;
2441 }
2442
2443
2444 static int
xtensa_translate_zero_immed(const char * old_op,const char * new_op,char ** popname,int * pnum_args,char ** arg_strings)2445 xtensa_translate_zero_immed (const char *old_op,
2446 const char *new_op,
2447 char **popname,
2448 int *pnum_args,
2449 char **arg_strings)
2450 {
2451 char *opname;
2452 offsetT val;
2453
2454 opname = *popname;
2455 gas_assert (opname[0] != '_');
2456
2457 if (strcmp (opname, old_op) != 0)
2458 return 0;
2459
2460 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2461 return -1;
2462 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2463 {
2464 xg_replace_opname (popname, new_op);
2465 free (arg_strings[1]);
2466 arg_strings[1] = arg_strings[2];
2467 arg_strings[2] = 0;
2468 *pnum_args = 2;
2469 }
2470
2471 return 0;
2472 }
2473
2474
2475 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2476 Returns non-zero if an error was found. */
2477
2478 static int
xg_translate_idioms(char ** popname,int * pnum_args,char ** arg_strings)2479 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2480 {
2481 char *opname = *popname;
2482 bfd_boolean has_underbar = FALSE;
2483
2484 if (*opname == '_')
2485 {
2486 has_underbar = TRUE;
2487 opname += 1;
2488 }
2489
2490 if (strcmp (opname, "mov") == 0)
2491 {
2492 if (use_transform () && !has_underbar && density_supported)
2493 xg_replace_opname (popname, "mov.n");
2494 else
2495 {
2496 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2497 return -1;
2498 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2499 arg_strings[2] = xstrdup (arg_strings[1]);
2500 *pnum_args = 3;
2501 }
2502 return 0;
2503 }
2504
2505 if (strcmp (opname, "bbsi.l") == 0)
2506 {
2507 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2508 return -1;
2509 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2510 if (target_big_endian)
2511 xg_reverse_shift_count (&arg_strings[1]);
2512 return 0;
2513 }
2514
2515 if (strcmp (opname, "bbci.l") == 0)
2516 {
2517 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2518 return -1;
2519 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2520 if (target_big_endian)
2521 xg_reverse_shift_count (&arg_strings[1]);
2522 return 0;
2523 }
2524
2525 /* Don't do anything special with NOPs inside FLIX instructions. They
2526 are handled elsewhere. Real NOP instructions are always available
2527 in configurations with FLIX, so this should never be an issue but
2528 check for it anyway. */
2529 if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
2530 && strcmp (opname, "nop") == 0)
2531 {
2532 if (use_transform () && !has_underbar && density_supported)
2533 xg_replace_opname (popname, "nop.n");
2534 else
2535 {
2536 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2537 return -1;
2538 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2539 arg_strings[0] = xstrdup ("a1");
2540 arg_strings[1] = xstrdup ("a1");
2541 arg_strings[2] = xstrdup ("a1");
2542 *pnum_args = 3;
2543 }
2544 return 0;
2545 }
2546
2547 /* Recognize [RW]UR and [RWX]SR. */
2548 if ((((opname[0] == 'r' || opname[0] == 'w')
2549 && (opname[1] == 'u' || opname[1] == 's'))
2550 || (opname[0] == 'x' && opname[1] == 's'))
2551 && opname[2] == 'r'
2552 && opname[3] == '\0')
2553 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2554
2555 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2556 [RW]<name> if <name> is the non-default name of a user register. */
2557 if ((opname[0] == 'r' || opname[0] == 'w')
2558 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2559 return xtensa_translate_old_userreg_ops (popname);
2560
2561 /* Relax branches that don't allow comparisons against an immediate value
2562 of zero to the corresponding branches with implicit zero immediates. */
2563 if (!has_underbar && use_transform ())
2564 {
2565 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2566 pnum_args, arg_strings))
2567 return -1;
2568
2569 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2570 pnum_args, arg_strings))
2571 return -1;
2572
2573 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2574 pnum_args, arg_strings))
2575 return -1;
2576
2577 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2578 pnum_args, arg_strings))
2579 return -1;
2580 }
2581
2582 return 0;
2583 }
2584
2585
2586 /* Functions for dealing with the Xtensa ISA. */
2587
2588 /* Currently the assembler only allows us to use a single target per
2589 fragment. Because of this, only one operand for a given
2590 instruction may be symbolic. If there is a PC-relative operand,
2591 the last one is chosen. Otherwise, the result is the number of the
2592 last immediate operand, and if there are none of those, we fail and
2593 return -1. */
2594
2595 static int
get_relaxable_immed(xtensa_opcode opcode)2596 get_relaxable_immed (xtensa_opcode opcode)
2597 {
2598 int last_immed = -1;
2599 int noperands, opi;
2600
2601 if (opcode == XTENSA_UNDEFINED)
2602 return -1;
2603
2604 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2605 for (opi = noperands - 1; opi >= 0; opi--)
2606 {
2607 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2608 continue;
2609 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2610 return opi;
2611 if (last_immed == -1
2612 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2613 last_immed = opi;
2614 }
2615 return last_immed;
2616 }
2617
2618
2619 static xtensa_opcode
get_opcode_from_buf(const char * buf,int slot)2620 get_opcode_from_buf (const char *buf, int slot)
2621 {
2622 static xtensa_insnbuf insnbuf = NULL;
2623 static xtensa_insnbuf slotbuf = NULL;
2624 xtensa_isa isa = xtensa_default_isa;
2625 xtensa_format fmt;
2626
2627 if (!insnbuf)
2628 {
2629 insnbuf = xtensa_insnbuf_alloc (isa);
2630 slotbuf = xtensa_insnbuf_alloc (isa);
2631 }
2632
2633 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
2634 fmt = xtensa_format_decode (isa, insnbuf);
2635 if (fmt == XTENSA_UNDEFINED)
2636 return XTENSA_UNDEFINED;
2637
2638 if (slot >= xtensa_format_num_slots (isa, fmt))
2639 return XTENSA_UNDEFINED;
2640
2641 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2642 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2643 }
2644
2645
2646 #ifdef TENSILICA_DEBUG
2647
2648 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2649
2650 static void
xtensa_print_insn_table(void)2651 xtensa_print_insn_table (void)
2652 {
2653 int num_opcodes, num_operands;
2654 xtensa_opcode opcode;
2655 xtensa_isa isa = xtensa_default_isa;
2656
2657 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2658 for (opcode = 0; opcode < num_opcodes; opcode++)
2659 {
2660 int opn;
2661 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2662 num_operands = xtensa_opcode_num_operands (isa, opcode);
2663 for (opn = 0; opn < num_operands; opn++)
2664 {
2665 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2666 continue;
2667 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2668 {
2669 xtensa_regfile opnd_rf =
2670 xtensa_operand_regfile (isa, opcode, opn);
2671 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2672 }
2673 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2674 fputs ("[lLr] ", stderr);
2675 else
2676 fputs ("i ", stderr);
2677 }
2678 fprintf (stderr, "\n");
2679 }
2680 }
2681
2682
2683 static void
print_vliw_insn(xtensa_insnbuf vbuf)2684 print_vliw_insn (xtensa_insnbuf vbuf)
2685 {
2686 xtensa_isa isa = xtensa_default_isa;
2687 xtensa_format f = xtensa_format_decode (isa, vbuf);
2688 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2689 int op;
2690
2691 fprintf (stderr, "format = %d\n", f);
2692
2693 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2694 {
2695 xtensa_opcode opcode;
2696 const char *opname;
2697 int operands;
2698
2699 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2700 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2701 opname = xtensa_opcode_name (isa, opcode);
2702
2703 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2704 fprintf (stderr, " operands = ");
2705 for (operands = 0;
2706 operands < xtensa_opcode_num_operands (isa, opcode);
2707 operands++)
2708 {
2709 unsigned int val;
2710 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2711 continue;
2712 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2713 xtensa_operand_decode (isa, opcode, operands, &val);
2714 fprintf (stderr, "%d ", val);
2715 }
2716 fprintf (stderr, "\n");
2717 }
2718 xtensa_insnbuf_free (isa, sbuf);
2719 }
2720
2721 #endif /* TENSILICA_DEBUG */
2722
2723
2724 static bfd_boolean
is_direct_call_opcode(xtensa_opcode opcode)2725 is_direct_call_opcode (xtensa_opcode opcode)
2726 {
2727 xtensa_isa isa = xtensa_default_isa;
2728 int n, num_operands;
2729
2730 if (xtensa_opcode_is_call (isa, opcode) != 1)
2731 return FALSE;
2732
2733 num_operands = xtensa_opcode_num_operands (isa, opcode);
2734 for (n = 0; n < num_operands; n++)
2735 {
2736 if (xtensa_operand_is_register (isa, opcode, n) == 0
2737 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2738 return TRUE;
2739 }
2740 return FALSE;
2741 }
2742
2743
2744 /* Convert from BFD relocation type code to slot and operand number.
2745 Returns non-zero on failure. */
2746
2747 static int
decode_reloc(bfd_reloc_code_real_type reloc,int * slot,bfd_boolean * is_alt)2748 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2749 {
2750 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2751 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2752 {
2753 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2754 *is_alt = FALSE;
2755 }
2756 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2757 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2758 {
2759 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2760 *is_alt = TRUE;
2761 }
2762 else
2763 return -1;
2764
2765 return 0;
2766 }
2767
2768
2769 /* Convert from slot number to BFD relocation type code for the
2770 standard PC-relative relocations. Return BFD_RELOC_NONE on
2771 failure. */
2772
2773 static bfd_reloc_code_real_type
encode_reloc(int slot)2774 encode_reloc (int slot)
2775 {
2776 if (slot < 0 || slot > 14)
2777 return BFD_RELOC_NONE;
2778
2779 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2780 }
2781
2782
2783 /* Convert from slot numbers to BFD relocation type code for the
2784 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2785
2786 static bfd_reloc_code_real_type
encode_alt_reloc(int slot)2787 encode_alt_reloc (int slot)
2788 {
2789 if (slot < 0 || slot > 14)
2790 return BFD_RELOC_NONE;
2791
2792 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2793 }
2794
2795
2796 static void
xtensa_insnbuf_set_operand(xtensa_insnbuf slotbuf,xtensa_format fmt,int slot,xtensa_opcode opcode,int operand,uint32 value,const char * file,unsigned int line)2797 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2798 xtensa_format fmt,
2799 int slot,
2800 xtensa_opcode opcode,
2801 int operand,
2802 uint32 value,
2803 const char *file,
2804 unsigned int line)
2805 {
2806 uint32 valbuf = value;
2807
2808 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2809 {
2810 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2811 == 1)
2812 as_bad_where ((char *) file, line,
2813 _("operand %d of '%s' has out of range value '%u'"),
2814 operand + 1,
2815 xtensa_opcode_name (xtensa_default_isa, opcode),
2816 value);
2817 else
2818 as_bad_where ((char *) file, line,
2819 _("operand %d of '%s' has invalid value '%u'"),
2820 operand + 1,
2821 xtensa_opcode_name (xtensa_default_isa, opcode),
2822 value);
2823 return;
2824 }
2825
2826 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2827 slotbuf, valbuf);
2828 }
2829
2830
2831 static uint32
xtensa_insnbuf_get_operand(xtensa_insnbuf slotbuf,xtensa_format fmt,int slot,xtensa_opcode opcode,int opnum)2832 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2833 xtensa_format fmt,
2834 int slot,
2835 xtensa_opcode opcode,
2836 int opnum)
2837 {
2838 uint32 val = 0;
2839 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2840 fmt, slot, slotbuf, &val);
2841 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2842 return val;
2843 }
2844
2845
2846 /* Checks for rules from xtensa-relax tables. */
2847
2848 /* The routine xg_instruction_matches_option_term must return TRUE
2849 when a given option term is true. The meaning of all of the option
2850 terms is given interpretation by this function. */
2851
2852 static bfd_boolean
xg_instruction_matches_option_term(TInsn * insn,const ReqOrOption * option)2853 xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
2854 {
2855 if (strcmp (option->option_name, "realnop") == 0
2856 || strncmp (option->option_name, "IsaUse", 6) == 0)
2857 {
2858 /* These conditions were evaluated statically when building the
2859 relaxation table. There's no need to reevaluate them now. */
2860 return TRUE;
2861 }
2862 else if (strcmp (option->option_name, "FREEREG") == 0)
2863 return insn->extra_arg.X_op == O_register;
2864 else
2865 {
2866 as_fatal (_("internal error: unknown option name '%s'"),
2867 option->option_name);
2868 }
2869 }
2870
2871
2872 static bfd_boolean
xg_instruction_matches_or_options(TInsn * insn,const ReqOrOptionList * or_option)2873 xg_instruction_matches_or_options (TInsn *insn,
2874 const ReqOrOptionList *or_option)
2875 {
2876 const ReqOrOption *option;
2877 /* Must match each of the AND terms. */
2878 for (option = or_option; option != NULL; option = option->next)
2879 {
2880 if (xg_instruction_matches_option_term (insn, option))
2881 return TRUE;
2882 }
2883 return FALSE;
2884 }
2885
2886
2887 static bfd_boolean
xg_instruction_matches_options(TInsn * insn,const ReqOptionList * options)2888 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2889 {
2890 const ReqOption *req_options;
2891 /* Must match each of the AND terms. */
2892 for (req_options = options;
2893 req_options != NULL;
2894 req_options = req_options->next)
2895 {
2896 /* Must match one of the OR clauses. */
2897 if (!xg_instruction_matches_or_options (insn,
2898 req_options->or_option_terms))
2899 return FALSE;
2900 }
2901 return TRUE;
2902 }
2903
2904
2905 /* Return the transition rule that matches or NULL if none matches. */
2906
2907 static bfd_boolean
xg_instruction_matches_rule(TInsn * insn,TransitionRule * rule)2908 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2909 {
2910 PreconditionList *condition_l;
2911
2912 if (rule->opcode != insn->opcode)
2913 return FALSE;
2914
2915 for (condition_l = rule->conditions;
2916 condition_l != NULL;
2917 condition_l = condition_l->next)
2918 {
2919 expressionS *exp1;
2920 expressionS *exp2;
2921 Precondition *cond = condition_l->precond;
2922
2923 switch (cond->typ)
2924 {
2925 case OP_CONSTANT:
2926 /* The expression must be the constant. */
2927 gas_assert (cond->op_num < insn->ntok);
2928 exp1 = &insn->tok[cond->op_num];
2929 if (expr_is_const (exp1))
2930 {
2931 switch (cond->cmp)
2932 {
2933 case OP_EQUAL:
2934 if (get_expr_const (exp1) != cond->op_data)
2935 return FALSE;
2936 break;
2937 case OP_NOTEQUAL:
2938 if (get_expr_const (exp1) == cond->op_data)
2939 return FALSE;
2940 break;
2941 default:
2942 return FALSE;
2943 }
2944 }
2945 else if (expr_is_register (exp1))
2946 {
2947 switch (cond->cmp)
2948 {
2949 case OP_EQUAL:
2950 if (get_expr_register (exp1) != cond->op_data)
2951 return FALSE;
2952 break;
2953 case OP_NOTEQUAL:
2954 if (get_expr_register (exp1) == cond->op_data)
2955 return FALSE;
2956 break;
2957 default:
2958 return FALSE;
2959 }
2960 }
2961 else
2962 return FALSE;
2963 break;
2964
2965 case OP_OPERAND:
2966 gas_assert (cond->op_num < insn->ntok);
2967 gas_assert (cond->op_data < insn->ntok);
2968 exp1 = &insn->tok[cond->op_num];
2969 exp2 = &insn->tok[cond->op_data];
2970
2971 switch (cond->cmp)
2972 {
2973 case OP_EQUAL:
2974 if (!expr_is_equal (exp1, exp2))
2975 return FALSE;
2976 break;
2977 case OP_NOTEQUAL:
2978 if (expr_is_equal (exp1, exp2))
2979 return FALSE;
2980 break;
2981 }
2982 break;
2983
2984 case OP_LITERAL:
2985 case OP_LABEL:
2986 default:
2987 return FALSE;
2988 }
2989 }
2990 if (!xg_instruction_matches_options (insn, rule->options))
2991 return FALSE;
2992
2993 return TRUE;
2994 }
2995
2996
2997 static int
transition_rule_cmp(const TransitionRule * a,const TransitionRule * b)2998 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2999 {
3000 bfd_boolean a_greater = FALSE;
3001 bfd_boolean b_greater = FALSE;
3002
3003 ReqOptionList *l_a = a->options;
3004 ReqOptionList *l_b = b->options;
3005
3006 /* We only care if they both are the same except for
3007 a const16 vs. an l32r. */
3008
3009 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3010 {
3011 ReqOrOptionList *l_or_a = l_a->or_option_terms;
3012 ReqOrOptionList *l_or_b = l_b->or_option_terms;
3013 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3014 {
3015 if (l_or_a->is_true != l_or_b->is_true)
3016 return 0;
3017 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
3018 {
3019 /* This is the case we care about. */
3020 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
3021 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
3022 {
3023 if (prefer_const16)
3024 a_greater = TRUE;
3025 else
3026 b_greater = TRUE;
3027 }
3028 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
3029 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
3030 {
3031 if (prefer_const16)
3032 b_greater = TRUE;
3033 else
3034 a_greater = TRUE;
3035 }
3036 else
3037 return 0;
3038 }
3039 l_or_a = l_or_a->next;
3040 l_or_b = l_or_b->next;
3041 }
3042 if (l_or_a || l_or_b)
3043 return 0;
3044
3045 l_a = l_a->next;
3046 l_b = l_b->next;
3047 }
3048 if (l_a || l_b)
3049 return 0;
3050
3051 /* Incomparable if the substitution was used differently in two cases. */
3052 if (a_greater && b_greater)
3053 return 0;
3054
3055 if (b_greater)
3056 return 1;
3057 if (a_greater)
3058 return -1;
3059
3060 return 0;
3061 }
3062
3063
3064 static TransitionRule *
xg_instruction_match(TInsn * insn)3065 xg_instruction_match (TInsn *insn)
3066 {
3067 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
3068 TransitionList *l;
3069 gas_assert (insn->opcode < table->num_opcodes);
3070
3071 /* Walk through all of the possible transitions. */
3072 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3073 {
3074 TransitionRule *rule = l->rule;
3075 if (xg_instruction_matches_rule (insn, rule))
3076 return rule;
3077 }
3078 return NULL;
3079 }
3080
3081
3082 /* Various Other Internal Functions. */
3083
3084 static bfd_boolean
is_unique_insn_expansion(TransitionRule * r)3085 is_unique_insn_expansion (TransitionRule *r)
3086 {
3087 if (!r->to_instr || r->to_instr->next != NULL)
3088 return FALSE;
3089 if (r->to_instr->typ != INSTR_INSTR)
3090 return FALSE;
3091 return TRUE;
3092 }
3093
3094
3095 /* Check if there is exactly one relaxation for INSN that converts it to
3096 another instruction of equal or larger size. If so, and if TARG is
3097 non-null, go ahead and generate the relaxed instruction into TARG. If
3098 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3099 instruction, i.e., ignore relaxations that convert to an instruction of
3100 equal size. In some contexts where this function is used, only
3101 a single widening is allowed and the NARROW_ONLY argument is used to
3102 exclude cases like ADDI being "widened" to an ADDMI, which may
3103 later be relaxed to an ADDMI/ADDI pair. */
3104
3105 bfd_boolean
xg_is_single_relaxable_insn(TInsn * insn,TInsn * targ,bfd_boolean narrow_only)3106 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
3107 {
3108 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3109 TransitionList *l;
3110 TransitionRule *match = 0;
3111
3112 gas_assert (insn->insn_type == ITYPE_INSN);
3113 gas_assert (insn->opcode < table->num_opcodes);
3114
3115 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3116 {
3117 TransitionRule *rule = l->rule;
3118
3119 if (xg_instruction_matches_rule (insn, rule)
3120 && is_unique_insn_expansion (rule)
3121 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
3122 <= xg_get_single_size (rule->to_instr->opcode)))
3123 {
3124 if (match)
3125 return FALSE;
3126 match = rule;
3127 }
3128 }
3129 if (!match)
3130 return FALSE;
3131
3132 if (targ)
3133 xg_build_to_insn (targ, insn, match->to_instr);
3134 return TRUE;
3135 }
3136
3137
3138 /* Return the maximum number of bytes this opcode can expand to. */
3139
3140 static int
xg_get_max_insn_widen_size(xtensa_opcode opcode)3141 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3142 {
3143 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3144 TransitionList *l;
3145 int max_size = xg_get_single_size (opcode);
3146
3147 gas_assert (opcode < table->num_opcodes);
3148
3149 for (l = table->table[opcode]; l != NULL; l = l->next)
3150 {
3151 TransitionRule *rule = l->rule;
3152 BuildInstr *build_list;
3153 int this_size = 0;
3154
3155 if (!rule)
3156 continue;
3157 build_list = rule->to_instr;
3158 if (is_unique_insn_expansion (rule))
3159 {
3160 gas_assert (build_list->typ == INSTR_INSTR);
3161 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3162 }
3163 else
3164 for (; build_list != NULL; build_list = build_list->next)
3165 {
3166 switch (build_list->typ)
3167 {
3168 case INSTR_INSTR:
3169 this_size += xg_get_single_size (build_list->opcode);
3170 break;
3171 case INSTR_LITERAL_DEF:
3172 case INSTR_LABEL_DEF:
3173 default:
3174 break;
3175 }
3176 }
3177 if (this_size > max_size)
3178 max_size = this_size;
3179 }
3180 return max_size;
3181 }
3182
3183
3184 /* Return the maximum number of literal bytes this opcode can generate. */
3185
3186 static int
xg_get_max_insn_widen_literal_size(xtensa_opcode opcode)3187 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3188 {
3189 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3190 TransitionList *l;
3191 int max_size = 0;
3192
3193 gas_assert (opcode < table->num_opcodes);
3194
3195 for (l = table->table[opcode]; l != NULL; l = l->next)
3196 {
3197 TransitionRule *rule = l->rule;
3198 BuildInstr *build_list;
3199 int this_size = 0;
3200
3201 if (!rule)
3202 continue;
3203 build_list = rule->to_instr;
3204 if (is_unique_insn_expansion (rule))
3205 {
3206 gas_assert (build_list->typ == INSTR_INSTR);
3207 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3208 }
3209 else
3210 for (; build_list != NULL; build_list = build_list->next)
3211 {
3212 switch (build_list->typ)
3213 {
3214 case INSTR_LITERAL_DEF:
3215 /* Hard-coded 4-byte literal. */
3216 this_size += 4;
3217 break;
3218 case INSTR_INSTR:
3219 case INSTR_LABEL_DEF:
3220 default:
3221 break;
3222 }
3223 }
3224 if (this_size > max_size)
3225 max_size = this_size;
3226 }
3227 return max_size;
3228 }
3229
3230
3231 static bfd_boolean
xg_is_relaxable_insn(TInsn * insn,int lateral_steps)3232 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3233 {
3234 int steps_taken = 0;
3235 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3236 TransitionList *l;
3237
3238 gas_assert (insn->insn_type == ITYPE_INSN);
3239 gas_assert (insn->opcode < table->num_opcodes);
3240
3241 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3242 {
3243 TransitionRule *rule = l->rule;
3244
3245 if (xg_instruction_matches_rule (insn, rule))
3246 {
3247 if (steps_taken == lateral_steps)
3248 return TRUE;
3249 steps_taken++;
3250 }
3251 }
3252 return FALSE;
3253 }
3254
3255
3256 static symbolS *
get_special_literal_symbol(void)3257 get_special_literal_symbol (void)
3258 {
3259 static symbolS *sym = NULL;
3260
3261 if (sym == NULL)
3262 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3263 return sym;
3264 }
3265
3266
3267 static symbolS *
get_special_label_symbol(void)3268 get_special_label_symbol (void)
3269 {
3270 static symbolS *sym = NULL;
3271
3272 if (sym == NULL)
3273 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3274 return sym;
3275 }
3276
3277
3278 static bfd_boolean
xg_valid_literal_expression(const expressionS * exp)3279 xg_valid_literal_expression (const expressionS *exp)
3280 {
3281 switch (exp->X_op)
3282 {
3283 case O_constant:
3284 case O_symbol:
3285 case O_big:
3286 case O_uminus:
3287 case O_subtract:
3288 case O_pltrel:
3289 case O_pcrel:
3290 case O_tlsfunc:
3291 case O_tlsarg:
3292 case O_tpoff:
3293 case O_dtpoff:
3294 return TRUE;
3295 default:
3296 return FALSE;
3297 }
3298 }
3299
3300
3301 /* This will check to see if the value can be converted into the
3302 operand type. It will return TRUE if it does not fit. */
3303
3304 static bfd_boolean
xg_check_operand(int32 value,xtensa_opcode opcode,int operand)3305 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3306 {
3307 uint32 valbuf = value;
3308 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3309 return TRUE;
3310 return FALSE;
3311 }
3312
3313
3314 /* Assumes: All immeds are constants. Check that all constants fit
3315 into their immeds; return FALSE if not. */
3316
3317 static bfd_boolean
xg_immeds_fit(const TInsn * insn)3318 xg_immeds_fit (const TInsn *insn)
3319 {
3320 xtensa_isa isa = xtensa_default_isa;
3321 int i;
3322
3323 int n = insn->ntok;
3324 gas_assert (insn->insn_type == ITYPE_INSN);
3325 for (i = 0; i < n; ++i)
3326 {
3327 const expressionS *exp = &insn->tok[i];
3328
3329 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3330 continue;
3331
3332 switch (exp->X_op)
3333 {
3334 case O_register:
3335 case O_constant:
3336 if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3337 return FALSE;
3338 break;
3339
3340 default:
3341 /* The symbol should have a fixup associated with it. */
3342 gas_assert (FALSE);
3343 break;
3344 }
3345 }
3346 return TRUE;
3347 }
3348
3349
3350 /* This should only be called after we have an initial
3351 estimate of the addresses. */
3352
3353 static bfd_boolean
xg_symbolic_immeds_fit(const TInsn * insn,segT pc_seg,fragS * pc_frag,offsetT pc_offset,long stretch)3354 xg_symbolic_immeds_fit (const TInsn *insn,
3355 segT pc_seg,
3356 fragS *pc_frag,
3357 offsetT pc_offset,
3358 long stretch)
3359 {
3360 xtensa_isa isa = xtensa_default_isa;
3361 symbolS *symbolP;
3362 fragS *sym_frag;
3363 offsetT target, pc;
3364 uint32 new_offset;
3365 int i;
3366 int n = insn->ntok;
3367
3368 gas_assert (insn->insn_type == ITYPE_INSN);
3369
3370 for (i = 0; i < n; ++i)
3371 {
3372 const expressionS *exp = &insn->tok[i];
3373
3374 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3375 continue;
3376
3377 switch (exp->X_op)
3378 {
3379 case O_register:
3380 case O_constant:
3381 if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3382 return FALSE;
3383 break;
3384
3385 case O_lo16:
3386 case O_hi16:
3387 /* Check for the worst case. */
3388 if (xg_check_operand (0xffff, insn->opcode, i))
3389 return FALSE;
3390 break;
3391
3392 case O_symbol:
3393 /* We only allow symbols for PC-relative references.
3394 If pc_frag == 0, then we don't have frag locations yet. */
3395 if (pc_frag == 0
3396 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
3397 return FALSE;
3398
3399 /* If it is a weak symbol or a symbol in a different section,
3400 it cannot be known to fit at assembly time. */
3401 if (S_IS_WEAK (exp->X_add_symbol)
3402 || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg)
3403 {
3404 /* For a direct call with --no-longcalls, be optimistic and
3405 assume it will be in range. If the symbol is weak and
3406 undefined, it may remain undefined at link-time, in which
3407 case it will have a zero value and almost certainly be out
3408 of range for a direct call; thus, relax for undefined weak
3409 symbols even if longcalls is not enabled. */
3410 if (is_direct_call_opcode (insn->opcode)
3411 && ! pc_frag->tc_frag_data.use_longcalls
3412 && (! S_IS_WEAK (exp->X_add_symbol)
3413 || S_IS_DEFINED (exp->X_add_symbol)))
3414 return TRUE;
3415
3416 return FALSE;
3417 }
3418
3419 symbolP = exp->X_add_symbol;
3420 sym_frag = symbol_get_frag (symbolP);
3421 target = S_GET_VALUE (symbolP) + exp->X_add_number;
3422 pc = pc_frag->fr_address + pc_offset;
3423
3424 /* If frag has yet to be reached on this pass, assume it
3425 will move by STRETCH just as we did. If this is not so,
3426 it will be because some frag between grows, and that will
3427 force another pass. Beware zero-length frags. There
3428 should be a faster way to do this. */
3429
3430 if (stretch != 0
3431 && sym_frag->relax_marker != pc_frag->relax_marker
3432 && S_GET_SEGMENT (symbolP) == pc_seg)
3433 {
3434 target += stretch;
3435 }
3436
3437 new_offset = target;
3438 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3439 if (xg_check_operand (new_offset, insn->opcode, i))
3440 return FALSE;
3441 break;
3442
3443 default:
3444 /* The symbol should have a fixup associated with it. */
3445 return FALSE;
3446 }
3447 }
3448
3449 return TRUE;
3450 }
3451
3452
3453 /* Return TRUE on success. */
3454
3455 static bfd_boolean
xg_build_to_insn(TInsn * targ,TInsn * insn,BuildInstr * bi)3456 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3457 {
3458 BuildOp *op;
3459 symbolS *sym;
3460
3461 tinsn_init (targ);
3462 targ->debug_line = insn->debug_line;
3463 targ->loc_directive_seen = insn->loc_directive_seen;
3464 switch (bi->typ)
3465 {
3466 case INSTR_INSTR:
3467 op = bi->ops;
3468 targ->opcode = bi->opcode;
3469 targ->insn_type = ITYPE_INSN;
3470 targ->is_specific_opcode = FALSE;
3471
3472 for (; op != NULL; op = op->next)
3473 {
3474 int op_num = op->op_num;
3475 int op_data = op->op_data;
3476
3477 gas_assert (op->op_num < MAX_INSN_ARGS);
3478
3479 if (targ->ntok <= op_num)
3480 targ->ntok = op_num + 1;
3481
3482 switch (op->typ)
3483 {
3484 case OP_CONSTANT:
3485 set_expr_const (&targ->tok[op_num], op_data);
3486 break;
3487 case OP_OPERAND:
3488 gas_assert (op_data < insn->ntok);
3489 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3490 break;
3491 case OP_FREEREG:
3492 if (insn->extra_arg.X_op != O_register)
3493 return FALSE;
3494 copy_expr (&targ->tok[op_num], &insn->extra_arg);
3495 break;
3496 case OP_LITERAL:
3497 sym = get_special_literal_symbol ();
3498 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3499 if (insn->tok[op_data].X_op == O_tlsfunc
3500 || insn->tok[op_data].X_op == O_tlsarg)
3501 copy_expr (&targ->extra_arg, &insn->tok[op_data]);
3502 break;
3503 case OP_LABEL:
3504 sym = get_special_label_symbol ();
3505 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3506 break;
3507 case OP_OPERAND_HI16U:
3508 case OP_OPERAND_LOW16U:
3509 gas_assert (op_data < insn->ntok);
3510 if (expr_is_const (&insn->tok[op_data]))
3511 {
3512 long val;
3513 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3514 val = xg_apply_userdef_op_fn (op->typ,
3515 targ->tok[op_num].
3516 X_add_number);
3517 targ->tok[op_num].X_add_number = val;
3518 }
3519 else
3520 {
3521 /* For const16 we can create relocations for these. */
3522 if (targ->opcode == XTENSA_UNDEFINED
3523 || (targ->opcode != xtensa_const16_opcode))
3524 return FALSE;
3525 gas_assert (op_data < insn->ntok);
3526 /* Need to build a O_lo16 or O_hi16. */
3527 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3528 if (targ->tok[op_num].X_op == O_symbol)
3529 {
3530 if (op->typ == OP_OPERAND_HI16U)
3531 targ->tok[op_num].X_op = O_hi16;
3532 else if (op->typ == OP_OPERAND_LOW16U)
3533 targ->tok[op_num].X_op = O_lo16;
3534 else
3535 return FALSE;
3536 }
3537 }
3538 break;
3539 default:
3540 /* currently handles:
3541 OP_OPERAND_LOW8
3542 OP_OPERAND_HI24S
3543 OP_OPERAND_F32MINUS */
3544 if (xg_has_userdef_op_fn (op->typ))
3545 {
3546 gas_assert (op_data < insn->ntok);
3547 if (expr_is_const (&insn->tok[op_data]))
3548 {
3549 long val;
3550 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3551 val = xg_apply_userdef_op_fn (op->typ,
3552 targ->tok[op_num].
3553 X_add_number);
3554 targ->tok[op_num].X_add_number = val;
3555 }
3556 else
3557 return FALSE; /* We cannot use a relocation for this. */
3558 break;
3559 }
3560 gas_assert (0);
3561 break;
3562 }
3563 }
3564 break;
3565
3566 case INSTR_LITERAL_DEF:
3567 op = bi->ops;
3568 targ->opcode = XTENSA_UNDEFINED;
3569 targ->insn_type = ITYPE_LITERAL;
3570 targ->is_specific_opcode = FALSE;
3571 for (; op != NULL; op = op->next)
3572 {
3573 int op_num = op->op_num;
3574 int op_data = op->op_data;
3575 gas_assert (op->op_num < MAX_INSN_ARGS);
3576
3577 if (targ->ntok <= op_num)
3578 targ->ntok = op_num + 1;
3579
3580 switch (op->typ)
3581 {
3582 case OP_OPERAND:
3583 gas_assert (op_data < insn->ntok);
3584 /* We can only pass resolvable literals through. */
3585 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3586 return FALSE;
3587 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3588 break;
3589 case OP_LITERAL:
3590 case OP_CONSTANT:
3591 case OP_LABEL:
3592 default:
3593 gas_assert (0);
3594 break;
3595 }
3596 }
3597 break;
3598
3599 case INSTR_LABEL_DEF:
3600 op = bi->ops;
3601 targ->opcode = XTENSA_UNDEFINED;
3602 targ->insn_type = ITYPE_LABEL;
3603 targ->is_specific_opcode = FALSE;
3604 /* Literal with no ops is a label? */
3605 gas_assert (op == NULL);
3606 break;
3607
3608 default:
3609 gas_assert (0);
3610 }
3611
3612 return TRUE;
3613 }
3614
3615
3616 /* Return TRUE on success. */
3617
3618 static bfd_boolean
xg_build_to_stack(IStack * istack,TInsn * insn,BuildInstr * bi)3619 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3620 {
3621 for (; bi != NULL; bi = bi->next)
3622 {
3623 TInsn *next_insn = istack_push_space (istack);
3624
3625 if (!xg_build_to_insn (next_insn, insn, bi))
3626 return FALSE;
3627 }
3628 return TRUE;
3629 }
3630
3631
3632 /* Return TRUE on valid expansion. */
3633
3634 static bfd_boolean
xg_expand_to_stack(IStack * istack,TInsn * insn,int lateral_steps)3635 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3636 {
3637 int stack_size = istack->ninsn;
3638 int steps_taken = 0;
3639 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3640 TransitionList *l;
3641
3642 gas_assert (insn->insn_type == ITYPE_INSN);
3643 gas_assert (insn->opcode < table->num_opcodes);
3644
3645 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3646 {
3647 TransitionRule *rule = l->rule;
3648
3649 if (xg_instruction_matches_rule (insn, rule))
3650 {
3651 if (lateral_steps == steps_taken)
3652 {
3653 int i;
3654
3655 /* This is it. Expand the rule to the stack. */
3656 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3657 return FALSE;
3658
3659 /* Check to see if it fits. */
3660 for (i = stack_size; i < istack->ninsn; i++)
3661 {
3662 TInsn *tinsn = &istack->insn[i];
3663
3664 if (tinsn->insn_type == ITYPE_INSN
3665 && !tinsn_has_symbolic_operands (tinsn)
3666 && !xg_immeds_fit (tinsn))
3667 {
3668 istack->ninsn = stack_size;
3669 return FALSE;
3670 }
3671 }
3672 return TRUE;
3673 }
3674 steps_taken++;
3675 }
3676 }
3677 return FALSE;
3678 }
3679
3680
3681 /* Relax the assembly instruction at least "min_steps".
3682 Return the number of steps taken.
3683
3684 For relaxation to correctly terminate, every relaxation chain must
3685 terminate in one of two ways:
3686
3687 1. If the chain from one instruction to the next consists entirely of
3688 single instructions, then the chain *must* handle all possible
3689 immediates without failing. It must not ever fail because an
3690 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3691 chain is one example. L32R loads 32 bits, and there cannot be an
3692 immediate larger than 32 bits, so it satisfies this condition.
3693 Single instruction relaxation chains are as defined by
3694 xg_is_single_relaxable_instruction.
3695
3696 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3697 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3698
3699 Strictly speaking, in most cases you can violate condition 1 and be OK
3700 -- in particular when the last two instructions have the same single
3701 size. But nevertheless, you should guarantee the above two conditions.
3702
3703 We could fix this so that single-instruction expansions correctly
3704 terminate when they can't handle the range, but the error messages are
3705 worse, and it actually turns out that in every case but one (18-bit wide
3706 branches), you need a multi-instruction expansion to get the full range
3707 anyway. And because 18-bit branches are handled identically to 15-bit
3708 branches, there isn't any point in changing it. */
3709
3710 static int
xg_assembly_relax(IStack * istack,TInsn * insn,segT pc_seg,fragS * pc_frag,offsetT pc_offset,int min_steps,long stretch)3711 xg_assembly_relax (IStack *istack,
3712 TInsn *insn,
3713 segT pc_seg,
3714 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3715 offsetT pc_offset, /* offset in fragment */
3716 int min_steps, /* minimum conversion steps */
3717 long stretch) /* number of bytes stretched so far */
3718 {
3719 int steps_taken = 0;
3720
3721 /* Some of its immeds don't fit. Try to build a relaxed version.
3722 This may go through a couple of stages of single instruction
3723 transformations before we get there. */
3724
3725 TInsn single_target;
3726 TInsn current_insn;
3727 int lateral_steps = 0;
3728 int istack_size = istack->ninsn;
3729
3730 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3731 && steps_taken >= min_steps)
3732 {
3733 istack_push (istack, insn);
3734 return steps_taken;
3735 }
3736 current_insn = *insn;
3737
3738 /* Walk through all of the single instruction expansions. */
3739 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE))
3740 {
3741 steps_taken++;
3742 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3743 stretch))
3744 {
3745 if (steps_taken >= min_steps)
3746 {
3747 istack_push (istack, &single_target);
3748 return steps_taken;
3749 }
3750 }
3751 current_insn = single_target;
3752 }
3753
3754 /* Now check for a multi-instruction expansion. */
3755 while (xg_is_relaxable_insn (¤t_insn, lateral_steps))
3756 {
3757 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset,
3758 stretch))
3759 {
3760 if (steps_taken >= min_steps)
3761 {
3762 istack_push (istack, ¤t_insn);
3763 return steps_taken;
3764 }
3765 }
3766 steps_taken++;
3767 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps))
3768 {
3769 if (steps_taken >= min_steps)
3770 return steps_taken;
3771 }
3772 lateral_steps++;
3773 istack->ninsn = istack_size;
3774 }
3775
3776 /* It's not going to work -- use the original. */
3777 istack_push (istack, insn);
3778 return steps_taken;
3779 }
3780
3781
3782 static void
xg_finish_frag(char * last_insn,enum xtensa_relax_statesE frag_state,enum xtensa_relax_statesE slot0_state,int max_growth,bfd_boolean is_insn)3783 xg_finish_frag (char *last_insn,
3784 enum xtensa_relax_statesE frag_state,
3785 enum xtensa_relax_statesE slot0_state,
3786 int max_growth,
3787 bfd_boolean is_insn)
3788 {
3789 /* Finish off this fragment so that it has at LEAST the desired
3790 max_growth. If it doesn't fit in this fragment, close this one
3791 and start a new one. In either case, return a pointer to the
3792 beginning of the growth area. */
3793
3794 fragS *old_frag;
3795
3796 frag_grow (max_growth);
3797 old_frag = frag_now;
3798
3799 frag_now->fr_opcode = last_insn;
3800 if (is_insn)
3801 frag_now->tc_frag_data.is_insn = TRUE;
3802
3803 frag_var (rs_machine_dependent, max_growth, max_growth,
3804 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3805
3806 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3807 xtensa_set_frag_assembly_state (frag_now);
3808
3809 /* Just to make sure that we did not split it up. */
3810 gas_assert (old_frag->fr_next == frag_now);
3811 }
3812
3813
3814 /* Return TRUE if the target frag is one of the next non-empty frags. */
3815
3816 static bfd_boolean
is_next_frag_target(const fragS * fragP,const fragS * target)3817 is_next_frag_target (const fragS *fragP, const fragS *target)
3818 {
3819 if (fragP == NULL)
3820 return FALSE;
3821
3822 for (; fragP; fragP = fragP->fr_next)
3823 {
3824 if (fragP == target)
3825 return TRUE;
3826 if (fragP->fr_fix != 0)
3827 return FALSE;
3828 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3829 return FALSE;
3830 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3831 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3832 return FALSE;
3833 if (fragP->fr_type == rs_space)
3834 return FALSE;
3835 }
3836 return FALSE;
3837 }
3838
3839
3840 static bfd_boolean
is_branch_jmp_to_next(TInsn * insn,fragS * fragP)3841 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3842 {
3843 xtensa_isa isa = xtensa_default_isa;
3844 int i;
3845 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3846 int target_op = -1;
3847 symbolS *sym;
3848 fragS *target_frag;
3849
3850 if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
3851 && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
3852 return FALSE;
3853
3854 for (i = 0; i < num_ops; i++)
3855 {
3856 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3857 {
3858 target_op = i;
3859 break;
3860 }
3861 }
3862 if (target_op == -1)
3863 return FALSE;
3864
3865 if (insn->ntok <= target_op)
3866 return FALSE;
3867
3868 if (insn->tok[target_op].X_op != O_symbol)
3869 return FALSE;
3870
3871 sym = insn->tok[target_op].X_add_symbol;
3872 if (sym == NULL)
3873 return FALSE;
3874
3875 if (insn->tok[target_op].X_add_number != 0)
3876 return FALSE;
3877
3878 target_frag = symbol_get_frag (sym);
3879 if (target_frag == NULL)
3880 return FALSE;
3881
3882 if (is_next_frag_target (fragP->fr_next, target_frag)
3883 && S_GET_VALUE (sym) == target_frag->fr_address)
3884 return TRUE;
3885
3886 return FALSE;
3887 }
3888
3889
3890 static void
xg_add_branch_and_loop_targets(TInsn * insn)3891 xg_add_branch_and_loop_targets (TInsn *insn)
3892 {
3893 xtensa_isa isa = xtensa_default_isa;
3894 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3895
3896 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3897 {
3898 int i = 1;
3899 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3900 && insn->tok[i].X_op == O_symbol)
3901 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3902 return;
3903 }
3904
3905 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3906 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3907 {
3908 int i;
3909
3910 for (i = 0; i < insn->ntok && i < num_ops; i++)
3911 {
3912 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3913 && insn->tok[i].X_op == O_symbol)
3914 {
3915 symbolS *sym = insn->tok[i].X_add_symbol;
3916 symbol_get_tc (sym)->is_branch_target = TRUE;
3917 if (S_IS_DEFINED (sym))
3918 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3919 }
3920 }
3921 }
3922 }
3923
3924
3925 /* Return FALSE if no error. */
3926
3927 static bfd_boolean
xg_build_token_insn(BuildInstr * instr_spec,TInsn * old_insn,TInsn * new_insn)3928 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3929 {
3930 int num_ops = 0;
3931 BuildOp *b_op;
3932
3933 switch (instr_spec->typ)
3934 {
3935 case INSTR_INSTR:
3936 new_insn->insn_type = ITYPE_INSN;
3937 new_insn->opcode = instr_spec->opcode;
3938 break;
3939 case INSTR_LITERAL_DEF:
3940 new_insn->insn_type = ITYPE_LITERAL;
3941 new_insn->opcode = XTENSA_UNDEFINED;
3942 break;
3943 case INSTR_LABEL_DEF:
3944 abort ();
3945 }
3946 new_insn->is_specific_opcode = FALSE;
3947 new_insn->debug_line = old_insn->debug_line;
3948 new_insn->loc_directive_seen = old_insn->loc_directive_seen;
3949
3950 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3951 {
3952 expressionS *exp;
3953 const expressionS *src_exp;
3954
3955 num_ops++;
3956 switch (b_op->typ)
3957 {
3958 case OP_CONSTANT:
3959 /* The expression must be the constant. */
3960 gas_assert (b_op->op_num < MAX_INSN_ARGS);
3961 exp = &new_insn->tok[b_op->op_num];
3962 set_expr_const (exp, b_op->op_data);
3963 break;
3964
3965 case OP_OPERAND:
3966 gas_assert (b_op->op_num < MAX_INSN_ARGS);
3967 gas_assert (b_op->op_data < (unsigned) old_insn->ntok);
3968 src_exp = &old_insn->tok[b_op->op_data];
3969 exp = &new_insn->tok[b_op->op_num];
3970 copy_expr (exp, src_exp);
3971 break;
3972
3973 case OP_LITERAL:
3974 case OP_LABEL:
3975 as_bad (_("can't handle generation of literal/labels yet"));
3976 gas_assert (0);
3977
3978 default:
3979 as_bad (_("can't handle undefined OP TYPE"));
3980 gas_assert (0);
3981 }
3982 }
3983
3984 new_insn->ntok = num_ops;
3985 return FALSE;
3986 }
3987
3988
3989 /* Return TRUE if it was simplified. */
3990
3991 static bfd_boolean
xg_simplify_insn(TInsn * old_insn,TInsn * new_insn)3992 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
3993 {
3994 TransitionRule *rule;
3995 BuildInstr *insn_spec;
3996
3997 if (old_insn->is_specific_opcode || !density_supported)
3998 return FALSE;
3999
4000 rule = xg_instruction_match (old_insn);
4001 if (rule == NULL)
4002 return FALSE;
4003
4004 insn_spec = rule->to_instr;
4005 /* There should only be one. */
4006 gas_assert (insn_spec != NULL);
4007 gas_assert (insn_spec->next == NULL);
4008 if (insn_spec->next != NULL)
4009 return FALSE;
4010
4011 xg_build_token_insn (insn_spec, old_insn, new_insn);
4012
4013 return TRUE;
4014 }
4015
4016
4017 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4018 l32i.n. (2) Check the number of operands. (3) Place the instruction
4019 tokens into the stack or relax it and place multiple
4020 instructions/literals onto the stack. Return FALSE if no error. */
4021
4022 static bfd_boolean
xg_expand_assembly_insn(IStack * istack,TInsn * orig_insn)4023 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
4024 {
4025 int noperands;
4026 TInsn new_insn;
4027 bfd_boolean do_expand;
4028
4029 tinsn_init (&new_insn);
4030
4031 /* Narrow it if we can. xg_simplify_insn now does all the
4032 appropriate checking (e.g., for the density option). */
4033 if (xg_simplify_insn (orig_insn, &new_insn))
4034 orig_insn = &new_insn;
4035
4036 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
4037 orig_insn->opcode);
4038 if (orig_insn->ntok < noperands)
4039 {
4040 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4041 "found %d operands for '%s': Expected %d",
4042 orig_insn->ntok),
4043 orig_insn->ntok,
4044 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4045 noperands);
4046 return TRUE;
4047 }
4048 if (orig_insn->ntok > noperands)
4049 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4050 "found %d operands for '%s': Expected %d",
4051 orig_insn->ntok),
4052 orig_insn->ntok,
4053 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4054 noperands);
4055
4056 /* If there are not enough operands, we will assert above. If there
4057 are too many, just cut out the extras here. */
4058 orig_insn->ntok = noperands;
4059
4060 if (tinsn_has_invalid_symbolic_operands (orig_insn))
4061 return TRUE;
4062
4063 /* Special case for extui opcode which has constraints not handled
4064 by the ordinary operand encoding checks. The number of operands
4065 and related syntax issues have already been checked. */
4066 if (orig_insn->opcode == xtensa_extui_opcode)
4067 {
4068 int shiftimm = orig_insn->tok[2].X_add_number;
4069 int maskimm = orig_insn->tok[3].X_add_number;
4070 if (shiftimm + maskimm > 32)
4071 {
4072 as_bad (_("immediate operands sum to greater than 32"));
4073 return TRUE;
4074 }
4075 }
4076
4077 /* If the instruction will definitely need to be relaxed, it is better
4078 to expand it now for better scheduling. Decide whether to expand
4079 now.... */
4080 do_expand = (!orig_insn->is_specific_opcode && use_transform ());
4081
4082 /* Calls should be expanded to longcalls only in the backend relaxation
4083 so that the assembly scheduler will keep the L32R/CALLX instructions
4084 adjacent. */
4085 if (is_direct_call_opcode (orig_insn->opcode))
4086 do_expand = FALSE;
4087
4088 if (tinsn_has_symbolic_operands (orig_insn))
4089 {
4090 /* The values of symbolic operands are not known yet, so only expand
4091 now if an operand is "complex" (e.g., difference of symbols) and
4092 will have to be stored as a literal regardless of the value. */
4093 if (!tinsn_has_complex_operands (orig_insn))
4094 do_expand = FALSE;
4095 }
4096 else if (xg_immeds_fit (orig_insn))
4097 do_expand = FALSE;
4098
4099 if (do_expand)
4100 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4101 else
4102 istack_push (istack, orig_insn);
4103
4104 return FALSE;
4105 }
4106
4107
4108 /* Return TRUE if the section flags are marked linkonce
4109 or the name is .gnu.linkonce.*. */
4110
4111 static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
4112
4113 static bfd_boolean
get_is_linkonce_section(bfd * abfd ATTRIBUTE_UNUSED,segT sec)4114 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4115 {
4116 flagword flags, link_once_flags;
4117
4118 flags = bfd_section_flags (sec);
4119 link_once_flags = (flags & SEC_LINK_ONCE);
4120
4121 /* Flags might not be set yet. */
4122 if (!link_once_flags
4123 && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
4124 link_once_flags = SEC_LINK_ONCE;
4125
4126 return (link_once_flags != 0);
4127 }
4128
4129
4130 static void
xtensa_add_literal_sym(symbolS * sym)4131 xtensa_add_literal_sym (symbolS *sym)
4132 {
4133 sym_list *l;
4134
4135 l = XNEW (sym_list);
4136 l->sym = sym;
4137 l->next = literal_syms;
4138 literal_syms = l;
4139 }
4140
4141
4142 static symbolS *
xtensa_create_literal_symbol(segT sec,fragS * frag)4143 xtensa_create_literal_symbol (segT sec, fragS *frag)
4144 {
4145 static int lit_num = 0;
4146 static char name[256];
4147 symbolS *symbolP;
4148
4149 sprintf (name, ".L_lit_sym%d", lit_num);
4150
4151 /* Create a local symbol. If it is in a linkonce section, we have to
4152 be careful to make sure that if it is used in a relocation that the
4153 symbol will be in the output file. */
4154 if (get_is_linkonce_section (stdoutput, sec))
4155 {
4156 symbolP = symbol_new (name, sec, 0, frag);
4157 S_CLEAR_EXTERNAL (symbolP);
4158 /* symbolP->local = 1; */
4159 }
4160 else
4161 symbolP = symbol_new (name, sec, 0, frag);
4162
4163 xtensa_add_literal_sym (symbolP);
4164
4165 lit_num++;
4166 return symbolP;
4167 }
4168
4169
4170 /* Currently all literals that are generated here are 32-bit L32R targets. */
4171
4172 static symbolS *
xg_assemble_literal(TInsn * insn)4173 xg_assemble_literal (/* const */ TInsn *insn)
4174 {
4175 emit_state state;
4176 symbolS *lit_sym = NULL;
4177 bfd_reloc_code_real_type reloc;
4178 bfd_boolean pcrel = FALSE;
4179 char *p;
4180
4181 /* size = 4 for L32R. It could easily be larger when we move to
4182 larger constants. Add a parameter later. */
4183 offsetT litsize = 4;
4184 offsetT litalign = 2; /* 2^2 = 4 */
4185 expressionS saved_loc;
4186 expressionS * emit_val;
4187
4188 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4189
4190 gas_assert (insn->insn_type == ITYPE_LITERAL);
4191 gas_assert (insn->ntok == 1); /* must be only one token here */
4192
4193 xtensa_switch_to_literal_fragment (&state);
4194
4195 emit_val = &insn->tok[0];
4196 if (emit_val->X_op == O_big)
4197 {
4198 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4199 if (size > litsize)
4200 {
4201 /* This happens when someone writes a "movi a2, big_number". */
4202 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4203 _("invalid immediate"));
4204 xtensa_restore_emit_state (&state);
4205 return NULL;
4206 }
4207 }
4208
4209 /* Force a 4-byte align here. Note that this opens a new frag, so all
4210 literals done with this function have a frag to themselves. That's
4211 important for the way text section literals work. */
4212 frag_align (litalign, 0, 0);
4213 record_alignment (now_seg, litalign);
4214
4215 switch (emit_val->X_op)
4216 {
4217 case O_pcrel:
4218 pcrel = TRUE;
4219 /* fall through */
4220 case O_pltrel:
4221 case O_tlsfunc:
4222 case O_tlsarg:
4223 case O_tpoff:
4224 case O_dtpoff:
4225 p = frag_more (litsize);
4226 xtensa_set_frag_assembly_state (frag_now);
4227 reloc = map_operator_to_reloc (emit_val->X_op, TRUE);
4228 if (emit_val->X_add_symbol)
4229 emit_val->X_op = O_symbol;
4230 else
4231 emit_val->X_op = O_constant;
4232 fix_new_exp (frag_now, p - frag_now->fr_literal,
4233 litsize, emit_val, pcrel, reloc);
4234 break;
4235
4236 default:
4237 emit_expr (emit_val, litsize);
4238 break;
4239 }
4240
4241 gas_assert (frag_now->tc_frag_data.literal_frag == NULL);
4242 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4243 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4244 lit_sym = frag_now->fr_symbol;
4245
4246 /* Go back. */
4247 xtensa_restore_emit_state (&state);
4248 return lit_sym;
4249 }
4250
4251
4252 static void
xg_assemble_literal_space(int size,int slot)4253 xg_assemble_literal_space (/* const */ int size, int slot)
4254 {
4255 emit_state state;
4256 /* We might have to do something about this alignment. It only
4257 takes effect if something is placed here. */
4258 offsetT litalign = 2; /* 2^2 = 4 */
4259 fragS *lit_saved_frag;
4260
4261 gas_assert (size % 4 == 0);
4262
4263 xtensa_switch_to_literal_fragment (&state);
4264
4265 /* Force a 4-byte align here. */
4266 frag_align (litalign, 0, 0);
4267 record_alignment (now_seg, litalign);
4268
4269 frag_grow (size);
4270
4271 lit_saved_frag = frag_now;
4272 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4273 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4274 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4275
4276 /* Go back. */
4277 xtensa_restore_emit_state (&state);
4278 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4279 }
4280
4281
4282 /* Put in a fixup record based on the opcode.
4283 Return TRUE on success. */
4284
4285 static bfd_boolean
xg_add_opcode_fix(TInsn * tinsn,int opnum,xtensa_format fmt,int slot,expressionS * exp,fragS * fragP,offsetT offset)4286 xg_add_opcode_fix (TInsn *tinsn,
4287 int opnum,
4288 xtensa_format fmt,
4289 int slot,
4290 expressionS *exp,
4291 fragS *fragP,
4292 offsetT offset)
4293 {
4294 xtensa_opcode opcode = tinsn->opcode;
4295 bfd_reloc_code_real_type reloc;
4296 reloc_howto_type *howto;
4297 int fmt_length;
4298 fixS *the_fix;
4299
4300 reloc = BFD_RELOC_NONE;
4301
4302 /* First try the special cases for "alternate" relocs. */
4303 if (opcode == xtensa_l32r_opcode)
4304 {
4305 if (fragP->tc_frag_data.use_absolute_literals)
4306 reloc = encode_alt_reloc (slot);
4307 }
4308 else if (opcode == xtensa_const16_opcode)
4309 {
4310 if (exp->X_op == O_lo16)
4311 {
4312 reloc = encode_reloc (slot);
4313 exp->X_op = O_symbol;
4314 }
4315 else if (exp->X_op == O_hi16)
4316 {
4317 reloc = encode_alt_reloc (slot);
4318 exp->X_op = O_symbol;
4319 }
4320 }
4321
4322 if (opnum != get_relaxable_immed (opcode))
4323 {
4324 as_bad (_("invalid relocation for operand %i of '%s'"),
4325 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4326 return FALSE;
4327 }
4328
4329 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4330 into the symbol table where the generic portions of the assembler
4331 won't know what to do with them. */
4332 if (exp->X_op == O_lo16 || exp->X_op == O_hi16)
4333 {
4334 as_bad (_("invalid expression for operand %i of '%s'"),
4335 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4336 return FALSE;
4337 }
4338
4339 /* Next try the generic relocs. */
4340 if (reloc == BFD_RELOC_NONE)
4341 reloc = encode_reloc (slot);
4342 if (reloc == BFD_RELOC_NONE)
4343 {
4344 as_bad (_("invalid relocation in instruction slot %i"), slot);
4345 return FALSE;
4346 }
4347
4348 howto = bfd_reloc_type_lookup (stdoutput, reloc);
4349 if (!howto)
4350 {
4351 as_bad (_("undefined symbol for opcode \"%s\""),
4352 xtensa_opcode_name (xtensa_default_isa, opcode));
4353 return FALSE;
4354 }
4355
4356 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4357 the_fix = fix_new_exp (fragP, offset, fmt_length, exp,
4358 howto->pc_relative, reloc);
4359 the_fix->fx_no_overflow = 1;
4360 the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol;
4361 the_fix->tc_fix_data.X_add_number = exp->X_add_number;
4362 the_fix->tc_fix_data.slot = slot;
4363
4364 return TRUE;
4365 }
4366
4367
4368 static bfd_boolean
xg_emit_insn_to_buf(TInsn * tinsn,char * buf,fragS * fragP,offsetT offset,bfd_boolean build_fix)4369 xg_emit_insn_to_buf (TInsn *tinsn,
4370 char *buf,
4371 fragS *fragP,
4372 offsetT offset,
4373 bfd_boolean build_fix)
4374 {
4375 static xtensa_insnbuf insnbuf = NULL;
4376 bfd_boolean has_symbolic_immed = FALSE;
4377 bfd_boolean ok = TRUE;
4378
4379 if (!insnbuf)
4380 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4381
4382 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4383 if (has_symbolic_immed && build_fix)
4384 {
4385 /* Add a fixup. */
4386 xtensa_format fmt = xg_get_single_format (tinsn->opcode);
4387 int slot = xg_get_single_slot (tinsn->opcode);
4388 int opnum = get_relaxable_immed (tinsn->opcode);
4389 expressionS *exp = &tinsn->tok[opnum];
4390
4391 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
4392 ok = FALSE;
4393 }
4394 fragP->tc_frag_data.is_insn = TRUE;
4395 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4396 (unsigned char *) buf, 0);
4397 return ok;
4398 }
4399
4400
4401 static void
xg_resolve_literals(TInsn * insn,symbolS * lit_sym)4402 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4403 {
4404 symbolS *sym = get_special_literal_symbol ();
4405 int i;
4406 if (lit_sym == 0)
4407 return;
4408 gas_assert (insn->insn_type == ITYPE_INSN);
4409 for (i = 0; i < insn->ntok; i++)
4410 if (insn->tok[i].X_add_symbol == sym)
4411 insn->tok[i].X_add_symbol = lit_sym;
4412
4413 }
4414
4415
4416 static void
xg_resolve_labels(TInsn * insn,symbolS * label_sym)4417 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4418 {
4419 symbolS *sym = get_special_label_symbol ();
4420 int i;
4421 for (i = 0; i < insn->ntok; i++)
4422 if (insn->tok[i].X_add_symbol == sym)
4423 insn->tok[i].X_add_symbol = label_sym;
4424
4425 }
4426
4427
4428 /* Return TRUE if the instruction can write to the specified
4429 integer register. */
4430
4431 static bfd_boolean
is_register_writer(const TInsn * insn,const char * regset,int regnum)4432 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4433 {
4434 int i;
4435 int num_ops;
4436 xtensa_isa isa = xtensa_default_isa;
4437
4438 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4439
4440 for (i = 0; i < num_ops; i++)
4441 {
4442 char inout;
4443 inout = xtensa_operand_inout (isa, insn->opcode, i);
4444 if ((inout == 'o' || inout == 'm')
4445 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4446 {
4447 xtensa_regfile opnd_rf =
4448 xtensa_operand_regfile (isa, insn->opcode, i);
4449 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4450 {
4451 if ((insn->tok[i].X_op == O_register)
4452 && (insn->tok[i].X_add_number == regnum))
4453 return TRUE;
4454 }
4455 }
4456 }
4457 return FALSE;
4458 }
4459
4460
4461 static bfd_boolean
is_bad_loopend_opcode(const TInsn * tinsn)4462 is_bad_loopend_opcode (const TInsn *tinsn)
4463 {
4464 xtensa_opcode opcode = tinsn->opcode;
4465
4466 if (opcode == XTENSA_UNDEFINED)
4467 return FALSE;
4468
4469 if (opcode == xtensa_call0_opcode
4470 || opcode == xtensa_callx0_opcode
4471 || opcode == xtensa_call4_opcode
4472 || opcode == xtensa_callx4_opcode
4473 || opcode == xtensa_call8_opcode
4474 || opcode == xtensa_callx8_opcode
4475 || opcode == xtensa_call12_opcode
4476 || opcode == xtensa_callx12_opcode
4477 || opcode == xtensa_isync_opcode
4478 || opcode == xtensa_ret_opcode
4479 || opcode == xtensa_ret_n_opcode
4480 || opcode == xtensa_retw_opcode
4481 || opcode == xtensa_retw_n_opcode
4482 || opcode == xtensa_waiti_opcode
4483 || opcode == xtensa_rsr_lcount_opcode)
4484 return TRUE;
4485
4486 return FALSE;
4487 }
4488
4489
4490 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4491 This allows the debugger to add unaligned labels.
4492 Also, the assembler generates stabs labels that need
4493 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4494
4495 static bfd_boolean
is_unaligned_label(symbolS * sym)4496 is_unaligned_label (symbolS *sym)
4497 {
4498 const char *name = S_GET_NAME (sym);
4499 static size_t fake_size = 0;
4500
4501 if (name
4502 && name[0] == '.'
4503 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4504 return TRUE;
4505
4506 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4507 if (fake_size == 0)
4508 fake_size = strlen (FAKE_LABEL_NAME);
4509
4510 if (name
4511 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4512 && (name[fake_size] == 'F'
4513 || name[fake_size] == 'L'
4514 || (name[fake_size] == 'e'
4515 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4516 return TRUE;
4517
4518 return FALSE;
4519 }
4520
4521
4522 static fragS *
next_non_empty_frag(const fragS * fragP)4523 next_non_empty_frag (const fragS *fragP)
4524 {
4525 fragS *next_fragP = fragP->fr_next;
4526
4527 /* Sometimes an empty will end up here due storage allocation issues.
4528 So we have to skip until we find something legit. */
4529 while (next_fragP && next_fragP->fr_fix == 0)
4530 next_fragP = next_fragP->fr_next;
4531
4532 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4533 return NULL;
4534
4535 return next_fragP;
4536 }
4537
4538
4539 static bfd_boolean
next_frag_opcode_is_loop(const fragS * fragP,xtensa_opcode * opcode)4540 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4541 {
4542 xtensa_opcode out_opcode;
4543 const fragS *next_fragP = next_non_empty_frag (fragP);
4544
4545 if (next_fragP == NULL)
4546 return FALSE;
4547
4548 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4549 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4550 {
4551 *opcode = out_opcode;
4552 return TRUE;
4553 }
4554 return FALSE;
4555 }
4556
4557
4558 static int
frag_format_size(const fragS * fragP)4559 frag_format_size (const fragS *fragP)
4560 {
4561 static xtensa_insnbuf insnbuf = NULL;
4562 xtensa_isa isa = xtensa_default_isa;
4563 xtensa_format fmt;
4564 int fmt_size;
4565
4566 if (!insnbuf)
4567 insnbuf = xtensa_insnbuf_alloc (isa);
4568
4569 if (fragP == NULL)
4570 return XTENSA_UNDEFINED;
4571
4572 xtensa_insnbuf_from_chars (isa, insnbuf,
4573 (unsigned char *) fragP->fr_literal, 0);
4574
4575 fmt = xtensa_format_decode (isa, insnbuf);
4576 if (fmt == XTENSA_UNDEFINED)
4577 return XTENSA_UNDEFINED;
4578 fmt_size = xtensa_format_length (isa, fmt);
4579
4580 /* If the next format won't be changing due to relaxation, just
4581 return the length of the first format. */
4582 if (fragP->fr_opcode != fragP->fr_literal)
4583 return fmt_size;
4584
4585 /* If during relaxation we have to pull an instruction out of a
4586 multi-slot instruction, we will return the more conservative
4587 number. This works because alignment on bigger instructions
4588 is more restrictive than alignment on smaller instructions.
4589 This is more conservative than we would like, but it happens
4590 infrequently. */
4591
4592 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4593 return fmt_size;
4594
4595 /* If we aren't doing one of our own relaxations or it isn't
4596 slot-based, then the insn size won't change. */
4597 if (fragP->fr_type != rs_machine_dependent)
4598 return fmt_size;
4599 if (fragP->fr_subtype != RELAX_SLOTS)
4600 return fmt_size;
4601
4602 /* If an instruction is about to grow, return the longer size. */
4603 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4604 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
4605 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
4606 {
4607 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4608 instruction in the relaxed version is of length 3. (The case
4609 where we have to pull the instruction out of a FLIX bundle
4610 is handled conservatively above.) However, frags with opcodes
4611 that are expanding to wide branches end up having formats that
4612 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4613 we can't tell directly what format the relaxer picked. This
4614 is a wart in the design of the relaxer that should someday be
4615 fixed, but would require major changes, or at least should
4616 be accompanied by major changes to make use of that data.
4617
4618 In any event, we can tell that we are expanding from a single-slot
4619 format to a wider one with the logic below. */
4620
4621 int i;
4622 int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0];
4623
4624 for (i = 0; i < xtensa_isa_num_formats (isa); i++)
4625 {
4626 if (relaxed_size == xtensa_format_length (isa, i))
4627 return relaxed_size;
4628 }
4629
4630 return 3;
4631 }
4632
4633 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4634 return 2 + fragP->tc_frag_data.text_expansion[0];
4635
4636 return fmt_size;
4637 }
4638
4639
4640 static int
next_frag_format_size(const fragS * fragP)4641 next_frag_format_size (const fragS *fragP)
4642 {
4643 const fragS *next_fragP = next_non_empty_frag (fragP);
4644 return frag_format_size (next_fragP);
4645 }
4646
4647
4648 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4649 required two-byte instructions to be treated as three-byte instructions
4650 for loop instruction alignment. This restriction was removed beginning
4651 with Xtensa LX. Now the only requirement on loop instruction alignment
4652 is that the first instruction of the loop must appear at an address that
4653 does not cross a fetch boundary. */
4654
4655 static int
get_loop_align_size(int insn_size)4656 get_loop_align_size (int insn_size)
4657 {
4658 if (insn_size == XTENSA_UNDEFINED)
4659 return xtensa_fetch_width;
4660
4661 if (enforce_three_byte_loop_align && insn_size == 2)
4662 return 3;
4663
4664 return insn_size;
4665 }
4666
4667
4668 /* If the next legit fragment is an end-of-loop marker,
4669 switch its state so it will instantiate a NOP. */
4670
4671 static void
update_next_frag_state(fragS * fragP)4672 update_next_frag_state (fragS *fragP)
4673 {
4674 fragS *next_fragP = fragP->fr_next;
4675 fragS *new_target = NULL;
4676
4677 if (align_targets)
4678 {
4679 /* We are guaranteed there will be one of these... */
4680 while (!(next_fragP->fr_type == rs_machine_dependent
4681 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4682 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4683 next_fragP = next_fragP->fr_next;
4684
4685 gas_assert (next_fragP->fr_type == rs_machine_dependent
4686 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4687 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4688
4689 /* ...and one of these. */
4690 new_target = next_fragP->fr_next;
4691 while (!(new_target->fr_type == rs_machine_dependent
4692 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4693 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4694 new_target = new_target->fr_next;
4695
4696 gas_assert (new_target->fr_type == rs_machine_dependent
4697 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4698 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4699 }
4700
4701 while (next_fragP && next_fragP->fr_fix == 0)
4702 {
4703 if (next_fragP->fr_type == rs_machine_dependent
4704 && next_fragP->fr_subtype == RELAX_LOOP_END)
4705 {
4706 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4707 return;
4708 }
4709
4710 next_fragP = next_fragP->fr_next;
4711 }
4712 }
4713
4714
4715 static bfd_boolean
next_frag_is_branch_target(const fragS * fragP)4716 next_frag_is_branch_target (const fragS *fragP)
4717 {
4718 /* Sometimes an empty will end up here due to storage allocation issues,
4719 so we have to skip until we find something legit. */
4720 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4721 {
4722 if (fragP->tc_frag_data.is_branch_target)
4723 return TRUE;
4724 if (fragP->fr_fix != 0)
4725 break;
4726 }
4727 return FALSE;
4728 }
4729
4730
4731 static bfd_boolean
next_frag_is_loop_target(const fragS * fragP)4732 next_frag_is_loop_target (const fragS *fragP)
4733 {
4734 /* Sometimes an empty will end up here due storage allocation issues.
4735 So we have to skip until we find something legit. */
4736 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4737 {
4738 if (fragP->tc_frag_data.is_loop_target)
4739 return TRUE;
4740 if (fragP->fr_fix != 0)
4741 break;
4742 }
4743 return FALSE;
4744 }
4745
4746
4747 /* As specified in the relaxation table, when a loop instruction is
4748 relaxed, there are 24 bytes between the loop instruction itself and
4749 the first instruction in the loop. */
4750
4751 #define RELAXED_LOOP_INSN_BYTES 24
4752
4753 static addressT
next_frag_pre_opcode_bytes(const fragS * fragp)4754 next_frag_pre_opcode_bytes (const fragS *fragp)
4755 {
4756 const fragS *next_fragp = fragp->fr_next;
4757 xtensa_opcode next_opcode;
4758
4759 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4760 return 0;
4761
4762 /* Sometimes an empty will end up here due to storage allocation issues,
4763 so we have to skip until we find something legit. */
4764 while (next_fragp->fr_fix == 0)
4765 next_fragp = next_fragp->fr_next;
4766
4767 if (next_fragp->fr_type != rs_machine_dependent)
4768 return 0;
4769
4770 /* There is some implicit knowledge encoded in here.
4771 The LOOP instructions that are NOT RELAX_IMMED have
4772 been relaxed. Note that we can assume that the LOOP
4773 instruction is in slot 0 because loops aren't bundleable. */
4774 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4775 return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES;
4776
4777 return 0;
4778 }
4779
4780
4781 /* Mark a location where we can later insert literal frags. Update
4782 the section's literal_pool_loc, so subsequent literals can be
4783 placed nearest to their use. */
4784
4785 static void
xtensa_mark_literal_pool_location(void)4786 xtensa_mark_literal_pool_location (void)
4787 {
4788 /* Any labels pointing to the current location need
4789 to be adjusted to after the literal pool. */
4790 fragS *pool_location;
4791
4792 if (use_literal_section)
4793 return;
4794
4795 /* We stash info in these frags so we can later move the literal's
4796 fixes into this frchain's fix list. */
4797 pool_location = frag_now;
4798 frag_now->tc_frag_data.lit_frchain = frchain_now;
4799 frag_now->tc_frag_data.literal_frag = frag_now;
4800 /* Just record this frag. */
4801 xtensa_maybe_create_literal_pool_frag (FALSE, FALSE);
4802 frag_variant (rs_machine_dependent, 0, 0,
4803 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4804 xtensa_set_frag_assembly_state (frag_now);
4805 frag_now->tc_frag_data.lit_seg = now_seg;
4806 frag_variant (rs_machine_dependent, 0, 0,
4807 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4808 xtensa_set_frag_assembly_state (frag_now);
4809
4810 set_literal_pool_location (now_seg, pool_location);
4811 }
4812
4813
4814 /* Build a nop of the correct size into tinsn. */
4815
4816 static void
build_nop(TInsn * tinsn,int size)4817 build_nop (TInsn *tinsn, int size)
4818 {
4819 tinsn_init (tinsn);
4820 switch (size)
4821 {
4822 case 2:
4823 tinsn->opcode = xtensa_nop_n_opcode;
4824 tinsn->ntok = 0;
4825 if (tinsn->opcode == XTENSA_UNDEFINED)
4826 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4827 break;
4828
4829 case 3:
4830 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4831 {
4832 tinsn->opcode = xtensa_or_opcode;
4833 set_expr_const (&tinsn->tok[0], 1);
4834 set_expr_const (&tinsn->tok[1], 1);
4835 set_expr_const (&tinsn->tok[2], 1);
4836 tinsn->ntok = 3;
4837 }
4838 else
4839 tinsn->opcode = xtensa_nop_opcode;
4840
4841 gas_assert (tinsn->opcode != XTENSA_UNDEFINED);
4842 }
4843 }
4844
4845
4846 /* Assemble a NOP of the requested size in the buffer. User must have
4847 allocated "buf" with at least "size" bytes. */
4848
4849 static void
assemble_nop(int size,char * buf)4850 assemble_nop (int size, char *buf)
4851 {
4852 static xtensa_insnbuf insnbuf = NULL;
4853 TInsn tinsn;
4854
4855 build_nop (&tinsn, size);
4856
4857 if (!insnbuf)
4858 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4859
4860 tinsn_to_insnbuf (&tinsn, insnbuf);
4861 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4862 (unsigned char *) buf, 0);
4863 }
4864
4865
4866 /* Return the number of bytes for the offset of the expanded loop
4867 instruction. This should be incorporated into the relaxation
4868 specification but is hard-coded here. This is used to auto-align
4869 the loop instruction. It is invalid to call this function if the
4870 configuration does not have loops or if the opcode is not a loop
4871 opcode. */
4872
4873 static addressT
get_expanded_loop_offset(xtensa_opcode opcode)4874 get_expanded_loop_offset (xtensa_opcode opcode)
4875 {
4876 /* This is the OFFSET of the loop instruction in the expanded loop.
4877 This MUST correspond directly to the specification of the loop
4878 expansion. It will be validated on fragment conversion. */
4879 gas_assert (opcode != XTENSA_UNDEFINED);
4880 if (opcode == xtensa_loop_opcode)
4881 return 0;
4882 if (opcode == xtensa_loopnez_opcode)
4883 return 3;
4884 if (opcode == xtensa_loopgtz_opcode)
4885 return 6;
4886 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4887 return 0;
4888 }
4889
4890
4891 static fragS *
get_literal_pool_location(segT seg)4892 get_literal_pool_location (segT seg)
4893 {
4894 if (auto_litpools)
4895 {
4896 struct litpool_seg *lps = litpool_seg_list.next;
4897 struct litpool_frag *lpf;
4898 for ( ; lps && lps->seg->id != seg->id; lps = lps->next)
4899 ;
4900 if (lps)
4901 {
4902 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4903 { /* Skip "candidates" for now. */
4904 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
4905 lpf->priority == 1)
4906 return lpf->fragP;
4907 }
4908 /* Must convert a lower-priority pool. */
4909 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4910 {
4911 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN)
4912 return lpf->fragP;
4913 }
4914 /* Still no match -- try for a low priority pool. */
4915 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4916 {
4917 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
4918 return lpf->fragP;
4919 }
4920 }
4921 }
4922 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4923 }
4924
4925
4926 static void
set_literal_pool_location(segT seg,fragS * literal_pool_loc)4927 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4928 {
4929 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4930 }
4931
4932
4933 /* Set frag assembly state should be called when a new frag is
4934 opened and after a frag has been closed. */
4935
4936 static void
xtensa_set_frag_assembly_state(fragS * fragP)4937 xtensa_set_frag_assembly_state (fragS *fragP)
4938 {
4939 if (!density_supported)
4940 fragP->tc_frag_data.is_no_density = TRUE;
4941
4942 /* This function is called from subsegs_finish, which is called
4943 after xtensa_end, so we can't use "use_transform" or
4944 "use_schedule" here. */
4945 if (!directive_state[directive_transform])
4946 fragP->tc_frag_data.is_no_transform = TRUE;
4947 if (directive_state[directive_longcalls])
4948 fragP->tc_frag_data.use_longcalls = TRUE;
4949 fragP->tc_frag_data.use_absolute_literals =
4950 directive_state[directive_absolute_literals];
4951 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4952 }
4953
4954
4955 static bfd_boolean
relaxable_section(asection * sec)4956 relaxable_section (asection *sec)
4957 {
4958 return ((sec->flags & SEC_DEBUGGING) == 0
4959 && strcmp (sec->name, ".eh_frame") != 0);
4960 }
4961
4962
4963 static void
xtensa_mark_frags_for_org(void)4964 xtensa_mark_frags_for_org (void)
4965 {
4966 segT *seclist;
4967
4968 /* Walk over each fragment of all of the current segments. If we find
4969 a .org frag in any of the segments, mark all frags prior to it as
4970 "no transform", which will prevent linker optimizations from messing
4971 up the .org distance. This should be done after
4972 xtensa_find_unmarked_state_frags, because we don't want to worry here
4973 about that function trashing the data we save here. */
4974
4975 for (seclist = &stdoutput->sections;
4976 seclist && *seclist;
4977 seclist = &(*seclist)->next)
4978 {
4979 segT sec = *seclist;
4980 segment_info_type *seginfo;
4981 fragS *fragP;
4982 flagword flags;
4983 flags = bfd_section_flags (sec);
4984 if (flags & SEC_DEBUGGING)
4985 continue;
4986 if (!(flags & SEC_ALLOC))
4987 continue;
4988
4989 seginfo = seg_info (sec);
4990 if (seginfo && seginfo->frchainP)
4991 {
4992 fragS *last_fragP = seginfo->frchainP->frch_root;
4993 for (fragP = seginfo->frchainP->frch_root; fragP;
4994 fragP = fragP->fr_next)
4995 {
4996 /* cvt_frag_to_fill has changed the fr_type of org frags to
4997 rs_fill, so use the value as cached in rs_subtype here. */
4998 if (fragP->fr_subtype == RELAX_ORG)
4999 {
5000 while (last_fragP != fragP->fr_next)
5001 {
5002 last_fragP->tc_frag_data.is_no_transform = TRUE;
5003 last_fragP = last_fragP->fr_next;
5004 }
5005 }
5006 }
5007 }
5008 }
5009 }
5010
5011
5012 static void
xtensa_find_unmarked_state_frags(void)5013 xtensa_find_unmarked_state_frags (void)
5014 {
5015 segT *seclist;
5016
5017 /* Walk over each fragment of all of the current segments. For each
5018 unmarked fragment, mark it with the same info as the previous
5019 fragment. */
5020 for (seclist = &stdoutput->sections;
5021 seclist && *seclist;
5022 seclist = &(*seclist)->next)
5023 {
5024 segT sec = *seclist;
5025 segment_info_type *seginfo;
5026 fragS *fragP;
5027 flagword flags;
5028 flags = bfd_section_flags (sec);
5029 if (flags & SEC_DEBUGGING)
5030 continue;
5031 if (!(flags & SEC_ALLOC))
5032 continue;
5033
5034 seginfo = seg_info (sec);
5035 if (seginfo && seginfo->frchainP)
5036 {
5037 fragS *last_fragP = 0;
5038 for (fragP = seginfo->frchainP->frch_root; fragP;
5039 fragP = fragP->fr_next)
5040 {
5041 if (fragP->fr_fix != 0
5042 && !fragP->tc_frag_data.is_assembly_state_set)
5043 {
5044 if (last_fragP == 0)
5045 {
5046 as_warn_where (fragP->fr_file, fragP->fr_line,
5047 _("assembly state not set for first frag in section %s"),
5048 sec->name);
5049 }
5050 else
5051 {
5052 fragP->tc_frag_data.is_assembly_state_set = TRUE;
5053 fragP->tc_frag_data.is_no_density =
5054 last_fragP->tc_frag_data.is_no_density;
5055 fragP->tc_frag_data.is_no_transform =
5056 last_fragP->tc_frag_data.is_no_transform;
5057 fragP->tc_frag_data.use_longcalls =
5058 last_fragP->tc_frag_data.use_longcalls;
5059 fragP->tc_frag_data.use_absolute_literals =
5060 last_fragP->tc_frag_data.use_absolute_literals;
5061 }
5062 }
5063 if (fragP->tc_frag_data.is_assembly_state_set)
5064 last_fragP = fragP;
5065 }
5066 }
5067 }
5068 }
5069
5070
5071 static void
xtensa_find_unaligned_branch_targets(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * unused ATTRIBUTE_UNUSED)5072 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
5073 asection *sec,
5074 void *unused ATTRIBUTE_UNUSED)
5075 {
5076 flagword flags = bfd_section_flags (sec);
5077 segment_info_type *seginfo = seg_info (sec);
5078 fragS *frag = seginfo->frchainP->frch_root;
5079
5080 if (flags & SEC_CODE)
5081 {
5082 xtensa_isa isa = xtensa_default_isa;
5083 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5084 while (frag != NULL)
5085 {
5086 if (frag->tc_frag_data.is_branch_target)
5087 {
5088 int op_size;
5089 addressT branch_align, frag_addr;
5090 xtensa_format fmt;
5091
5092 xtensa_insnbuf_from_chars
5093 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5094 fmt = xtensa_format_decode (isa, insnbuf);
5095 op_size = xtensa_format_length (isa, fmt);
5096 branch_align = 1 << branch_align_power (sec);
5097 frag_addr = frag->fr_address % branch_align;
5098 if (frag_addr + op_size > branch_align)
5099 as_warn_where (frag->fr_file, frag->fr_line,
5100 _("unaligned branch target: %d bytes at 0x%lx"),
5101 op_size, (long) frag->fr_address);
5102 }
5103 frag = frag->fr_next;
5104 }
5105 xtensa_insnbuf_free (isa, insnbuf);
5106 }
5107 }
5108
5109
5110 static void
xtensa_find_unaligned_loops(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * unused ATTRIBUTE_UNUSED)5111 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
5112 asection *sec,
5113 void *unused ATTRIBUTE_UNUSED)
5114 {
5115 flagword flags = bfd_section_flags (sec);
5116 segment_info_type *seginfo = seg_info (sec);
5117 fragS *frag = seginfo->frchainP->frch_root;
5118 xtensa_isa isa = xtensa_default_isa;
5119
5120 if (flags & SEC_CODE)
5121 {
5122 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5123 while (frag != NULL)
5124 {
5125 if (frag->tc_frag_data.is_first_loop_insn)
5126 {
5127 int op_size;
5128 addressT frag_addr;
5129 xtensa_format fmt;
5130
5131 if (frag->fr_fix == 0)
5132 frag = next_non_empty_frag (frag);
5133
5134 if (frag)
5135 {
5136 xtensa_insnbuf_from_chars
5137 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5138 fmt = xtensa_format_decode (isa, insnbuf);
5139 op_size = xtensa_format_length (isa, fmt);
5140 frag_addr = frag->fr_address % xtensa_fetch_width;
5141
5142 if (frag_addr + op_size > xtensa_fetch_width)
5143 as_warn_where (frag->fr_file, frag->fr_line,
5144 _("unaligned loop: %d bytes at 0x%lx"),
5145 op_size, (long) frag->fr_address);
5146 }
5147 }
5148 frag = frag->fr_next;
5149 }
5150 xtensa_insnbuf_free (isa, insnbuf);
5151 }
5152 }
5153
5154
5155 static int
xg_apply_fix_value(fixS * fixP,valueT val)5156 xg_apply_fix_value (fixS *fixP, valueT val)
5157 {
5158 xtensa_isa isa = xtensa_default_isa;
5159 static xtensa_insnbuf insnbuf = NULL;
5160 static xtensa_insnbuf slotbuf = NULL;
5161 xtensa_format fmt;
5162 int slot;
5163 bfd_boolean alt_reloc;
5164 xtensa_opcode opcode;
5165 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5166
5167 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc)
5168 || alt_reloc)
5169 as_fatal (_("unexpected fix"));
5170
5171 if (!insnbuf)
5172 {
5173 insnbuf = xtensa_insnbuf_alloc (isa);
5174 slotbuf = xtensa_insnbuf_alloc (isa);
5175 }
5176
5177 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5178 fmt = xtensa_format_decode (isa, insnbuf);
5179 if (fmt == XTENSA_UNDEFINED)
5180 as_fatal (_("undecodable fix"));
5181 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5182 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5183 if (opcode == XTENSA_UNDEFINED)
5184 as_fatal (_("undecodable fix"));
5185
5186 /* CONST16 immediates are not PC-relative, despite the fact that we
5187 reuse the normal PC-relative operand relocations for the low part
5188 of a CONST16 operand. */
5189 if (opcode == xtensa_const16_opcode)
5190 return 0;
5191
5192 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5193 get_relaxable_immed (opcode), val,
5194 fixP->fx_file, fixP->fx_line);
5195
5196 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5197 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5198
5199 return 1;
5200 }
5201
5202
5203 /* External Functions and Other GAS Hooks. */
5204
5205 const char *
xtensa_target_format(void)5206 xtensa_target_format (void)
5207 {
5208 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5209 }
5210
5211
5212 void
xtensa_file_arch_init(bfd * abfd)5213 xtensa_file_arch_init (bfd *abfd)
5214 {
5215 bfd_set_private_flags (abfd, 0x100 | 0x200);
5216 }
5217
5218
5219 void
md_number_to_chars(char * buf,valueT val,int n)5220 md_number_to_chars (char *buf, valueT val, int n)
5221 {
5222 if (target_big_endian)
5223 number_to_chars_bigendian (buf, val, n);
5224 else
5225 number_to_chars_littleendian (buf, val, n);
5226 }
5227
5228 static void
xg_init_global_config(void)5229 xg_init_global_config (void)
5230 {
5231 target_big_endian = XCHAL_HAVE_BE;
5232
5233 density_supported = XCHAL_HAVE_DENSITY;
5234 absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
5235 xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
5236
5237 directive_state[directive_density] = XCHAL_HAVE_DENSITY;
5238 directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS;
5239 }
5240
5241 void
xtensa_init(int argc ATTRIBUTE_UNUSED,char ** argv ATTRIBUTE_UNUSED)5242 xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED)
5243 {
5244 xg_init_global_config ();
5245 }
5246
5247 /* This function is called once, at assembler startup time. It should
5248 set up all the tables, etc. that the MD part of the assembler will
5249 need. */
5250
5251 void
md_begin(void)5252 md_begin (void)
5253 {
5254 segT current_section = now_seg;
5255 int current_subsec = now_subseg;
5256 xtensa_isa isa;
5257 int i;
5258
5259 xtensa_default_isa = xtensa_isa_init (0, 0);
5260 isa = xtensa_default_isa;
5261
5262 linkrelax = opt_linkrelax;
5263
5264 /* Set up the literal sections. */
5265 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5266
5267 subseg_set (current_section, current_subsec);
5268
5269 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5270 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5271 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5272 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5273 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5274 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5275 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5276 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5277 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5278 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5279 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5280 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5281 xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui");
5282 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5283 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5284 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5285 xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
5286 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5287 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5288 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5289 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5290 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5291 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5292 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5293 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5294 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5295 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5296 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5297 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5298 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5299 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5300
5301 for (i = 0; i < xtensa_isa_num_formats (isa); i++)
5302 {
5303 int format_slots = xtensa_format_num_slots (isa, i);
5304 if (format_slots > config_max_slots)
5305 config_max_slots = format_slots;
5306 }
5307
5308 xg_init_vinsn (&cur_vinsn);
5309
5310 xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa);
5311
5312 init_op_placement_info_table ();
5313
5314 /* Set up the assembly state. */
5315 if (!frag_now->tc_frag_data.is_assembly_state_set)
5316 xtensa_set_frag_assembly_state (frag_now);
5317
5318 if (!use_literal_section)
5319 xtensa_mark_literal_pool_location ();
5320 }
5321
5322
5323 /* TC_INIT_FIX_DATA hook */
5324
5325 void
xtensa_init_fix_data(fixS * x)5326 xtensa_init_fix_data (fixS *x)
5327 {
5328 x->tc_fix_data.slot = 0;
5329 x->tc_fix_data.X_add_symbol = NULL;
5330 x->tc_fix_data.X_add_number = 0;
5331 }
5332
5333
5334 /* tc_frob_label hook */
5335
5336 void
xtensa_frob_label(symbolS * sym)5337 xtensa_frob_label (symbolS *sym)
5338 {
5339 float freq;
5340
5341 if (cur_vinsn.inside_bundle)
5342 {
5343 as_bad (_("labels are not valid inside bundles"));
5344 return;
5345 }
5346
5347 freq = get_subseg_target_freq (now_seg, now_subseg);
5348
5349 /* Since the label was already attached to a frag associated with the
5350 previous basic block, it now needs to be reset to the current frag. */
5351 symbol_set_frag (sym, frag_now);
5352 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5353
5354 if (generating_literals)
5355 xtensa_add_literal_sym (sym);
5356 else
5357 xtensa_add_insn_label (sym);
5358
5359 if (symbol_get_tc (sym)->is_loop_target)
5360 {
5361 if ((get_last_insn_flags (now_seg, now_subseg)
5362 & FLAG_IS_BAD_LOOPEND) != 0)
5363 as_bad (_("invalid last instruction for a zero-overhead loop"));
5364
5365 xtensa_set_frag_assembly_state (frag_now);
5366 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5367 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5368
5369 xtensa_set_frag_assembly_state (frag_now);
5370 xtensa_move_labels (frag_now, 0);
5371 }
5372
5373 /* No target aligning in the absolute section. */
5374 if (now_seg != absolute_section
5375 && !is_unaligned_label (sym)
5376 && !generating_literals)
5377 {
5378 xtensa_set_frag_assembly_state (frag_now);
5379
5380 if (do_align_targets ())
5381 frag_var (rs_machine_dependent, 0, (int) freq,
5382 RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol,
5383 frag_now->fr_offset, NULL);
5384 else
5385 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
5386 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5387 xtensa_set_frag_assembly_state (frag_now);
5388 xtensa_move_labels (frag_now, 0);
5389 }
5390
5391 /* We need to mark the following properties even if we aren't aligning. */
5392
5393 /* If the label is already known to be a branch target, i.e., a
5394 forward branch, mark the frag accordingly. Backward branches
5395 are handled by xg_add_branch_and_loop_targets. */
5396 if (symbol_get_tc (sym)->is_branch_target)
5397 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5398
5399 /* Loops only go forward, so they can be identified here. */
5400 if (symbol_get_tc (sym)->is_loop_target)
5401 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5402
5403 dwarf2_emit_label (sym);
5404 }
5405
5406
5407 /* tc_unrecognized_line hook */
5408
5409 int
xtensa_unrecognized_line(int ch)5410 xtensa_unrecognized_line (int ch)
5411 {
5412 switch (ch)
5413 {
5414 case '{' :
5415 if (cur_vinsn.inside_bundle == 0)
5416 {
5417 /* PR8110: Cannot emit line number info inside a FLIX bundle
5418 when using --gstabs. Temporarily disable debug info. */
5419 generate_lineno_debug ();
5420 if (debug_type == DEBUG_STABS)
5421 {
5422 xt_saved_debug_type = debug_type;
5423 debug_type = DEBUG_NONE;
5424 }
5425
5426 cur_vinsn.inside_bundle = 1;
5427 }
5428 else
5429 {
5430 as_bad (_("extra opening brace"));
5431 return 0;
5432 }
5433 break;
5434
5435 case '}' :
5436 if (cur_vinsn.inside_bundle)
5437 finish_vinsn (&cur_vinsn);
5438 else
5439 {
5440 as_bad (_("extra closing brace"));
5441 return 0;
5442 }
5443 break;
5444 default:
5445 as_bad (_("syntax error"));
5446 return 0;
5447 }
5448 return 1;
5449 }
5450
5451
5452 /* md_flush_pending_output hook */
5453
5454 void
xtensa_flush_pending_output(void)5455 xtensa_flush_pending_output (void)
5456 {
5457 /* This line fixes a bug where automatically generated gstabs info
5458 separates a function label from its entry instruction, ending up
5459 with the literal position between the function label and the entry
5460 instruction and crashing code. It only happens with --gstabs and
5461 --text-section-literals, and when several other obscure relaxation
5462 conditions are met. */
5463 if (outputting_stabs_line_debug)
5464 return;
5465
5466 if (cur_vinsn.inside_bundle)
5467 as_bad (_("missing closing brace"));
5468
5469 /* If there is a non-zero instruction fragment, close it. */
5470 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5471 {
5472 frag_wane (frag_now);
5473 frag_new (0);
5474 xtensa_set_frag_assembly_state (frag_now);
5475 }
5476 frag_now->tc_frag_data.is_insn = FALSE;
5477
5478 xtensa_clear_insn_labels ();
5479 }
5480
5481
5482 /* We had an error while parsing an instruction. The string might look
5483 like this: "insn arg1, arg2 }". If so, we need to see the closing
5484 brace and reset some fields. Otherwise, the vinsn never gets closed
5485 and the num_slots field will grow past the end of the array of slots,
5486 and bad things happen. */
5487
5488 static void
error_reset_cur_vinsn(void)5489 error_reset_cur_vinsn (void)
5490 {
5491 if (cur_vinsn.inside_bundle)
5492 {
5493 if (*input_line_pointer == '}'
5494 || *(input_line_pointer - 1) == '}'
5495 || *(input_line_pointer - 2) == '}')
5496 xg_clear_vinsn (&cur_vinsn);
5497 }
5498 }
5499
5500
5501 void
md_assemble(char * str)5502 md_assemble (char *str)
5503 {
5504 xtensa_isa isa = xtensa_default_isa;
5505 char *opname;
5506 unsigned opnamelen;
5507 bfd_boolean has_underbar = FALSE;
5508 char *arg_strings[MAX_INSN_ARGS];
5509 int num_args;
5510 TInsn orig_insn; /* Original instruction from the input. */
5511
5512 tinsn_init (&orig_insn);
5513
5514 /* Split off the opcode. */
5515 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5516 opname = xstrndup (str, opnamelen);
5517
5518 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5519 if (num_args == -1)
5520 {
5521 as_bad (_("syntax error"));
5522 return;
5523 }
5524
5525 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5526 return;
5527
5528 /* Check for an underbar prefix. */
5529 if (*opname == '_')
5530 {
5531 has_underbar = TRUE;
5532 opname += 1;
5533 }
5534
5535 orig_insn.insn_type = ITYPE_INSN;
5536 orig_insn.ntok = 0;
5537 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5538 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5539
5540 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5541 extra argument and set the opcode to "CALLXn". */
5542 if (orig_insn.opcode == XTENSA_UNDEFINED
5543 && strncasecmp (opname, "callx", 5) == 0)
5544 {
5545 unsigned long window_size;
5546 char *suffix;
5547
5548 window_size = strtoul (opname + 5, &suffix, 10);
5549 if (suffix != opname + 5
5550 && (window_size == 0
5551 || window_size == 4
5552 || window_size == 8
5553 || window_size == 12)
5554 && strcasecmp (suffix, ".tls") == 0)
5555 {
5556 switch (window_size)
5557 {
5558 case 0: orig_insn.opcode = xtensa_callx0_opcode; break;
5559 case 4: orig_insn.opcode = xtensa_callx4_opcode; break;
5560 case 8: orig_insn.opcode = xtensa_callx8_opcode; break;
5561 case 12: orig_insn.opcode = xtensa_callx12_opcode; break;
5562 }
5563
5564 if (num_args != 2)
5565 as_bad (_("wrong number of operands for '%s'"), opname);
5566 else
5567 {
5568 bfd_reloc_code_real_type reloc;
5569 char *old_input_line_pointer;
5570 expressionS *tok = &orig_insn.extra_arg;
5571
5572 old_input_line_pointer = input_line_pointer;
5573 input_line_pointer = arg_strings[num_args - 1];
5574
5575 expression (tok);
5576 if (tok->X_op == O_symbol
5577 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
5578 == BFD_RELOC_XTENSA_TLS_CALL))
5579 tok->X_op = map_suffix_reloc_to_operator (reloc);
5580 else
5581 as_bad (_("bad relocation expression for '%s'"), opname);
5582
5583 input_line_pointer = old_input_line_pointer;
5584 num_args -= 1;
5585 }
5586 }
5587 }
5588
5589 /* Special case: Check for "j.l" pseudo op. */
5590 if (orig_insn.opcode == XTENSA_UNDEFINED
5591 && strncasecmp (opname, "j.l", 3) == 0)
5592 {
5593 if (num_args != 2)
5594 as_bad (_("wrong number of operands for '%s'"), opname);
5595 else
5596 {
5597 char *old_input_line_pointer;
5598 expressionS *tok = &orig_insn.extra_arg;
5599
5600 old_input_line_pointer = input_line_pointer;
5601 input_line_pointer = arg_strings[num_args - 1];
5602
5603 expression_maybe_register (xtensa_jx_opcode, 0, tok);
5604 input_line_pointer = old_input_line_pointer;
5605
5606 num_args -= 1;
5607 orig_insn.opcode = xtensa_j_opcode;
5608 }
5609 }
5610
5611 if (orig_insn.opcode == XTENSA_UNDEFINED)
5612 {
5613 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5614 if (fmt == XTENSA_UNDEFINED)
5615 {
5616 as_bad (_("unknown opcode or format name '%s'"), opname);
5617 error_reset_cur_vinsn ();
5618 return;
5619 }
5620 if (!cur_vinsn.inside_bundle)
5621 {
5622 as_bad (_("format names only valid inside bundles"));
5623 error_reset_cur_vinsn ();
5624 return;
5625 }
5626 if (cur_vinsn.format != XTENSA_UNDEFINED)
5627 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5628 opname);
5629 cur_vinsn.format = fmt;
5630 free (has_underbar ? opname - 1 : opname);
5631 error_reset_cur_vinsn ();
5632 return;
5633 }
5634
5635 /* Parse the arguments. */
5636 if (parse_arguments (&orig_insn, num_args, arg_strings))
5637 {
5638 as_bad (_("syntax error"));
5639 error_reset_cur_vinsn ();
5640 return;
5641 }
5642
5643 /* Free the opcode and argument strings, now that they've been parsed. */
5644 free (has_underbar ? opname - 1 : opname);
5645 opname = 0;
5646 while (num_args-- > 0)
5647 free (arg_strings[num_args]);
5648
5649 /* Get expressions for invisible operands. */
5650 if (get_invisible_operands (&orig_insn))
5651 {
5652 error_reset_cur_vinsn ();
5653 return;
5654 }
5655
5656 /* Check for the right number and type of arguments. */
5657 if (tinsn_check_arguments (&orig_insn))
5658 {
5659 error_reset_cur_vinsn ();
5660 return;
5661 }
5662
5663 /* Record the line number for each TInsn, because a FLIX bundle may be
5664 spread across multiple input lines and individual instructions may be
5665 moved around in some cases. */
5666 orig_insn.loc_directive_seen = dwarf2_loc_directive_seen;
5667 dwarf2_where (&orig_insn.debug_line);
5668 dwarf2_consume_line_info ();
5669
5670 xg_add_branch_and_loop_targets (&orig_insn);
5671
5672 /* Check that immediate value for ENTRY is >= 16. */
5673 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
5674 {
5675 expressionS *exp = &orig_insn.tok[2];
5676 if (exp->X_op == O_constant && exp->X_add_number < 16)
5677 as_warn (_("entry instruction with stack decrement < 16"));
5678 }
5679
5680 /* Finish it off:
5681 assemble_tokens (opcode, tok, ntok);
5682 expand the tokens from the orig_insn into the
5683 stack of instructions that will not expand
5684 unless required at relaxation time. */
5685
5686 if (!cur_vinsn.inside_bundle)
5687 emit_single_op (&orig_insn);
5688 else /* We are inside a bundle. */
5689 {
5690 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5691 cur_vinsn.num_slots++;
5692 if (*input_line_pointer == '}'
5693 || *(input_line_pointer - 1) == '}'
5694 || *(input_line_pointer - 2) == '}')
5695 finish_vinsn (&cur_vinsn);
5696 }
5697
5698 /* We've just emitted a new instruction so clear the list of labels. */
5699 xtensa_clear_insn_labels ();
5700
5701 xtensa_check_frag_count ();
5702 }
5703
5704
5705 /* HANDLE_ALIGN hook */
5706
5707 /* For a .align directive, we mark the previous block with the alignment
5708 information. This will be placed in the object file in the
5709 property section corresponding to this section. */
5710
5711 void
xtensa_handle_align(fragS * fragP)5712 xtensa_handle_align (fragS *fragP)
5713 {
5714 if (linkrelax
5715 && ! fragP->tc_frag_data.is_literal
5716 && (fragP->fr_type == rs_align
5717 || fragP->fr_type == rs_align_code)
5718 && fragP->fr_offset > 0
5719 && now_seg != bss_section)
5720 {
5721 fragP->tc_frag_data.is_align = TRUE;
5722 fragP->tc_frag_data.alignment = fragP->fr_offset;
5723 }
5724
5725 if (fragP->fr_type == rs_align_test)
5726 {
5727 int count;
5728 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5729 if (count != 0)
5730 as_bad_where (fragP->fr_file, fragP->fr_line,
5731 _("unaligned entry instruction"));
5732 }
5733
5734 if (linkrelax && fragP->fr_type == rs_org)
5735 fragP->fr_subtype = RELAX_ORG;
5736 }
5737
5738
5739 /* TC_FRAG_INIT hook */
5740
5741 void
xtensa_frag_init(fragS * frag)5742 xtensa_frag_init (fragS *frag)
5743 {
5744 xtensa_set_frag_assembly_state (frag);
5745 }
5746
5747
5748 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)5749 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5750 {
5751 return NULL;
5752 }
5753
5754
5755 /* Round up a section size to the appropriate boundary. */
5756
5757 valueT
md_section_align(segT segment ATTRIBUTE_UNUSED,valueT size)5758 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5759 {
5760 return size; /* Byte alignment is fine. */
5761 }
5762
5763
5764 long
md_pcrel_from(fixS * fixP)5765 md_pcrel_from (fixS *fixP)
5766 {
5767 char *insn_p;
5768 static xtensa_insnbuf insnbuf = NULL;
5769 static xtensa_insnbuf slotbuf = NULL;
5770 int opnum;
5771 uint32 opnd_value;
5772 xtensa_opcode opcode;
5773 xtensa_format fmt;
5774 int slot;
5775 xtensa_isa isa = xtensa_default_isa;
5776 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5777 bfd_boolean alt_reloc;
5778
5779 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5780 return 0;
5781
5782 if (fixP->fx_r_type == BFD_RELOC_32_PCREL)
5783 return addr;
5784
5785 if (!insnbuf)
5786 {
5787 insnbuf = xtensa_insnbuf_alloc (isa);
5788 slotbuf = xtensa_insnbuf_alloc (isa);
5789 }
5790
5791 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5792 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
5793 fmt = xtensa_format_decode (isa, insnbuf);
5794
5795 if (fmt == XTENSA_UNDEFINED)
5796 as_fatal (_("bad instruction format"));
5797
5798 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5799 as_fatal (_("invalid relocation"));
5800
5801 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5802 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5803
5804 /* Check for "alternate" relocations (operand not specified). None
5805 of the current uses for these are really PC-relative. */
5806 if (alt_reloc || opcode == xtensa_const16_opcode)
5807 {
5808 if (opcode != xtensa_l32r_opcode
5809 && opcode != xtensa_const16_opcode)
5810 as_fatal (_("invalid relocation for '%s' instruction"),
5811 xtensa_opcode_name (isa, opcode));
5812 return 0;
5813 }
5814
5815 opnum = get_relaxable_immed (opcode);
5816 opnd_value = 0;
5817 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5818 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5819 {
5820 as_bad_where (fixP->fx_file,
5821 fixP->fx_line,
5822 _("invalid relocation for operand %d of '%s'"),
5823 opnum, xtensa_opcode_name (isa, opcode));
5824 return 0;
5825 }
5826 return 0 - opnd_value;
5827 }
5828
5829
5830 /* TC_FORCE_RELOCATION hook */
5831
5832 int
xtensa_force_relocation(fixS * fix)5833 xtensa_force_relocation (fixS *fix)
5834 {
5835 switch (fix->fx_r_type)
5836 {
5837 case BFD_RELOC_XTENSA_ASM_EXPAND:
5838 case BFD_RELOC_XTENSA_SLOT0_ALT:
5839 case BFD_RELOC_XTENSA_SLOT1_ALT:
5840 case BFD_RELOC_XTENSA_SLOT2_ALT:
5841 case BFD_RELOC_XTENSA_SLOT3_ALT:
5842 case BFD_RELOC_XTENSA_SLOT4_ALT:
5843 case BFD_RELOC_XTENSA_SLOT5_ALT:
5844 case BFD_RELOC_XTENSA_SLOT6_ALT:
5845 case BFD_RELOC_XTENSA_SLOT7_ALT:
5846 case BFD_RELOC_XTENSA_SLOT8_ALT:
5847 case BFD_RELOC_XTENSA_SLOT9_ALT:
5848 case BFD_RELOC_XTENSA_SLOT10_ALT:
5849 case BFD_RELOC_XTENSA_SLOT11_ALT:
5850 case BFD_RELOC_XTENSA_SLOT12_ALT:
5851 case BFD_RELOC_XTENSA_SLOT13_ALT:
5852 case BFD_RELOC_XTENSA_SLOT14_ALT:
5853 return 1;
5854 default:
5855 break;
5856 }
5857
5858 if (linkrelax && fix->fx_addsy
5859 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5860 return 1;
5861
5862 return generic_force_reloc (fix);
5863 }
5864
5865
5866 /* TC_VALIDATE_FIX_SUB hook */
5867
5868 int
xtensa_validate_fix_sub(fixS * fix)5869 xtensa_validate_fix_sub (fixS *fix)
5870 {
5871 segT add_symbol_segment, sub_symbol_segment;
5872
5873 /* The difference of two symbols should be resolved by the assembler when
5874 linkrelax is not set. If the linker may relax the section containing
5875 the symbols, then an Xtensa DIFF relocation must be generated so that
5876 the linker knows to adjust the difference value. */
5877 if (!linkrelax || fix->fx_addsy == NULL)
5878 return 0;
5879
5880 /* Make sure both symbols are in the same segment, and that segment is
5881 "normal" and relaxable. If the segment is not "normal", then the
5882 fix is not valid. If the segment is not "relaxable", then the fix
5883 should have been handled earlier. */
5884 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5885 if (! SEG_NORMAL (add_symbol_segment) ||
5886 ! relaxable_section (add_symbol_segment))
5887 return 0;
5888 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5889 return (sub_symbol_segment == add_symbol_segment);
5890 }
5891
5892
5893 /* NO_PSEUDO_DOT hook */
5894
5895 /* This function has nothing to do with pseudo dots, but this is the
5896 nearest macro to where the check needs to take place. FIXME: This
5897 seems wrong. */
5898
5899 bfd_boolean
xtensa_check_inside_bundle(void)5900 xtensa_check_inside_bundle (void)
5901 {
5902 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5903 as_bad (_("directives are not valid inside bundles"));
5904
5905 /* This function must always return FALSE because it is called via a
5906 macro that has nothing to do with bundling. */
5907 return FALSE;
5908 }
5909
5910
5911 /* md_elf_section_change_hook */
5912
5913 void
xtensa_elf_section_change_hook(void)5914 xtensa_elf_section_change_hook (void)
5915 {
5916 /* Set up the assembly state. */
5917 if (!frag_now->tc_frag_data.is_assembly_state_set)
5918 xtensa_set_frag_assembly_state (frag_now);
5919
5920 if (!use_literal_section
5921 && seg_info (now_seg)->tc_segment_info_data.literal_pool_loc == NULL
5922 && !xtensa_is_init_fini (now_seg))
5923 xtensa_mark_literal_pool_location ();
5924 }
5925
5926
5927 /* tc_fix_adjustable hook */
5928
5929 bfd_boolean
xtensa_fix_adjustable(fixS * fixP)5930 xtensa_fix_adjustable (fixS *fixP)
5931 {
5932 /* We need the symbol name for the VTABLE entries. */
5933 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5934 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5935 return 0;
5936
5937 return 1;
5938 }
5939
5940
5941 /* tc_symbol_new_hook */
5942
5943 symbolS *expr_symbols = NULL;
5944
5945 void
xtensa_symbol_new_hook(symbolS * sym)5946 xtensa_symbol_new_hook (symbolS *sym)
5947 {
5948 if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section)
5949 {
5950 symbol_get_tc (sym)->next_expr_symbol = expr_symbols;
5951 expr_symbols = sym;
5952 }
5953 }
5954
5955
5956 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg)5957 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
5958 {
5959 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5960 valueT val = 0;
5961
5962 /* Subtracted symbols are only allowed for a few relocation types, and
5963 unless linkrelax is enabled, they should not make it to this point. */
5964 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
5965 || fixP->fx_r_type == BFD_RELOC_16
5966 || fixP->fx_r_type == BFD_RELOC_8)))
5967 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
5968
5969 switch (fixP->fx_r_type)
5970 {
5971 case BFD_RELOC_32_PCREL:
5972 case BFD_RELOC_32:
5973 case BFD_RELOC_16:
5974 case BFD_RELOC_8:
5975 if (fixP->fx_subsy)
5976 {
5977 switch (fixP->fx_r_type)
5978 {
5979 case BFD_RELOC_8:
5980 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5981 fixP->fx_signed = 0;
5982 break;
5983 case BFD_RELOC_16:
5984 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5985 fixP->fx_signed = 0;
5986 break;
5987 case BFD_RELOC_32:
5988 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5989 fixP->fx_signed = 0;
5990 break;
5991 default:
5992 break;
5993 }
5994
5995 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5996 - S_GET_VALUE (fixP->fx_subsy));
5997
5998 /* The difference value gets written out, and the DIFF reloc
5999 identifies the address of the subtracted symbol (i.e., the one
6000 with the lowest address). */
6001 *valP = val;
6002 fixP->fx_offset -= val;
6003 fixP->fx_subsy = NULL;
6004 }
6005 else if (! fixP->fx_addsy)
6006 {
6007 val = *valP;
6008 fixP->fx_done = 1;
6009 }
6010 else if (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section)
6011 {
6012 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
6013 *valP = val;
6014 fixP->fx_done = 1;
6015 }
6016 /* fall through */
6017
6018 case BFD_RELOC_XTENSA_PLT:
6019 md_number_to_chars (fixpos, val, fixP->fx_size);
6020 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
6021 break;
6022
6023 case BFD_RELOC_XTENSA_TLSDESC_FN:
6024 case BFD_RELOC_XTENSA_TLSDESC_ARG:
6025 case BFD_RELOC_XTENSA_TLS_TPOFF:
6026 case BFD_RELOC_XTENSA_TLS_DTPOFF:
6027 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6028 md_number_to_chars (fixpos, 0, fixP->fx_size);
6029 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
6030 break;
6031
6032 case BFD_RELOC_XTENSA_SLOT0_OP:
6033 case BFD_RELOC_XTENSA_SLOT1_OP:
6034 case BFD_RELOC_XTENSA_SLOT2_OP:
6035 case BFD_RELOC_XTENSA_SLOT3_OP:
6036 case BFD_RELOC_XTENSA_SLOT4_OP:
6037 case BFD_RELOC_XTENSA_SLOT5_OP:
6038 case BFD_RELOC_XTENSA_SLOT6_OP:
6039 case BFD_RELOC_XTENSA_SLOT7_OP:
6040 case BFD_RELOC_XTENSA_SLOT8_OP:
6041 case BFD_RELOC_XTENSA_SLOT9_OP:
6042 case BFD_RELOC_XTENSA_SLOT10_OP:
6043 case BFD_RELOC_XTENSA_SLOT11_OP:
6044 case BFD_RELOC_XTENSA_SLOT12_OP:
6045 case BFD_RELOC_XTENSA_SLOT13_OP:
6046 case BFD_RELOC_XTENSA_SLOT14_OP:
6047 if (linkrelax)
6048 {
6049 /* Write the tentative value of a PC-relative relocation to a
6050 local symbol into the instruction. The value will be ignored
6051 by the linker, and it makes the object file disassembly
6052 readable when all branch targets are encoded in relocations. */
6053
6054 gas_assert (fixP->fx_addsy);
6055 if (S_GET_SEGMENT (fixP->fx_addsy) == seg
6056 && !S_FORCE_RELOC (fixP->fx_addsy, 1))
6057 {
6058 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6059 - md_pcrel_from (fixP));
6060 (void) xg_apply_fix_value (fixP, val);
6061 }
6062 }
6063 else if (! fixP->fx_addsy)
6064 {
6065 val = *valP;
6066 if (xg_apply_fix_value (fixP, val))
6067 fixP->fx_done = 1;
6068 }
6069 break;
6070
6071 case BFD_RELOC_XTENSA_ASM_EXPAND:
6072 case BFD_RELOC_XTENSA_TLS_FUNC:
6073 case BFD_RELOC_XTENSA_TLS_ARG:
6074 case BFD_RELOC_XTENSA_TLS_CALL:
6075 case BFD_RELOC_XTENSA_SLOT0_ALT:
6076 case BFD_RELOC_XTENSA_SLOT1_ALT:
6077 case BFD_RELOC_XTENSA_SLOT2_ALT:
6078 case BFD_RELOC_XTENSA_SLOT3_ALT:
6079 case BFD_RELOC_XTENSA_SLOT4_ALT:
6080 case BFD_RELOC_XTENSA_SLOT5_ALT:
6081 case BFD_RELOC_XTENSA_SLOT6_ALT:
6082 case BFD_RELOC_XTENSA_SLOT7_ALT:
6083 case BFD_RELOC_XTENSA_SLOT8_ALT:
6084 case BFD_RELOC_XTENSA_SLOT9_ALT:
6085 case BFD_RELOC_XTENSA_SLOT10_ALT:
6086 case BFD_RELOC_XTENSA_SLOT11_ALT:
6087 case BFD_RELOC_XTENSA_SLOT12_ALT:
6088 case BFD_RELOC_XTENSA_SLOT13_ALT:
6089 case BFD_RELOC_XTENSA_SLOT14_ALT:
6090 /* These all need to be resolved at link-time. Do nothing now. */
6091 break;
6092
6093 case BFD_RELOC_VTABLE_INHERIT:
6094 case BFD_RELOC_VTABLE_ENTRY:
6095 fixP->fx_done = 0;
6096 break;
6097
6098 default:
6099 as_bad (_("unhandled local relocation fix %s"),
6100 bfd_get_reloc_code_name (fixP->fx_r_type));
6101 }
6102 }
6103
6104
6105 const char *
md_atof(int type,char * litP,int * sizeP)6106 md_atof (int type, char *litP, int *sizeP)
6107 {
6108 return ieee_md_atof (type, litP, sizeP, target_big_endian);
6109 }
6110
6111
6112 int
md_estimate_size_before_relax(fragS * fragP,segT seg ATTRIBUTE_UNUSED)6113 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
6114 {
6115 return total_frag_text_expansion (fragP);
6116 }
6117
6118
6119 /* Translate internal representation of relocation info to BFD target
6120 format. */
6121
6122 arelent *
tc_gen_reloc(asection * section ATTRIBUTE_UNUSED,fixS * fixp)6123 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
6124 {
6125 arelent *reloc;
6126
6127 reloc = XNEW (arelent);
6128 reloc->sym_ptr_ptr = XNEW (asymbol *);
6129 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6130 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6131
6132 /* Make sure none of our internal relocations make it this far.
6133 They'd better have been fully resolved by this point. */
6134 gas_assert ((int) fixp->fx_r_type > 0);
6135
6136 reloc->addend = fixp->fx_offset;
6137
6138 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
6139 if (reloc->howto == NULL)
6140 {
6141 as_bad_where (fixp->fx_file, fixp->fx_line,
6142 _("cannot represent `%s' relocation in object file"),
6143 bfd_get_reloc_code_name (fixp->fx_r_type));
6144 free (reloc->sym_ptr_ptr);
6145 free (reloc);
6146 return NULL;
6147 }
6148
6149 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
6150 as_fatal (_("internal error; cannot generate `%s' relocation"),
6151 bfd_get_reloc_code_name (fixp->fx_r_type));
6152
6153 return reloc;
6154 }
6155
6156
6157 /* Checks for resource conflicts between instructions. */
6158
6159 /* The func unit stuff could be implemented as bit-vectors rather
6160 than the iterative approach here. If it ends up being too
6161 slow, we will switch it. */
6162
6163 resource_table *
new_resource_table(void * data,int cycles,int nu,unit_num_copies_func uncf,opcode_num_units_func onuf,opcode_funcUnit_use_unit_func ouuf,opcode_funcUnit_use_stage_func ousf)6164 new_resource_table (void *data,
6165 int cycles,
6166 int nu,
6167 unit_num_copies_func uncf,
6168 opcode_num_units_func onuf,
6169 opcode_funcUnit_use_unit_func ouuf,
6170 opcode_funcUnit_use_stage_func ousf)
6171 {
6172 int i;
6173 resource_table *rt = XNEW (resource_table);
6174 rt->data = data;
6175 rt->cycles = cycles;
6176 rt->allocated_cycles = cycles;
6177 rt->num_units = nu;
6178 rt->unit_num_copies = uncf;
6179 rt->opcode_num_units = onuf;
6180 rt->opcode_unit_use = ouuf;
6181 rt->opcode_unit_stage = ousf;
6182
6183 rt->units = XCNEWVEC (unsigned char *, cycles);
6184 for (i = 0; i < cycles; i++)
6185 rt->units[i] = XCNEWVEC (unsigned char, nu);
6186
6187 return rt;
6188 }
6189
6190
6191 void
clear_resource_table(resource_table * rt)6192 clear_resource_table (resource_table *rt)
6193 {
6194 int i, j;
6195 for (i = 0; i < rt->allocated_cycles; i++)
6196 for (j = 0; j < rt->num_units; j++)
6197 rt->units[i][j] = 0;
6198 }
6199
6200
6201 /* We never shrink it, just fake it into thinking so. */
6202
6203 void
resize_resource_table(resource_table * rt,int cycles)6204 resize_resource_table (resource_table *rt, int cycles)
6205 {
6206 int i, old_cycles;
6207
6208 rt->cycles = cycles;
6209 if (cycles <= rt->allocated_cycles)
6210 return;
6211
6212 old_cycles = rt->allocated_cycles;
6213 rt->allocated_cycles = cycles;
6214
6215 rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles);
6216 for (i = 0; i < old_cycles; i++)
6217 rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units);
6218 for (i = old_cycles; i < cycles; i++)
6219 rt->units[i] = XCNEWVEC (unsigned char, rt->num_units);
6220 }
6221
6222
6223 bfd_boolean
resources_available(resource_table * rt,xtensa_opcode opcode,int cycle)6224 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
6225 {
6226 int i;
6227 int uses = (rt->opcode_num_units) (rt->data, opcode);
6228
6229 for (i = 0; i < uses; i++)
6230 {
6231 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6232 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6233 int copies_in_use = rt->units[stage + cycle][unit];
6234 int copies = (rt->unit_num_copies) (rt->data, unit);
6235 if (copies_in_use >= copies)
6236 return FALSE;
6237 }
6238 return TRUE;
6239 }
6240
6241
6242 void
reserve_resources(resource_table * rt,xtensa_opcode opcode,int cycle)6243 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6244 {
6245 int i;
6246 int uses = (rt->opcode_num_units) (rt->data, opcode);
6247
6248 for (i = 0; i < uses; i++)
6249 {
6250 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6251 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6252 /* Note that this allows resources to be oversubscribed. That's
6253 essential to the way the optional scheduler works.
6254 resources_available reports when a resource is over-subscribed,
6255 so it's easy to tell. */
6256 rt->units[stage + cycle][unit]++;
6257 }
6258 }
6259
6260
6261 void
release_resources(resource_table * rt,xtensa_opcode opcode,int cycle)6262 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6263 {
6264 int i;
6265 int uses = (rt->opcode_num_units) (rt->data, opcode);
6266
6267 for (i = 0; i < uses; i++)
6268 {
6269 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6270 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6271 gas_assert (rt->units[stage + cycle][unit] > 0);
6272 rt->units[stage + cycle][unit]--;
6273 }
6274 }
6275
6276
6277 /* Wrapper functions make parameterized resource reservation
6278 more convenient. */
6279
6280 int
opcode_funcUnit_use_unit(void * data,xtensa_opcode opcode,int idx)6281 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6282 {
6283 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6284 return use->unit;
6285 }
6286
6287
6288 int
opcode_funcUnit_use_stage(void * data,xtensa_opcode opcode,int idx)6289 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6290 {
6291 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6292 return use->stage;
6293 }
6294
6295
6296 /* Note that this function does not check issue constraints, but
6297 solely whether the hardware is available to execute the given
6298 instructions together. It also doesn't check if the tinsns
6299 write the same state, or access the same tieports. That is
6300 checked by check_t1_t2_reads_and_writes. */
6301
6302 static bfd_boolean
resources_conflict(vliw_insn * vinsn)6303 resources_conflict (vliw_insn *vinsn)
6304 {
6305 int i;
6306 static resource_table *rt = NULL;
6307
6308 /* This is the most common case by far. Optimize it. */
6309 if (vinsn->num_slots == 1)
6310 return FALSE;
6311
6312 if (rt == NULL)
6313 {
6314 xtensa_isa isa = xtensa_default_isa;
6315 rt = new_resource_table
6316 (isa, xtensa_num_pipe_stages,
6317 xtensa_isa_num_funcUnits (isa),
6318 (unit_num_copies_func) xtensa_funcUnit_num_copies,
6319 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6320 opcode_funcUnit_use_unit,
6321 opcode_funcUnit_use_stage);
6322 }
6323
6324 clear_resource_table (rt);
6325
6326 for (i = 0; i < vinsn->num_slots; i++)
6327 {
6328 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6329 return TRUE;
6330 reserve_resources (rt, vinsn->slots[i].opcode, 0);
6331 }
6332
6333 return FALSE;
6334 }
6335
6336
6337 /* finish_vinsn, emit_single_op and helper functions. */
6338
6339 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6340 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6341 static void xg_assemble_vliw_tokens (vliw_insn *);
6342
6343
6344 /* We have reached the end of a bundle; emit into the frag. */
6345
6346 static void
finish_vinsn(vliw_insn * vinsn)6347 finish_vinsn (vliw_insn *vinsn)
6348 {
6349 IStack slotstack;
6350 int i;
6351 int slots;
6352
6353 if (find_vinsn_conflicts (vinsn))
6354 {
6355 xg_clear_vinsn (vinsn);
6356 return;
6357 }
6358
6359 /* First, find a format that works. */
6360 if (vinsn->format == XTENSA_UNDEFINED)
6361 vinsn->format = xg_find_narrowest_format (vinsn);
6362
6363 slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format);
6364 if (slots > 1
6365 && produce_flix == FLIX_NONE)
6366 {
6367 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6368 xg_clear_vinsn (vinsn);
6369 return;
6370 }
6371
6372 if (vinsn->format == XTENSA_UNDEFINED)
6373 {
6374 as_bad (_("couldn't find a valid instruction format"));
6375 fprintf (stderr, _(" ops were: "));
6376 for (i = 0; i < vinsn->num_slots; i++)
6377 fprintf (stderr, _(" %s;"),
6378 xtensa_opcode_name (xtensa_default_isa,
6379 vinsn->slots[i].opcode));
6380 fprintf (stderr, _("\n"));
6381 xg_clear_vinsn (vinsn);
6382 return;
6383 }
6384
6385 if (vinsn->num_slots != slots)
6386 {
6387 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6388 xtensa_format_name (xtensa_default_isa, vinsn->format),
6389 slots, vinsn->num_slots);
6390 xg_clear_vinsn (vinsn);
6391 return;
6392 }
6393
6394 if (resources_conflict (vinsn))
6395 {
6396 as_bad (_("illegal resource usage in bundle"));
6397 fprintf (stderr, " ops were: ");
6398 for (i = 0; i < vinsn->num_slots; i++)
6399 fprintf (stderr, " %s;",
6400 xtensa_opcode_name (xtensa_default_isa,
6401 vinsn->slots[i].opcode));
6402 fprintf (stderr, "\n");
6403 xg_clear_vinsn (vinsn);
6404 return;
6405 }
6406
6407 for (i = 0; i < vinsn->num_slots; i++)
6408 {
6409 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6410 {
6411 symbolS *lit_sym = NULL;
6412 int j;
6413 bfd_boolean e = FALSE;
6414 bfd_boolean saved_density = density_supported;
6415
6416 /* We don't want to narrow ops inside multi-slot bundles. */
6417 if (vinsn->num_slots > 1)
6418 density_supported = FALSE;
6419
6420 istack_init (&slotstack);
6421 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6422 {
6423 vinsn->slots[i].opcode =
6424 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6425 vinsn->format, i);
6426 vinsn->slots[i].ntok = 0;
6427 }
6428
6429 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6430 {
6431 e = TRUE;
6432 continue;
6433 }
6434
6435 density_supported = saved_density;
6436
6437 if (e)
6438 {
6439 xg_clear_vinsn (vinsn);
6440 return;
6441 }
6442
6443 for (j = 0; j < slotstack.ninsn; j++)
6444 {
6445 TInsn *insn = &slotstack.insn[j];
6446 if (insn->insn_type == ITYPE_LITERAL)
6447 {
6448 gas_assert (lit_sym == NULL);
6449 lit_sym = xg_assemble_literal (insn);
6450 }
6451 else
6452 {
6453 gas_assert (insn->insn_type == ITYPE_INSN);
6454 if (lit_sym)
6455 xg_resolve_literals (insn, lit_sym);
6456 if (j != slotstack.ninsn - 1)
6457 emit_single_op (insn);
6458 }
6459 }
6460
6461 if (vinsn->num_slots > 1)
6462 {
6463 if (opcode_fits_format_slot
6464 (slotstack.insn[slotstack.ninsn - 1].opcode,
6465 vinsn->format, i))
6466 {
6467 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6468 }
6469 else
6470 {
6471 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6472 if (vinsn->format == XTENSA_UNDEFINED)
6473 vinsn->slots[i].opcode = xtensa_nop_opcode;
6474 else
6475 vinsn->slots[i].opcode
6476 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6477 vinsn->format, i);
6478
6479 vinsn->slots[i].ntok = 0;
6480 }
6481 }
6482 else
6483 {
6484 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6485 vinsn->format = XTENSA_UNDEFINED;
6486 }
6487 }
6488 }
6489
6490 /* Now check resource conflicts on the modified bundle. */
6491 if (resources_conflict (vinsn))
6492 {
6493 as_bad (_("illegal resource usage in bundle"));
6494 fprintf (stderr, " ops were: ");
6495 for (i = 0; i < vinsn->num_slots; i++)
6496 fprintf (stderr, " %s;",
6497 xtensa_opcode_name (xtensa_default_isa,
6498 vinsn->slots[i].opcode));
6499 fprintf (stderr, "\n");
6500 xg_clear_vinsn (vinsn);
6501 return;
6502 }
6503
6504 /* First, find a format that works. */
6505 if (vinsn->format == XTENSA_UNDEFINED)
6506 vinsn->format = xg_find_narrowest_format (vinsn);
6507
6508 xg_assemble_vliw_tokens (vinsn);
6509
6510 xg_clear_vinsn (vinsn);
6511
6512 xtensa_check_frag_count ();
6513 }
6514
6515
6516 /* Given an vliw instruction, what conflicts are there in register
6517 usage and in writes to states and queues?
6518
6519 This function does two things:
6520 1. Reports an error when a vinsn contains illegal combinations
6521 of writes to registers states or queues.
6522 2. Marks individual tinsns as not relaxable if the combination
6523 contains antidependencies.
6524
6525 Job 2 handles things like swap semantics in instructions that need
6526 to be relaxed. For example,
6527
6528 addi a0, a1, 100000
6529
6530 normally would be relaxed to
6531
6532 l32r a0, some_label
6533 add a0, a1, a0
6534
6535 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6536
6537 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6538
6539 then we can't relax it into
6540
6541 l32r a0, some_label
6542 { add a0, a1, a0 ; add a2, a0, a4 ; }
6543
6544 because the value of a0 is trashed before the second add can read it. */
6545
6546 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6547
6548 static bfd_boolean
find_vinsn_conflicts(vliw_insn * vinsn)6549 find_vinsn_conflicts (vliw_insn *vinsn)
6550 {
6551 int i, j;
6552 int branches = 0;
6553 xtensa_isa isa = xtensa_default_isa;
6554
6555 gas_assert (!past_xtensa_end);
6556
6557 for (i = 0 ; i < vinsn->num_slots; i++)
6558 {
6559 TInsn *op1 = &vinsn->slots[i];
6560 if (op1->is_specific_opcode)
6561 op1->keep_wide = TRUE;
6562 else
6563 op1->keep_wide = FALSE;
6564 }
6565
6566 for (i = 0 ; i < vinsn->num_slots; i++)
6567 {
6568 TInsn *op1 = &vinsn->slots[i];
6569
6570 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6571 branches++;
6572
6573 for (j = 0; j < vinsn->num_slots; j++)
6574 {
6575 if (i != j)
6576 {
6577 TInsn *op2 = &vinsn->slots[j];
6578 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6579 switch (conflict_type)
6580 {
6581 case 'c':
6582 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6583 xtensa_opcode_name (isa, op1->opcode), i,
6584 xtensa_opcode_name (isa, op2->opcode), j);
6585 return TRUE;
6586 case 'd':
6587 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6588 xtensa_opcode_name (isa, op1->opcode), i,
6589 xtensa_opcode_name (isa, op2->opcode), j);
6590 return TRUE;
6591 case 'e':
6592 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6593 xtensa_opcode_name (isa, op1->opcode), i,
6594 xtensa_opcode_name (isa, op2->opcode), j);
6595 return TRUE;
6596 case 'f':
6597 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6598 xtensa_opcode_name (isa, op1->opcode), i,
6599 xtensa_opcode_name (isa, op2->opcode), j);
6600 return TRUE;
6601 default:
6602 /* Everything is OK. */
6603 break;
6604 }
6605 op2->is_specific_opcode = (op2->is_specific_opcode
6606 || conflict_type == 'a');
6607 }
6608 }
6609 }
6610
6611 if (branches > 1)
6612 {
6613 as_bad (_("multiple branches or jumps in the same bundle"));
6614 return TRUE;
6615 }
6616
6617 return FALSE;
6618 }
6619
6620
6621 /* Check how the state used by t1 and t2 relate.
6622 Cases found are:
6623
6624 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6625 case B: no relationship between what is read and written (both could
6626 read the same reg though)
6627 case C: t1 writes a register t2 writes (a register conflict within a
6628 bundle)
6629 case D: t1 writes a state that t2 also writes
6630 case E: t1 writes a tie queue that t2 also writes
6631 case F: two volatile queue accesses
6632 */
6633
6634 static char
check_t1_t2_reads_and_writes(TInsn * t1,TInsn * t2)6635 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6636 {
6637 xtensa_isa isa = xtensa_default_isa;
6638 xtensa_regfile t1_regfile, t2_regfile;
6639 int t1_reg, t2_reg;
6640 int t1_base_reg, t1_last_reg;
6641 int t2_base_reg, t2_last_reg;
6642 char t1_inout, t2_inout;
6643 int i, j;
6644 char conflict = 'b';
6645 int t1_states;
6646 int t2_states;
6647 int t1_interfaces;
6648 int t2_interfaces;
6649 bfd_boolean t1_volatile = FALSE;
6650 bfd_boolean t2_volatile = FALSE;
6651
6652 /* Check registers. */
6653 for (j = 0; j < t2->ntok; j++)
6654 {
6655 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6656 continue;
6657
6658 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6659 t2_base_reg = t2->tok[j].X_add_number;
6660 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6661
6662 for (i = 0; i < t1->ntok; i++)
6663 {
6664 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6665 continue;
6666
6667 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6668
6669 if (t1_regfile != t2_regfile)
6670 continue;
6671
6672 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6673 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6674
6675 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6676 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6677 {
6678 if (t1_inout == 'm' || t1_inout == 'o'
6679 || t2_inout == 'm' || t2_inout == 'o')
6680 {
6681 conflict = 'a';
6682 continue;
6683 }
6684 }
6685
6686 t1_base_reg = t1->tok[i].X_add_number;
6687 t1_last_reg = (t1_base_reg
6688 + xtensa_operand_num_regs (isa, t1->opcode, i));
6689
6690 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6691 {
6692 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6693 {
6694 if (t1_reg != t2_reg)
6695 continue;
6696
6697 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6698 {
6699 conflict = 'a';
6700 continue;
6701 }
6702
6703 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6704 {
6705 conflict = 'a';
6706 continue;
6707 }
6708
6709 if (t1_inout != 'i' && t2_inout != 'i')
6710 return 'c';
6711 }
6712 }
6713 }
6714 }
6715
6716 /* Check states. */
6717 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6718 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6719 for (j = 0; j < t2_states; j++)
6720 {
6721 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6722 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6723 for (i = 0; i < t1_states; i++)
6724 {
6725 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6726 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6727 if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1)
6728 continue;
6729
6730 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6731 {
6732 conflict = 'a';
6733 continue;
6734 }
6735
6736 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6737 {
6738 conflict = 'a';
6739 continue;
6740 }
6741
6742 if (t1_inout != 'i' && t2_inout != 'i')
6743 return 'd';
6744 }
6745 }
6746
6747 /* Check tieports. */
6748 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6749 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6750 for (j = 0; j < t2_interfaces; j++)
6751 {
6752 xtensa_interface t2_int
6753 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6754 int t2_class = xtensa_interface_class_id (isa, t2_int);
6755
6756 t2_inout = xtensa_interface_inout (isa, t2_int);
6757 if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6758 t2_volatile = TRUE;
6759
6760 for (i = 0; i < t1_interfaces; i++)
6761 {
6762 xtensa_interface t1_int
6763 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6764 int t1_class = xtensa_interface_class_id (isa, t1_int);
6765
6766 t1_inout = xtensa_interface_inout (isa, t1_int);
6767 if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6768 t1_volatile = TRUE;
6769
6770 if (t1_volatile && t2_volatile && (t1_class == t2_class))
6771 return 'f';
6772
6773 if (t1_int != t2_int)
6774 continue;
6775
6776 if (t2_inout == 'i' && t1_inout == 'o')
6777 {
6778 conflict = 'a';
6779 continue;
6780 }
6781
6782 if (t1_inout == 'i' && t2_inout == 'o')
6783 {
6784 conflict = 'a';
6785 continue;
6786 }
6787
6788 if (t1_inout != 'i' && t2_inout != 'i')
6789 return 'e';
6790 }
6791 }
6792
6793 return conflict;
6794 }
6795
6796
6797 static xtensa_format
xg_find_narrowest_format(vliw_insn * vinsn)6798 xg_find_narrowest_format (vliw_insn *vinsn)
6799 {
6800 /* Right now we assume that the ops within the vinsn are properly
6801 ordered for the slots that the programmer wanted them in. In
6802 other words, we don't rearrange the ops in hopes of finding a
6803 better format. The scheduler handles that. */
6804
6805 xtensa_isa isa = xtensa_default_isa;
6806 xtensa_format format;
6807 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6808
6809 if (vinsn->num_slots == 1)
6810 return xg_get_single_format (vinsn->slots[0].opcode);
6811
6812 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6813 {
6814 vliw_insn v_copy;
6815 xg_copy_vinsn (&v_copy, vinsn);
6816 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6817 {
6818 int slot;
6819 int fit = 0;
6820 for (slot = 0; slot < v_copy.num_slots; slot++)
6821 {
6822 if (v_copy.slots[slot].opcode == nop_opcode)
6823 {
6824 v_copy.slots[slot].opcode =
6825 xtensa_format_slot_nop_opcode (isa, format, slot);
6826 v_copy.slots[slot].ntok = 0;
6827 }
6828
6829 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6830 format, slot))
6831 fit++;
6832 else if (v_copy.num_slots > 1)
6833 {
6834 TInsn widened;
6835 /* Try the widened version. */
6836 if (!v_copy.slots[slot].keep_wide
6837 && !v_copy.slots[slot].is_specific_opcode
6838 && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6839 &widened, TRUE)
6840 && opcode_fits_format_slot (widened.opcode,
6841 format, slot))
6842 {
6843 v_copy.slots[slot] = widened;
6844 fit++;
6845 }
6846 }
6847 }
6848 if (fit == v_copy.num_slots)
6849 {
6850 xg_copy_vinsn (vinsn, &v_copy);
6851 xtensa_format_encode (isa, format, vinsn->insnbuf);
6852 vinsn->format = format;
6853 break;
6854 }
6855 }
6856 }
6857
6858 if (format == xtensa_isa_num_formats (isa))
6859 return XTENSA_UNDEFINED;
6860
6861 return format;
6862 }
6863
6864
6865 /* Return the additional space needed in a frag
6866 for possible relaxations of any ops in a VLIW insn.
6867 Also fill out the relaxations that might be required of
6868 each tinsn in the vinsn. */
6869
6870 static int
relaxation_requirements(vliw_insn * vinsn,bfd_boolean * pfinish_frag)6871 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
6872 {
6873 bfd_boolean finish_frag = FALSE;
6874 int extra_space = 0;
6875 int slot;
6876
6877 for (slot = 0; slot < vinsn->num_slots; slot++)
6878 {
6879 TInsn *tinsn = &vinsn->slots[slot];
6880 if (!tinsn_has_symbolic_operands (tinsn))
6881 {
6882 /* A narrow instruction could be widened later to help
6883 alignment issues. */
6884 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
6885 && !tinsn->is_specific_opcode
6886 && vinsn->num_slots == 1)
6887 {
6888 /* Difference in bytes between narrow and wide insns... */
6889 extra_space += 1;
6890 tinsn->subtype = RELAX_NARROW;
6891 }
6892 }
6893 else
6894 {
6895 if (workaround_b_j_loop_end
6896 && tinsn->opcode == xtensa_jx_opcode
6897 && use_transform ())
6898 {
6899 /* Add 2 of these. */
6900 extra_space += 3; /* for the nop size */
6901 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6902 }
6903
6904 /* Need to assemble it with space for the relocation. */
6905 if (xg_is_relaxable_insn (tinsn, 0)
6906 && !tinsn->is_specific_opcode)
6907 {
6908 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6909 int max_literal_size =
6910 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6911
6912 tinsn->literal_space = max_literal_size;
6913
6914 tinsn->subtype = RELAX_IMMED;
6915 extra_space += max_size;
6916 }
6917 else
6918 {
6919 /* A fix record will be added for this instruction prior
6920 to relaxation, so make it end the frag. */
6921 finish_frag = TRUE;
6922 }
6923 }
6924 }
6925 *pfinish_frag = finish_frag;
6926 return extra_space;
6927 }
6928
6929
6930 static void
bundle_tinsn(TInsn * tinsn,vliw_insn * vinsn)6931 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
6932 {
6933 xtensa_isa isa = xtensa_default_isa;
6934 int slot, chosen_slot;
6935
6936 vinsn->format = xg_get_single_format (tinsn->opcode);
6937 gas_assert (vinsn->format != XTENSA_UNDEFINED);
6938 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
6939
6940 chosen_slot = xg_get_single_slot (tinsn->opcode);
6941 for (slot = 0; slot < vinsn->num_slots; slot++)
6942 {
6943 if (slot == chosen_slot)
6944 vinsn->slots[slot] = *tinsn;
6945 else
6946 {
6947 vinsn->slots[slot].opcode =
6948 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
6949 vinsn->slots[slot].ntok = 0;
6950 vinsn->slots[slot].insn_type = ITYPE_INSN;
6951 }
6952 }
6953 }
6954
6955
6956 static bfd_boolean
emit_single_op(TInsn * orig_insn)6957 emit_single_op (TInsn *orig_insn)
6958 {
6959 int i;
6960 IStack istack; /* put instructions into here */
6961 symbolS *lit_sym = NULL;
6962 symbolS *label_sym = NULL;
6963
6964 istack_init (&istack);
6965
6966 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6967 Because the scheduling and bundling characteristics of movi and
6968 l32r or const16 are so different, we can do much better if we relax
6969 it prior to scheduling and bundling, rather than after. */
6970 if ((orig_insn->opcode == xtensa_movi_opcode
6971 || orig_insn->opcode == xtensa_movi_n_opcode)
6972 && !cur_vinsn.inside_bundle
6973 && (orig_insn->tok[1].X_op == O_symbol
6974 || orig_insn->tok[1].X_op == O_pltrel
6975 || orig_insn->tok[1].X_op == O_tlsfunc
6976 || orig_insn->tok[1].X_op == O_tlsarg
6977 || orig_insn->tok[1].X_op == O_tpoff
6978 || orig_insn->tok[1].X_op == O_dtpoff)
6979 && !orig_insn->is_specific_opcode && use_transform ())
6980 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6981 else
6982 if (xg_expand_assembly_insn (&istack, orig_insn))
6983 return TRUE;
6984
6985 for (i = 0; i < istack.ninsn; i++)
6986 {
6987 TInsn *insn = &istack.insn[i];
6988 switch (insn->insn_type)
6989 {
6990 case ITYPE_LITERAL:
6991 gas_assert (lit_sym == NULL);
6992 lit_sym = xg_assemble_literal (insn);
6993 break;
6994 case ITYPE_LABEL:
6995 {
6996 static int relaxed_sym_idx = 0;
6997 char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12);
6998 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6999 colon (label);
7000 gas_assert (label_sym == NULL);
7001 label_sym = symbol_find_or_make (label);
7002 gas_assert (label_sym);
7003 free (label);
7004 }
7005 break;
7006 case ITYPE_INSN:
7007 {
7008 vliw_insn v;
7009 if (lit_sym)
7010 xg_resolve_literals (insn, lit_sym);
7011 if (label_sym)
7012 xg_resolve_labels (insn, label_sym);
7013 xg_init_vinsn (&v);
7014 bundle_tinsn (insn, &v);
7015 finish_vinsn (&v);
7016 xg_free_vinsn (&v);
7017 }
7018 break;
7019 default:
7020 gas_assert (0);
7021 break;
7022 }
7023 }
7024 return FALSE;
7025 }
7026
7027
7028 static int
total_frag_text_expansion(fragS * fragP)7029 total_frag_text_expansion (fragS *fragP)
7030 {
7031 int slot;
7032 int total_expansion = 0;
7033
7034 for (slot = 0; slot < config_max_slots; slot++)
7035 total_expansion += fragP->tc_frag_data.text_expansion[slot];
7036
7037 return total_expansion;
7038 }
7039
7040
7041 /* Emit a vliw instruction to the current fragment. */
7042
7043 static void
xg_assemble_vliw_tokens(vliw_insn * vinsn)7044 xg_assemble_vliw_tokens (vliw_insn *vinsn)
7045 {
7046 bfd_boolean finish_frag;
7047 bfd_boolean is_jump = FALSE;
7048 bfd_boolean is_branch = FALSE;
7049 xtensa_isa isa = xtensa_default_isa;
7050 int insn_size;
7051 int extra_space;
7052 char *f = NULL;
7053 int slot;
7054 struct dwarf2_line_info debug_line;
7055 bfd_boolean loc_directive_seen = FALSE;
7056 TInsn *tinsn;
7057
7058 memset (&debug_line, 0, sizeof (struct dwarf2_line_info));
7059
7060 if (generating_literals)
7061 {
7062 static int reported = 0;
7063 if (reported < 4)
7064 as_bad_where (frag_now->fr_file, frag_now->fr_line,
7065 _("cannot assemble into a literal fragment"));
7066 if (reported == 3)
7067 as_bad (_("..."));
7068 reported++;
7069 return;
7070 }
7071
7072 if (frag_now_fix () != 0
7073 && (! frag_now->tc_frag_data.is_insn
7074 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7075 || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform
7076 || (directive_state[directive_longcalls]
7077 != frag_now->tc_frag_data.use_longcalls)
7078 || (directive_state[directive_absolute_literals]
7079 != frag_now->tc_frag_data.use_absolute_literals)))
7080 {
7081 frag_wane (frag_now);
7082 frag_new (0);
7083 xtensa_set_frag_assembly_state (frag_now);
7084 }
7085
7086 if (workaround_a0_b_retw
7087 && vinsn->num_slots == 1
7088 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
7089 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
7090 && use_transform ())
7091 {
7092 has_a0_b_retw = TRUE;
7093
7094 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7095 After the first assembly pass we will check all of them and
7096 add a nop if needed. */
7097 frag_now->tc_frag_data.is_insn = TRUE;
7098 frag_var (rs_machine_dependent, 4, 4,
7099 RELAX_ADD_NOP_IF_A0_B_RETW,
7100 frag_now->fr_symbol,
7101 frag_now->fr_offset,
7102 NULL);
7103 xtensa_set_frag_assembly_state (frag_now);
7104 frag_now->tc_frag_data.is_insn = TRUE;
7105 frag_var (rs_machine_dependent, 4, 4,
7106 RELAX_ADD_NOP_IF_A0_B_RETW,
7107 frag_now->fr_symbol,
7108 frag_now->fr_offset,
7109 NULL);
7110 xtensa_set_frag_assembly_state (frag_now);
7111 }
7112
7113 for (slot = 0; slot < vinsn->num_slots; slot++)
7114 {
7115 tinsn = &vinsn->slots[slot];
7116
7117 /* See if the instruction implies an aligned section. */
7118 if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1)
7119 record_alignment (now_seg, 2);
7120
7121 /* Determine the best line number for debug info. */
7122 if ((tinsn->loc_directive_seen || !loc_directive_seen)
7123 && (tinsn->debug_line.filenum != debug_line.filenum
7124 || tinsn->debug_line.line < debug_line.line
7125 || tinsn->debug_line.column < debug_line.column))
7126 debug_line = tinsn->debug_line;
7127 if (tinsn->loc_directive_seen)
7128 loc_directive_seen = TRUE;
7129 }
7130
7131 /* Special cases for instructions that force an alignment... */
7132 /* None of these opcodes are bundle-able. */
7133 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
7134 {
7135 int max_fill;
7136
7137 /* Remember the symbol that marks the end of the loop in the frag
7138 that marks the start of the loop. This way we can easily find
7139 the end of the loop at the beginning, without adding special code
7140 to mark the loop instructions themselves. */
7141 symbolS *target_sym = NULL;
7142 if (vinsn->slots[0].tok[1].X_op == O_symbol)
7143 target_sym = vinsn->slots[0].tok[1].X_add_symbol;
7144
7145 xtensa_set_frag_assembly_state (frag_now);
7146 frag_now->tc_frag_data.is_insn = TRUE;
7147
7148 max_fill = get_text_align_max_fill_size
7149 (get_text_align_power (xtensa_fetch_width),
7150 TRUE, frag_now->tc_frag_data.is_no_density);
7151
7152 if (use_transform ())
7153 frag_var (rs_machine_dependent, max_fill, max_fill,
7154 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7155 else
7156 frag_var (rs_machine_dependent, 0, 0,
7157 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7158 xtensa_set_frag_assembly_state (frag_now);
7159 }
7160
7161 if (vinsn->slots[0].opcode == xtensa_entry_opcode
7162 && !vinsn->slots[0].is_specific_opcode)
7163 {
7164 xtensa_mark_literal_pool_location ();
7165 xtensa_move_labels (frag_now, 0);
7166 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
7167 }
7168
7169 if (vinsn->num_slots == 1)
7170 {
7171 if (workaround_a0_b_retw && use_transform ())
7172 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
7173 is_register_writer (&vinsn->slots[0], "a", 0));
7174
7175 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
7176 is_bad_loopend_opcode (&vinsn->slots[0]));
7177 }
7178 else
7179 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
7180
7181 insn_size = xtensa_format_length (isa, vinsn->format);
7182
7183 extra_space = relaxation_requirements (vinsn, &finish_frag);
7184
7185 /* vinsn_to_insnbuf will produce the error. */
7186 if (vinsn->format != XTENSA_UNDEFINED)
7187 {
7188 f = frag_more (insn_size + extra_space);
7189 xtensa_set_frag_assembly_state (frag_now);
7190 frag_now->tc_frag_data.is_insn = TRUE;
7191 }
7192
7193 vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
7194 if (vinsn->format == XTENSA_UNDEFINED)
7195 return;
7196
7197 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
7198
7199 if (debug_type == DEBUG_DWARF2 || loc_directive_seen)
7200 dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space),
7201 &debug_line);
7202
7203 for (slot = 0; slot < vinsn->num_slots; slot++)
7204 {
7205 tinsn = &vinsn->slots[slot];
7206 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7207 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7208 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
7209 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7210 if (tinsn->opcode == xtensa_l32r_opcode)
7211 frag_now->tc_frag_data.literal_frags[slot]
7212 = symbol_get_frag (tinsn->tok[1].X_add_symbol);
7213 if (tinsn->literal_space != 0)
7214 xg_assemble_literal_space (tinsn->literal_space, slot);
7215 frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg;
7216
7217 if (tinsn->subtype == RELAX_NARROW)
7218 gas_assert (vinsn->num_slots == 1);
7219 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7220 is_jump = TRUE;
7221 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7222 is_branch = TRUE;
7223
7224 if (tinsn->subtype || tinsn->symbol || tinsn->offset
7225 || tinsn->literal_frag || is_jump || is_branch)
7226 finish_frag = TRUE;
7227 }
7228
7229 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7230 frag_now->tc_frag_data.is_specific_opcode = TRUE;
7231
7232 if (finish_frag)
7233 {
7234 frag_variant (rs_machine_dependent,
7235 extra_space, extra_space, RELAX_SLOTS,
7236 frag_now->fr_symbol, frag_now->fr_offset, f);
7237 xtensa_set_frag_assembly_state (frag_now);
7238 }
7239
7240 /* Special cases for loops:
7241 close_loop_end should be inserted AFTER short_loop.
7242 Make sure that CLOSE loops are processed BEFORE short_loops
7243 when converting them. */
7244
7245 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7246 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
7247 && !vinsn->slots[0].is_specific_opcode)
7248 {
7249 if (workaround_short_loop && use_transform ())
7250 {
7251 maybe_has_short_loop = TRUE;
7252 frag_now->tc_frag_data.is_insn = TRUE;
7253 frag_var (rs_machine_dependent, 4, 4,
7254 RELAX_ADD_NOP_IF_SHORT_LOOP,
7255 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7256 frag_now->tc_frag_data.is_insn = TRUE;
7257 frag_var (rs_machine_dependent, 4, 4,
7258 RELAX_ADD_NOP_IF_SHORT_LOOP,
7259 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7260 }
7261
7262 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7263 loop at least 12 bytes away from another loop's end. */
7264 if (workaround_close_loop_end && use_transform ())
7265 {
7266 maybe_has_close_loop_end = TRUE;
7267 frag_now->tc_frag_data.is_insn = TRUE;
7268 frag_var (rs_machine_dependent, 12, 12,
7269 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7270 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7271 }
7272 }
7273
7274 if (use_transform ())
7275 {
7276 if (is_jump)
7277 {
7278 gas_assert (finish_frag);
7279 frag_var (rs_machine_dependent,
7280 xtensa_fetch_width, xtensa_fetch_width,
7281 RELAX_UNREACHABLE,
7282 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7283 xtensa_set_frag_assembly_state (frag_now);
7284 xtensa_maybe_create_trampoline_frag ();
7285 /* Always create one here. */
7286 xtensa_maybe_create_literal_pool_frag (TRUE, FALSE);
7287 }
7288 else if (is_branch && do_align_targets ())
7289 {
7290 gas_assert (finish_frag);
7291 frag_var (rs_machine_dependent,
7292 xtensa_fetch_width, xtensa_fetch_width,
7293 RELAX_MAYBE_UNREACHABLE,
7294 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7295 xtensa_set_frag_assembly_state (frag_now);
7296 frag_var (rs_machine_dependent,
7297 0, 0,
7298 RELAX_MAYBE_DESIRE_ALIGN,
7299 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7300 xtensa_set_frag_assembly_state (frag_now);
7301 }
7302 }
7303
7304 /* Now, if the original opcode was a call... */
7305 if (do_align_targets ()
7306 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7307 {
7308 float freq = get_subseg_total_freq (now_seg, now_subseg);
7309 frag_now->tc_frag_data.is_insn = TRUE;
7310 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7311 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7312 xtensa_set_frag_assembly_state (frag_now);
7313 }
7314
7315 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7316 {
7317 frag_wane (frag_now);
7318 frag_new (0);
7319 xtensa_set_frag_assembly_state (frag_now);
7320 }
7321 }
7322
7323
7324 /* xtensa_end and helper functions. */
7325
7326 static void xtensa_cleanup_align_frags (void);
7327 static void xtensa_fix_target_frags (void);
7328 static void xtensa_mark_narrow_branches (void);
7329 static void xtensa_mark_zcl_first_insns (void);
7330 static void xtensa_mark_difference_of_two_symbols (void);
7331 static void xtensa_fix_a0_b_retw_frags (void);
7332 static void xtensa_fix_b_j_loop_end_frags (void);
7333 static void xtensa_fix_close_loop_end_frags (void);
7334 static void xtensa_fix_short_loop_frags (void);
7335 static void xtensa_sanity_check (void);
7336 static void xtensa_add_config_info (void);
7337
7338 void
xtensa_end(void)7339 xtensa_end (void)
7340 {
7341 directive_balance ();
7342 xtensa_flush_pending_output ();
7343
7344 past_xtensa_end = TRUE;
7345
7346 xtensa_move_literals ();
7347
7348 xtensa_reorder_segments ();
7349 xtensa_cleanup_align_frags ();
7350 xtensa_fix_target_frags ();
7351 if (workaround_a0_b_retw && has_a0_b_retw)
7352 xtensa_fix_a0_b_retw_frags ();
7353 if (workaround_b_j_loop_end)
7354 xtensa_fix_b_j_loop_end_frags ();
7355
7356 /* "close_loop_end" should be processed BEFORE "short_loop". */
7357 if (workaround_close_loop_end && maybe_has_close_loop_end)
7358 xtensa_fix_close_loop_end_frags ();
7359
7360 if (workaround_short_loop && maybe_has_short_loop)
7361 xtensa_fix_short_loop_frags ();
7362 if (align_targets)
7363 xtensa_mark_narrow_branches ();
7364 xtensa_mark_zcl_first_insns ();
7365
7366 xtensa_sanity_check ();
7367
7368 xtensa_add_config_info ();
7369
7370 xtensa_check_frag_count ();
7371 }
7372
7373 struct trampoline_chain_entry
7374 {
7375 symbolS *sym;
7376 addressT offset;
7377 };
7378
7379 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7380 of locations of trampoline jumps leading there. Jumps are represented
7381 as pairs (sym, offset): trampoline frag symbol and offset of the jump
7382 inside the frag. */
7383 struct trampoline_chain
7384 {
7385 struct trampoline_chain_entry target;
7386 struct trampoline_chain_entry *entry;
7387 size_t n_entries;
7388 size_t n_max;
7389 bfd_boolean needs_sorting;
7390 };
7391
7392 struct trampoline_chain_index
7393 {
7394 struct trampoline_chain *entry;
7395 size_t n_entries;
7396 size_t n_max;
7397 bfd_boolean needs_sorting;
7398 };
7399
7400 struct trampoline_index
7401 {
7402 fragS **entry;
7403 size_t n_entries;
7404 size_t n_max;
7405 };
7406
7407 struct trampoline_seg
7408 {
7409 struct trampoline_seg *next;
7410 asection *seg;
7411 /* Trampolines ordered by their frag fr_address */
7412 struct trampoline_index index;
7413 /* Known trampoline chains ordered by (sym, offset) pair */
7414 struct trampoline_chain_index chain_index;
7415 };
7416
7417 static struct trampoline_seg trampoline_seg_list;
7418 #define J_RANGE (128 * 1024)
7419 #define J_MARGIN 4096
7420
7421 static int unreachable_count = 0;
7422
7423
7424 static void
xtensa_maybe_create_trampoline_frag(void)7425 xtensa_maybe_create_trampoline_frag (void)
7426 {
7427 if (!use_trampolines)
7428 return;
7429
7430 /* We create an area for possible trampolines every 10 unreachable frags.
7431 These are preferred over the ones not preceded by an unreachable frag,
7432 because we don't have to jump around them. This function is called after
7433 each RELAX_UNREACHABLE frag is created. */
7434
7435 if (++unreachable_count > 10)
7436 {
7437 xtensa_create_trampoline_frag (FALSE);
7438 clear_frag_count ();
7439 unreachable_count = 0;
7440 }
7441 }
7442
7443 static void
xtensa_check_frag_count(void)7444 xtensa_check_frag_count (void)
7445 {
7446 if (!use_trampolines || frag_now->tc_frag_data.is_no_transform)
7447 return;
7448
7449 /* We create an area for possible trampolines every 8000 frags or so. This
7450 is an estimate based on the max range of a "j" insn (+/-128K) divided
7451 by a typical frag byte count (16), minus a few for safety. This function
7452 is called after each source line is processed. */
7453
7454 if (get_frag_count () > 8000)
7455 {
7456 xtensa_create_trampoline_frag (TRUE);
7457 clear_frag_count ();
7458 unreachable_count = 0;
7459 }
7460
7461 /* We create an area for a possible literal pool every N (default 5000)
7462 frags or so. */
7463 xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
7464 }
7465
7466 static xtensa_insnbuf trampoline_buf = NULL;
7467 static xtensa_insnbuf trampoline_slotbuf = NULL;
7468
7469 static xtensa_insnbuf litpool_buf = NULL;
7470 static xtensa_insnbuf litpool_slotbuf = NULL;
7471
7472 #define TRAMPOLINE_FRAG_SIZE 3000
7473
7474 static struct trampoline_seg *
find_trampoline_seg(asection * seg)7475 find_trampoline_seg (asection *seg)
7476 {
7477 struct trampoline_seg *ts = trampoline_seg_list.next;
7478 static struct trampoline_seg *mr;
7479
7480 if (mr && mr->seg == seg)
7481 return mr;
7482
7483 for ( ; ts; ts = ts->next)
7484 {
7485 if (ts->seg == seg)
7486 {
7487 mr = ts;
7488 return ts;
7489 }
7490 }
7491
7492 return NULL;
7493 }
7494
xg_find_trampoline(const struct trampoline_index * idx,addressT addr)7495 static size_t xg_find_trampoline (const struct trampoline_index *idx,
7496 addressT addr)
7497 {
7498 size_t a = 0;
7499 size_t b = idx->n_entries;
7500
7501 while (b - a > 1)
7502 {
7503 size_t c = (a + b) / 2;
7504
7505 if (idx->entry[c]->fr_address <= addr)
7506 a = c;
7507 else
7508 b = c;
7509 }
7510 return a;
7511 }
7512
xg_add_trampoline_to_index(struct trampoline_index * idx,fragS * fragP)7513 static void xg_add_trampoline_to_index (struct trampoline_index *idx,
7514 fragS *fragP)
7515 {
7516 if (idx->n_entries == idx->n_max)
7517 {
7518 idx->n_max = (idx->n_entries + 1) * 2;
7519 idx->entry = xrealloc (idx->entry,
7520 sizeof (*idx->entry) * idx->n_max);
7521 }
7522 idx->entry[idx->n_entries] = fragP;
7523 ++idx->n_entries;
7524 }
7525
xg_remove_trampoline_from_index(struct trampoline_index * idx,size_t i)7526 static void xg_remove_trampoline_from_index (struct trampoline_index *idx,
7527 size_t i)
7528 {
7529 gas_assert (i < idx->n_entries);
7530 memmove (idx->entry + i, idx->entry + i + 1,
7531 (idx->n_entries - i - 1) * sizeof (*idx->entry));
7532 --idx->n_entries;
7533 }
7534
xg_add_trampoline_to_seg(struct trampoline_seg * ts,fragS * fragP)7535 static void xg_add_trampoline_to_seg (struct trampoline_seg *ts,
7536 fragS *fragP)
7537 {
7538 xg_add_trampoline_to_index (&ts->index, fragP);
7539 }
7540
7541 static void
xtensa_create_trampoline_frag(bfd_boolean needs_jump_around)7542 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around)
7543 {
7544 /* Emit a frag where we can place intermediate jump instructions,
7545 in case we need to jump farther than 128K bytes.
7546 Each jump instruction takes three bytes.
7547 We allocate enough for 1000 trampolines in each frag.
7548 If that's not enough, oh well. */
7549
7550 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
7551 char *varP;
7552 fragS *fragP;
7553 int size = TRAMPOLINE_FRAG_SIZE;
7554
7555 if (ts == NULL)
7556 {
7557 ts = XCNEW(struct trampoline_seg);
7558 ts->next = trampoline_seg_list.next;
7559 trampoline_seg_list.next = ts;
7560 ts->seg = now_seg;
7561 }
7562
7563 frag_wane (frag_now);
7564 frag_new (0);
7565 xtensa_set_frag_assembly_state (frag_now);
7566 varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL);
7567 fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG);
7568 if (trampoline_buf == NULL)
7569 {
7570 trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa);
7571 trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7572 }
7573 fragP->tc_frag_data.needs_jump_around = needs_jump_around;
7574 xg_add_trampoline_to_seg (ts, fragP);
7575 }
7576
xg_is_trampoline_frag_full(const fragS * fragP)7577 static bfd_boolean xg_is_trampoline_frag_full (const fragS *fragP)
7578 {
7579 return fragP->fr_var < 3;
7580 }
7581
xg_order_trampoline_chain_entry(const void * a,const void * b)7582 static int xg_order_trampoline_chain_entry (const void *a, const void *b)
7583 {
7584 const struct trampoline_chain_entry *pa = a;
7585 const struct trampoline_chain_entry *pb = b;
7586
7587 if (pa->sym != pb->sym)
7588 {
7589 valueT aval = S_GET_VALUE (pa->sym);
7590 valueT bval = S_GET_VALUE (pb->sym);
7591
7592 if (aval != bval)
7593 return aval < bval ? -1 : 1;
7594 }
7595 if (pa->offset != pb->offset)
7596 return pa->offset < pb->offset ? -1 : 1;
7597 return 0;
7598 }
7599
xg_sort_trampoline_chain(struct trampoline_chain * tc)7600 static void xg_sort_trampoline_chain (struct trampoline_chain *tc)
7601 {
7602 qsort (tc->entry, tc->n_entries, sizeof (*tc->entry),
7603 xg_order_trampoline_chain_entry);
7604 tc->needs_sorting = FALSE;
7605 }
7606
7607 /* Find entry index in the given chain with maximal address <= source. */
xg_find_chain_entry(struct trampoline_chain * tc,addressT source)7608 static size_t xg_find_chain_entry (struct trampoline_chain *tc,
7609 addressT source)
7610 {
7611 size_t a = 0;
7612 size_t b = tc->n_entries;
7613
7614 if (tc->needs_sorting)
7615 xg_sort_trampoline_chain (tc);
7616
7617 while (b - a > 1)
7618 {
7619 size_t c = (a + b) / 2;
7620 struct trampoline_chain_entry *e = tc->entry + c;
7621
7622 if (S_GET_VALUE(e->sym) + e->offset <= source)
7623 a = c;
7624 else
7625 b = c;
7626 }
7627 return a;
7628 }
7629
7630 /* Find the best jump target for the source in the given trampoline chain.
7631 The best jump target is the one that results in the shortest path to the
7632 final target, it's the location of the jump closest to the final target,
7633 but within the J_RANGE - J_MARGIN from the source. */
7634 static struct trampoline_chain_entry *
xg_get_best_chain_entry(struct trampoline_chain * tc,addressT source)7635 xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source)
7636 {
7637 addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset;
7638 size_t i = xg_find_chain_entry (tc, source);
7639 struct trampoline_chain_entry *e = tc->entry + i;
7640 int step = target < source ? -1 : 1;
7641 addressT chained_target;
7642 offsetT off;
7643
7644 if (target > source &&
7645 S_GET_VALUE(e->sym) + e->offset <= source &&
7646 i + 1 < tc->n_entries)
7647 ++i;
7648
7649 while (i + step < tc->n_entries)
7650 {
7651 struct trampoline_chain_entry *next = tc->entry + i + step;
7652
7653 chained_target = S_GET_VALUE(next->sym) + next->offset;
7654 off = source - chained_target;
7655
7656 if (labs (off) >= J_RANGE - J_MARGIN)
7657 break;
7658
7659 i += step;
7660 }
7661
7662 e = tc->entry + i;
7663 chained_target = S_GET_VALUE(e->sym) + e->offset;
7664 off = source - chained_target;
7665
7666 if (labs (off) < J_MARGIN ||
7667 labs (off) >= J_RANGE - J_MARGIN)
7668 return &tc->target;
7669 return tc->entry + i;
7670 }
7671
xg_order_trampoline_chain(const void * a,const void * b)7672 static int xg_order_trampoline_chain (const void *a, const void *b)
7673 {
7674 const struct trampoline_chain *_pa = a;
7675 const struct trampoline_chain *_pb = b;
7676 const struct trampoline_chain_entry *pa = &_pa->target;
7677 const struct trampoline_chain_entry *pb = &_pb->target;
7678 symbolS *s1 = pa->sym;
7679 symbolS *s2 = pb->sym;
7680
7681 if (s1 != s2)
7682 {
7683 symbolS *tmp = symbol_symbolS (s1);
7684 if (tmp)
7685 s1 = tmp;
7686
7687 tmp = symbol_symbolS (s2);
7688 if (tmp)
7689 s2 = tmp;
7690
7691 if (s1 != s2)
7692 return s1 < s2 ? -1 : 1;
7693 }
7694
7695 if (pa->offset != pb->offset)
7696 return pa->offset < pb->offset ? -1 : 1;
7697 return 0;
7698 }
7699
7700 static struct trampoline_chain *
xg_get_trampoline_chain(struct trampoline_seg * ts,symbolS * sym,addressT offset)7701 xg_get_trampoline_chain (struct trampoline_seg *ts,
7702 symbolS *sym,
7703 addressT offset)
7704 {
7705 struct trampoline_chain_index *idx = &ts->chain_index;
7706 struct trampoline_chain c;
7707
7708 if (idx->needs_sorting)
7709 {
7710 qsort (idx->entry, idx->n_entries, sizeof (*idx->entry),
7711 xg_order_trampoline_chain);
7712 idx->needs_sorting = FALSE;
7713 }
7714 c.target.sym = sym;
7715 c.target.offset = offset;
7716 return bsearch (&c, idx->entry, idx->n_entries,
7717 sizeof (struct trampoline_chain),
7718 xg_order_trampoline_chain);
7719 }
7720
7721 /* Find trampoline chain in the given trampoline segment that is going
7722 to the *sym + *offset. If found, replace *sym and *offset with the
7723 best jump target in that chain. */
7724 static struct trampoline_chain *
xg_find_best_eq_target(struct trampoline_seg * ts,addressT source,symbolS ** sym,addressT * offset)7725 xg_find_best_eq_target (struct trampoline_seg *ts,
7726 addressT source, symbolS **sym,
7727 addressT *offset)
7728 {
7729 struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset);
7730
7731 if (tc)
7732 {
7733 struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source);
7734
7735 *sym = e->sym;
7736 *offset = e->offset;
7737 }
7738 return tc;
7739 }
7740
xg_add_location_to_chain(struct trampoline_chain * tc,symbolS * sym,addressT offset)7741 static void xg_add_location_to_chain (struct trampoline_chain *tc,
7742 symbolS *sym, addressT offset)
7743 {
7744 struct trampoline_chain_entry *e;
7745
7746 if (tc->n_entries == tc->n_max)
7747 {
7748 tc->n_max = (tc->n_max + 1) * 2;
7749 tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max);
7750 }
7751 e = tc->entry + tc->n_entries;
7752 e->sym = sym;
7753 e->offset = offset;
7754 ++tc->n_entries;
7755 tc->needs_sorting = TRUE;
7756 }
7757
7758 static struct trampoline_chain *
xg_create_trampoline_chain(struct trampoline_seg * ts,symbolS * sym,addressT offset)7759 xg_create_trampoline_chain (struct trampoline_seg *ts,
7760 symbolS *sym, addressT offset)
7761 {
7762 struct trampoline_chain_index *idx = &ts->chain_index;
7763 struct trampoline_chain *tc;
7764
7765 if (idx->n_entries == idx->n_max)
7766 {
7767 idx->n_max = (idx->n_max + 1) * 2;
7768 idx->entry = xrealloc (idx->entry,
7769 sizeof (*idx->entry) * idx->n_max);
7770 }
7771
7772 tc = idx->entry + idx->n_entries;
7773 tc->target.sym = sym;
7774 tc->target.offset = offset;
7775 tc->entry = NULL;
7776 tc->n_entries = 0;
7777 tc->n_max = 0;
7778 xg_add_location_to_chain (tc, sym, offset);
7779
7780 ++idx->n_entries;
7781 idx->needs_sorting = TRUE;
7782
7783 return tc;
7784 }
7785
7786 void dump_trampolines (void);
7787
7788 void
dump_trampolines(void)7789 dump_trampolines (void)
7790 {
7791 struct trampoline_seg *ts = trampoline_seg_list.next;
7792
7793 for ( ; ts; ts = ts->next)
7794 {
7795 size_t i;
7796 asection *seg = ts->seg;
7797
7798 if (seg == NULL)
7799 continue;
7800 fprintf(stderr, "SECTION %s\n", seg->name);
7801
7802 for (i = 0; i < ts->index.n_entries; ++i)
7803 {
7804 fragS *tf = ts->index.entry[i];
7805
7806 fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n",
7807 (int)tf->fr_address, (int)tf->fr_fix,
7808 tf->tc_frag_data.needs_jump_around ? "T" : "F");
7809 }
7810 }
7811 }
7812
7813 static void dump_litpools (void) __attribute__ ((unused));
7814
7815 static void
dump_litpools(void)7816 dump_litpools (void)
7817 {
7818 struct litpool_seg *lps = litpool_seg_list.next;
7819 struct litpool_frag *lpf;
7820
7821 for ( ; lps ; lps = lps->next )
7822 {
7823 printf("litpool seg %s\n", lps->seg->name);
7824 for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next )
7825 {
7826 fragS *litfrag = lpf->fragP->fr_next;
7827 int count = 0;
7828 while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END)
7829 {
7830 if (litfrag->fr_fix == 4)
7831 count++;
7832 litfrag = litfrag->fr_next;
7833 }
7834 printf(" %ld <%d:%d> (%d) [%d]: ",
7835 lpf->addr, lpf->priority, lpf->original_priority,
7836 lpf->fragP->fr_line, count);
7837 //dump_frag(lpf->fragP);
7838 }
7839 }
7840 }
7841
7842 static void
xtensa_maybe_create_literal_pool_frag(bfd_boolean create,bfd_boolean only_if_needed)7843 xtensa_maybe_create_literal_pool_frag (bfd_boolean create,
7844 bfd_boolean only_if_needed)
7845 {
7846 struct litpool_seg *lps = litpool_seg_list.next;
7847 fragS *fragP;
7848 struct litpool_frag *lpf;
7849 bfd_boolean needed = FALSE;
7850
7851 if (use_literal_section || !auto_litpools)
7852 return;
7853
7854 for ( ; lps ; lps = lps->next )
7855 {
7856 if (lps->seg == now_seg)
7857 break;
7858 }
7859
7860 if (lps == NULL)
7861 {
7862 lps = XCNEW (struct litpool_seg);
7863 lps->next = litpool_seg_list.next;
7864 litpool_seg_list.next = lps;
7865 lps->seg = now_seg;
7866 lps->frag_list.next = &lps->frag_list;
7867 lps->frag_list.prev = &lps->frag_list;
7868 /* Put candidate literal pool at the beginning of every section,
7869 so that even when section starts with literal load there's a
7870 literal pool available. */
7871 lps->frag_count = auto_litpool_limit;
7872 }
7873
7874 lps->frag_count++;
7875
7876 if (create)
7877 {
7878 if (only_if_needed)
7879 {
7880 if (past_xtensa_end || !use_transform() ||
7881 frag_now->tc_frag_data.is_no_transform)
7882 {
7883 return;
7884 }
7885 if (auto_litpool_limit <= 0)
7886 {
7887 /* Don't create a litpool based only on frag count. */
7888 return;
7889 }
7890 else if (lps->frag_count > auto_litpool_limit)
7891 {
7892 needed = TRUE;
7893 }
7894 else
7895 {
7896 return;
7897 }
7898 }
7899 else
7900 {
7901 needed = TRUE;
7902 }
7903 }
7904
7905 if (needed)
7906 {
7907 int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */
7908 /* Create a potential site for a literal pool. */
7909 frag_wane (frag_now);
7910 frag_new (0);
7911 xtensa_set_frag_assembly_state (frag_now);
7912 fragP = frag_now;
7913 fragP->tc_frag_data.lit_frchain = frchain_now;
7914 fragP->tc_frag_data.literal_frag = fragP;
7915 frag_var (rs_machine_dependent, size, size,
7916 (only_if_needed) ?
7917 RELAX_LITERAL_POOL_CANDIDATE_BEGIN :
7918 RELAX_LITERAL_POOL_BEGIN,
7919 NULL, 0, NULL);
7920 frag_now->tc_frag_data.lit_seg = now_seg;
7921 frag_variant (rs_machine_dependent, 0, 0,
7922 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
7923 xtensa_set_frag_assembly_state (frag_now);
7924 }
7925 else
7926 {
7927 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7928 just record it here. */
7929 fragP = frag_now;
7930 }
7931
7932 lpf = XNEW (struct litpool_frag);
7933 /* Insert at tail of circular list. */
7934 lpf->addr = 0;
7935 lps->frag_list.prev->next = lpf;
7936 lpf->next = &lps->frag_list;
7937 lpf->prev = lps->frag_list.prev;
7938 lps->frag_list.prev = lpf;
7939 lpf->fragP = fragP;
7940 lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1;
7941 lpf->original_priority = lpf->priority;
7942 lpf->literal_count = 0;
7943
7944 lps->frag_count = 0;
7945 }
7946
7947 static void
xtensa_cleanup_align_frags(void)7948 xtensa_cleanup_align_frags (void)
7949 {
7950 frchainS *frchP;
7951 asection *s;
7952
7953 for (s = stdoutput->sections; s; s = s->next)
7954 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7955 {
7956 fragS *fragP;
7957 /* Walk over all of the fragments in a subsection. */
7958 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7959 {
7960 if ((fragP->fr_type == rs_align
7961 || fragP->fr_type == rs_align_code
7962 || (fragP->fr_type == rs_machine_dependent
7963 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7964 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7965 && fragP->fr_fix == 0)
7966 {
7967 fragS *next = fragP->fr_next;
7968
7969 while (next
7970 && next->fr_fix == 0
7971 && next->fr_type == rs_machine_dependent
7972 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7973 {
7974 frag_wane (next);
7975 next = next->fr_next;
7976 }
7977 }
7978 /* If we don't widen branch targets, then they
7979 will be easier to align. */
7980 if (fragP->tc_frag_data.is_branch_target
7981 && fragP->fr_opcode == fragP->fr_literal
7982 && fragP->fr_type == rs_machine_dependent
7983 && fragP->fr_subtype == RELAX_SLOTS
7984 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7985 frag_wane (fragP);
7986 if (fragP->fr_type == rs_machine_dependent
7987 && fragP->fr_subtype == RELAX_UNREACHABLE)
7988 fragP->tc_frag_data.is_unreachable = TRUE;
7989 }
7990 }
7991 }
7992
7993
7994 /* Re-process all of the fragments looking to convert all of the
7995 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7996 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7997 Otherwise, convert to a .fill 0. */
7998
7999 static void
xtensa_fix_target_frags(void)8000 xtensa_fix_target_frags (void)
8001 {
8002 frchainS *frchP;
8003 asection *s;
8004
8005 /* When this routine is called, all of the subsections are still intact
8006 so we walk over subsections instead of sections. */
8007 for (s = stdoutput->sections; s; s = s->next)
8008 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8009 {
8010 fragS *fragP;
8011
8012 /* Walk over all of the fragments in a subsection. */
8013 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8014 {
8015 if (fragP->fr_type == rs_machine_dependent
8016 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
8017 {
8018 if (next_frag_is_branch_target (fragP))
8019 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
8020 else
8021 frag_wane (fragP);
8022 }
8023 }
8024 }
8025 }
8026
8027
8028 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
8029
8030 static void
xtensa_mark_narrow_branches(void)8031 xtensa_mark_narrow_branches (void)
8032 {
8033 frchainS *frchP;
8034 asection *s;
8035
8036 for (s = stdoutput->sections; s; s = s->next)
8037 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8038 {
8039 fragS *fragP;
8040 /* Walk over all of the fragments in a subsection. */
8041 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8042 {
8043 if (fragP->fr_type == rs_machine_dependent
8044 && fragP->fr_subtype == RELAX_SLOTS
8045 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8046 {
8047 vliw_insn vinsn;
8048
8049 vinsn_from_chars (&vinsn, fragP->fr_opcode);
8050 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
8051
8052 if (vinsn.num_slots == 1
8053 && xtensa_opcode_is_branch (xtensa_default_isa,
8054 vinsn.slots[0].opcode) == 1
8055 && xg_get_single_size (vinsn.slots[0].opcode) == 2
8056 && is_narrow_branch_guaranteed_in_range (fragP,
8057 &vinsn.slots[0]))
8058 {
8059 fragP->fr_subtype = RELAX_SLOTS;
8060 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
8061 fragP->tc_frag_data.is_aligning_branch = 1;
8062 }
8063 }
8064 }
8065 }
8066 }
8067
8068
8069 /* A branch is typically widened only when its target is out of
8070 range. However, we would like to widen them to align a subsequent
8071 branch target when possible.
8072
8073 Because the branch relaxation code is so convoluted, the optimal solution
8074 (combining the two cases) is difficult to get right in all circumstances.
8075 We therefore go with an "almost as good" solution, where we only
8076 use for alignment narrow branches that definitely will not expand to a
8077 jump and a branch. These functions find and mark these cases. */
8078
8079 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
8080 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8081 We start counting beginning with the frag after the 2-byte branch, so the
8082 maximum offset is (4 - 2) + 63 = 65. */
8083 #define MAX_IMMED6 65
8084
8085 static offsetT unrelaxed_frag_max_size (fragS *);
8086
8087 static bfd_boolean
is_narrow_branch_guaranteed_in_range(fragS * fragP,TInsn * tinsn)8088 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
8089 {
8090 const expressionS *exp = &tinsn->tok[1];
8091 symbolS *symbolP = exp->X_add_symbol;
8092 offsetT max_distance = exp->X_add_number;
8093 fragS *target_frag;
8094
8095 if (exp->X_op != O_symbol)
8096 return FALSE;
8097
8098 target_frag = symbol_get_frag (symbolP);
8099
8100 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
8101 if (is_branch_jmp_to_next (tinsn, fragP))
8102 return FALSE;
8103
8104 /* The branch doesn't branch over it's own frag,
8105 but over the subsequent ones. */
8106 fragP = fragP->fr_next;
8107 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
8108 {
8109 max_distance += unrelaxed_frag_max_size (fragP);
8110 fragP = fragP->fr_next;
8111 }
8112 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
8113 return TRUE;
8114 return FALSE;
8115 }
8116
8117
8118 static void
xtensa_mark_zcl_first_insns(void)8119 xtensa_mark_zcl_first_insns (void)
8120 {
8121 frchainS *frchP;
8122 asection *s;
8123
8124 for (s = stdoutput->sections; s; s = s->next)
8125 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8126 {
8127 fragS *fragP;
8128 /* Walk over all of the fragments in a subsection. */
8129 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8130 {
8131 if (fragP->fr_type == rs_machine_dependent
8132 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8133 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8134 {
8135 /* Find the loop frag. */
8136 fragS *loop_frag = next_non_empty_frag (fragP);
8137 /* Find the first insn frag. */
8138 fragS *targ_frag = next_non_empty_frag (loop_frag);
8139
8140 /* Handle a corner case that comes up in hardware
8141 diagnostics. The original assembly looks like this:
8142
8143 loop aX, LabelA
8144 <empty_frag>--not found by next_non_empty_frag
8145 loop aY, LabelB
8146
8147 Depending on the start address, the assembler may or
8148 may not change it to look something like this:
8149
8150 loop aX, LabelA
8151 nop--frag isn't empty anymore
8152 loop aY, LabelB
8153
8154 So set up to check the alignment of the nop if it
8155 exists */
8156 while (loop_frag != targ_frag)
8157 {
8158 if (loop_frag->fr_type == rs_machine_dependent
8159 && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8160 || loop_frag->fr_subtype
8161 == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8162 targ_frag = loop_frag;
8163 else
8164 loop_frag = loop_frag->fr_next;
8165 }
8166
8167 /* Of course, sometimes (mostly for toy test cases) a
8168 zero-cost loop instruction is the last in a section. */
8169 if (targ_frag)
8170 {
8171 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
8172 /* Do not widen a frag that is the first instruction of a
8173 zero-cost loop. It makes that loop harder to align. */
8174 if (targ_frag->fr_type == rs_machine_dependent
8175 && targ_frag->fr_subtype == RELAX_SLOTS
8176 && (targ_frag->tc_frag_data.slot_subtypes[0]
8177 == RELAX_NARROW))
8178 {
8179 if (targ_frag->tc_frag_data.is_aligning_branch)
8180 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
8181 else
8182 {
8183 frag_wane (targ_frag);
8184 targ_frag->tc_frag_data.slot_subtypes[0] = 0;
8185 }
8186 }
8187 }
8188 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
8189 frag_wane (fragP);
8190 }
8191 }
8192 }
8193 }
8194
8195
8196 /* When a difference-of-symbols expression is encoded as a uleb128 or
8197 sleb128 value, the linker is unable to adjust that value to account for
8198 link-time relaxation. Mark all the code between such symbols so that
8199 its size cannot be changed by linker relaxation. */
8200
8201 static void
xtensa_mark_difference_of_two_symbols(void)8202 xtensa_mark_difference_of_two_symbols (void)
8203 {
8204 symbolS *expr_sym;
8205
8206 for (expr_sym = expr_symbols; expr_sym;
8207 expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
8208 {
8209 expressionS *exp = symbol_get_value_expression (expr_sym);
8210
8211 if (exp->X_op == O_subtract)
8212 {
8213 symbolS *left = exp->X_add_symbol;
8214 symbolS *right = exp->X_op_symbol;
8215
8216 /* Difference of two symbols not in the same section
8217 are handled with relocations in the linker. */
8218 if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
8219 {
8220 fragS *start;
8221 fragS *end;
8222 fragS *walk;
8223
8224 if (symbol_get_frag (left)->fr_address
8225 <= symbol_get_frag (right)->fr_address)
8226 {
8227 start = symbol_get_frag (left);
8228 end = symbol_get_frag (right);
8229 }
8230 else
8231 {
8232 start = symbol_get_frag (right);
8233 end = symbol_get_frag (left);
8234 }
8235
8236 if (start->tc_frag_data.no_transform_end != NULL)
8237 walk = start->tc_frag_data.no_transform_end;
8238 else
8239 walk = start;
8240 do
8241 {
8242 walk->tc_frag_data.is_no_transform = 1;
8243 walk = walk->fr_next;
8244 }
8245 while (walk && walk->fr_address < end->fr_address);
8246
8247 start->tc_frag_data.no_transform_end = walk;
8248 }
8249 }
8250 }
8251 }
8252
8253
8254 /* Re-process all of the fragments looking to convert all of the
8255 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8256 conditional branch or a retw/retw.n, convert this frag to one that
8257 will generate a NOP. In any case close it off with a .fill 0. */
8258
8259 static bfd_boolean next_instrs_are_b_retw (fragS *);
8260
8261 static void
xtensa_fix_a0_b_retw_frags(void)8262 xtensa_fix_a0_b_retw_frags (void)
8263 {
8264 frchainS *frchP;
8265 asection *s;
8266
8267 /* When this routine is called, all of the subsections are still intact
8268 so we walk over subsections instead of sections. */
8269 for (s = stdoutput->sections; s; s = s->next)
8270 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8271 {
8272 fragS *fragP;
8273
8274 /* Walk over all of the fragments in a subsection. */
8275 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8276 {
8277 if (fragP->fr_type == rs_machine_dependent
8278 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
8279 {
8280 if (next_instrs_are_b_retw (fragP))
8281 {
8282 if (fragP->tc_frag_data.is_no_transform)
8283 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8284 else
8285 relax_frag_add_nop (fragP);
8286 }
8287 frag_wane (fragP);
8288 }
8289 }
8290 }
8291 }
8292
8293
8294 static bfd_boolean
next_instrs_are_b_retw(fragS * fragP)8295 next_instrs_are_b_retw (fragS *fragP)
8296 {
8297 xtensa_opcode opcode;
8298 xtensa_format fmt;
8299 const fragS *next_fragP = next_non_empty_frag (fragP);
8300 static xtensa_insnbuf insnbuf = NULL;
8301 static xtensa_insnbuf slotbuf = NULL;
8302 xtensa_isa isa = xtensa_default_isa;
8303 unsigned int offset = 0;
8304 int slot;
8305 bfd_boolean branch_seen = FALSE;
8306
8307 if (!insnbuf)
8308 {
8309 insnbuf = xtensa_insnbuf_alloc (isa);
8310 slotbuf = xtensa_insnbuf_alloc (isa);
8311 }
8312
8313 if (next_fragP == NULL)
8314 return FALSE;
8315
8316 /* Check for the conditional branch. */
8317 xtensa_insnbuf_from_chars
8318 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8319 fmt = xtensa_format_decode (isa, insnbuf);
8320 if (fmt == XTENSA_UNDEFINED)
8321 return FALSE;
8322
8323 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8324 {
8325 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
8326 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
8327
8328 branch_seen = (branch_seen
8329 || xtensa_opcode_is_branch (isa, opcode) == 1);
8330 }
8331
8332 if (!branch_seen)
8333 return FALSE;
8334
8335 offset += xtensa_format_length (isa, fmt);
8336 if (offset == next_fragP->fr_fix)
8337 {
8338 next_fragP = next_non_empty_frag (next_fragP);
8339 offset = 0;
8340 }
8341
8342 if (next_fragP == NULL)
8343 return FALSE;
8344
8345 /* Check for the retw/retw.n. */
8346 xtensa_insnbuf_from_chars
8347 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8348 fmt = xtensa_format_decode (isa, insnbuf);
8349
8350 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8351 have no problems. */
8352 if (fmt == XTENSA_UNDEFINED
8353 || xtensa_format_num_slots (isa, fmt) != 1)
8354 return FALSE;
8355
8356 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
8357 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
8358
8359 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
8360 return TRUE;
8361
8362 return FALSE;
8363 }
8364
8365
8366 /* Re-process all of the fragments looking to convert all of the
8367 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8368 loop end label, convert this frag to one that will generate a NOP.
8369 In any case close it off with a .fill 0. */
8370
8371 static bfd_boolean next_instr_is_loop_end (fragS *);
8372
8373 static void
xtensa_fix_b_j_loop_end_frags(void)8374 xtensa_fix_b_j_loop_end_frags (void)
8375 {
8376 frchainS *frchP;
8377 asection *s;
8378
8379 /* When this routine is called, all of the subsections are still intact
8380 so we walk over subsections instead of sections. */
8381 for (s = stdoutput->sections; s; s = s->next)
8382 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8383 {
8384 fragS *fragP;
8385
8386 /* Walk over all of the fragments in a subsection. */
8387 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8388 {
8389 if (fragP->fr_type == rs_machine_dependent
8390 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
8391 {
8392 if (next_instr_is_loop_end (fragP))
8393 {
8394 if (fragP->tc_frag_data.is_no_transform)
8395 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8396 else
8397 relax_frag_add_nop (fragP);
8398 }
8399 frag_wane (fragP);
8400 }
8401 }
8402 }
8403 }
8404
8405
8406 static bfd_boolean
next_instr_is_loop_end(fragS * fragP)8407 next_instr_is_loop_end (fragS *fragP)
8408 {
8409 const fragS *next_fragP;
8410
8411 if (next_frag_is_loop_target (fragP))
8412 return FALSE;
8413
8414 next_fragP = next_non_empty_frag (fragP);
8415 if (next_fragP == NULL)
8416 return FALSE;
8417
8418 if (!next_frag_is_loop_target (next_fragP))
8419 return FALSE;
8420
8421 /* If the size is >= 3 then there is more than one instruction here.
8422 The hardware bug will not fire. */
8423 if (next_fragP->fr_fix > 3)
8424 return FALSE;
8425
8426 return TRUE;
8427 }
8428
8429
8430 /* Re-process all of the fragments looking to convert all of the
8431 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8432 not MY loop's loop end within 12 bytes, add enough nops here to
8433 make it at least 12 bytes away. In any case close it off with a
8434 .fill 0. */
8435
8436 static offsetT min_bytes_to_other_loop_end
8437 (fragS *, fragS *, offsetT);
8438
8439 static void
xtensa_fix_close_loop_end_frags(void)8440 xtensa_fix_close_loop_end_frags (void)
8441 {
8442 frchainS *frchP;
8443 asection *s;
8444
8445 /* When this routine is called, all of the subsections are still intact
8446 so we walk over subsections instead of sections. */
8447 for (s = stdoutput->sections; s; s = s->next)
8448 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8449 {
8450 fragS *fragP;
8451
8452 fragS *current_target = NULL;
8453
8454 /* Walk over all of the fragments in a subsection. */
8455 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8456 {
8457 if (fragP->fr_type == rs_machine_dependent
8458 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8459 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8460 current_target = symbol_get_frag (fragP->fr_symbol);
8461
8462 if (current_target
8463 && fragP->fr_type == rs_machine_dependent
8464 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
8465 {
8466 offsetT min_bytes;
8467 int bytes_added = 0;
8468
8469 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8470 /* Max out at 12. */
8471 min_bytes = min_bytes_to_other_loop_end
8472 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
8473
8474 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
8475 {
8476 if (fragP->tc_frag_data.is_no_transform)
8477 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8478 else
8479 {
8480 while (min_bytes + bytes_added
8481 < REQUIRED_LOOP_DIVIDING_BYTES)
8482 {
8483 int length = 3;
8484
8485 if (fragP->fr_var < length)
8486 as_fatal (_("fr_var %lu < length %d"),
8487 (long) fragP->fr_var, length);
8488 else
8489 {
8490 assemble_nop (length,
8491 fragP->fr_literal + fragP->fr_fix);
8492 fragP->fr_fix += length;
8493 fragP->fr_var -= length;
8494 }
8495 bytes_added += length;
8496 }
8497 }
8498 }
8499 frag_wane (fragP);
8500 }
8501 gas_assert (fragP->fr_type != rs_machine_dependent
8502 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
8503 }
8504 }
8505 }
8506
8507
8508 static offsetT unrelaxed_frag_min_size (fragS *);
8509
8510 static offsetT
min_bytes_to_other_loop_end(fragS * fragP,fragS * current_target,offsetT max_size)8511 min_bytes_to_other_loop_end (fragS *fragP,
8512 fragS *current_target,
8513 offsetT max_size)
8514 {
8515 offsetT offset = 0;
8516 fragS *current_fragP;
8517
8518 for (current_fragP = fragP;
8519 current_fragP;
8520 current_fragP = current_fragP->fr_next)
8521 {
8522 if (current_fragP->tc_frag_data.is_loop_target
8523 && current_fragP != current_target)
8524 return offset;
8525
8526 offset += unrelaxed_frag_min_size (current_fragP);
8527
8528 if (offset >= max_size)
8529 return max_size;
8530 }
8531 return max_size;
8532 }
8533
8534
8535 static offsetT
unrelaxed_frag_min_size(fragS * fragP)8536 unrelaxed_frag_min_size (fragS *fragP)
8537 {
8538 offsetT size = fragP->fr_fix;
8539
8540 /* Add fill size. */
8541 if (fragP->fr_type == rs_fill)
8542 size += fragP->fr_offset;
8543
8544 return size;
8545 }
8546
8547
8548 static offsetT
unrelaxed_frag_max_size(fragS * fragP)8549 unrelaxed_frag_max_size (fragS *fragP)
8550 {
8551 offsetT size = fragP->fr_fix;
8552 switch (fragP->fr_type)
8553 {
8554 case 0:
8555 /* Empty frags created by the obstack allocation scheme
8556 end up with type 0. */
8557 break;
8558 case rs_fill:
8559 case rs_org:
8560 case rs_space:
8561 size += fragP->fr_offset;
8562 break;
8563 case rs_align:
8564 case rs_align_code:
8565 case rs_align_test:
8566 case rs_leb128:
8567 case rs_cfa:
8568 case rs_dwarf2dbg:
8569 /* No further adjustments needed. */
8570 break;
8571 case rs_machine_dependent:
8572 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
8573 size += fragP->fr_var;
8574 break;
8575 default:
8576 /* We had darn well better know how big it is. */
8577 gas_assert (0);
8578 break;
8579 }
8580
8581 return size;
8582 }
8583
8584
8585 /* Re-process all of the fragments looking to convert all
8586 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8587
8588 A)
8589 1) the instruction size count to the loop end label
8590 is too short (<= 2 instructions),
8591 2) loop has a jump or branch in it
8592
8593 or B)
8594 1) workaround_all_short_loops is TRUE
8595 2) The generating loop was a 'loopgtz' or 'loopnez'
8596 3) the instruction size count to the loop end label is too short
8597 (<= 2 instructions)
8598 then convert this frag (and maybe the next one) to generate a NOP.
8599 In any case close it off with a .fill 0. */
8600
8601 static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
8602 static bfd_boolean branch_before_loop_end (fragS *);
8603
8604 static void
xtensa_fix_short_loop_frags(void)8605 xtensa_fix_short_loop_frags (void)
8606 {
8607 frchainS *frchP;
8608 asection *s;
8609
8610 /* When this routine is called, all of the subsections are still intact
8611 so we walk over subsections instead of sections. */
8612 for (s = stdoutput->sections; s; s = s->next)
8613 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8614 {
8615 fragS *fragP;
8616 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
8617
8618 /* Walk over all of the fragments in a subsection. */
8619 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8620 {
8621 if (fragP->fr_type == rs_machine_dependent
8622 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8623 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8624 {
8625 TInsn t_insn;
8626 fragS *loop_frag = next_non_empty_frag (fragP);
8627 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
8628 current_opcode = t_insn.opcode;
8629 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa,
8630 current_opcode) == 1);
8631 }
8632
8633 if (fragP->fr_type == rs_machine_dependent
8634 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8635 {
8636 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
8637 && (branch_before_loop_end (fragP->fr_next)
8638 || (workaround_all_short_loops
8639 && current_opcode != XTENSA_UNDEFINED
8640 && current_opcode != xtensa_loop_opcode)))
8641 {
8642 if (fragP->tc_frag_data.is_no_transform)
8643 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8644 else
8645 relax_frag_add_nop (fragP);
8646 }
8647 frag_wane (fragP);
8648 }
8649 }
8650 }
8651 }
8652
8653
8654 static int unrelaxed_frag_min_insn_count (fragS *);
8655
8656 static int
count_insns_to_loop_end(fragS * base_fragP,bfd_boolean count_relax_add,int max_count)8657 count_insns_to_loop_end (fragS *base_fragP,
8658 bfd_boolean count_relax_add,
8659 int max_count)
8660 {
8661 fragS *fragP = NULL;
8662 int insn_count = 0;
8663
8664 fragP = base_fragP;
8665
8666 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
8667 {
8668 insn_count += unrelaxed_frag_min_insn_count (fragP);
8669 if (insn_count >= max_count)
8670 return max_count;
8671
8672 if (count_relax_add)
8673 {
8674 if (fragP->fr_type == rs_machine_dependent
8675 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8676 {
8677 /* In order to add the appropriate number of
8678 NOPs, we count an instruction for downstream
8679 occurrences. */
8680 insn_count++;
8681 if (insn_count >= max_count)
8682 return max_count;
8683 }
8684 }
8685 }
8686 return insn_count;
8687 }
8688
8689
8690 static int
unrelaxed_frag_min_insn_count(fragS * fragP)8691 unrelaxed_frag_min_insn_count (fragS *fragP)
8692 {
8693 xtensa_isa isa = xtensa_default_isa;
8694 static xtensa_insnbuf insnbuf = NULL;
8695 int insn_count = 0;
8696 unsigned int offset = 0;
8697
8698 if (!fragP->tc_frag_data.is_insn)
8699 return insn_count;
8700
8701 if (!insnbuf)
8702 insnbuf = xtensa_insnbuf_alloc (isa);
8703
8704 /* Decode the fixed instructions. */
8705 while (offset < fragP->fr_fix)
8706 {
8707 xtensa_format fmt;
8708
8709 xtensa_insnbuf_from_chars
8710 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8711 fmt = xtensa_format_decode (isa, insnbuf);
8712
8713 if (fmt == XTENSA_UNDEFINED)
8714 {
8715 as_fatal (_("undecodable instruction in instruction frag"));
8716 return insn_count;
8717 }
8718 offset += xtensa_format_length (isa, fmt);
8719 insn_count++;
8720 }
8721
8722 return insn_count;
8723 }
8724
8725
8726 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
8727
8728 static bfd_boolean
branch_before_loop_end(fragS * base_fragP)8729 branch_before_loop_end (fragS *base_fragP)
8730 {
8731 fragS *fragP;
8732
8733 for (fragP = base_fragP;
8734 fragP && !fragP->tc_frag_data.is_loop_target;
8735 fragP = fragP->fr_next)
8736 {
8737 if (unrelaxed_frag_has_b_j (fragP))
8738 return TRUE;
8739 }
8740 return FALSE;
8741 }
8742
8743
8744 static bfd_boolean
unrelaxed_frag_has_b_j(fragS * fragP)8745 unrelaxed_frag_has_b_j (fragS *fragP)
8746 {
8747 static xtensa_insnbuf insnbuf = NULL;
8748 xtensa_isa isa = xtensa_default_isa;
8749 unsigned int offset = 0;
8750
8751 if (!fragP->tc_frag_data.is_insn)
8752 return FALSE;
8753
8754 if (!insnbuf)
8755 insnbuf = xtensa_insnbuf_alloc (isa);
8756
8757 /* Decode the fixed instructions. */
8758 while (offset < fragP->fr_fix)
8759 {
8760 xtensa_format fmt;
8761 int slot;
8762
8763 xtensa_insnbuf_from_chars
8764 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8765 fmt = xtensa_format_decode (isa, insnbuf);
8766 if (fmt == XTENSA_UNDEFINED)
8767 return FALSE;
8768
8769 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8770 {
8771 xtensa_opcode opcode =
8772 get_opcode_from_buf (fragP->fr_literal + offset, slot);
8773 if (xtensa_opcode_is_branch (isa, opcode) == 1
8774 || xtensa_opcode_is_jump (isa, opcode) == 1)
8775 return TRUE;
8776 }
8777 offset += xtensa_format_length (isa, fmt);
8778 }
8779 return FALSE;
8780 }
8781
8782
8783 /* Checks to be made after initial assembly but before relaxation. */
8784
8785 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
8786 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
8787
8788 static void
xtensa_sanity_check(void)8789 xtensa_sanity_check (void)
8790 {
8791 const char *file_name;
8792 unsigned line;
8793 frchainS *frchP;
8794 asection *s;
8795
8796 file_name = as_where (&line);
8797 for (s = stdoutput->sections; s; s = s->next)
8798 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8799 {
8800 fragS *fragP;
8801
8802 /* Walk over all of the fragments in a subsection. */
8803 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8804 {
8805 if (fragP->fr_type == rs_machine_dependent
8806 && fragP->fr_subtype == RELAX_SLOTS
8807 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8808 {
8809 static xtensa_insnbuf insnbuf = NULL;
8810 TInsn t_insn;
8811
8812 if (fragP->fr_opcode != NULL)
8813 {
8814 if (!insnbuf)
8815 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
8816 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8817 tinsn_immed_from_frag (&t_insn, fragP, 0);
8818
8819 if (xtensa_opcode_is_loop (xtensa_default_isa,
8820 t_insn.opcode) == 1)
8821 {
8822 if (is_empty_loop (&t_insn, fragP))
8823 {
8824 new_logical_line (fragP->fr_file, fragP->fr_line);
8825 as_bad (_("invalid empty loop"));
8826 }
8827 if (!is_local_forward_loop (&t_insn, fragP))
8828 {
8829 new_logical_line (fragP->fr_file, fragP->fr_line);
8830 as_bad (_("loop target does not follow "
8831 "loop instruction in section"));
8832 }
8833 }
8834 }
8835 }
8836 }
8837 }
8838 new_logical_line (file_name, line);
8839 }
8840
8841
8842 #define LOOP_IMMED_OPN 1
8843
8844 /* Return TRUE if the loop target is the next non-zero fragment. */
8845
8846 static bfd_boolean
is_empty_loop(const TInsn * insn,fragS * fragP)8847 is_empty_loop (const TInsn *insn, fragS *fragP)
8848 {
8849 const expressionS *exp;
8850 symbolS *symbolP;
8851 fragS *next_fragP;
8852
8853 if (insn->insn_type != ITYPE_INSN)
8854 return FALSE;
8855
8856 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8857 return FALSE;
8858
8859 if (insn->ntok <= LOOP_IMMED_OPN)
8860 return FALSE;
8861
8862 exp = &insn->tok[LOOP_IMMED_OPN];
8863
8864 if (exp->X_op != O_symbol)
8865 return FALSE;
8866
8867 symbolP = exp->X_add_symbol;
8868 if (!symbolP)
8869 return FALSE;
8870
8871 if (symbol_get_frag (symbolP) == NULL)
8872 return FALSE;
8873
8874 if (S_GET_VALUE (symbolP) != 0)
8875 return FALSE;
8876
8877 /* Walk through the zero-size fragments from this one. If we find
8878 the target fragment, then this is a zero-size loop. */
8879
8880 for (next_fragP = fragP->fr_next;
8881 next_fragP != NULL;
8882 next_fragP = next_fragP->fr_next)
8883 {
8884 if (next_fragP == symbol_get_frag (symbolP))
8885 return TRUE;
8886 if (next_fragP->fr_fix != 0)
8887 return FALSE;
8888 }
8889 return FALSE;
8890 }
8891
8892
8893 static bfd_boolean
is_local_forward_loop(const TInsn * insn,fragS * fragP)8894 is_local_forward_loop (const TInsn *insn, fragS *fragP)
8895 {
8896 const expressionS *exp;
8897 symbolS *symbolP;
8898 fragS *next_fragP;
8899
8900 if (insn->insn_type != ITYPE_INSN)
8901 return FALSE;
8902
8903 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8904 return FALSE;
8905
8906 if (insn->ntok <= LOOP_IMMED_OPN)
8907 return FALSE;
8908
8909 exp = &insn->tok[LOOP_IMMED_OPN];
8910
8911 if (exp->X_op != O_symbol)
8912 return FALSE;
8913
8914 symbolP = exp->X_add_symbol;
8915 if (!symbolP)
8916 return FALSE;
8917
8918 if (symbol_get_frag (symbolP) == NULL)
8919 return FALSE;
8920
8921 /* Walk through fragments until we find the target.
8922 If we do not find the target, then this is an invalid loop. */
8923
8924 for (next_fragP = fragP->fr_next;
8925 next_fragP != NULL;
8926 next_fragP = next_fragP->fr_next)
8927 {
8928 if (next_fragP == symbol_get_frag (symbolP))
8929 return TRUE;
8930 }
8931
8932 return FALSE;
8933 }
8934
8935
8936 #define XTINFO_NAME "Xtensa_Info"
8937 #define XTINFO_NAMESZ 12
8938 #define XTINFO_TYPE 1
8939
8940 static void
xtensa_add_config_info(void)8941 xtensa_add_config_info (void)
8942 {
8943 asection *info_sec;
8944 char *data, *p;
8945 int sz;
8946
8947 info_sec = subseg_new (".xtensa.info", 0);
8948 bfd_set_section_flags (info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
8949
8950 data = XNEWVEC (char, 100);
8951 sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8952 XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI);
8953 sz = strlen (data) + 1;
8954
8955 /* Add enough null terminators to pad to a word boundary. */
8956 do
8957 data[sz++] = 0;
8958 while ((sz & 3) != 0);
8959
8960 /* Follow the standard note section layout:
8961 First write the length of the name string. */
8962 p = frag_more (4);
8963 md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
8964
8965 /* Next comes the length of the "descriptor", i.e., the actual data. */
8966 p = frag_more (4);
8967 md_number_to_chars (p, (valueT) sz, 4);
8968
8969 /* Write the note type. */
8970 p = frag_more (4);
8971 md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
8972
8973 /* Write the name field. */
8974 p = frag_more (XTINFO_NAMESZ);
8975 memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
8976
8977 /* Finally, write the descriptor. */
8978 p = frag_more (sz);
8979 memcpy (p, data, sz);
8980
8981 free (data);
8982 }
8983
8984
8985 /* Alignment Functions. */
8986
8987 static int
get_text_align_power(unsigned target_size)8988 get_text_align_power (unsigned target_size)
8989 {
8990 if (target_size <= 4)
8991 return 2;
8992
8993 if (target_size <= 8)
8994 return 3;
8995
8996 if (target_size <= 16)
8997 return 4;
8998
8999 if (target_size <= 32)
9000 return 5;
9001
9002 if (target_size <= 64)
9003 return 6;
9004
9005 if (target_size <= 128)
9006 return 7;
9007
9008 if (target_size <= 256)
9009 return 8;
9010
9011 if (target_size <= 512)
9012 return 9;
9013
9014 if (target_size <= 1024)
9015 return 10;
9016
9017 gas_assert (0);
9018 return 0;
9019 }
9020
9021
9022 static int
get_text_align_max_fill_size(int align_pow,bfd_boolean use_nops,bfd_boolean use_no_density)9023 get_text_align_max_fill_size (int align_pow,
9024 bfd_boolean use_nops,
9025 bfd_boolean use_no_density)
9026 {
9027 if (!use_nops)
9028 return (1 << align_pow);
9029 if (use_no_density)
9030 return 3 * (1 << align_pow);
9031
9032 return 1 + (1 << align_pow);
9033 }
9034
9035
9036 /* Calculate the minimum bytes of fill needed at "address" to align a
9037 target instruction of size "target_size" so that it does not cross a
9038 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
9039 the fill can be an arbitrary number of bytes. Otherwise, the space must
9040 be filled by NOP instructions. */
9041
9042 static int
get_text_align_fill_size(addressT address,int align_pow,int target_size,bfd_boolean use_nops,bfd_boolean use_no_density)9043 get_text_align_fill_size (addressT address,
9044 int align_pow,
9045 int target_size,
9046 bfd_boolean use_nops,
9047 bfd_boolean use_no_density)
9048 {
9049 addressT alignment, fill, fill_limit, fill_step;
9050 bfd_boolean skip_one = FALSE;
9051
9052 alignment = (1 << align_pow);
9053 gas_assert (target_size > 0 && alignment >= (addressT) target_size);
9054
9055 if (!use_nops)
9056 {
9057 fill_limit = alignment;
9058 fill_step = 1;
9059 }
9060 else if (!use_no_density)
9061 {
9062 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
9063 fill_limit = alignment * 2;
9064 fill_step = 1;
9065 skip_one = TRUE;
9066 }
9067 else
9068 {
9069 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
9070 fill_limit = alignment * 3;
9071 fill_step = 3;
9072 }
9073
9074 /* Try all fill sizes until finding one that works. */
9075 for (fill = 0; fill < fill_limit; fill += fill_step)
9076 {
9077 if (skip_one && fill == 1)
9078 continue;
9079 if ((address + fill) >> align_pow
9080 == (address + fill + target_size - 1) >> align_pow)
9081 return fill;
9082 }
9083 gas_assert (0);
9084 return 0;
9085 }
9086
9087
9088 static int
branch_align_power(segT sec)9089 branch_align_power (segT sec)
9090 {
9091 /* If the Xtensa processor has a fetch width of X, and
9092 the section is aligned to at least that boundary, then a branch
9093 target need only fit within that aligned block of memory to avoid
9094 a stall. Otherwise, try to fit branch targets within 4-byte
9095 aligned blocks (which may be insufficient, e.g., if the section
9096 has no alignment, but it's good enough). */
9097 int fetch_align = get_text_align_power(xtensa_fetch_width);
9098 int sec_align = get_recorded_alignment (sec);
9099
9100 if (sec_align >= fetch_align)
9101 return fetch_align;
9102
9103 return 2;
9104 }
9105
9106
9107 /* This will assert if it is not possible. */
9108
9109 static int
get_text_align_nop_count(offsetT fill_size,bfd_boolean use_no_density)9110 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
9111 {
9112 int count = 0;
9113
9114 if (use_no_density)
9115 {
9116 gas_assert (fill_size % 3 == 0);
9117 return (fill_size / 3);
9118 }
9119
9120 gas_assert (fill_size != 1); /* Bad argument. */
9121
9122 while (fill_size > 1)
9123 {
9124 int insn_size = 3;
9125 if (fill_size == 2 || fill_size == 4)
9126 insn_size = 2;
9127 fill_size -= insn_size;
9128 count++;
9129 }
9130 gas_assert (fill_size != 1); /* Bad algorithm. */
9131 return count;
9132 }
9133
9134
9135 static int
get_text_align_nth_nop_size(offsetT fill_size,int n,bfd_boolean use_no_density)9136 get_text_align_nth_nop_size (offsetT fill_size,
9137 int n,
9138 bfd_boolean use_no_density)
9139 {
9140 int count = 0;
9141
9142 if (use_no_density)
9143 return 3;
9144
9145 gas_assert (fill_size != 1); /* Bad argument. */
9146
9147 while (fill_size > 1)
9148 {
9149 int insn_size = 3;
9150 if (fill_size == 2 || fill_size == 4)
9151 insn_size = 2;
9152 fill_size -= insn_size;
9153 count++;
9154 if (n + 1 == count)
9155 return insn_size;
9156 }
9157 gas_assert (0);
9158 return 0;
9159 }
9160
9161
9162 /* For the given fragment, find the appropriate address
9163 for it to begin at if we are using NOPs to align it. */
9164
9165 static addressT
get_noop_aligned_address(fragS * fragP,addressT address)9166 get_noop_aligned_address (fragS *fragP, addressT address)
9167 {
9168 /* The rule is: get next fragment's FIRST instruction. Find
9169 the smallest number of bytes that need to be added to
9170 ensure that the next fragment's FIRST instruction will fit
9171 in a single word.
9172
9173 E.G., 2 bytes : 0, 1, 2 mod 4
9174 3 bytes: 0, 1 mod 4
9175
9176 If the FIRST instruction MIGHT be relaxed,
9177 assume that it will become a 3-byte instruction.
9178
9179 Note again here that LOOP instructions are not bundleable,
9180 and this relaxation only applies to LOOP opcodes. */
9181
9182 int fill_size = 0;
9183 int first_insn_size;
9184 int loop_insn_size;
9185 addressT pre_opcode_bytes;
9186 int align_power;
9187 fragS *first_insn;
9188 xtensa_opcode opcode;
9189 bfd_boolean is_loop;
9190
9191 gas_assert (fragP->fr_type == rs_machine_dependent);
9192 gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
9193
9194 /* Find the loop frag. */
9195 first_insn = next_non_empty_frag (fragP);
9196 /* Now find the first insn frag. */
9197 first_insn = next_non_empty_frag (first_insn);
9198
9199 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
9200 gas_assert (is_loop);
9201 loop_insn_size = xg_get_single_size (opcode);
9202
9203 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
9204 pre_opcode_bytes += loop_insn_size;
9205
9206 /* For loops, the alignment depends on the size of the
9207 instruction following the loop, not the LOOP instruction. */
9208
9209 if (first_insn == NULL)
9210 first_insn_size = xtensa_fetch_width;
9211 else
9212 first_insn_size = get_loop_align_size (frag_format_size (first_insn));
9213
9214 /* If it was 8, then we'll need a larger alignment for the section. */
9215 align_power = get_text_align_power (first_insn_size);
9216 record_alignment (now_seg, align_power);
9217
9218 fill_size = get_text_align_fill_size
9219 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
9220 fragP->tc_frag_data.is_no_density);
9221
9222 return address + fill_size;
9223 }
9224
9225
9226 /* 3 mechanisms for relaxing an alignment:
9227
9228 Align to a power of 2.
9229 Align so the next fragment's instruction does not cross a word boundary.
9230 Align the current instruction so that if the next instruction
9231 were 3 bytes, it would not cross a word boundary.
9232
9233 We can align with:
9234
9235 zeros - This is easy; always insert zeros.
9236 nops - 3-byte and 2-byte instructions
9237 2 - 2-byte nop
9238 3 - 3-byte nop
9239 4 - 2 2-byte nops
9240 >=5 : 3-byte instruction + fn (n-3)
9241 widening - widen previous instructions. */
9242
9243 static offsetT
get_aligned_diff(fragS * fragP,addressT address,offsetT * max_diff)9244 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
9245 {
9246 addressT target_address, loop_insn_offset;
9247 int target_size;
9248 xtensa_opcode loop_opcode;
9249 bfd_boolean is_loop;
9250 int align_power;
9251 offsetT opt_diff;
9252 offsetT branch_align;
9253 fragS *loop_frag;
9254
9255 gas_assert (fragP->fr_type == rs_machine_dependent);
9256 switch (fragP->fr_subtype)
9257 {
9258 case RELAX_DESIRE_ALIGN:
9259 target_size = next_frag_format_size (fragP);
9260 if (target_size == XTENSA_UNDEFINED)
9261 target_size = 3;
9262 align_power = branch_align_power (now_seg);
9263 branch_align = 1 << align_power;
9264 /* Don't count on the section alignment being as large as the target. */
9265 if (target_size > branch_align)
9266 target_size = branch_align;
9267 opt_diff = get_text_align_fill_size (address, align_power,
9268 target_size, FALSE, FALSE);
9269
9270 *max_diff = (opt_diff + branch_align
9271 - (target_size + ((address + opt_diff) % branch_align)));
9272 gas_assert (*max_diff >= opt_diff);
9273 return opt_diff;
9274
9275 case RELAX_ALIGN_NEXT_OPCODE:
9276 /* The next non-empty frag after this one holds the LOOP instruction
9277 that needs to be aligned. The required alignment depends on the
9278 size of the next non-empty frag after the loop frag, i.e., the
9279 first instruction in the loop. */
9280 loop_frag = next_non_empty_frag (fragP);
9281 target_size = get_loop_align_size (next_frag_format_size (loop_frag));
9282 loop_insn_offset = 0;
9283 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
9284 gas_assert (is_loop);
9285
9286 /* If the loop has been expanded then the LOOP instruction
9287 could be at an offset from this fragment. */
9288 if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED)
9289 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
9290
9291 /* In an ideal world, which is what we are shooting for here,
9292 we wouldn't need to use any NOPs immediately prior to the
9293 LOOP instruction. If this approach fails, relax_frag_loop_align
9294 will call get_noop_aligned_address. */
9295 target_address =
9296 address + loop_insn_offset + xg_get_single_size (loop_opcode);
9297 align_power = get_text_align_power (target_size);
9298 opt_diff = get_text_align_fill_size (target_address, align_power,
9299 target_size, FALSE, FALSE);
9300
9301 *max_diff = xtensa_fetch_width
9302 - ((target_address + opt_diff) % xtensa_fetch_width)
9303 - target_size + opt_diff;
9304 gas_assert (*max_diff >= opt_diff);
9305 return opt_diff;
9306
9307 default:
9308 break;
9309 }
9310 gas_assert (0);
9311 return 0;
9312 }
9313
9314
9315 /* md_relax_frag Hook and Helper Functions. */
9316
9317 static long relax_frag_loop_align (fragS *, long);
9318 static long relax_frag_for_align (fragS *, long);
9319 static long relax_frag_immed
9320 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
9321
9322 /* Get projected address for the first fulcrum on a path from source to
9323 target. */
xg_get_fulcrum(addressT source,addressT target)9324 static addressT xg_get_fulcrum (addressT source, addressT target)
9325 {
9326 offsetT delta = target - source;
9327 int n;
9328
9329 n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN);
9330 return source + delta / n;
9331 }
9332
9333 /* Given trampoline index, source and target of a jump find the best
9334 candidate trampoline for the first fulcrum. The best trampoline is
9335 the one in the reach of "j' instruction from the source, closest to
9336 the projected fulcrum address, and preferrably w/o a jump around or
9337 with already initialized jump around. */
xg_find_best_trampoline(struct trampoline_index * idx,addressT source,addressT target)9338 static size_t xg_find_best_trampoline (struct trampoline_index *idx,
9339 addressT source, addressT target)
9340 {
9341 addressT fulcrum = xg_get_fulcrum (source, target);
9342 size_t dist = 0;
9343 size_t best = -1;
9344 size_t base_tr = xg_find_trampoline (idx, fulcrum);
9345 int checked = 1;
9346
9347 /* Check trampoline frags around the base_tr to find the best. */
9348 for (dist = 0; checked; ++dist)
9349 {
9350 int i;
9351 size_t tr = base_tr - dist;
9352
9353 checked = 0;
9354
9355 /* Trampolines are checked in the following order:
9356 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */
9357 for (i = 0; i < 2; ++i, tr = base_tr + dist + 1)
9358 if (tr < idx->n_entries)
9359 {
9360 fragS *trampoline_frag = idx->entry[tr];
9361 offsetT off;
9362
9363 /* Don't check trampolines outside source - target interval. */
9364 if ((trampoline_frag->fr_address < source &&
9365 trampoline_frag->fr_address < target) ||
9366 (trampoline_frag->fr_address > source &&
9367 trampoline_frag->fr_address > target))
9368 continue;
9369
9370 /* Don't choose trampoline that contains the source. */
9371 if (source >= trampoline_frag->fr_address
9372 && source <= trampoline_frag->fr_address +
9373 trampoline_frag->fr_fix)
9374 continue;
9375
9376 off = trampoline_frag->fr_address - fulcrum;
9377 /* Stop if some trampoline is found and the search is more than
9378 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump
9379 around is nice, but it shouldn't have much overhead. */
9380 if (best < idx->n_entries && labs (off) > J_RANGE / 4)
9381 return best;
9382
9383 off = trampoline_frag->fr_address - source;
9384 if (labs (off) < J_RANGE - J_MARGIN)
9385 {
9386 ++checked;
9387 /* Stop if a trampoline w/o jump around is found or initialized
9388 trampoline with jump around is found. */
9389 if (!trampoline_frag->tc_frag_data.needs_jump_around ||
9390 trampoline_frag->fr_fix)
9391 return tr;
9392 else if (best >= idx->n_entries)
9393 best = tr;
9394 }
9395 }
9396 }
9397
9398 if (best < idx->n_entries)
9399 return best;
9400 else
9401 as_fatal (_("cannot find suitable trampoline"));
9402 }
9403
xg_relax_fixup(struct trampoline_index * idx,fixS * fixP)9404 static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP)
9405 {
9406 symbolS *s = fixP->fx_addsy;
9407 addressT source = fixP->fx_frag->fr_address;
9408 addressT target = S_GET_VALUE (s) + fixP->fx_offset;
9409 size_t tr = xg_find_best_trampoline (idx, source, target);
9410 fragS *trampoline_frag = idx->entry[tr];
9411 fixS *newfixP;
9412
9413 init_trampoline_frag (trampoline_frag);
9414 newfixP = xg_append_jump (trampoline_frag,
9415 fixP->fx_addsy, fixP->fx_offset);
9416
9417 /* Adjust the fixup for the original "j" instruction to
9418 point to the newly added jump. */
9419 fixP->fx_addsy = trampoline_frag->fr_symbol;
9420 fixP->fx_offset = trampoline_frag->fr_fix - 3;
9421 fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol;
9422 fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3;
9423
9424 trampoline_frag->tc_frag_data.relax_seen = FALSE;
9425
9426 if (xg_is_trampoline_frag_full (trampoline_frag))
9427 xg_remove_trampoline_from_index (idx, tr);
9428
9429 return newfixP;
9430 }
9431
xg_is_relaxable_fixup(fixS * fixP)9432 static bfd_boolean xg_is_relaxable_fixup (fixS *fixP)
9433 {
9434 xtensa_isa isa = xtensa_default_isa;
9435 addressT addr = fixP->fx_frag->fr_address;
9436 addressT target;
9437 offsetT delta;
9438 symbolS *s = fixP->fx_addsy;
9439 int slot;
9440 xtensa_format fmt;
9441 xtensa_opcode opcode;
9442
9443 if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP ||
9444 fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP)
9445 return FALSE;
9446
9447 target = S_GET_VALUE (s) + fixP->fx_offset;
9448 delta = target - addr;
9449
9450 if (labs (delta) < J_RANGE - J_MARGIN)
9451 return FALSE;
9452
9453 xtensa_insnbuf_from_chars (isa, trampoline_buf,
9454 (unsigned char *) fixP->fx_frag->fr_literal +
9455 fixP->fx_where, 0);
9456 fmt = xtensa_format_decode (isa, trampoline_buf);
9457 gas_assert (fmt != XTENSA_UNDEFINED);
9458 slot = fixP->tc_fix_data.slot;
9459 xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf);
9460 opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf);
9461 return opcode == xtensa_j_opcode;
9462 }
9463
xg_relax_fixups(struct trampoline_seg * ts)9464 static void xg_relax_fixups (struct trampoline_seg *ts)
9465 {
9466 struct trampoline_index *idx = &ts->index;
9467 segment_info_type *seginfo = seg_info (now_seg);
9468 fixS *fx;
9469
9470 for (fx = seginfo->fix_root; fx; fx = fx->fx_next)
9471 {
9472 fixS *fixP = fx;
9473 struct trampoline_chain *tc = NULL;
9474
9475 if (xg_is_relaxable_fixup (fixP))
9476 {
9477 tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address,
9478 &fixP->fx_addsy, &fixP->fx_offset);
9479 if (!tc)
9480 tc = xg_create_trampoline_chain (ts, fixP->fx_addsy,
9481 fixP->fx_offset);
9482 gas_assert (tc);
9483 }
9484
9485 while (xg_is_relaxable_fixup (fixP))
9486 {
9487 fixP = xg_relax_fixup (idx, fixP);
9488 xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
9489 fixP->fx_where);
9490 }
9491 }
9492 }
9493
9494 /* Given a trampoline frag relax all jumps that might want to use this
9495 trampoline. Only do real work once per relaxation cycle, when
9496 xg_relax_trampoline is called for the first trampoline in the now_seg.
9497 Don't use stretch, don't update new_stretch: place fulcrums with a
9498 slack to tolerate code movement. In the worst case if a jump between
9499 two trampolines wouldn't reach the next relaxation pass will fix it. */
xg_relax_trampoline(fragS * fragP,long stretch ATTRIBUTE_UNUSED,long * new_stretch ATTRIBUTE_UNUSED)9500 static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED,
9501 long *new_stretch ATTRIBUTE_UNUSED)
9502 {
9503 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
9504
9505 if (ts->index.n_entries && ts->index.entry[0] == fragP)
9506 xg_relax_fixups (ts);
9507 }
9508
9509 /* Return the number of bytes added to this fragment, given that the
9510 input has been stretched already by "stretch". */
9511
9512 long
xtensa_relax_frag(fragS * fragP,long stretch,int * stretched_p)9513 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
9514 {
9515 xtensa_isa isa = xtensa_default_isa;
9516 int unreported = fragP->tc_frag_data.unreported_expansion;
9517 long new_stretch = 0;
9518 const char *file_name;
9519 unsigned line;
9520 int lit_size;
9521 static xtensa_insnbuf vbuf = NULL;
9522 int slot, num_slots;
9523 xtensa_format fmt;
9524
9525 file_name = as_where (&line);
9526 new_logical_line (fragP->fr_file, fragP->fr_line);
9527
9528 fragP->tc_frag_data.unreported_expansion = 0;
9529
9530 switch (fragP->fr_subtype)
9531 {
9532 case RELAX_ALIGN_NEXT_OPCODE:
9533 /* Always convert. */
9534 if (fragP->tc_frag_data.relax_seen)
9535 new_stretch = relax_frag_loop_align (fragP, stretch);
9536 break;
9537
9538 case RELAX_LOOP_END:
9539 /* Do nothing. */
9540 break;
9541
9542 case RELAX_LOOP_END_ADD_NOP:
9543 /* Add a NOP and switch to .fill 0. */
9544 new_stretch = relax_frag_add_nop (fragP);
9545 frag_wane (fragP);
9546 break;
9547
9548 case RELAX_DESIRE_ALIGN:
9549 /* Do nothing. The narrowing before this frag will either align
9550 it or not. */
9551 break;
9552
9553 case RELAX_LITERAL:
9554 case RELAX_LITERAL_FINAL:
9555 return 0;
9556
9557 case RELAX_LITERAL_NR:
9558 lit_size = 4;
9559 fragP->fr_subtype = RELAX_LITERAL_FINAL;
9560 gas_assert (unreported == lit_size);
9561 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
9562 fragP->fr_var -= lit_size;
9563 fragP->fr_fix += lit_size;
9564 new_stretch = 4;
9565 break;
9566
9567 case RELAX_SLOTS:
9568 if (vbuf == NULL)
9569 vbuf = xtensa_insnbuf_alloc (isa);
9570
9571 xtensa_insnbuf_from_chars
9572 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
9573 fmt = xtensa_format_decode (isa, vbuf);
9574 num_slots = xtensa_format_num_slots (isa, fmt);
9575
9576 for (slot = 0; slot < num_slots; slot++)
9577 {
9578 switch (fragP->tc_frag_data.slot_subtypes[slot])
9579 {
9580 case RELAX_NARROW:
9581 if (fragP->tc_frag_data.relax_seen)
9582 new_stretch += relax_frag_for_align (fragP, stretch);
9583 break;
9584
9585 case RELAX_IMMED:
9586 case RELAX_IMMED_STEP1:
9587 case RELAX_IMMED_STEP2:
9588 case RELAX_IMMED_STEP3:
9589 /* Place the immediate. */
9590 new_stretch += relax_frag_immed
9591 (now_seg, fragP, stretch,
9592 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9593 fmt, slot, stretched_p, FALSE);
9594 break;
9595
9596 default:
9597 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9598 break;
9599 }
9600 }
9601 break;
9602
9603 case RELAX_LITERAL_POOL_BEGIN:
9604 if (fragP->fr_var != 0)
9605 {
9606 /* We have a converted "candidate" literal pool;
9607 assemble a jump around it. */
9608 TInsn insn;
9609 if (!litpool_slotbuf)
9610 {
9611 litpool_buf = xtensa_insnbuf_alloc (isa);
9612 litpool_slotbuf = xtensa_insnbuf_alloc (isa);
9613 }
9614 new_stretch += 3;
9615 fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */
9616 fragP->tc_frag_data.is_insn = TRUE;
9617 tinsn_init (&insn);
9618 insn.insn_type = ITYPE_INSN;
9619 insn.opcode = xtensa_j_opcode;
9620 insn.ntok = 1;
9621 set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol,
9622 fragP->fr_fix);
9623 fmt = xg_get_single_format (xtensa_j_opcode);
9624 tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf);
9625 xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf);
9626 xtensa_insnbuf_to_chars (isa, litpool_buf,
9627 (unsigned char *)fragP->fr_literal +
9628 fragP->fr_fix, 3);
9629 fragP->fr_fix += 3;
9630 fragP->fr_var -= 3;
9631 /* Add a fix-up. */
9632 fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE,
9633 BFD_RELOC_XTENSA_SLOT0_OP);
9634 }
9635 break;
9636
9637 case RELAX_LITERAL_POOL_END:
9638 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN:
9639 case RELAX_MAYBE_UNREACHABLE:
9640 case RELAX_MAYBE_DESIRE_ALIGN:
9641 /* No relaxation required. */
9642 break;
9643
9644 case RELAX_FILL_NOP:
9645 case RELAX_UNREACHABLE:
9646 if (fragP->tc_frag_data.relax_seen)
9647 new_stretch += relax_frag_for_align (fragP, stretch);
9648 break;
9649
9650 case RELAX_TRAMPOLINE:
9651 if (fragP->tc_frag_data.relax_seen)
9652 xg_relax_trampoline (fragP, stretch, &new_stretch);
9653 break;
9654
9655 default:
9656 as_bad (_("bad relaxation state"));
9657 }
9658
9659 /* Tell gas we need another relaxation pass. */
9660 if (! fragP->tc_frag_data.relax_seen)
9661 {
9662 fragP->tc_frag_data.relax_seen = TRUE;
9663 *stretched_p = 1;
9664 }
9665
9666 new_logical_line (file_name, line);
9667 return new_stretch;
9668 }
9669
9670
9671 static long
relax_frag_loop_align(fragS * fragP,long stretch)9672 relax_frag_loop_align (fragS *fragP, long stretch)
9673 {
9674 addressT old_address, old_next_address, old_size;
9675 addressT new_address, new_next_address, new_size;
9676 addressT growth;
9677
9678 /* All the frags with relax_frag_for_alignment prior to this one in the
9679 section have been done, hopefully eliminating the need for a NOP here.
9680 But, this will put it in if necessary. */
9681
9682 /* Calculate the old address of this fragment and the next fragment. */
9683 old_address = fragP->fr_address - stretch;
9684 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
9685 fragP->tc_frag_data.text_expansion[0]);
9686 old_size = old_next_address - old_address;
9687
9688 /* Calculate the new address of this fragment and the next fragment. */
9689 new_address = fragP->fr_address;
9690 new_next_address =
9691 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
9692 new_size = new_next_address - new_address;
9693
9694 growth = new_size - old_size;
9695
9696 /* Fix up the text_expansion field and return the new growth. */
9697 fragP->tc_frag_data.text_expansion[0] += growth;
9698 return growth;
9699 }
9700
9701
9702 /* Add a NOP instruction. */
9703
9704 static long
relax_frag_add_nop(fragS * fragP)9705 relax_frag_add_nop (fragS *fragP)
9706 {
9707 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
9708 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
9709 assemble_nop (length, nop_buf);
9710 fragP->tc_frag_data.is_insn = TRUE;
9711
9712 if (fragP->fr_var < length)
9713 {
9714 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
9715 return 0;
9716 }
9717
9718 fragP->fr_fix += length;
9719 fragP->fr_var -= length;
9720 return length;
9721 }
9722
9723
9724 static long future_alignment_required (fragS *, long);
9725
9726 static long
relax_frag_for_align(fragS * fragP,long stretch)9727 relax_frag_for_align (fragS *fragP, long stretch)
9728 {
9729 /* Overview of the relaxation procedure for alignment:
9730 We can widen with NOPs or by widening instructions or by filling
9731 bytes after jump instructions. Find the opportune places and widen
9732 them if necessary. */
9733
9734 long stretch_me;
9735 long diff;
9736
9737 gas_assert (fragP->fr_subtype == RELAX_FILL_NOP
9738 || fragP->fr_subtype == RELAX_UNREACHABLE
9739 || (fragP->fr_subtype == RELAX_SLOTS
9740 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
9741
9742 stretch_me = future_alignment_required (fragP, stretch);
9743 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
9744 if (diff == 0)
9745 return 0;
9746
9747 if (diff < 0)
9748 {
9749 /* We expanded on a previous pass. Can we shrink now? */
9750 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
9751 if (shrink <= stretch && stretch > 0)
9752 {
9753 fragP->tc_frag_data.text_expansion[0] = stretch_me;
9754 return -shrink;
9755 }
9756 return 0;
9757 }
9758
9759 /* Below here, diff > 0. */
9760 fragP->tc_frag_data.text_expansion[0] = stretch_me;
9761
9762 return diff;
9763 }
9764
9765
9766 /* Return the address of the next frag that should be aligned.
9767
9768 By "address" we mean the address it _would_ be at if there
9769 is no action taken to align it between here and the target frag.
9770 In other words, if no narrows and no fill nops are used between
9771 here and the frag to align, _even_if_ some of the frags we use
9772 to align targets have already expanded on a previous relaxation
9773 pass.
9774
9775 Also, count each frag that may be used to help align the target.
9776
9777 Return 0 if there are no frags left in the chain that need to be
9778 aligned. */
9779
9780 static addressT
find_address_of_next_align_frag(fragS ** fragPP,int * wide_nops,int * narrow_nops,int * widens,bfd_boolean * paddable)9781 find_address_of_next_align_frag (fragS **fragPP,
9782 int *wide_nops,
9783 int *narrow_nops,
9784 int *widens,
9785 bfd_boolean *paddable)
9786 {
9787 fragS *fragP = *fragPP;
9788 addressT address = fragP->fr_address;
9789
9790 /* Do not reset the counts to 0. */
9791
9792 while (fragP)
9793 {
9794 /* Limit this to a small search. */
9795 if (*widens >= (int) xtensa_fetch_width)
9796 {
9797 *fragPP = fragP;
9798 return 0;
9799 }
9800 address += fragP->fr_fix;
9801
9802 if (fragP->fr_type == rs_fill)
9803 address += fragP->fr_offset * fragP->fr_var;
9804 else if (fragP->fr_type == rs_machine_dependent)
9805 {
9806 switch (fragP->fr_subtype)
9807 {
9808 case RELAX_UNREACHABLE:
9809 *paddable = TRUE;
9810 break;
9811
9812 case RELAX_FILL_NOP:
9813 (*wide_nops)++;
9814 if (!fragP->tc_frag_data.is_no_density)
9815 (*narrow_nops)++;
9816 break;
9817
9818 case RELAX_SLOTS:
9819 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9820 {
9821 (*widens)++;
9822 break;
9823 }
9824 address += total_frag_text_expansion (fragP);
9825 break;
9826
9827 case RELAX_IMMED:
9828 address += fragP->tc_frag_data.text_expansion[0];
9829 break;
9830
9831 case RELAX_ALIGN_NEXT_OPCODE:
9832 case RELAX_DESIRE_ALIGN:
9833 *fragPP = fragP;
9834 return address;
9835
9836 case RELAX_MAYBE_UNREACHABLE:
9837 case RELAX_MAYBE_DESIRE_ALIGN:
9838 /* Do nothing. */
9839 break;
9840
9841 default:
9842 /* Just punt if we don't know the type. */
9843 *fragPP = fragP;
9844 return 0;
9845 }
9846 }
9847 else
9848 {
9849 /* Just punt if we don't know the type. */
9850 *fragPP = fragP;
9851 return 0;
9852 }
9853 fragP = fragP->fr_next;
9854 }
9855
9856 *fragPP = fragP;
9857 return 0;
9858 }
9859
9860
9861 static long bytes_to_stretch (fragS *, int, int, int, int);
9862
9863 static long
future_alignment_required(fragS * fragP,long stretch ATTRIBUTE_UNUSED)9864 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
9865 {
9866 fragS *this_frag = fragP;
9867 long address;
9868 int num_widens = 0;
9869 int wide_nops = 0;
9870 int narrow_nops = 0;
9871 bfd_boolean paddable = FALSE;
9872 offsetT local_opt_diff;
9873 offsetT opt_diff;
9874 offsetT max_diff;
9875 int stretch_amount = 0;
9876 int local_stretch_amount;
9877 int global_stretch_amount;
9878
9879 address = find_address_of_next_align_frag
9880 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
9881
9882 if (!address)
9883 {
9884 if (this_frag->tc_frag_data.is_aligning_branch)
9885 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
9886 else
9887 frag_wane (this_frag);
9888 }
9889 else
9890 {
9891 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
9892 opt_diff = local_opt_diff;
9893 gas_assert (opt_diff >= 0);
9894 gas_assert (max_diff >= opt_diff);
9895 if (max_diff == 0)
9896 return 0;
9897
9898 if (fragP)
9899 fragP = fragP->fr_next;
9900
9901 while (fragP && opt_diff < max_diff && address)
9902 {
9903 /* We only use these to determine if we can exit early
9904 because there will be plenty of ways to align future
9905 align frags. */
9906 int glob_widens = 0;
9907 int dnn = 0;
9908 int dw = 0;
9909 bfd_boolean glob_pad = 0;
9910 address = find_address_of_next_align_frag
9911 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
9912 /* If there is a padable portion, then skip. */
9913 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
9914 address = 0;
9915
9916 if (address)
9917 {
9918 offsetT next_m_diff;
9919 offsetT next_o_diff;
9920
9921 /* Downrange frags haven't had stretch added to them yet. */
9922 address += stretch;
9923
9924 /* The address also includes any text expansion from this
9925 frag in a previous pass, but we don't want that. */
9926 address -= this_frag->tc_frag_data.text_expansion[0];
9927
9928 /* Assume we are going to move at least opt_diff. In
9929 reality, we might not be able to, but assuming that
9930 we will helps catch cases where moving opt_diff pushes
9931 the next target from aligned to unaligned. */
9932 address += opt_diff;
9933
9934 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
9935
9936 /* Now cleanup for the adjustments to address. */
9937 next_o_diff += opt_diff;
9938 next_m_diff += opt_diff;
9939 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
9940 opt_diff = next_o_diff;
9941 if (next_m_diff < max_diff)
9942 max_diff = next_m_diff;
9943 fragP = fragP->fr_next;
9944 }
9945 }
9946
9947 /* If there are enough wideners in between, do it. */
9948 if (paddable)
9949 {
9950 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
9951 {
9952 gas_assert (opt_diff <= (signed) xtensa_fetch_width);
9953 return opt_diff;
9954 }
9955 return 0;
9956 }
9957 local_stretch_amount
9958 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9959 num_widens, local_opt_diff);
9960 global_stretch_amount
9961 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9962 num_widens, opt_diff);
9963 /* If the condition below is true, then the frag couldn't
9964 stretch the correct amount for the global case, so we just
9965 optimize locally. We'll rely on the subsequent frags to get
9966 the correct alignment in the global case. */
9967 if (global_stretch_amount < local_stretch_amount)
9968 stretch_amount = local_stretch_amount;
9969 else
9970 stretch_amount = global_stretch_amount;
9971
9972 if (this_frag->fr_subtype == RELAX_SLOTS
9973 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9974 gas_assert (stretch_amount <= 1);
9975 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
9976 {
9977 if (this_frag->tc_frag_data.is_no_density)
9978 gas_assert (stretch_amount == 3 || stretch_amount == 0);
9979 else
9980 gas_assert (stretch_amount <= 3);
9981 }
9982 }
9983 return stretch_amount;
9984 }
9985
9986
9987 /* The idea: widen everything you can to get a target or loop aligned,
9988 then start using NOPs.
9989
9990 wide_nops = the number of wide NOPs available for aligning
9991 narrow_nops = the number of narrow NOPs available for aligning
9992 (a subset of wide_nops)
9993 widens = the number of narrow instructions that should be widened
9994
9995 */
9996
9997 static long
bytes_to_stretch(fragS * this_frag,int wide_nops,int narrow_nops,int num_widens,int desired_diff)9998 bytes_to_stretch (fragS *this_frag,
9999 int wide_nops,
10000 int narrow_nops,
10001 int num_widens,
10002 int desired_diff)
10003 {
10004 int nops_needed;
10005 int nop_bytes;
10006 int extra_bytes;
10007 int bytes_short = desired_diff - num_widens;
10008
10009 gas_assert (desired_diff >= 0
10010 && desired_diff < (signed) xtensa_fetch_width);
10011 if (desired_diff == 0)
10012 return 0;
10013
10014 gas_assert (wide_nops > 0 || num_widens > 0);
10015
10016 /* Always prefer widening to NOP-filling. */
10017 if (bytes_short < 0)
10018 {
10019 /* There are enough RELAX_NARROW frags after this one
10020 to align the target without widening this frag in any way. */
10021 return 0;
10022 }
10023
10024 if (bytes_short == 0)
10025 {
10026 /* Widen every narrow between here and the align target
10027 and the align target will be properly aligned. */
10028 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10029 return 0;
10030 else
10031 return 1;
10032 }
10033
10034 /* From here we will need at least one NOP to get an alignment.
10035 However, we may not be able to align at all, in which case,
10036 don't widen. */
10037 nops_needed = desired_diff / 3;
10038
10039 /* If there aren't enough nops, don't widen. */
10040 if (nops_needed > wide_nops)
10041 return 0;
10042
10043 /* First try it with all wide nops. */
10044 nop_bytes = nops_needed * 3;
10045 extra_bytes = desired_diff - nop_bytes;
10046
10047 if (nop_bytes + num_widens >= desired_diff)
10048 {
10049 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10050 return 3;
10051 else if (num_widens == extra_bytes)
10052 return 1;
10053 return 0;
10054 }
10055
10056 /* Add a narrow nop. */
10057 nops_needed++;
10058 nop_bytes += 2;
10059 extra_bytes -= 2;
10060 if (narrow_nops == 0 || nops_needed > wide_nops)
10061 return 0;
10062
10063 if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0)
10064 {
10065 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10066 return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
10067 else if (num_widens == extra_bytes)
10068 return 1;
10069 return 0;
10070 }
10071
10072 /* Replace a wide nop with a narrow nop--we can get here if
10073 extra_bytes was negative in the previous conditional. */
10074 if (narrow_nops == 1)
10075 return 0;
10076 nop_bytes--;
10077 extra_bytes++;
10078 if (nop_bytes + num_widens >= desired_diff)
10079 {
10080 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10081 return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
10082 else if (num_widens == extra_bytes)
10083 return 1;
10084 return 0;
10085 }
10086
10087 /* If we can't satisfy any of the above cases, then we can't align
10088 using padding or fill nops. */
10089 return 0;
10090 }
10091
10092
10093 static fragS *
xg_find_best_trampoline_for_tinsn(TInsn * tinsn,fragS * fragP)10094 xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP)
10095 {
10096 symbolS *sym = tinsn->tok[0].X_add_symbol;
10097 addressT source = fragP->fr_address;
10098 addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number;
10099 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
10100 size_t i;
10101
10102 if (!ts || !ts->index.n_entries)
10103 return NULL;
10104
10105 i = xg_find_best_trampoline (&ts->index, source, target);
10106
10107 return ts->index.entry[i];
10108 }
10109
10110
10111 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10112 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var
10113 and finish the frag if it's full (but don't remove it from the trampoline
10114 frag index). Return fixup for the newly created jump. */
xg_append_jump(fragS * fragP,symbolS * sym,offsetT offset)10115 static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset)
10116 {
10117 fixS *fixP;
10118 TInsn insn;
10119 xtensa_format fmt;
10120 xtensa_isa isa = xtensa_default_isa;
10121
10122 gas_assert (fragP->fr_var >= 3);
10123 tinsn_init (&insn);
10124 insn.insn_type = ITYPE_INSN;
10125 insn.opcode = xtensa_j_opcode;
10126 insn.ntok = 1;
10127 set_expr_symbol_offset (&insn.tok[0], sym, offset);
10128 fmt = xg_get_single_format (xtensa_j_opcode);
10129 tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf);
10130 xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
10131 xtensa_insnbuf_to_chars (isa, trampoline_buf,
10132 (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3);
10133 fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, TRUE,
10134 BFD_RELOC_XTENSA_SLOT0_OP);
10135 fixP->tc_fix_data.slot = 0;
10136
10137 fragP->fr_fix += 3;
10138 fragP->fr_var -= 3;
10139
10140 /* Adjust the jump around this trampoline (if present). */
10141 if (fragP->tc_frag_data.jump_around_fix)
10142 fragP->tc_frag_data.jump_around_fix->fx_offset += 3;
10143
10144 /* Do we have room for more? */
10145 if (xg_is_trampoline_frag_full (fragP))
10146 {
10147 frag_wane (fragP);
10148 fragP->fr_subtype = 0;
10149 }
10150
10151 return fixP;
10152 }
10153
10154
10155 static int
init_trampoline_frag(fragS * fp)10156 init_trampoline_frag (fragS *fp)
10157 {
10158 int growth = 0;
10159
10160 if (fp->fr_fix == 0)
10161 {
10162 symbolS *lsym;
10163 char label[10 + 2 * sizeof(fp)];
10164
10165 sprintf (label, ".L0_TR_%p", fp);
10166 lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp);
10167 fp->fr_symbol = lsym;
10168 if (fp->tc_frag_data.needs_jump_around)
10169 {
10170 fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3);
10171 growth = 3;
10172 }
10173 }
10174 return growth;
10175 }
10176
10177 static int
xg_get_single_symbol_slot(fragS * fragP)10178 xg_get_single_symbol_slot (fragS *fragP)
10179 {
10180 int i;
10181 int slot = -1;
10182
10183 for (i = 0; i < MAX_SLOTS; ++i)
10184 if (fragP->tc_frag_data.slot_symbols[i])
10185 {
10186 gas_assert (slot == -1);
10187 slot = i;
10188 }
10189
10190 gas_assert (slot >= 0 && slot < MAX_SLOTS);
10191
10192 return slot;
10193 }
10194
10195 static fixS *
add_jump_to_trampoline(fragS * tramp,fragS * origfrag)10196 add_jump_to_trampoline (fragS *tramp, fragS *origfrag)
10197 {
10198 int slot = xg_get_single_symbol_slot (origfrag);
10199 fixS *fixP;
10200
10201 /* Assemble a jump to the target label in the trampoline frag. */
10202 fixP = xg_append_jump (tramp,
10203 origfrag->tc_frag_data.slot_symbols[slot],
10204 origfrag->tc_frag_data.slot_offsets[slot]);
10205
10206 /* Modify the original j to point here. */
10207 origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol;
10208 origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3;
10209
10210 /* If trampoline is full, remove it from the list. */
10211 if (xg_is_trampoline_frag_full (tramp))
10212 {
10213 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
10214 size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address);
10215
10216 gas_assert (ts->index.entry[tr] == tramp);
10217 xg_remove_trampoline_from_index (&ts->index, tr);
10218 }
10219
10220 return fixP;
10221 }
10222
10223
10224 static long
relax_frag_immed(segT segP,fragS * fragP,long stretch,int min_steps,xtensa_format fmt,int slot,int * stretched_p,bfd_boolean estimate_only)10225 relax_frag_immed (segT segP,
10226 fragS *fragP,
10227 long stretch,
10228 int min_steps,
10229 xtensa_format fmt,
10230 int slot,
10231 int *stretched_p,
10232 bfd_boolean estimate_only)
10233 {
10234 TInsn tinsn;
10235 int old_size;
10236 bfd_boolean negatable_branch = FALSE;
10237 bfd_boolean branch_jmp_to_next = FALSE;
10238 bfd_boolean from_wide_insn = FALSE;
10239 xtensa_isa isa = xtensa_default_isa;
10240 IStack istack;
10241 offsetT frag_offset;
10242 int num_steps;
10243 int num_text_bytes, num_literal_bytes;
10244 int literal_diff, total_text_diff, this_text_diff;
10245
10246 gas_assert (fragP->fr_opcode != NULL);
10247
10248 xg_clear_vinsn (&cur_vinsn);
10249 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
10250 if (cur_vinsn.num_slots > 1)
10251 from_wide_insn = TRUE;
10252
10253 tinsn = cur_vinsn.slots[slot];
10254 tinsn_immed_from_frag (&tinsn, fragP, slot);
10255
10256 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
10257 return 0;
10258
10259 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10260 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
10261
10262 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
10263
10264 old_size = xtensa_format_length (isa, fmt);
10265
10266 /* Special case: replace a branch to the next instruction with a NOP.
10267 This is required to work around a hardware bug in T1040.0 and also
10268 serves as an optimization. */
10269
10270 if (branch_jmp_to_next
10271 && ((old_size == 2) || (old_size == 3))
10272 && !next_frag_is_loop_target (fragP))
10273 return 0;
10274
10275 /* Here is the fun stuff: Get the immediate field from this
10276 instruction. If it fits, we are done. If not, find the next
10277 instruction sequence that fits. */
10278
10279 frag_offset = fragP->fr_opcode - fragP->fr_literal;
10280 istack_init (&istack);
10281 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
10282 min_steps, stretch);
10283 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10284
10285 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
10286
10287 /* Figure out the number of bytes needed. */
10288 num_literal_bytes = get_num_stack_literal_bytes (&istack);
10289 literal_diff
10290 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10291 num_text_bytes = get_num_stack_text_bytes (&istack);
10292
10293 if (from_wide_insn)
10294 {
10295 int first = 0;
10296 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
10297 first++;
10298
10299 num_text_bytes += old_size;
10300 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
10301 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
10302 else
10303 {
10304 /* The first instruction in the relaxed sequence will go after
10305 the current wide instruction, and thus its symbolic immediates
10306 might not fit. */
10307
10308 istack_init (&istack);
10309 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
10310 frag_offset + old_size,
10311 min_steps, stretch + old_size);
10312 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10313
10314 fragP->tc_frag_data.slot_subtypes[slot]
10315 = (int) RELAX_IMMED + num_steps;
10316
10317 num_literal_bytes = get_num_stack_literal_bytes (&istack);
10318 literal_diff
10319 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10320
10321 num_text_bytes = get_num_stack_text_bytes (&istack) + old_size;
10322 }
10323 }
10324
10325 total_text_diff = num_text_bytes - old_size;
10326 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
10327
10328 /* It MUST get larger. If not, we could get an infinite loop. */
10329 gas_assert (num_text_bytes >= 0);
10330 gas_assert (literal_diff >= 0);
10331 gas_assert (total_text_diff >= 0);
10332
10333 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
10334 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
10335 gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
10336 gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
10337
10338 /* Find the associated expandable literal for this. */
10339 if (literal_diff != 0)
10340 {
10341 fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot];
10342 if (lit_fragP)
10343 {
10344 gas_assert (literal_diff == 4);
10345 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
10346
10347 /* We expect that the literal section state has NOT been
10348 modified yet. */
10349 gas_assert (lit_fragP->fr_type == rs_machine_dependent
10350 && lit_fragP->fr_subtype == RELAX_LITERAL);
10351 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
10352
10353 /* We need to mark this section for another iteration
10354 of relaxation. */
10355 (*stretched_p)++;
10356 }
10357 }
10358
10359 if (negatable_branch && istack.ninsn > 1)
10360 update_next_frag_state (fragP);
10361
10362 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10363 if (istack.ninsn > 2 &&
10364 istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL &&
10365 istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN &&
10366 istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode)
10367 {
10368 TInsn *jinsn = &istack.insn[istack.ninsn - 2];
10369 struct trampoline_seg *ts = find_trampoline_seg (segP);
10370 struct trampoline_chain *tc = NULL;
10371
10372 if (ts &&
10373 !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset,
10374 total_text_diff))
10375 {
10376 int s = xg_get_single_symbol_slot (fragP);
10377 addressT offset = fragP->tc_frag_data.slot_offsets[s];
10378
10379 tc = xg_find_best_eq_target (ts, fragP->fr_address,
10380 &fragP->tc_frag_data.slot_symbols[s],
10381 &offset);
10382
10383 if (!tc)
10384 tc = xg_create_trampoline_chain (ts,
10385 fragP->tc_frag_data.slot_symbols[s],
10386 offset);
10387 fragP->tc_frag_data.slot_offsets[s] = offset;
10388 tinsn_immed_from_frag (jinsn, fragP, s);
10389 }
10390
10391 if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset,
10392 total_text_diff))
10393 {
10394 fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP);
10395
10396 if (tf)
10397 {
10398 fixS *fixP;
10399
10400 this_text_diff += init_trampoline_frag (tf) + 3;
10401 fixP = add_jump_to_trampoline (tf, fragP);
10402 xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
10403 fixP->fx_where);
10404 fragP->tc_frag_data.relax_seen = FALSE;
10405 }
10406 else
10407 {
10408 /* If target symbol is undefined, assume it will reach once linked. */
10409 expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0];
10410
10411 if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol))
10412 {
10413 as_bad_where (fragP->fr_file, fragP->fr_line,
10414 _("jump target out of range; no usable trampoline found"));
10415 }
10416 }
10417 }
10418 }
10419
10420 return this_text_diff;
10421 }
10422
10423
10424 /* md_convert_frag Hook and Helper Functions. */
10425
10426 static void convert_frag_align_next_opcode (fragS *);
10427 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
10428 static void convert_frag_fill_nop (fragS *);
10429 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
10430
10431 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec,fragS * fragp)10432 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
10433 {
10434 static xtensa_insnbuf vbuf = NULL;
10435 xtensa_isa isa = xtensa_default_isa;
10436 int slot;
10437 int num_slots;
10438 xtensa_format fmt;
10439 const char *file_name;
10440 unsigned line;
10441
10442 file_name = as_where (&line);
10443 new_logical_line (fragp->fr_file, fragp->fr_line);
10444
10445 switch (fragp->fr_subtype)
10446 {
10447 case RELAX_ALIGN_NEXT_OPCODE:
10448 /* Always convert. */
10449 convert_frag_align_next_opcode (fragp);
10450 break;
10451
10452 case RELAX_DESIRE_ALIGN:
10453 /* Do nothing. If not aligned already, too bad. */
10454 break;
10455
10456 case RELAX_LITERAL:
10457 case RELAX_LITERAL_FINAL:
10458 break;
10459
10460 case RELAX_SLOTS:
10461 if (vbuf == NULL)
10462 vbuf = xtensa_insnbuf_alloc (isa);
10463
10464 xtensa_insnbuf_from_chars
10465 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
10466 fmt = xtensa_format_decode (isa, vbuf);
10467 num_slots = xtensa_format_num_slots (isa, fmt);
10468
10469 for (slot = 0; slot < num_slots; slot++)
10470 {
10471 switch (fragp->tc_frag_data.slot_subtypes[slot])
10472 {
10473 case RELAX_NARROW:
10474 convert_frag_narrow (sec, fragp, fmt, slot);
10475 break;
10476
10477 case RELAX_IMMED:
10478 case RELAX_IMMED_STEP1:
10479 case RELAX_IMMED_STEP2:
10480 case RELAX_IMMED_STEP3:
10481 /* Place the immediate. */
10482 convert_frag_immed
10483 (sec, fragp,
10484 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
10485 fmt, slot);
10486 break;
10487
10488 default:
10489 /* This is OK because some slots could have
10490 relaxations and others have none. */
10491 break;
10492 }
10493 }
10494 break;
10495
10496 case RELAX_UNREACHABLE:
10497 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
10498 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
10499 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
10500 frag_wane (fragp);
10501 break;
10502
10503 case RELAX_MAYBE_UNREACHABLE:
10504 case RELAX_MAYBE_DESIRE_ALIGN:
10505 frag_wane (fragp);
10506 break;
10507
10508 case RELAX_FILL_NOP:
10509 convert_frag_fill_nop (fragp);
10510 break;
10511
10512 case RELAX_LITERAL_NR:
10513 if (use_literal_section)
10514 {
10515 /* This should have been handled during relaxation. When
10516 relaxing a code segment, literals sometimes need to be
10517 added to the corresponding literal segment. If that
10518 literal segment has already been relaxed, then we end up
10519 in this situation. Marking the literal segments as data
10520 would make this happen less often (since GAS always relaxes
10521 code before data), but we could still get into trouble if
10522 there are instructions in a segment that is not marked as
10523 containing code. Until we can implement a better solution,
10524 cheat and adjust the addresses of all the following frags.
10525 This could break subsequent alignments, but the linker's
10526 literal coalescing will do that anyway. */
10527
10528 fragS *f;
10529 fragp->fr_subtype = RELAX_LITERAL_FINAL;
10530 gas_assert (fragp->tc_frag_data.unreported_expansion == 4);
10531 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
10532 fragp->fr_var -= 4;
10533 fragp->fr_fix += 4;
10534 for (f = fragp->fr_next; f; f = f->fr_next)
10535 f->fr_address += 4;
10536 }
10537 else
10538 as_bad (_("invalid relaxation fragment result"));
10539 break;
10540
10541 case RELAX_TRAMPOLINE:
10542 break;
10543 }
10544
10545 fragp->fr_var = 0;
10546 new_logical_line (file_name, line);
10547 }
10548
10549
10550 static void
convert_frag_align_next_opcode(fragS * fragp)10551 convert_frag_align_next_opcode (fragS *fragp)
10552 {
10553 char *nop_buf; /* Location for Writing. */
10554 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
10555 addressT aligned_address;
10556 offsetT fill_size;
10557 int nop, nop_count;
10558
10559 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
10560 fragp->fr_fix);
10561 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
10562 nop_count = get_text_align_nop_count (fill_size, use_no_density);
10563 nop_buf = fragp->fr_literal + fragp->fr_fix;
10564
10565 for (nop = 0; nop < nop_count; nop++)
10566 {
10567 int nop_size;
10568 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
10569
10570 assemble_nop (nop_size, nop_buf);
10571 nop_buf += nop_size;
10572 }
10573
10574 fragp->fr_fix += fill_size;
10575 fragp->fr_var -= fill_size;
10576 }
10577
10578
10579 static void
convert_frag_narrow(segT segP,fragS * fragP,xtensa_format fmt,int slot)10580 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
10581 {
10582 TInsn tinsn, single_target;
10583 int size, old_size, diff;
10584 offsetT frag_offset;
10585
10586 gas_assert (slot == 0);
10587 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
10588
10589 if (fragP->tc_frag_data.is_aligning_branch == 1)
10590 {
10591 gas_assert (fragP->tc_frag_data.text_expansion[0] == 1
10592 || fragP->tc_frag_data.text_expansion[0] == 0);
10593 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
10594 fmt, slot);
10595 return;
10596 }
10597
10598 if (fragP->tc_frag_data.text_expansion[0] == 0)
10599 {
10600 /* No conversion. */
10601 fragP->fr_var = 0;
10602 return;
10603 }
10604
10605 gas_assert (fragP->fr_opcode != NULL);
10606
10607 /* Frags in this relaxation state should only contain
10608 single instruction bundles. */
10609 tinsn_immed_from_frag (&tinsn, fragP, 0);
10610
10611 /* Just convert it to a wide form.... */
10612 size = 0;
10613 old_size = xg_get_single_size (tinsn.opcode);
10614
10615 tinsn_init (&single_target);
10616 frag_offset = fragP->fr_opcode - fragP->fr_literal;
10617
10618 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
10619 {
10620 as_bad (_("unable to widen instruction"));
10621 return;
10622 }
10623
10624 size = xg_get_single_size (single_target.opcode);
10625 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
10626 frag_offset, TRUE);
10627
10628 diff = size - old_size;
10629 gas_assert (diff >= 0);
10630 gas_assert (diff <= fragP->fr_var);
10631 fragP->fr_var -= diff;
10632 fragP->fr_fix += diff;
10633
10634 /* clean it up */
10635 fragP->fr_var = 0;
10636 }
10637
10638
10639 static void
convert_frag_fill_nop(fragS * fragP)10640 convert_frag_fill_nop (fragS *fragP)
10641 {
10642 char *loc = &fragP->fr_literal[fragP->fr_fix];
10643 int size = fragP->tc_frag_data.text_expansion[0];
10644 gas_assert ((unsigned) size == (fragP->fr_next->fr_address
10645 - fragP->fr_address - fragP->fr_fix));
10646 if (size == 0)
10647 {
10648 /* No conversion. */
10649 fragP->fr_var = 0;
10650 return;
10651 }
10652 assemble_nop (size, loc);
10653 fragP->tc_frag_data.is_insn = TRUE;
10654 fragP->fr_var -= size;
10655 fragP->fr_fix += size;
10656 frag_wane (fragP);
10657 }
10658
10659
10660 static fixS *fix_new_exp_in_seg
10661 (segT, subsegT, fragS *, int, int, expressionS *, int,
10662 bfd_reloc_code_real_type);
10663
10664 static void
convert_frag_immed(segT segP,fragS * fragP,int min_steps,xtensa_format fmt,int slot)10665 convert_frag_immed (segT segP,
10666 fragS *fragP,
10667 int min_steps,
10668 xtensa_format fmt,
10669 int slot)
10670 {
10671 char *immed_instr = fragP->fr_opcode;
10672 TInsn orig_tinsn;
10673 bfd_boolean expanded = FALSE;
10674 bfd_boolean branch_jmp_to_next = FALSE;
10675 char *fr_opcode = fragP->fr_opcode;
10676 xtensa_isa isa = xtensa_default_isa;
10677 bfd_boolean from_wide_insn = FALSE;
10678 int bytes;
10679 bfd_boolean is_loop;
10680
10681 gas_assert (fr_opcode != NULL);
10682
10683 xg_clear_vinsn (&cur_vinsn);
10684
10685 vinsn_from_chars (&cur_vinsn, fr_opcode);
10686 if (cur_vinsn.num_slots > 1)
10687 from_wide_insn = TRUE;
10688
10689 orig_tinsn = cur_vinsn.slots[slot];
10690 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
10691
10692 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
10693
10694 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10695 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
10696
10697 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
10698 {
10699 /* Conversion just inserts a NOP and marks the fix as completed. */
10700 bytes = xtensa_format_length (isa, fmt);
10701 if (bytes >= 4)
10702 {
10703 cur_vinsn.slots[slot].opcode =
10704 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
10705 cur_vinsn.slots[slot].ntok = 0;
10706 }
10707 else
10708 {
10709 bytes += fragP->tc_frag_data.text_expansion[0];
10710 gas_assert (bytes == 2 || bytes == 3);
10711 build_nop (&cur_vinsn.slots[0], bytes);
10712 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
10713 }
10714 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
10715 xtensa_insnbuf_to_chars
10716 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
10717 fragP->fr_var = 0;
10718 }
10719 else
10720 {
10721 /* Here is the fun stuff: Get the immediate field from this
10722 instruction. If it fits, we're done. If not, find the next
10723 instruction sequence that fits. */
10724
10725 IStack istack;
10726 int i;
10727 symbolS *lit_sym = NULL;
10728 int total_size = 0;
10729 int target_offset = 0;
10730 int old_size;
10731 int diff;
10732 symbolS *gen_label = NULL;
10733 offsetT frag_offset;
10734 bfd_boolean first = TRUE;
10735
10736 /* It does not fit. Find something that does and
10737 convert immediately. */
10738 frag_offset = fr_opcode - fragP->fr_literal;
10739 istack_init (&istack);
10740 xg_assembly_relax (&istack, &orig_tinsn,
10741 segP, fragP, frag_offset, min_steps, 0);
10742
10743 old_size = xtensa_format_length (isa, fmt);
10744
10745 /* Assemble this right inline. */
10746
10747 /* First, create the mapping from a label name to the REAL label. */
10748 target_offset = 0;
10749 for (i = 0; i < istack.ninsn; i++)
10750 {
10751 TInsn *tinsn = &istack.insn[i];
10752 fragS *lit_frag;
10753
10754 switch (tinsn->insn_type)
10755 {
10756 case ITYPE_LITERAL:
10757 if (lit_sym != NULL)
10758 as_bad (_("multiple literals in expansion"));
10759 /* First find the appropriate space in the literal pool. */
10760 lit_frag = fragP->tc_frag_data.literal_frags[slot];
10761 if (lit_frag == NULL)
10762 as_bad (_("no registered fragment for literal"));
10763 if (tinsn->ntok != 1)
10764 as_bad (_("number of literal tokens != 1"));
10765
10766 /* Set the literal symbol and add a fixup. */
10767 lit_sym = lit_frag->fr_symbol;
10768 break;
10769
10770 case ITYPE_LABEL:
10771 if (align_targets && !is_loop)
10772 {
10773 fragS *unreach = fragP->fr_next;
10774 while (!(unreach->fr_type == rs_machine_dependent
10775 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10776 || unreach->fr_subtype == RELAX_UNREACHABLE)))
10777 {
10778 unreach = unreach->fr_next;
10779 }
10780
10781 gas_assert (unreach->fr_type == rs_machine_dependent
10782 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10783 || unreach->fr_subtype == RELAX_UNREACHABLE));
10784
10785 target_offset += unreach->tc_frag_data.text_expansion[0];
10786 }
10787 gas_assert (gen_label == NULL);
10788 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
10789 fr_opcode - fragP->fr_literal
10790 + target_offset, fragP);
10791 break;
10792
10793 case ITYPE_INSN:
10794 if (first && from_wide_insn)
10795 {
10796 target_offset += xtensa_format_length (isa, fmt);
10797 first = FALSE;
10798 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10799 target_offset += xg_get_single_size (tinsn->opcode);
10800 }
10801 else
10802 target_offset += xg_get_single_size (tinsn->opcode);
10803 break;
10804 }
10805 }
10806
10807 total_size = 0;
10808 first = TRUE;
10809 for (i = 0; i < istack.ninsn; i++)
10810 {
10811 TInsn *tinsn = &istack.insn[i];
10812 fragS *lit_frag;
10813 int size;
10814 segT target_seg;
10815 bfd_reloc_code_real_type reloc_type;
10816
10817 switch (tinsn->insn_type)
10818 {
10819 case ITYPE_LITERAL:
10820 lit_frag = fragP->tc_frag_data.literal_frags[slot];
10821 /* Already checked. */
10822 gas_assert (lit_frag != NULL);
10823 gas_assert (lit_sym != NULL);
10824 gas_assert (tinsn->ntok == 1);
10825 /* Add a fixup. */
10826 target_seg = S_GET_SEGMENT (lit_sym);
10827 gas_assert (target_seg);
10828 reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE);
10829 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
10830 &tinsn->tok[0], FALSE, reloc_type);
10831 break;
10832
10833 case ITYPE_LABEL:
10834 break;
10835
10836 case ITYPE_INSN:
10837 xg_resolve_labels (tinsn, gen_label);
10838 xg_resolve_literals (tinsn, lit_sym);
10839 if (from_wide_insn && first)
10840 {
10841 first = FALSE;
10842 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10843 {
10844 cur_vinsn.slots[slot] = *tinsn;
10845 }
10846 else
10847 {
10848 cur_vinsn.slots[slot].opcode =
10849 xtensa_format_slot_nop_opcode (isa, fmt, slot);
10850 cur_vinsn.slots[slot].ntok = 0;
10851 }
10852 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
10853 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
10854 (unsigned char *) immed_instr, 0);
10855 fragP->tc_frag_data.is_insn = TRUE;
10856 size = xtensa_format_length (isa, fmt);
10857 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10858 {
10859 xg_emit_insn_to_buf
10860 (tinsn, immed_instr + size, fragP,
10861 immed_instr - fragP->fr_literal + size, TRUE);
10862 size += xg_get_single_size (tinsn->opcode);
10863 }
10864 }
10865 else
10866 {
10867 size = xg_get_single_size (tinsn->opcode);
10868 xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
10869 immed_instr - fragP->fr_literal, TRUE);
10870 }
10871 immed_instr += size;
10872 total_size += size;
10873 break;
10874 }
10875 }
10876
10877 diff = total_size - old_size;
10878 gas_assert (diff >= 0);
10879 if (diff != 0)
10880 expanded = TRUE;
10881 gas_assert (diff <= fragP->fr_var);
10882 fragP->fr_var -= diff;
10883 fragP->fr_fix += diff;
10884 }
10885
10886 /* Check for undefined immediates in LOOP instructions. */
10887 if (is_loop)
10888 {
10889 symbolS *sym;
10890 sym = orig_tinsn.tok[1].X_add_symbol;
10891 if (sym != NULL && !S_IS_DEFINED (sym))
10892 {
10893 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10894 return;
10895 }
10896 sym = orig_tinsn.tok[1].X_op_symbol;
10897 if (sym != NULL && !S_IS_DEFINED (sym))
10898 {
10899 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10900 return;
10901 }
10902 }
10903
10904 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
10905 {
10906 /* Add an expansion note on the expanded instruction. */
10907 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
10908 &orig_tinsn.tok[0], TRUE,
10909 BFD_RELOC_XTENSA_ASM_EXPAND);
10910 }
10911 }
10912
10913
10914 /* Add a new fix expression into the desired segment. We have to
10915 switch to that segment to do this. */
10916
10917 static fixS *
fix_new_exp_in_seg(segT new_seg,subsegT new_subseg,fragS * frag,int where,int size,expressionS * exp,int pcrel,bfd_reloc_code_real_type r_type)10918 fix_new_exp_in_seg (segT new_seg,
10919 subsegT new_subseg,
10920 fragS *frag,
10921 int where,
10922 int size,
10923 expressionS *exp,
10924 int pcrel,
10925 bfd_reloc_code_real_type r_type)
10926 {
10927 fixS *new_fix;
10928 segT seg = now_seg;
10929 subsegT subseg = now_subseg;
10930
10931 gas_assert (new_seg != 0);
10932 subseg_set (new_seg, new_subseg);
10933
10934 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
10935 subseg_set (seg, subseg);
10936 return new_fix;
10937 }
10938
10939
10940
10941 /* A map that keeps information on a per-subsegment basis. This is
10942 maintained during initial assembly, but is invalid once the
10943 subsegments are smashed together. I.E., it cannot be used during
10944 the relaxation. */
10945
10946 typedef struct subseg_map_struct
10947 {
10948 /* the key */
10949 segT seg;
10950 subsegT subseg;
10951
10952 /* the data */
10953 unsigned flags;
10954 float total_freq; /* fall-through + branch target frequency */
10955 float target_freq; /* branch target frequency alone */
10956
10957 struct subseg_map_struct *next;
10958 } subseg_map;
10959
10960
10961 static subseg_map *sseg_map = NULL;
10962
10963 static subseg_map *
get_subseg_info(segT seg,subsegT subseg)10964 get_subseg_info (segT seg, subsegT subseg)
10965 {
10966 subseg_map *subseg_e;
10967
10968 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
10969 {
10970 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
10971 break;
10972 }
10973 return subseg_e;
10974 }
10975
10976
10977 static subseg_map *
add_subseg_info(segT seg,subsegT subseg)10978 add_subseg_info (segT seg, subsegT subseg)
10979 {
10980 subseg_map *subseg_e = XNEW (subseg_map);
10981 memset (subseg_e, 0, sizeof (subseg_map));
10982 subseg_e->seg = seg;
10983 subseg_e->subseg = subseg;
10984 subseg_e->flags = 0;
10985 /* Start off considering every branch target very important. */
10986 subseg_e->target_freq = 1.0;
10987 subseg_e->total_freq = 1.0;
10988 subseg_e->next = sseg_map;
10989 sseg_map = subseg_e;
10990 return subseg_e;
10991 }
10992
10993
10994 static unsigned
get_last_insn_flags(segT seg,subsegT subseg)10995 get_last_insn_flags (segT seg, subsegT subseg)
10996 {
10997 subseg_map *subseg_e = get_subseg_info (seg, subseg);
10998 if (subseg_e)
10999 return subseg_e->flags;
11000 return 0;
11001 }
11002
11003
11004 static void
set_last_insn_flags(segT seg,subsegT subseg,unsigned fl,bfd_boolean val)11005 set_last_insn_flags (segT seg,
11006 subsegT subseg,
11007 unsigned fl,
11008 bfd_boolean val)
11009 {
11010 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11011 if (! subseg_e)
11012 subseg_e = add_subseg_info (seg, subseg);
11013 if (val)
11014 subseg_e->flags |= fl;
11015 else
11016 subseg_e->flags &= ~fl;
11017 }
11018
11019
11020 static float
get_subseg_total_freq(segT seg,subsegT subseg)11021 get_subseg_total_freq (segT seg, subsegT subseg)
11022 {
11023 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11024 if (subseg_e)
11025 return subseg_e->total_freq;
11026 return 1.0;
11027 }
11028
11029
11030 static float
get_subseg_target_freq(segT seg,subsegT subseg)11031 get_subseg_target_freq (segT seg, subsegT subseg)
11032 {
11033 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11034 if (subseg_e)
11035 return subseg_e->target_freq;
11036 return 1.0;
11037 }
11038
11039
11040 static void
set_subseg_freq(segT seg,subsegT subseg,float total_f,float target_f)11041 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
11042 {
11043 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11044 if (! subseg_e)
11045 subseg_e = add_subseg_info (seg, subseg);
11046 subseg_e->total_freq = total_f;
11047 subseg_e->target_freq = target_f;
11048 }
11049
11050
11051 /* Segment Lists and emit_state Stuff. */
11052
11053 static void
xtensa_move_seg_list_to_beginning(seg_list * head)11054 xtensa_move_seg_list_to_beginning (seg_list *head)
11055 {
11056 head = head->next;
11057 while (head)
11058 {
11059 segT literal_section = head->seg;
11060
11061 /* Move the literal section to the front of the section list. */
11062 gas_assert (literal_section);
11063 if (literal_section != stdoutput->sections)
11064 {
11065 bfd_section_list_remove (stdoutput, literal_section);
11066 bfd_section_list_prepend (stdoutput, literal_section);
11067 }
11068 head = head->next;
11069 }
11070 }
11071
11072
11073 static void mark_literal_frags (seg_list *);
11074
11075 static void
xg_promote_candidate_litpool(struct litpool_seg * lps,struct litpool_frag * lp)11076 xg_promote_candidate_litpool (struct litpool_seg *lps,
11077 struct litpool_frag *lp)
11078 {
11079 fragS *poolbeg;
11080 fragS *poolend;
11081 symbolS *lsym;
11082 char label[10 + 2 * sizeof (fragS *)];
11083
11084 poolbeg = lp->fragP;
11085 lp->priority = 1;
11086 poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN;
11087 poolend = poolbeg->fr_next;
11088 gas_assert (poolend->fr_type == rs_machine_dependent &&
11089 poolend->fr_subtype == RELAX_LITERAL_POOL_END);
11090 /* Create a local symbol pointing to the
11091 end of the pool. */
11092 sprintf (label, ".L0_LT_%p", poolbeg);
11093 lsym = (symbolS *)local_symbol_make (label, lps->seg,
11094 0, poolend);
11095 poolbeg->fr_symbol = lsym;
11096 /* Rest is done in xtensa_relax_frag. */
11097 }
11098
xg_find_litpool(struct litpool_seg * lps,struct litpool_frag * lpf,addressT addr)11099 static struct litpool_frag *xg_find_litpool (struct litpool_seg *lps,
11100 struct litpool_frag *lpf,
11101 addressT addr)
11102 {
11103 struct litpool_frag *lp = lpf->prev;
11104
11105 gas_assert (lp->fragP);
11106
11107 while (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11108 {
11109 lp = lp->prev;
11110 if (lp->fragP == NULL)
11111 {
11112 /* End of list; have to bite the bullet.
11113 Take the nearest. */
11114 lp = lpf->prev;
11115 break;
11116 }
11117 /* Does it (conservatively) reach? */
11118 if (addr - lp->addr <= 128 * 1024)
11119 {
11120 if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
11121 lp->literal_count < MAX_POOL_LITERALS)
11122 {
11123 /* Found a good one. */
11124 break;
11125 }
11126 else if (lp->prev->fragP &&
11127 addr - lp->prev->addr > 128 * 1024 &&
11128 lp->prev->literal_count < MAX_POOL_LITERALS)
11129 {
11130 /* This is still a "candidate" but the next one
11131 will be too far away, so revert to the nearest
11132 one, convert it and add the jump around. */
11133 lp = lpf->prev;
11134 break;
11135 }
11136 }
11137 }
11138
11139 if (lp->literal_count >= MAX_POOL_LITERALS)
11140 {
11141 lp = lpf->prev;
11142 while (lp && lp->fragP && lp->literal_count >= MAX_POOL_LITERALS)
11143 {
11144 lp = lp->prev;
11145 }
11146 gas_assert (lp);
11147 }
11148
11149 gas_assert (lp && lp->fragP && lp->literal_count < MAX_POOL_LITERALS);
11150 ++lp->literal_count;
11151
11152 /* Convert candidate and add the jump around. */
11153 if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11154 xg_promote_candidate_litpool (lps, lp);
11155
11156 return lp;
11157 }
11158
xtensa_is_init_fini(segT seg)11159 static bfd_boolean xtensa_is_init_fini (segT seg)
11160 {
11161 if (!seg)
11162 return 0;
11163 return strcmp (segment_name (seg), INIT_SECTION_NAME) == 0
11164 || strcmp (segment_name (seg), FINI_SECTION_NAME) == 0;
11165 }
11166
11167 static void
xtensa_assign_litpool_addresses(void)11168 xtensa_assign_litpool_addresses (void)
11169 {
11170 struct litpool_seg *lps;
11171
11172 for (lps = litpool_seg_list.next; lps; lps = lps->next)
11173 {
11174 frchainS *frchP = seg_info (lps->seg)->frchainP;
11175 struct litpool_frag *lpf = lps->frag_list.next;
11176 addressT addr = 0;
11177
11178 if (xtensa_is_init_fini (lps->seg))
11179 continue;
11180
11181 for ( ; frchP; frchP = frchP->frch_next)
11182 {
11183 fragS *fragP;
11184 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
11185 {
11186 if (lpf && fragP == lpf->fragP)
11187 {
11188 gas_assert(fragP->fr_type == rs_machine_dependent &&
11189 (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN ||
11190 fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN));
11191 /* Found a litpool location. */
11192 lpf->addr = addr;
11193 lpf = lpf->next;
11194 }
11195 if (fragP->fr_type == rs_machine_dependent &&
11196 fragP->fr_subtype == RELAX_SLOTS)
11197 {
11198 int slot;
11199 for (slot = 0; slot < MAX_SLOTS; slot++)
11200 {
11201 fragS *litfrag = fragP->tc_frag_data.literal_frags[slot];
11202
11203 if (litfrag
11204 && litfrag->tc_frag_data.is_literal
11205 && !litfrag->tc_frag_data.literal_frag)
11206 {
11207 /* L32R referring .literal or generated as a result
11208 of relaxation. Point its literal to the nearest
11209 litpool preferring non-"candidate" positions to
11210 avoid the jump-around. */
11211
11212 struct litpool_frag *lp;
11213
11214 lp = xg_find_litpool (lps, lpf, addr);
11215 /* Take earliest use of this literal to avoid
11216 forward refs. */
11217 litfrag->tc_frag_data.literal_frag = lp->fragP;
11218 }
11219 }
11220 }
11221 addr += fragP->fr_fix;
11222 if (fragP->fr_type == rs_fill)
11223 addr += fragP->fr_offset;
11224 }
11225 }
11226 }
11227 }
11228
11229 static void
xtensa_move_literals(void)11230 xtensa_move_literals (void)
11231 {
11232 seg_list *segment;
11233 frchainS *frchain_from, *frchain_to;
11234 fragS *search_frag, *next_frag, *literal_pool, *insert_after;
11235 fragS **frag_splice;
11236 emit_state state;
11237 segT dest_seg;
11238 fixS *fix, *next_fix, **fix_splice;
11239 sym_list *lit;
11240 const char *init_name = INIT_SECTION_NAME;
11241 const char *fini_name = FINI_SECTION_NAME;
11242 int init_name_len = strlen(init_name);
11243 int fini_name_len = strlen(fini_name);
11244
11245 mark_literal_frags (literal_head->next);
11246
11247 if (use_literal_section)
11248 return;
11249
11250 /* Assign addresses (rough estimates) to the potential literal pool locations
11251 and create new ones if the gaps are too large. */
11252
11253 xtensa_assign_litpool_addresses ();
11254
11255 /* Walk through the literal segments. */
11256 for (segment = literal_head->next; segment; segment = segment->next)
11257 {
11258 const char *seg_name = segment_name (segment->seg);
11259
11260 /* Keep the literals for .init and .fini in separate sections. */
11261 if ((!memcmp (seg_name, init_name, init_name_len) &&
11262 !strcmp (seg_name + init_name_len, ".literal")) ||
11263 (!memcmp (seg_name, fini_name, fini_name_len) &&
11264 !strcmp (seg_name + fini_name_len, ".literal")))
11265 continue;
11266
11267 frchain_from = seg_info (segment->seg)->frchainP;
11268 search_frag = frchain_from->frch_root;
11269 literal_pool = NULL;
11270 frchain_to = NULL;
11271 frag_splice = &(frchain_from->frch_root);
11272
11273 while (search_frag && !search_frag->tc_frag_data.literal_frag)
11274 {
11275 gas_assert (search_frag->fr_fix == 0
11276 || search_frag->fr_type == rs_align);
11277 search_frag = search_frag->fr_next;
11278 }
11279
11280 if (!search_frag)
11281 continue;
11282
11283 gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype
11284 == RELAX_LITERAL_POOL_BEGIN);
11285 xtensa_switch_section_emit_state (&state, segment->seg, 0);
11286
11287 /* Make sure that all the frags in this series are closed, and
11288 that there is at least one left over of zero-size. This
11289 prevents us from making a segment with an frchain without any
11290 frags in it. */
11291 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11292 xtensa_set_frag_assembly_state (frag_now);
11293 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11294 xtensa_set_frag_assembly_state (frag_now);
11295
11296 while (search_frag != frag_now)
11297 {
11298 next_frag = search_frag->fr_next;
11299 if (search_frag->tc_frag_data.literal_frag)
11300 {
11301 literal_pool = search_frag->tc_frag_data.literal_frag;
11302 gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
11303 frchain_to = literal_pool->tc_frag_data.lit_frchain;
11304 gas_assert (frchain_to);
11305 }
11306
11307 if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0)
11308 {
11309 /* Skip empty fill frags. */
11310 *frag_splice = next_frag;
11311 search_frag = next_frag;
11312 continue;
11313 }
11314
11315 if (search_frag->fr_type == rs_align)
11316 {
11317 /* Skip alignment frags, because the pool as a whole will be
11318 aligned if used, and we don't want to force alignment if the
11319 pool is unused. */
11320 *frag_splice = next_frag;
11321 search_frag = next_frag;
11322 continue;
11323 }
11324
11325 /* First, move the frag out of the literal section and
11326 to the appropriate place. */
11327
11328 /* Insert an alignment frag at start of pool. */
11329 if (literal_pool->fr_next->fr_type == rs_machine_dependent &&
11330 literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END)
11331 {
11332 segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg;
11333 emit_state prev_state;
11334 fragS *prev_frag;
11335 fragS *align_frag;
11336 xtensa_switch_section_emit_state (&prev_state, pool_seg, 0);
11337 prev_frag = frag_now;
11338 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11339 align_frag = frag_now;
11340 frag_align (2, 0, 0);
11341 /* Splice it into the right place. */
11342 prev_frag->fr_next = align_frag->fr_next;
11343 align_frag->fr_next = literal_pool->fr_next;
11344 literal_pool->fr_next = align_frag;
11345 /* Insert after this one. */
11346 literal_pool->tc_frag_data.literal_frag = align_frag;
11347 xtensa_restore_emit_state (&prev_state);
11348 }
11349 insert_after = literal_pool->tc_frag_data.literal_frag;
11350 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
11351 /* Skip align frag. */
11352 if (insert_after->fr_next->fr_type == rs_align)
11353 {
11354 insert_after = insert_after->fr_next;
11355 }
11356
11357 *frag_splice = next_frag;
11358 search_frag->fr_next = insert_after->fr_next;
11359 insert_after->fr_next = search_frag;
11360 search_frag->tc_frag_data.lit_seg = dest_seg;
11361 literal_pool->tc_frag_data.literal_frag = search_frag;
11362
11363 /* Now move any fixups associated with this frag to the
11364 right section. */
11365 fix = frchain_from->fix_root;
11366 fix_splice = &(frchain_from->fix_root);
11367 while (fix)
11368 {
11369 next_fix = fix->fx_next;
11370 if (fix->fx_frag == search_frag)
11371 {
11372 *fix_splice = next_fix;
11373 fix->fx_next = frchain_to->fix_root;
11374 frchain_to->fix_root = fix;
11375 if (frchain_to->fix_tail == NULL)
11376 frchain_to->fix_tail = fix;
11377 }
11378 else
11379 fix_splice = &(fix->fx_next);
11380 fix = next_fix;
11381 }
11382 search_frag = next_frag;
11383 }
11384
11385 if (frchain_from->fix_root != NULL)
11386 {
11387 frchain_from = seg_info (segment->seg)->frchainP;
11388 as_warn (_("fixes not all moved from %s"), segment->seg->name);
11389
11390 gas_assert (frchain_from->fix_root == NULL);
11391 }
11392 frchain_from->fix_tail = NULL;
11393 xtensa_restore_emit_state (&state);
11394 }
11395
11396 /* Now fix up the SEGMENT value for all the literal symbols. */
11397 for (lit = literal_syms; lit; lit = lit->next)
11398 {
11399 symbolS *lit_sym = lit->sym;
11400 segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
11401 if (dseg)
11402 S_SET_SEGMENT (lit_sym, dseg);
11403 }
11404 }
11405
11406
11407 /* Walk over all the frags for segments in a list and mark them as
11408 containing literals. As clunky as this is, we can't rely on frag_var
11409 and frag_variant to get called in all situations. */
11410
11411 static void
mark_literal_frags(seg_list * segment)11412 mark_literal_frags (seg_list *segment)
11413 {
11414 frchainS *frchain_from;
11415 fragS *search_frag;
11416
11417 while (segment)
11418 {
11419 frchain_from = seg_info (segment->seg)->frchainP;
11420 search_frag = frchain_from->frch_root;
11421 while (search_frag)
11422 {
11423 search_frag->tc_frag_data.is_literal = TRUE;
11424 search_frag = search_frag->fr_next;
11425 }
11426 segment = segment->next;
11427 }
11428 }
11429
11430
11431 static void
xtensa_reorder_seg_list(seg_list * head,segT after)11432 xtensa_reorder_seg_list (seg_list *head, segT after)
11433 {
11434 /* Move all of the sections in the section list to come
11435 after "after" in the gnu segment list. */
11436
11437 head = head->next;
11438 while (head)
11439 {
11440 segT literal_section = head->seg;
11441
11442 /* Move the literal section after "after". */
11443 gas_assert (literal_section);
11444 if (literal_section != after)
11445 {
11446 bfd_section_list_remove (stdoutput, literal_section);
11447 bfd_section_list_insert_after (stdoutput, after, literal_section);
11448 }
11449
11450 head = head->next;
11451 }
11452 }
11453
11454
11455 /* Push all the literal segments to the end of the gnu list. */
11456
11457 static void
xtensa_reorder_segments(void)11458 xtensa_reorder_segments (void)
11459 {
11460 segT sec;
11461 segT last_sec = 0;
11462 int old_count = 0;
11463 int new_count = 0;
11464
11465 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11466 {
11467 last_sec = sec;
11468 old_count++;
11469 }
11470
11471 /* Now that we have the last section, push all the literal
11472 sections to the end. */
11473 xtensa_reorder_seg_list (literal_head, last_sec);
11474
11475 /* Now perform the final error check. */
11476 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11477 new_count++;
11478 gas_assert (new_count == old_count);
11479 }
11480
11481
11482 /* Change the emit state (seg, subseg, and frag related stuff) to the
11483 correct location. Return a emit_state which can be passed to
11484 xtensa_restore_emit_state to return to current fragment. */
11485
11486 static void
xtensa_switch_to_literal_fragment(emit_state * result)11487 xtensa_switch_to_literal_fragment (emit_state *result)
11488 {
11489 if (directive_state[directive_absolute_literals])
11490 {
11491 segT lit4_seg = cache_literal_section (TRUE);
11492 xtensa_switch_section_emit_state (result, lit4_seg, 0);
11493 }
11494 else
11495 xtensa_switch_to_non_abs_literal_fragment (result);
11496
11497 /* Do a 4-byte align here. */
11498 frag_align (2, 0, 0);
11499 record_alignment (now_seg, 2);
11500 }
11501
11502
11503 static void
xtensa_switch_to_non_abs_literal_fragment(emit_state * result)11504 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
11505 {
11506 fragS *pool_location = get_literal_pool_location (now_seg);
11507 segT lit_seg;
11508 bfd_boolean is_init_fini = xtensa_is_init_fini (now_seg);
11509
11510 if (pool_location == NULL
11511 && !use_literal_section
11512 && !is_init_fini)
11513 {
11514 if (!auto_litpools)
11515 {
11516 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11517 }
11518 xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
11519 pool_location = get_literal_pool_location (now_seg);
11520 }
11521
11522 lit_seg = cache_literal_section (FALSE);
11523 xtensa_switch_section_emit_state (result, lit_seg, 0);
11524
11525 if (!use_literal_section
11526 && !is_init_fini
11527 && get_literal_pool_location (now_seg) != pool_location)
11528 {
11529 /* Close whatever frag is there. */
11530 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11531 xtensa_set_frag_assembly_state (frag_now);
11532 frag_now->tc_frag_data.literal_frag = pool_location;
11533 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11534 xtensa_set_frag_assembly_state (frag_now);
11535 }
11536 }
11537
11538
11539 /* Call this function before emitting data into the literal section.
11540 This is a helper function for xtensa_switch_to_literal_fragment.
11541 This is similar to a .section new_now_seg subseg. */
11542
11543 static void
xtensa_switch_section_emit_state(emit_state * state,segT new_now_seg,subsegT new_now_subseg)11544 xtensa_switch_section_emit_state (emit_state *state,
11545 segT new_now_seg,
11546 subsegT new_now_subseg)
11547 {
11548 state->name = now_seg->name;
11549 state->now_seg = now_seg;
11550 state->now_subseg = now_subseg;
11551 state->generating_literals = generating_literals;
11552 generating_literals++;
11553 subseg_set (new_now_seg, new_now_subseg);
11554 }
11555
11556
11557 /* Use to restore the emitting into the normal place. */
11558
11559 static void
xtensa_restore_emit_state(emit_state * state)11560 xtensa_restore_emit_state (emit_state *state)
11561 {
11562 generating_literals = state->generating_literals;
11563 subseg_set (state->now_seg, state->now_subseg);
11564 }
11565
11566
11567 /* Predicate function used to look up a section in a particular group. */
11568
11569 static bfd_boolean
match_section_group(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * inf)11570 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
11571 {
11572 const char *gname = inf;
11573 const char *group_name = elf_group_name (sec);
11574
11575 return (group_name == gname
11576 || (group_name != NULL
11577 && gname != NULL
11578 && strcmp (group_name, gname) == 0));
11579 }
11580
11581
11582 /* Get the literal section to be used for the current text section.
11583 The result may be cached in the default_lit_sections structure. */
11584
11585 static segT
cache_literal_section(bfd_boolean use_abs_literals)11586 cache_literal_section (bfd_boolean use_abs_literals)
11587 {
11588 const char *text_name, *group_name = 0;
11589 const char *base_name, *suffix;
11590 char *name;
11591 segT *pcached;
11592 segT seg, current_section;
11593 int current_subsec;
11594 bfd_boolean linkonce = FALSE;
11595
11596 /* Save the current section/subsection. */
11597 current_section = now_seg;
11598 current_subsec = now_subseg;
11599
11600 /* Clear the cached values if they are no longer valid. */
11601 if (now_seg != default_lit_sections.current_text_seg)
11602 {
11603 default_lit_sections.current_text_seg = now_seg;
11604 default_lit_sections.lit_seg = NULL;
11605 default_lit_sections.lit4_seg = NULL;
11606 }
11607
11608 /* Check if the literal section is already cached. */
11609 if (use_abs_literals)
11610 pcached = &default_lit_sections.lit4_seg;
11611 else
11612 pcached = &default_lit_sections.lit_seg;
11613
11614 if (*pcached)
11615 return *pcached;
11616
11617 text_name = default_lit_sections.lit_prefix;
11618 if (! text_name || ! *text_name)
11619 {
11620 text_name = segment_name (current_section);
11621 group_name = elf_group_name (current_section);
11622 linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
11623 }
11624
11625 base_name = use_abs_literals ? ".lit4" : ".literal";
11626 if (group_name)
11627 {
11628 name = concat (base_name, ".", group_name, (char *) NULL);
11629 }
11630 else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
11631 {
11632 suffix = strchr (text_name + linkonce_len, '.');
11633
11634 name = concat (".gnu.linkonce", base_name, suffix ? suffix : "",
11635 (char *) NULL);
11636 linkonce = TRUE;
11637 }
11638 else
11639 {
11640 /* If the section name begins or ends with ".text", then replace
11641 that portion instead of appending an additional suffix. */
11642 size_t len = strlen (text_name);
11643 if (len >= 5
11644 && (strcmp (text_name + len - 5, ".text") == 0
11645 || strncmp (text_name, ".text", 5) == 0))
11646 len -= 5;
11647
11648 name = XNEWVEC (char, len + strlen (base_name) + 1);
11649 if (strncmp (text_name, ".text", 5) == 0)
11650 {
11651 strcpy (name, base_name);
11652 strcat (name, text_name + 5);
11653 }
11654 else
11655 {
11656 strcpy (name, text_name);
11657 strcpy (name + len, base_name);
11658 }
11659 }
11660
11661 /* Canonicalize section names to allow renaming literal sections.
11662 The group name, if any, came from the current text section and
11663 has already been canonicalized. */
11664 name = tc_canonicalize_symbol_name (name);
11665
11666 seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
11667 (void *) group_name);
11668 if (! seg)
11669 {
11670 flagword flags;
11671
11672 seg = subseg_force_new (name, 0);
11673
11674 if (! use_abs_literals)
11675 {
11676 /* Add the newly created literal segment to the list. */
11677 seg_list *n = XNEW (seg_list);
11678 n->seg = seg;
11679 n->next = literal_head->next;
11680 literal_head->next = n;
11681 }
11682
11683 flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
11684 | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
11685 | (use_abs_literals ? SEC_DATA : SEC_CODE));
11686
11687 elf_group_name (seg) = group_name;
11688
11689 bfd_set_section_flags (seg, flags);
11690 bfd_set_section_alignment (seg, 2);
11691 }
11692
11693 *pcached = seg;
11694 subseg_set (current_section, current_subsec);
11695 return seg;
11696 }
11697
11698
11699 /* Property Tables Stuff. */
11700
11701 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11702 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11703 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11704
11705 typedef bfd_boolean (*frag_predicate) (const fragS *);
11706 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
11707
11708 static bfd_boolean get_frag_is_literal (const fragS *);
11709 static void xtensa_create_property_segments
11710 (frag_predicate, frag_predicate, const char *, xt_section_type);
11711 static void xtensa_create_xproperty_segments
11712 (frag_flags_fn, const char *, xt_section_type);
11713 static bfd_boolean exclude_section_from_property_tables (segT);
11714 static bfd_boolean section_has_property (segT, frag_predicate);
11715 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
11716 static void add_xt_block_frags
11717 (segT, xtensa_block_info **, frag_predicate, frag_predicate);
11718 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
11719 static void xtensa_frag_flags_init (frag_flags *);
11720 static void get_frag_property_flags (const fragS *, frag_flags *);
11721 static flagword frag_flags_to_number (const frag_flags *);
11722 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn);
11723
11724 /* Set up property tables after relaxation. */
11725
11726 void
xtensa_post_relax_hook(void)11727 xtensa_post_relax_hook (void)
11728 {
11729 xtensa_move_seg_list_to_beginning (literal_head);
11730
11731 xtensa_find_unmarked_state_frags ();
11732 xtensa_mark_frags_for_org ();
11733 xtensa_mark_difference_of_two_symbols ();
11734
11735 xtensa_create_property_segments (get_frag_is_literal,
11736 NULL,
11737 XTENSA_LIT_SEC_NAME,
11738 xt_literal_sec);
11739 xtensa_create_xproperty_segments (get_frag_property_flags,
11740 XTENSA_PROP_SEC_NAME,
11741 xt_prop_sec);
11742
11743 if (warn_unaligned_branch_targets)
11744 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
11745 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
11746 }
11747
11748
11749 /* This function is only meaningful after xtensa_move_literals. */
11750
11751 static bfd_boolean
get_frag_is_literal(const fragS * fragP)11752 get_frag_is_literal (const fragS *fragP)
11753 {
11754 gas_assert (fragP != NULL);
11755 return fragP->tc_frag_data.is_literal;
11756 }
11757
11758
11759 static void
xtensa_create_property_segments(frag_predicate property_function,frag_predicate end_property_function,const char * section_name_base,xt_section_type sec_type)11760 xtensa_create_property_segments (frag_predicate property_function,
11761 frag_predicate end_property_function,
11762 const char *section_name_base,
11763 xt_section_type sec_type)
11764 {
11765 segT *seclist;
11766
11767 /* Walk over all of the current segments.
11768 Walk over each fragment
11769 For each non-empty fragment,
11770 Build a property record (append where possible). */
11771
11772 for (seclist = &stdoutput->sections;
11773 seclist && *seclist;
11774 seclist = &(*seclist)->next)
11775 {
11776 segT sec = *seclist;
11777
11778 if (exclude_section_from_property_tables (sec))
11779 continue;
11780
11781 if (section_has_property (sec, property_function))
11782 {
11783 segment_info_type *xt_seg_info;
11784 xtensa_block_info **xt_blocks;
11785 segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11786
11787 prop_sec->output_section = prop_sec;
11788 subseg_set (prop_sec, 0);
11789 xt_seg_info = seg_info (prop_sec);
11790 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11791
11792 /* Walk over all of the frchains here and add new sections. */
11793 add_xt_block_frags (sec, xt_blocks, property_function,
11794 end_property_function);
11795 }
11796 }
11797
11798 /* Now we fill them out.... */
11799
11800 for (seclist = &stdoutput->sections;
11801 seclist && *seclist;
11802 seclist = &(*seclist)->next)
11803 {
11804 segment_info_type *seginfo;
11805 xtensa_block_info *block;
11806 segT sec = *seclist;
11807
11808 seginfo = seg_info (sec);
11809 block = seginfo->tc_segment_info_data.blocks[sec_type];
11810
11811 if (block)
11812 {
11813 xtensa_block_info *cur_block;
11814 int num_recs = 0;
11815 bfd_size_type rec_size;
11816
11817 for (cur_block = block; cur_block; cur_block = cur_block->next)
11818 num_recs++;
11819
11820 rec_size = num_recs * 8;
11821 bfd_set_section_size (sec, rec_size);
11822
11823 if (num_recs)
11824 {
11825 char *frag_data;
11826 int i;
11827
11828 subseg_set (sec, 0);
11829 frag_data = frag_more (rec_size);
11830 cur_block = block;
11831 for (i = 0; i < num_recs; i++)
11832 {
11833 fixS *fix;
11834
11835 /* Write the fixup. */
11836 gas_assert (cur_block);
11837 fix = fix_new (frag_now, i * 8, 4,
11838 section_symbol (cur_block->sec),
11839 cur_block->offset,
11840 FALSE, BFD_RELOC_32);
11841 fix->fx_file = "<internal>";
11842 fix->fx_line = 0;
11843
11844 /* Write the length. */
11845 md_number_to_chars (&frag_data[4 + i * 8],
11846 cur_block->size, 4);
11847 cur_block = cur_block->next;
11848 }
11849 frag_wane (frag_now);
11850 frag_new (0);
11851 frag_wane (frag_now);
11852 }
11853 }
11854 }
11855 }
11856
11857
11858 static void
xtensa_create_xproperty_segments(frag_flags_fn flag_fn,const char * section_name_base,xt_section_type sec_type)11859 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
11860 const char *section_name_base,
11861 xt_section_type sec_type)
11862 {
11863 segT *seclist;
11864
11865 /* Walk over all of the current segments.
11866 Walk over each fragment.
11867 For each fragment that has instructions,
11868 build an instruction record (append where possible). */
11869
11870 for (seclist = &stdoutput->sections;
11871 seclist && *seclist;
11872 seclist = &(*seclist)->next)
11873 {
11874 segT sec = *seclist;
11875
11876 if (exclude_section_from_property_tables (sec))
11877 continue;
11878
11879 if (section_has_xproperty (sec, flag_fn))
11880 {
11881 segment_info_type *xt_seg_info;
11882 xtensa_block_info **xt_blocks;
11883 segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11884
11885 prop_sec->output_section = prop_sec;
11886 subseg_set (prop_sec, 0);
11887 xt_seg_info = seg_info (prop_sec);
11888 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11889
11890 /* Walk over all of the frchains here and add new sections. */
11891 add_xt_prop_frags (sec, xt_blocks, flag_fn);
11892 }
11893 }
11894
11895 /* Now we fill them out.... */
11896
11897 for (seclist = &stdoutput->sections;
11898 seclist && *seclist;
11899 seclist = &(*seclist)->next)
11900 {
11901 segment_info_type *seginfo;
11902 xtensa_block_info *block;
11903 segT sec = *seclist;
11904
11905 seginfo = seg_info (sec);
11906 block = seginfo->tc_segment_info_data.blocks[sec_type];
11907
11908 if (block)
11909 {
11910 xtensa_block_info *cur_block;
11911 int num_recs = 0;
11912 bfd_size_type rec_size;
11913
11914 for (cur_block = block; cur_block; cur_block = cur_block->next)
11915 num_recs++;
11916
11917 rec_size = num_recs * (8 + 4);
11918 bfd_set_section_size (sec, rec_size);
11919 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11920
11921 if (num_recs)
11922 {
11923 char *frag_data;
11924 int i;
11925
11926 subseg_set (sec, 0);
11927 frag_data = frag_more (rec_size);
11928 cur_block = block;
11929 for (i = 0; i < num_recs; i++)
11930 {
11931 fixS *fix;
11932
11933 /* Write the fixup. */
11934 gas_assert (cur_block);
11935 fix = fix_new (frag_now, i * 12, 4,
11936 section_symbol (cur_block->sec),
11937 cur_block->offset,
11938 FALSE, BFD_RELOC_32);
11939 fix->fx_file = "<internal>";
11940 fix->fx_line = 0;
11941
11942 /* Write the length. */
11943 md_number_to_chars (&frag_data[4 + i * 12],
11944 cur_block->size, 4);
11945 md_number_to_chars (&frag_data[8 + i * 12],
11946 frag_flags_to_number (&cur_block->flags),
11947 sizeof (flagword));
11948 cur_block = cur_block->next;
11949 }
11950 frag_wane (frag_now);
11951 frag_new (0);
11952 frag_wane (frag_now);
11953 }
11954 }
11955 }
11956 }
11957
11958
11959 static bfd_boolean
exclude_section_from_property_tables(segT sec)11960 exclude_section_from_property_tables (segT sec)
11961 {
11962 flagword flags = bfd_section_flags (sec);
11963
11964 /* Sections that don't contribute to the memory footprint are excluded. */
11965 if ((flags & SEC_DEBUGGING)
11966 || !(flags & SEC_ALLOC)
11967 || (flags & SEC_MERGE))
11968 return TRUE;
11969
11970 /* Linker cie and fde optimizations mess up property entries for
11971 eh_frame sections, but there is nothing inside them relevant to
11972 property tables anyway. */
11973 if (strcmp (sec->name, ".eh_frame") == 0)
11974 return TRUE;
11975
11976 return FALSE;
11977 }
11978
11979
11980 static bfd_boolean
section_has_property(segT sec,frag_predicate property_function)11981 section_has_property (segT sec, frag_predicate property_function)
11982 {
11983 segment_info_type *seginfo = seg_info (sec);
11984 fragS *fragP;
11985
11986 if (seginfo && seginfo->frchainP)
11987 {
11988 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
11989 {
11990 if (property_function (fragP)
11991 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
11992 return TRUE;
11993 }
11994 }
11995 return FALSE;
11996 }
11997
11998
11999 static bfd_boolean
section_has_xproperty(segT sec,frag_flags_fn property_function)12000 section_has_xproperty (segT sec, frag_flags_fn property_function)
12001 {
12002 segment_info_type *seginfo = seg_info (sec);
12003 fragS *fragP;
12004
12005 if (seginfo && seginfo->frchainP)
12006 {
12007 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
12008 {
12009 frag_flags prop_flags;
12010 property_function (fragP, &prop_flags);
12011 if (!xtensa_frag_flags_is_empty (&prop_flags))
12012 return TRUE;
12013 }
12014 }
12015 return FALSE;
12016 }
12017
12018
12019 /* Two types of block sections exist right now: literal and insns. */
12020
12021 static void
add_xt_block_frags(segT sec,xtensa_block_info ** xt_block,frag_predicate property_function,frag_predicate end_property_function)12022 add_xt_block_frags (segT sec,
12023 xtensa_block_info **xt_block,
12024 frag_predicate property_function,
12025 frag_predicate end_property_function)
12026 {
12027 fragS *fragP;
12028
12029 /* Build it if needed. */
12030 while (*xt_block != NULL)
12031 xt_block = &(*xt_block)->next;
12032 /* We are either at NULL at the beginning or at the end. */
12033
12034 /* Walk through the frags. */
12035 if (seg_info (sec)->frchainP)
12036 {
12037 for (fragP = seg_info (sec)->frchainP->frch_root;
12038 fragP;
12039 fragP = fragP->fr_next)
12040 {
12041 if (property_function (fragP)
12042 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
12043 {
12044 if (*xt_block != NULL)
12045 {
12046 if ((*xt_block)->offset + (*xt_block)->size
12047 == fragP->fr_address)
12048 (*xt_block)->size += fragP->fr_fix;
12049 else
12050 xt_block = &((*xt_block)->next);
12051 }
12052 if (*xt_block == NULL)
12053 {
12054 xtensa_block_info *new_block = XNEW (xtensa_block_info);
12055 new_block->sec = sec;
12056 new_block->offset = fragP->fr_address;
12057 new_block->size = fragP->fr_fix;
12058 new_block->next = NULL;
12059 xtensa_frag_flags_init (&new_block->flags);
12060 *xt_block = new_block;
12061 }
12062 if (end_property_function
12063 && end_property_function (fragP))
12064 {
12065 xt_block = &((*xt_block)->next);
12066 }
12067 }
12068 }
12069 }
12070 }
12071
12072
12073 /* Break the encapsulation of add_xt_prop_frags here. */
12074
12075 static bfd_boolean
xtensa_frag_flags_is_empty(const frag_flags * prop_flags)12076 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
12077 {
12078 if (prop_flags->is_literal
12079 || prop_flags->is_insn
12080 || prop_flags->is_data
12081 || prop_flags->is_unreachable)
12082 return FALSE;
12083 return TRUE;
12084 }
12085
12086
12087 static void
xtensa_frag_flags_init(frag_flags * prop_flags)12088 xtensa_frag_flags_init (frag_flags *prop_flags)
12089 {
12090 memset (prop_flags, 0, sizeof (frag_flags));
12091 }
12092
12093
12094 static void
get_frag_property_flags(const fragS * fragP,frag_flags * prop_flags)12095 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
12096 {
12097 xtensa_frag_flags_init (prop_flags);
12098 if (fragP->tc_frag_data.is_literal)
12099 prop_flags->is_literal = TRUE;
12100 if (fragP->tc_frag_data.is_specific_opcode
12101 || fragP->tc_frag_data.is_no_transform)
12102 {
12103 prop_flags->is_no_transform = TRUE;
12104 if (xtensa_frag_flags_is_empty (prop_flags))
12105 prop_flags->is_data = TRUE;
12106 }
12107 if (fragP->tc_frag_data.is_unreachable)
12108 prop_flags->is_unreachable = TRUE;
12109 else if (fragP->tc_frag_data.is_insn)
12110 {
12111 prop_flags->is_insn = TRUE;
12112 if (fragP->tc_frag_data.is_loop_target)
12113 prop_flags->insn.is_loop_target = TRUE;
12114 if (fragP->tc_frag_data.is_branch_target)
12115 prop_flags->insn.is_branch_target = TRUE;
12116 if (fragP->tc_frag_data.is_no_density)
12117 prop_flags->insn.is_no_density = TRUE;
12118 if (fragP->tc_frag_data.use_absolute_literals)
12119 prop_flags->insn.is_abslit = TRUE;
12120 }
12121 if (fragP->tc_frag_data.is_align)
12122 {
12123 prop_flags->is_align = TRUE;
12124 prop_flags->alignment = fragP->tc_frag_data.alignment;
12125 if (xtensa_frag_flags_is_empty (prop_flags))
12126 prop_flags->is_data = TRUE;
12127 }
12128 }
12129
12130
12131 static flagword
frag_flags_to_number(const frag_flags * prop_flags)12132 frag_flags_to_number (const frag_flags *prop_flags)
12133 {
12134 flagword num = 0;
12135 if (prop_flags->is_literal)
12136 num |= XTENSA_PROP_LITERAL;
12137 if (prop_flags->is_insn)
12138 num |= XTENSA_PROP_INSN;
12139 if (prop_flags->is_data)
12140 num |= XTENSA_PROP_DATA;
12141 if (prop_flags->is_unreachable)
12142 num |= XTENSA_PROP_UNREACHABLE;
12143 if (prop_flags->insn.is_loop_target)
12144 num |= XTENSA_PROP_INSN_LOOP_TARGET;
12145 if (prop_flags->insn.is_branch_target)
12146 {
12147 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
12148 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
12149 }
12150
12151 if (prop_flags->insn.is_no_density)
12152 num |= XTENSA_PROP_INSN_NO_DENSITY;
12153 if (prop_flags->is_no_transform)
12154 num |= XTENSA_PROP_NO_TRANSFORM;
12155 if (prop_flags->insn.is_no_reorder)
12156 num |= XTENSA_PROP_INSN_NO_REORDER;
12157 if (prop_flags->insn.is_abslit)
12158 num |= XTENSA_PROP_INSN_ABSLIT;
12159
12160 if (prop_flags->is_align)
12161 {
12162 num |= XTENSA_PROP_ALIGN;
12163 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
12164 }
12165
12166 return num;
12167 }
12168
12169
12170 static bfd_boolean
xtensa_frag_flags_combinable(const frag_flags * prop_flags_1,const frag_flags * prop_flags_2)12171 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
12172 const frag_flags *prop_flags_2)
12173 {
12174 /* Cannot combine with an end marker. */
12175
12176 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
12177 return FALSE;
12178 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
12179 return FALSE;
12180 if (prop_flags_1->is_data != prop_flags_2->is_data)
12181 return FALSE;
12182
12183 if (prop_flags_1->is_insn)
12184 {
12185 /* Properties of the beginning of the frag. */
12186 if (prop_flags_2->insn.is_loop_target)
12187 return FALSE;
12188 if (prop_flags_2->insn.is_branch_target)
12189 return FALSE;
12190 if (prop_flags_1->insn.is_no_density !=
12191 prop_flags_2->insn.is_no_density)
12192 return FALSE;
12193 if (prop_flags_1->is_no_transform !=
12194 prop_flags_2->is_no_transform)
12195 return FALSE;
12196 if (prop_flags_1->insn.is_no_reorder !=
12197 prop_flags_2->insn.is_no_reorder)
12198 return FALSE;
12199 if (prop_flags_1->insn.is_abslit !=
12200 prop_flags_2->insn.is_abslit)
12201 return FALSE;
12202 }
12203
12204 if (prop_flags_1->is_align)
12205 return FALSE;
12206
12207 return TRUE;
12208 }
12209
12210
12211 static bfd_vma
xt_block_aligned_size(const xtensa_block_info * xt_block)12212 xt_block_aligned_size (const xtensa_block_info *xt_block)
12213 {
12214 bfd_vma end_addr;
12215 unsigned align_bits;
12216
12217 if (!xt_block->flags.is_align)
12218 return xt_block->size;
12219
12220 end_addr = xt_block->offset + xt_block->size;
12221 align_bits = xt_block->flags.alignment;
12222 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
12223 return end_addr - xt_block->offset;
12224 }
12225
12226
12227 static bfd_boolean
xtensa_xt_block_combine(xtensa_block_info * xt_block,const xtensa_block_info * xt_block_2)12228 xtensa_xt_block_combine (xtensa_block_info *xt_block,
12229 const xtensa_block_info *xt_block_2)
12230 {
12231 if (xt_block->sec != xt_block_2->sec)
12232 return FALSE;
12233 if (xt_block->offset + xt_block_aligned_size (xt_block)
12234 != xt_block_2->offset)
12235 return FALSE;
12236
12237 if (xt_block_2->size == 0
12238 && (!xt_block_2->flags.is_unreachable
12239 || xt_block->flags.is_unreachable))
12240 {
12241 if (xt_block_2->flags.is_align
12242 && xt_block->flags.is_align)
12243 {
12244 /* Nothing needed. */
12245 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
12246 return TRUE;
12247 }
12248 else
12249 {
12250 if (xt_block_2->flags.is_align)
12251 {
12252 /* Push alignment to previous entry. */
12253 xt_block->flags.is_align = xt_block_2->flags.is_align;
12254 xt_block->flags.alignment = xt_block_2->flags.alignment;
12255 }
12256 return TRUE;
12257 }
12258 }
12259 if (!xtensa_frag_flags_combinable (&xt_block->flags,
12260 &xt_block_2->flags))
12261 return FALSE;
12262
12263 xt_block->size += xt_block_2->size;
12264
12265 if (xt_block_2->flags.is_align)
12266 {
12267 xt_block->flags.is_align = TRUE;
12268 xt_block->flags.alignment = xt_block_2->flags.alignment;
12269 }
12270
12271 return TRUE;
12272 }
12273
12274
12275 static void
add_xt_prop_frags(segT sec,xtensa_block_info ** xt_block,frag_flags_fn property_function)12276 add_xt_prop_frags (segT sec,
12277 xtensa_block_info **xt_block,
12278 frag_flags_fn property_function)
12279 {
12280 fragS *fragP;
12281
12282 /* Build it if needed. */
12283 while (*xt_block != NULL)
12284 {
12285 xt_block = &(*xt_block)->next;
12286 }
12287 /* We are either at NULL at the beginning or at the end. */
12288
12289 /* Walk through the frags. */
12290 if (seg_info (sec)->frchainP)
12291 {
12292 for (fragP = seg_info (sec)->frchainP->frch_root; fragP;
12293 fragP = fragP->fr_next)
12294 {
12295 xtensa_block_info tmp_block;
12296 tmp_block.sec = sec;
12297 tmp_block.offset = fragP->fr_address;
12298 tmp_block.size = fragP->fr_fix;
12299 tmp_block.next = NULL;
12300 property_function (fragP, &tmp_block.flags);
12301
12302 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
12303 /* && fragP->fr_fix != 0) */
12304 {
12305 if ((*xt_block) == NULL
12306 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
12307 {
12308 xtensa_block_info *new_block;
12309 if ((*xt_block) != NULL)
12310 xt_block = &(*xt_block)->next;
12311 new_block = XNEW (xtensa_block_info);
12312 *new_block = tmp_block;
12313 *xt_block = new_block;
12314 }
12315 }
12316 }
12317 }
12318 }
12319
12320
12321 /* op_placement_info_table */
12322
12323 /* op_placement_info makes it easier to determine which
12324 ops can go in which slots. */
12325
12326 static void
init_op_placement_info_table(void)12327 init_op_placement_info_table (void)
12328 {
12329 xtensa_isa isa = xtensa_default_isa;
12330 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
12331 xtensa_opcode opcode;
12332 xtensa_format fmt;
12333 int slot;
12334 int num_opcodes = xtensa_isa_num_opcodes (isa);
12335
12336 op_placement_table = XNEWVEC (op_placement_info, num_opcodes);
12337 gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
12338
12339 for (opcode = 0; opcode < num_opcodes; opcode++)
12340 {
12341 op_placement_info *opi = &op_placement_table[opcode];
12342 /* FIXME: Make tinsn allocation dynamic. */
12343 if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS)
12344 as_fatal (_("too many operands in instruction"));
12345 opi->narrowest = XTENSA_UNDEFINED;
12346 opi->narrowest_size = 0x7F;
12347 opi->narrowest_slot = 0;
12348 opi->formats = 0;
12349 opi->num_formats = 0;
12350 opi->issuef = 0;
12351 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
12352 {
12353 opi->slots[fmt] = 0;
12354 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
12355 {
12356 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
12357 {
12358 int fmt_length = xtensa_format_length (isa, fmt);
12359 opi->issuef++;
12360 set_bit (fmt, opi->formats);
12361 set_bit (slot, opi->slots[fmt]);
12362 if (fmt_length < opi->narrowest_size
12363 || (fmt_length == opi->narrowest_size
12364 && (xtensa_format_num_slots (isa, fmt)
12365 < xtensa_format_num_slots (isa,
12366 opi->narrowest))))
12367 {
12368 opi->narrowest = fmt;
12369 opi->narrowest_size = fmt_length;
12370 opi->narrowest_slot = slot;
12371 }
12372 }
12373 }
12374 if (opi->formats)
12375 opi->num_formats++;
12376 }
12377 }
12378 xtensa_insnbuf_free (isa, ibuf);
12379 }
12380
12381
12382 bfd_boolean
opcode_fits_format_slot(xtensa_opcode opcode,xtensa_format fmt,int slot)12383 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
12384 {
12385 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
12386 }
12387
12388
12389 /* If the opcode is available in a single slot format, return its size. */
12390
12391 static int
xg_get_single_size(xtensa_opcode opcode)12392 xg_get_single_size (xtensa_opcode opcode)
12393 {
12394 return op_placement_table[opcode].narrowest_size;
12395 }
12396
12397
12398 static xtensa_format
xg_get_single_format(xtensa_opcode opcode)12399 xg_get_single_format (xtensa_opcode opcode)
12400 {
12401 return op_placement_table[opcode].narrowest;
12402 }
12403
12404
12405 static int
xg_get_single_slot(xtensa_opcode opcode)12406 xg_get_single_slot (xtensa_opcode opcode)
12407 {
12408 return op_placement_table[opcode].narrowest_slot;
12409 }
12410
12411
12412 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12413
12414 void
istack_init(IStack * stack)12415 istack_init (IStack *stack)
12416 {
12417 stack->ninsn = 0;
12418 }
12419
12420
12421 bfd_boolean
istack_empty(IStack * stack)12422 istack_empty (IStack *stack)
12423 {
12424 return (stack->ninsn == 0);
12425 }
12426
12427
12428 bfd_boolean
istack_full(IStack * stack)12429 istack_full (IStack *stack)
12430 {
12431 return (stack->ninsn == MAX_ISTACK);
12432 }
12433
12434
12435 /* Return a pointer to the top IStack entry.
12436 It is an error to call this if istack_empty () is TRUE. */
12437
12438 TInsn *
istack_top(IStack * stack)12439 istack_top (IStack *stack)
12440 {
12441 int rec = stack->ninsn - 1;
12442 gas_assert (!istack_empty (stack));
12443 return &stack->insn[rec];
12444 }
12445
12446
12447 /* Add a new TInsn to an IStack.
12448 It is an error to call this if istack_full () is TRUE. */
12449
12450 void
istack_push(IStack * stack,TInsn * insn)12451 istack_push (IStack *stack, TInsn *insn)
12452 {
12453 int rec = stack->ninsn;
12454 gas_assert (!istack_full (stack));
12455 stack->insn[rec] = *insn;
12456 stack->ninsn++;
12457 }
12458
12459
12460 /* Clear space for the next TInsn on the IStack and return a pointer
12461 to it. It is an error to call this if istack_full () is TRUE. */
12462
12463 TInsn *
istack_push_space(IStack * stack)12464 istack_push_space (IStack *stack)
12465 {
12466 int rec = stack->ninsn;
12467 TInsn *insn;
12468 gas_assert (!istack_full (stack));
12469 insn = &stack->insn[rec];
12470 tinsn_init (insn);
12471 stack->ninsn++;
12472 return insn;
12473 }
12474
12475
12476 /* Remove the last pushed instruction. It is an error to call this if
12477 istack_empty () returns TRUE. */
12478
12479 void
istack_pop(IStack * stack)12480 istack_pop (IStack *stack)
12481 {
12482 int rec = stack->ninsn - 1;
12483 gas_assert (!istack_empty (stack));
12484 stack->ninsn--;
12485 tinsn_init (&stack->insn[rec]);
12486 }
12487
12488
12489 /* TInsn functions. */
12490
12491 void
tinsn_init(TInsn * dst)12492 tinsn_init (TInsn *dst)
12493 {
12494 memset (dst, 0, sizeof (TInsn));
12495 }
12496
12497
12498 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12499
12500 static bfd_boolean
tinsn_has_symbolic_operands(const TInsn * insn)12501 tinsn_has_symbolic_operands (const TInsn *insn)
12502 {
12503 int i;
12504 int n = insn->ntok;
12505
12506 gas_assert (insn->insn_type == ITYPE_INSN);
12507
12508 for (i = 0; i < n; ++i)
12509 {
12510 switch (insn->tok[i].X_op)
12511 {
12512 case O_register:
12513 case O_constant:
12514 break;
12515 default:
12516 return TRUE;
12517 }
12518 }
12519 return FALSE;
12520 }
12521
12522
12523 bfd_boolean
tinsn_has_invalid_symbolic_operands(const TInsn * insn)12524 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
12525 {
12526 xtensa_isa isa = xtensa_default_isa;
12527 int i;
12528 int n = insn->ntok;
12529
12530 gas_assert (insn->insn_type == ITYPE_INSN);
12531
12532 for (i = 0; i < n; ++i)
12533 {
12534 switch (insn->tok[i].X_op)
12535 {
12536 case O_register:
12537 case O_constant:
12538 break;
12539 case O_big:
12540 case O_illegal:
12541 case O_absent:
12542 /* Errors for these types are caught later. */
12543 break;
12544 case O_hi16:
12545 case O_lo16:
12546 default:
12547 /* Symbolic immediates are only allowed on the last immediate
12548 operand. At this time, CONST16 is the only opcode where we
12549 support non-PC-relative relocations. */
12550 if (i != get_relaxable_immed (insn->opcode)
12551 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
12552 && insn->opcode != xtensa_const16_opcode))
12553 {
12554 as_bad (_("invalid symbolic operand"));
12555 return TRUE;
12556 }
12557 }
12558 }
12559 return FALSE;
12560 }
12561
12562
12563 /* For assembly code with complex expressions (e.g. subtraction),
12564 we have to build them in the literal pool so that
12565 their results are calculated correctly after relaxation.
12566 The relaxation only handles expressions that
12567 boil down to SYMBOL + OFFSET. */
12568
12569 static bfd_boolean
tinsn_has_complex_operands(const TInsn * insn)12570 tinsn_has_complex_operands (const TInsn *insn)
12571 {
12572 int i;
12573 int n = insn->ntok;
12574 gas_assert (insn->insn_type == ITYPE_INSN);
12575 for (i = 0; i < n; ++i)
12576 {
12577 switch (insn->tok[i].X_op)
12578 {
12579 case O_register:
12580 case O_constant:
12581 case O_symbol:
12582 case O_lo16:
12583 case O_hi16:
12584 break;
12585 default:
12586 return TRUE;
12587 }
12588 }
12589 return FALSE;
12590 }
12591
12592
12593 /* Encode a TInsn opcode and its constant operands into slotbuf.
12594 Return TRUE if there is a symbol in the immediate field. This
12595 function assumes that:
12596 1) The number of operands are correct.
12597 2) The insn_type is ITYPE_INSN.
12598 3) The opcode can be encoded in the specified format and slot.
12599 4) Operands are either O_constant or O_symbol, and all constants fit. */
12600
12601 static bfd_boolean
tinsn_to_slotbuf(xtensa_format fmt,int slot,TInsn * tinsn,xtensa_insnbuf slotbuf)12602 tinsn_to_slotbuf (xtensa_format fmt,
12603 int slot,
12604 TInsn *tinsn,
12605 xtensa_insnbuf slotbuf)
12606 {
12607 xtensa_isa isa = xtensa_default_isa;
12608 xtensa_opcode opcode = tinsn->opcode;
12609 bfd_boolean has_fixup = FALSE;
12610 int noperands = xtensa_opcode_num_operands (isa, opcode);
12611 int i;
12612
12613 gas_assert (tinsn->insn_type == ITYPE_INSN);
12614 if (noperands != tinsn->ntok)
12615 as_fatal (_("operand number mismatch"));
12616
12617 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
12618 {
12619 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12620 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
12621 return FALSE;
12622 }
12623
12624 for (i = 0; i < noperands; i++)
12625 {
12626 expressionS *exp = &tinsn->tok[i];
12627 int rc;
12628 unsigned line;
12629 const char *file_name;
12630 uint32 opnd_value;
12631
12632 switch (exp->X_op)
12633 {
12634 case O_register:
12635 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12636 break;
12637 /* The register number has already been checked in
12638 expression_maybe_register, so we don't need to check here. */
12639 opnd_value = exp->X_add_number;
12640 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
12641 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
12642 opnd_value);
12643 if (rc != 0)
12644 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
12645 break;
12646
12647 case O_constant:
12648 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12649 break;
12650 file_name = as_where (&line);
12651 /* It is a constant and we called this function
12652 then we have to try to fit it. */
12653 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
12654 exp->X_add_number, file_name, line);
12655 break;
12656
12657 default:
12658 has_fixup = TRUE;
12659 break;
12660 }
12661 }
12662
12663 return has_fixup;
12664 }
12665
12666
12667 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12668 into a multi-slot instruction, fill the other slots with NOPs.
12669 Return TRUE if there is a symbol in the immediate field. See also the
12670 assumptions listed for tinsn_to_slotbuf. */
12671
12672 static bfd_boolean
tinsn_to_insnbuf(TInsn * tinsn,xtensa_insnbuf insnbuf)12673 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
12674 {
12675 static xtensa_insnbuf slotbuf = 0;
12676 static vliw_insn vinsn;
12677 xtensa_isa isa = xtensa_default_isa;
12678 bfd_boolean has_fixup = FALSE;
12679 int i;
12680
12681 if (!slotbuf)
12682 {
12683 slotbuf = xtensa_insnbuf_alloc (isa);
12684 xg_init_vinsn (&vinsn);
12685 }
12686
12687 xg_clear_vinsn (&vinsn);
12688
12689 bundle_tinsn (tinsn, &vinsn);
12690
12691 xtensa_format_encode (isa, vinsn.format, insnbuf);
12692
12693 for (i = 0; i < vinsn.num_slots; i++)
12694 {
12695 /* Only one slot may have a fix-up because the rest contains NOPs. */
12696 has_fixup |=
12697 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
12698 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
12699 }
12700
12701 return has_fixup;
12702 }
12703
12704
12705 /* Check the instruction arguments. Return TRUE on failure. */
12706
12707 static bfd_boolean
tinsn_check_arguments(const TInsn * insn)12708 tinsn_check_arguments (const TInsn *insn)
12709 {
12710 xtensa_isa isa = xtensa_default_isa;
12711 xtensa_opcode opcode = insn->opcode;
12712 xtensa_regfile t1_regfile, t2_regfile;
12713 int t1_reg, t2_reg;
12714 int t1_base_reg, t1_last_reg;
12715 int t2_base_reg, t2_last_reg;
12716 char t1_inout, t2_inout;
12717 int i, j;
12718
12719 if (opcode == XTENSA_UNDEFINED)
12720 {
12721 as_bad (_("invalid opcode"));
12722 return TRUE;
12723 }
12724
12725 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
12726 {
12727 as_bad (_("too few operands"));
12728 return TRUE;
12729 }
12730
12731 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
12732 {
12733 as_bad (_("too many operands"));
12734 return TRUE;
12735 }
12736
12737 /* Check registers. */
12738 for (j = 0; j < insn->ntok; j++)
12739 {
12740 if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
12741 continue;
12742
12743 t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
12744 t2_base_reg = insn->tok[j].X_add_number;
12745 t2_last_reg
12746 = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
12747
12748 for (i = 0; i < insn->ntok; i++)
12749 {
12750 if (i == j)
12751 continue;
12752
12753 if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
12754 continue;
12755
12756 t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
12757
12758 if (t1_regfile != t2_regfile)
12759 continue;
12760
12761 t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
12762 t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
12763
12764 t1_base_reg = insn->tok[i].X_add_number;
12765 t1_last_reg = (t1_base_reg
12766 + xtensa_operand_num_regs (isa, insn->opcode, i));
12767
12768 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
12769 {
12770 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
12771 {
12772 if (t1_reg != t2_reg)
12773 continue;
12774
12775 if (t1_inout != 'i' && t2_inout != 'i')
12776 {
12777 as_bad (_("multiple writes to the same register"));
12778 return TRUE;
12779 }
12780 }
12781 }
12782 }
12783 }
12784 return FALSE;
12785 }
12786
12787
12788 /* Load an instruction from its encoded form. */
12789
12790 static void
tinsn_from_chars(TInsn * tinsn,char * f,int slot)12791 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
12792 {
12793 vliw_insn vinsn;
12794
12795 xg_init_vinsn (&vinsn);
12796 vinsn_from_chars (&vinsn, f);
12797
12798 *tinsn = vinsn.slots[slot];
12799 xg_free_vinsn (&vinsn);
12800 }
12801
12802
12803 static void
tinsn_from_insnbuf(TInsn * tinsn,xtensa_insnbuf slotbuf,xtensa_format fmt,int slot)12804 tinsn_from_insnbuf (TInsn *tinsn,
12805 xtensa_insnbuf slotbuf,
12806 xtensa_format fmt,
12807 int slot)
12808 {
12809 int i;
12810 xtensa_isa isa = xtensa_default_isa;
12811
12812 /* Find the immed. */
12813 tinsn_init (tinsn);
12814 tinsn->insn_type = ITYPE_INSN;
12815 tinsn->is_specific_opcode = FALSE; /* must not be specific */
12816 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
12817 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
12818 for (i = 0; i < tinsn->ntok; i++)
12819 {
12820 set_expr_const (&tinsn->tok[i],
12821 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
12822 tinsn->opcode, i));
12823 }
12824 }
12825
12826
12827 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12828
12829 static void
tinsn_immed_from_frag(TInsn * tinsn,fragS * fragP,int slot)12830 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
12831 {
12832 xtensa_opcode opcode = tinsn->opcode;
12833 int opnum;
12834
12835 if (fragP->tc_frag_data.slot_symbols[slot])
12836 {
12837 opnum = get_relaxable_immed (opcode);
12838 gas_assert (opnum >= 0);
12839 set_expr_symbol_offset (&tinsn->tok[opnum],
12840 fragP->tc_frag_data.slot_symbols[slot],
12841 fragP->tc_frag_data.slot_offsets[slot]);
12842 }
12843 tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot];
12844 }
12845
12846
12847 static int
get_num_stack_text_bytes(IStack * istack)12848 get_num_stack_text_bytes (IStack *istack)
12849 {
12850 int i;
12851 int text_bytes = 0;
12852
12853 for (i = 0; i < istack->ninsn; i++)
12854 {
12855 TInsn *tinsn = &istack->insn[i];
12856 if (tinsn->insn_type == ITYPE_INSN)
12857 text_bytes += xg_get_single_size (tinsn->opcode);
12858 }
12859 return text_bytes;
12860 }
12861
12862
12863 static int
get_num_stack_literal_bytes(IStack * istack)12864 get_num_stack_literal_bytes (IStack *istack)
12865 {
12866 int i;
12867 int lit_bytes = 0;
12868
12869 for (i = 0; i < istack->ninsn; i++)
12870 {
12871 TInsn *tinsn = &istack->insn[i];
12872 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
12873 lit_bytes += 4;
12874 }
12875 return lit_bytes;
12876 }
12877
12878
12879 /* vliw_insn functions. */
12880
12881 static void
xg_init_vinsn(vliw_insn * v)12882 xg_init_vinsn (vliw_insn *v)
12883 {
12884 int i;
12885 xtensa_isa isa = xtensa_default_isa;
12886
12887 xg_clear_vinsn (v);
12888
12889 v->insnbuf = xtensa_insnbuf_alloc (isa);
12890 if (v->insnbuf == NULL)
12891 as_fatal (_("out of memory"));
12892
12893 for (i = 0; i < config_max_slots; i++)
12894 {
12895 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
12896 if (v->slotbuf[i] == NULL)
12897 as_fatal (_("out of memory"));
12898 }
12899 }
12900
12901
12902 static void
xg_clear_vinsn(vliw_insn * v)12903 xg_clear_vinsn (vliw_insn *v)
12904 {
12905 int i;
12906
12907 memset (v, 0, offsetof (vliw_insn, slots)
12908 + sizeof(TInsn) * config_max_slots);
12909
12910 v->format = XTENSA_UNDEFINED;
12911 v->num_slots = 0;
12912 v->inside_bundle = FALSE;
12913
12914 if (xt_saved_debug_type != DEBUG_NONE)
12915 debug_type = xt_saved_debug_type;
12916
12917 for (i = 0; i < config_max_slots; i++)
12918 v->slots[i].opcode = XTENSA_UNDEFINED;
12919 }
12920
12921
12922 static void
xg_copy_vinsn(vliw_insn * dst,vliw_insn * src)12923 xg_copy_vinsn (vliw_insn *dst, vliw_insn *src)
12924 {
12925 memcpy (dst, src,
12926 offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn));
12927 dst->insnbuf = src->insnbuf;
12928 memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf));
12929 }
12930
12931
12932 static bfd_boolean
vinsn_has_specific_opcodes(vliw_insn * v)12933 vinsn_has_specific_opcodes (vliw_insn *v)
12934 {
12935 int i;
12936
12937 for (i = 0; i < v->num_slots; i++)
12938 {
12939 if (v->slots[i].is_specific_opcode)
12940 return TRUE;
12941 }
12942 return FALSE;
12943 }
12944
12945
12946 static void
xg_free_vinsn(vliw_insn * v)12947 xg_free_vinsn (vliw_insn *v)
12948 {
12949 int i;
12950 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
12951 for (i = 0; i < config_max_slots; i++)
12952 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
12953 }
12954
12955
12956 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12957 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12958
12959 static bfd_boolean
vinsn_to_insnbuf(vliw_insn * vinsn,char * frag_offset,fragS * fragP,bfd_boolean record_fixup)12960 vinsn_to_insnbuf (vliw_insn *vinsn,
12961 char *frag_offset,
12962 fragS *fragP,
12963 bfd_boolean record_fixup)
12964 {
12965 xtensa_isa isa = xtensa_default_isa;
12966 xtensa_format fmt = vinsn->format;
12967 xtensa_insnbuf insnbuf = vinsn->insnbuf;
12968 int slot;
12969 bfd_boolean has_fixup = FALSE;
12970
12971 xtensa_format_encode (isa, fmt, insnbuf);
12972
12973 for (slot = 0; slot < vinsn->num_slots; slot++)
12974 {
12975 TInsn *tinsn = &vinsn->slots[slot];
12976 expressionS *extra_arg = &tinsn->extra_arg;
12977 bfd_boolean tinsn_has_fixup =
12978 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
12979 vinsn->slotbuf[slot]);
12980
12981 xtensa_format_set_slot (isa, fmt, slot,
12982 insnbuf, vinsn->slotbuf[slot]);
12983 if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register)
12984 {
12985 if (vinsn->num_slots != 1)
12986 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12987 else if (record_fixup)
12988 /* Instructions that generate TLS relocations should always be
12989 relaxed in the front-end. If "record_fixup" is set, then this
12990 function is being called during back-end relaxation, so flag
12991 the unexpected behavior as an error. */
12992 as_bad (_("unexpected TLS relocation"));
12993 else
12994 fix_new (fragP, frag_offset - fragP->fr_literal,
12995 xtensa_format_length (isa, fmt),
12996 extra_arg->X_add_symbol, extra_arg->X_add_number,
12997 FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE));
12998 }
12999 if (tinsn_has_fixup)
13000 {
13001 int i;
13002 xtensa_opcode opcode = tinsn->opcode;
13003 int noperands = xtensa_opcode_num_operands (isa, opcode);
13004 has_fixup = TRUE;
13005
13006 for (i = 0; i < noperands; i++)
13007 {
13008 expressionS* exp = &tinsn->tok[i];
13009 switch (exp->X_op)
13010 {
13011 case O_symbol:
13012 case O_lo16:
13013 case O_hi16:
13014 if (get_relaxable_immed (opcode) == i)
13015 {
13016 /* Add a fix record for the instruction, except if this
13017 function is being called prior to relaxation, i.e.,
13018 if record_fixup is false, and the instruction might
13019 be relaxed later. */
13020 if (record_fixup
13021 || tinsn->is_specific_opcode
13022 || !xg_is_relaxable_insn (tinsn, 0))
13023 {
13024 xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP,
13025 frag_offset - fragP->fr_literal);
13026 }
13027 else
13028 {
13029 if (exp->X_op != O_symbol)
13030 as_bad (_("invalid operand"));
13031 tinsn->symbol = exp->X_add_symbol;
13032 tinsn->offset = exp->X_add_number;
13033 }
13034 }
13035 else
13036 as_bad (_("symbolic operand not allowed"));
13037 break;
13038
13039 case O_constant:
13040 case O_register:
13041 break;
13042
13043 default:
13044 as_bad (_("expression too complex"));
13045 break;
13046 }
13047 }
13048 }
13049 }
13050
13051 return has_fixup;
13052 }
13053
13054
13055 static void
vinsn_from_chars(vliw_insn * vinsn,char * f)13056 vinsn_from_chars (vliw_insn *vinsn, char *f)
13057 {
13058 static xtensa_insnbuf insnbuf = NULL;
13059 static xtensa_insnbuf slotbuf = NULL;
13060 int i;
13061 xtensa_format fmt;
13062 xtensa_isa isa = xtensa_default_isa;
13063
13064 if (!insnbuf)
13065 {
13066 insnbuf = xtensa_insnbuf_alloc (isa);
13067 slotbuf = xtensa_insnbuf_alloc (isa);
13068 }
13069
13070 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
13071 fmt = xtensa_format_decode (isa, insnbuf);
13072 if (fmt == XTENSA_UNDEFINED)
13073 as_fatal (_("cannot decode instruction format"));
13074 vinsn->format = fmt;
13075 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
13076
13077 for (i = 0; i < vinsn->num_slots; i++)
13078 {
13079 TInsn *tinsn = &vinsn->slots[i];
13080 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
13081 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
13082 }
13083 }
13084
13085
13086 /* Expression utilities. */
13087
13088 /* Return TRUE if the expression is an integer constant. */
13089
13090 bfd_boolean
expr_is_const(const expressionS * s)13091 expr_is_const (const expressionS *s)
13092 {
13093 return (s->X_op == O_constant);
13094 }
13095
13096
13097 /* Get the expression constant.
13098 Calling this is illegal if expr_is_const () returns TRUE. */
13099
13100 offsetT
get_expr_const(const expressionS * s)13101 get_expr_const (const expressionS *s)
13102 {
13103 gas_assert (expr_is_const (s));
13104 return s->X_add_number;
13105 }
13106
13107
13108 /* Set the expression to a constant value. */
13109
13110 void
set_expr_const(expressionS * s,offsetT val)13111 set_expr_const (expressionS *s, offsetT val)
13112 {
13113 s->X_op = O_constant;
13114 s->X_add_number = val;
13115 s->X_add_symbol = NULL;
13116 s->X_op_symbol = NULL;
13117 }
13118
13119
13120 bfd_boolean
expr_is_register(const expressionS * s)13121 expr_is_register (const expressionS *s)
13122 {
13123 return (s->X_op == O_register);
13124 }
13125
13126
13127 /* Get the expression constant.
13128 Calling this is illegal if expr_is_const () returns TRUE. */
13129
13130 offsetT
get_expr_register(const expressionS * s)13131 get_expr_register (const expressionS *s)
13132 {
13133 gas_assert (expr_is_register (s));
13134 return s->X_add_number;
13135 }
13136
13137
13138 /* Set the expression to a symbol + constant offset. */
13139
13140 void
set_expr_symbol_offset(expressionS * s,symbolS * sym,offsetT offset)13141 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
13142 {
13143 s->X_op = O_symbol;
13144 s->X_add_symbol = sym;
13145 s->X_op_symbol = NULL; /* unused */
13146 s->X_add_number = offset;
13147 }
13148
13149
13150 /* Return TRUE if the two expressions are equal. */
13151
13152 bfd_boolean
expr_is_equal(expressionS * s1,expressionS * s2)13153 expr_is_equal (expressionS *s1, expressionS *s2)
13154 {
13155 if (s1->X_op != s2->X_op)
13156 return FALSE;
13157 if (s1->X_add_symbol != s2->X_add_symbol)
13158 return FALSE;
13159 if (s1->X_op_symbol != s2->X_op_symbol)
13160 return FALSE;
13161 if (s1->X_add_number != s2->X_add_number)
13162 return FALSE;
13163 return TRUE;
13164 }
13165
13166
13167 static void
copy_expr(expressionS * dst,const expressionS * src)13168 copy_expr (expressionS *dst, const expressionS *src)
13169 {
13170 memcpy (dst, src, sizeof (expressionS));
13171 }
13172
13173
13174 /* Support for the "--rename-section" option. */
13175
13176 struct rename_section_struct
13177 {
13178 const char *old_name;
13179 char *new_name;
13180 struct rename_section_struct *next;
13181 };
13182
13183 static struct rename_section_struct *section_rename;
13184
13185
13186 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13187 entries to the section_rename list. Note: Specifying multiple
13188 renamings separated by colons is not documented and is retained only
13189 for backward compatibility. */
13190
13191 static void
build_section_rename(const char * arg)13192 build_section_rename (const char *arg)
13193 {
13194 struct rename_section_struct *r;
13195 char *this_arg = NULL;
13196 char *next_arg = NULL;
13197
13198 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
13199 {
13200 char *old_name, *new_name;
13201
13202 if (this_arg)
13203 {
13204 next_arg = strchr (this_arg, ':');
13205 if (next_arg)
13206 {
13207 *next_arg = '\0';
13208 next_arg++;
13209 }
13210 }
13211
13212 old_name = this_arg;
13213 new_name = strchr (this_arg, '=');
13214
13215 if (*old_name == '\0')
13216 {
13217 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13218 continue;
13219 }
13220 if (!new_name || new_name[1] == '\0')
13221 {
13222 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13223 old_name);
13224 continue;
13225 }
13226 *new_name = '\0';
13227 new_name++;
13228
13229 /* Check for invalid section renaming. */
13230 for (r = section_rename; r != NULL; r = r->next)
13231 {
13232 if (strcmp (r->old_name, old_name) == 0)
13233 as_bad (_("section %s renamed multiple times"), old_name);
13234 if (strcmp (r->new_name, new_name) == 0)
13235 as_bad (_("multiple sections remapped to output section %s"),
13236 new_name);
13237 }
13238
13239 /* Now add it. */
13240 r = XNEW (struct rename_section_struct);
13241 r->old_name = xstrdup (old_name);
13242 r->new_name = xstrdup (new_name);
13243 r->next = section_rename;
13244 section_rename = r;
13245 }
13246 }
13247
13248
13249 char *
xtensa_section_rename(const char * name)13250 xtensa_section_rename (const char *name)
13251 {
13252 struct rename_section_struct *r = section_rename;
13253
13254 for (r = section_rename; r != NULL; r = r->next)
13255 {
13256 if (strcmp (r->old_name, name) == 0)
13257 return r->new_name;
13258 }
13259
13260 return (char *) name;
13261 }
13262