1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. 2 Copyright (C) 1994-2020 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #ifndef GCC_ARC_H 21 #define GCC_ARC_H 22 23 #include <stdbool.h> 24 25 /* Things to do: 26 27 - incscc, decscc? 28 29 */ 30 31 #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0) 32 #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1) 33 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2) 34 #define SYMBOL_FLAG_CMEM (SYMBOL_FLAG_MACH_DEP << 3) 35 36 #ifndef TARGET_CPU_DEFAULT 37 #define TARGET_CPU_DEFAULT PROCESSOR_arc700 38 #endif 39 40 /* Check if this symbol has a long_call attribute in its declaration */ 41 #define SYMBOL_REF_LONG_CALL_P(X) \ 42 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 43 44 /* Check if this symbol has a medium_call attribute in its declaration */ 45 #define SYMBOL_REF_MEDIUM_CALL_P(X) \ 46 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0) 47 48 /* Check if this symbol has a short_call attribute in its declaration */ 49 #define SYMBOL_REF_SHORT_CALL_P(X) \ 50 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0) 51 52 /* Names to predefine in the preprocessor for this target machine. */ 53 #define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile) 54 55 /* Macros enabled by specific command line option. FIXME: to be 56 deprecatd. */ 57 #define CPP_SPEC "\ 58 %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \ 59 %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \ 60 %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \ 61 %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \ 62 %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \ 63 %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \ 64 %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \ 65 %(subtarget_cpp_spec)" 66 67 #undef CC1_SPEC 68 #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \ 69 %{EB:-mbig-endian} %{EL:-mlittle-endian} \ 70 %{G*} \ 71 " 72 extern const char *arc_cpu_to_as (int argc, const char **argv); 73 74 #define EXTRA_SPEC_FUNCTIONS \ 75 { "cpu_to_as", arc_cpu_to_as }, 76 77 /* This macro defines names of additional specifications to put in the specs 78 that can be used in various specifications like CC1_SPEC. Its definition 79 is an initializer with a subgrouping for each command option. 80 81 Each subgrouping contains a string constant, that defines the 82 specification name, and a string constant that used by the GCC driver 83 program. 84 85 Do not define this macro if it does not need to do anything. */ 86 #define EXTRA_SPECS \ 87 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 88 SUBTARGET_EXTRA_SPECS 89 90 #ifndef SUBTARGET_EXTRA_SPECS 91 #define SUBTARGET_EXTRA_SPECS 92 #endif 93 94 #ifndef SUBTARGET_CPP_SPEC 95 #define SUBTARGET_CPP_SPEC "" 96 #endif 97 98 #undef ASM_SPEC 99 #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ 100 "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \ 101 "%{mfpu=fpuda*:-mfpuda} %{mcode-density}" 102 103 #define OPTION_DEFAULT_SPECS \ 104 {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" } 105 106 #ifndef DRIVER_ENDIAN_SELF_SPECS 107 #define DRIVER_ENDIAN_SELF_SPECS "" 108 #endif 109 110 #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \ 111 "%{mARC600|mA6: -mcpu=arc600 %<mARC600 %<mA6 %<mARC600}" \ 112 "%{mARC601: -mcpu=arc601 %<mARC601}" \ 113 "%{mARC700|mA7: -mcpu=arc700 %<mARC700 %<mA7}" \ 114 "%{mEA: -mea %<mEA}" 115 116 /* Run-time compilation parameters selecting different hardware subsets. */ 117 118 #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET) 119 120 #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET) 121 #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \ 122 || TARGET_FP_DP_AX) 123 124 #define SUBTARGET_SWITCHES 125 126 /* Instruction set characteristics. 127 These are internal macros, set by the appropriate -m option. */ 128 129 /* Non-zero means the cpu supports norm instruction. This flag is set by 130 default for A7, and only for pre A7 cores when -mnorm is given. */ 131 #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS) 132 /* Indicate if an optimized floating point emulation library is available. */ 133 #define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK) 134 135 /* Non-zero means the cpu supports swap instruction. This flag is set by 136 default for A7, and only for pre A7 cores when -mswap is given. */ 137 #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET) 138 139 /* Provide some macros for size / scheduling features of the ARC700, so 140 that we can pick & choose features if we get a new cpu family member. */ 141 142 /* Should we try to unalign likely taken branches without a delay slot. */ 143 #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size) 144 145 /* Should we add padding before a return insn to avoid mispredict? */ 146 #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size) 147 148 /* For an anulled-true delay slot insn for a delayed branch, should we only 149 use conditional execution? */ 150 #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2) 151 152 #define TARGET_ARC600 ((arc_selected_cpu->arch_info->arch_id \ 153 == BASE_ARCH_6xx) \ 154 && (TARGET_BARREL_SHIFTER)) 155 #define TARGET_ARC601 ((arc_selected_cpu->arch_info->arch_id \ 156 == BASE_ARCH_6xx) \ 157 && (!TARGET_BARREL_SHIFTER)) 158 #define TARGET_ARC700 (arc_selected_cpu->arch_info->arch_id \ 159 == BASE_ARCH_700) 160 /* An NPS400 is a specialisation of ARC700, so it is correct for NPS400 161 TARGET_ARC700 is true, and TARGET_NPS400 is true. */ 162 #define TARGET_NPS400 ((arc_selected_cpu->arch_info->arch_id \ 163 == BASE_ARCH_700) \ 164 && (arc_selected_cpu->processor \ 165 == PROCESSOR_nps400)) 166 #define TARGET_EM (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_em) 167 #define TARGET_HS (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_hs) 168 #define TARGET_V2 (TARGET_EM || TARGET_HS) 169 170 #ifndef UNALIGNED_ACCESS_DEFAULT 171 #define UNALIGNED_ACCESS_DEFAULT 0 172 #endif 173 174 #ifndef TARGET_NPS_BITOPS_DEFAULT 175 #define TARGET_NPS_BITOPS_DEFAULT 0 176 #endif 177 178 #ifndef TARGET_NPS_CMEM_DEFAULT 179 #define TARGET_NPS_CMEM_DEFAULT 0 180 #endif 181 182 /* Enable the RRQ instruction alternatives. */ 183 184 #define TARGET_RRQ_CLASS TARGET_NPS_BITOPS 185 186 /* Target machine storage layout. */ 187 188 /* We want zero_extract to mean the same 189 no matter what the byte endianness is. */ 190 #define BITS_BIG_ENDIAN 0 191 192 /* Define this if most significant byte of a word is the lowest numbered. */ 193 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) 194 195 /* Define this if most significant word of a multiword number is the lowest 196 numbered. */ 197 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) 198 199 /* Width in bits of a "word", which is the contents of a machine register. 200 Note that this is not necessarily the width of data type `int'; 201 if using 16-bit ints on a 68000, this would still be 32. 202 But on a machine with 16-bit registers, this would be 16. */ 203 #define BITS_PER_WORD 32 204 205 /* Width of a word, in units (bytes). */ 206 #define UNITS_PER_WORD 4 207 208 /* Define this macro if it is advisable to hold scalars in registers 209 in a wider mode than that declared by the program. In such cases, 210 the value is constrained to be within the bounds of the declared 211 type, but kept valid in the wider mode. The signedness of the 212 extension may differ from that of the type. */ 213 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 214 if (GET_MODE_CLASS (MODE) == MODE_INT \ 215 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 216 { \ 217 (MODE) = SImode; \ 218 } 219 220 /* Width in bits of a pointer. 221 See also the macro `Pmode' defined below. */ 222 #define POINTER_SIZE 32 223 224 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 225 #define PARM_BOUNDARY 32 226 227 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 228 /* TOCHECK: Changed from 64 to 32 */ 229 #define STACK_BOUNDARY 32 230 231 /* ALIGN FRAMES on word boundaries. */ 232 #define ARC_STACK_ALIGN(LOC) \ 233 (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT) 234 235 /* Allocation boundary (in *bits*) for the code of a function. */ 236 #define FUNCTION_BOUNDARY 32 237 238 /* Alignment of field after `int : 0' in a structure. */ 239 #define EMPTY_FIELD_BOUNDARY 32 240 241 /* Every structure's size must be a multiple of this. */ 242 #define STRUCTURE_SIZE_BOUNDARY 8 243 244 /* A bitfield declared as `int' forces `int' alignment for the struct. */ 245 #define PCC_BITFIELD_TYPE_MATTERS 1 246 247 /* An expression for the alignment of a structure field FIELD if the 248 alignment computed in the usual way (including applying of 249 `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the 250 alignment) is COMPUTED. It overrides alignment only if the field 251 alignment has not been set by the `__attribute__ ((aligned (N)))' 252 construct. 253 */ 254 255 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 256 (TYPE_MODE (strip_array_types (TYPE)) == DFmode \ 257 ? MIN ((COMPUTED), 32) : (COMPUTED)) 258 259 260 261 /* No data type wants to be aligned rounder than this. */ 262 /* This is bigger than currently necessary for the ARC. If 8 byte floats are 263 ever added it's not clear whether they'll need such alignment or not. For 264 now we assume they will. We can always relax it if necessary but the 265 reverse isn't true. */ 266 /* TOCHECK: Changed from 64 to 32 */ 267 #define BIGGEST_ALIGNMENT 32 268 269 /* The best alignment to use in cases where we have a choice. */ 270 #define FASTEST_ALIGNMENT 32 271 272 /* Make arrays of chars word-aligned for the same reasons. */ 273 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 274 (TREE_CODE (TYPE) == ARRAY_TYPE \ 275 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 276 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 277 278 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 279 (TREE_CODE (TYPE) == ARRAY_TYPE \ 280 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 281 && arc_size_opt_level < 3 \ 282 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 283 284 /* Set this nonzero if move instructions will actually fail to work 285 when given unaligned data. */ 286 /* On the ARC the lower address bits are masked to 0 as necessary. The chip 287 won't croak when given an unaligned address, but the insn will still fail 288 to produce the correct result. */ 289 #define STRICT_ALIGNMENT (!unaligned_access) 290 291 /* Layout of source language data types. */ 292 293 #define SHORT_TYPE_SIZE 16 294 #define INT_TYPE_SIZE 32 295 #define LONG_TYPE_SIZE 32 296 #define LONG_LONG_TYPE_SIZE 64 297 #define FLOAT_TYPE_SIZE 32 298 #define DOUBLE_TYPE_SIZE 64 299 #define LONG_DOUBLE_TYPE_SIZE 64 300 301 /* Define this as 1 if `char' should by default be signed; else as 0. */ 302 #define DEFAULT_SIGNED_CHAR 0 303 304 #undef SIZE_TYPE 305 #define SIZE_TYPE "unsigned int" 306 307 #undef PTRDIFF_TYPE 308 #define PTRDIFF_TYPE "int" 309 310 #undef WCHAR_TYPE 311 #define WCHAR_TYPE "int" 312 313 #undef WCHAR_TYPE_SIZE 314 #define WCHAR_TYPE_SIZE 32 315 316 /* Standard register usage. */ 317 318 /* Number of actual hardware registers. 319 The hardware registers are assigned numbers for the compiler 320 from 0 to just below FIRST_PSEUDO_REGISTER. 321 All registers that the compiler knows about must be given numbers, 322 even those that are not normally considered general registers. 323 324 Registers 61, 62, and 63 are not really registers and we needn't treat 325 them as such. We still need a register for the condition code and 326 argument pointer. */ 327 328 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs 329 r144, r145 = ARG_POINTER, FRAME_POINTER 330 and therefore the pseudo registers start from r146. */ 331 #define FIRST_PSEUDO_REGISTER 146 332 333 /* 1 for registers that have pervasive standard uses 334 and are not available for the register allocator. 335 336 0-28 - general purpose registers 337 29 - ilink1 (interrupt link register) 338 30 - ilink2 (interrupt link register) 339 31 - blink (branch link register) 340 32-59 - reserved for extensions 341 60 - LP_COUNT 342 61 - condition code 343 62 - argument pointer 344 63 - program counter 345 346 FWIW, this is how the 61-63 encodings are used by the hardware: 347 61 - reserved 348 62 - long immediate data indicator 349 63 - PCL (program counter aligned to 32 bit, read-only) 350 351 The general purpose registers are further broken down into: 352 353 0-7 - arguments/results 354 8-12 - call used (r11 - static chain pointer) 355 13-25 - call saved 356 26 - global pointer 357 27 - frame pointer 358 28 - stack pointer 359 29 - ilink1 360 30 - ilink2 361 31 - return address register 362 363 By default, the extension registers are not available. */ 364 /* Present implementations only have VR0-VR23 only. */ 365 #define FIXED_REGISTERS \ 366 { 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0, 0, 0, \ 368 0, 0, 0, 0, 0, 0, 0, 0, \ 369 0, 0, 1, 0, 1, 1, 1, 1, \ 370 \ 371 1, 1, 1, 1, 1, 1, 1, 1, \ 372 0, 0, 0, 0, 1, 1, 1, 1, \ 373 1, 1, 1, 1, 1, 1, 1, 1, \ 374 1, 1, 1, 1, 1, 1, 1, 1, \ 375 \ 376 0, 0, 0, 0, 0, 0, 0, 0, \ 377 0, 0, 0, 0, 0, 0, 0, 0, \ 378 0, 0, 0, 0, 0, 0, 0, 0, \ 379 1, 1, 1, 1, 1, 1, 1, 1, \ 380 \ 381 1, 1, 1, 1, 1, 1, 1, 1, \ 382 1, 1, 1, 1, 1, 1, 1, 1, \ 383 1, 1, 1, 1, 1, 1, 1, 1, \ 384 1, 1, 1, 1, 1, 1, 1, 1, \ 385 \ 386 0, 0, 0, 0, 0, 0, 0, 0, \ 387 0, 0, 0, 0, 0, 0, 0, 0, \ 388 1, 1} 389 390 /* 1 for registers not available across function calls. 391 These must include the FIXED_REGISTERS and also any 392 registers that can be used without being saved. 393 The latter must include the registers where values are returned 394 and the register where structure-value addresses are passed. 395 Aside from that, you can include as many other registers as you like. */ 396 #define CALL_USED_REGISTERS \ 397 { \ 398 1, 1, 1, 1, 1, 1, 1, 1, \ 399 1, 1, 1, 1, 1, 0, 0, 0, \ 400 0, 0, 0, 0, 0, 0, 0, 0, \ 401 0, 0, 1, 0, 1, 1, 1, 1, \ 402 \ 403 1, 1, 1, 1, 1, 1, 1, 1, \ 404 1, 1, 1, 1, 1, 1, 1, 1, \ 405 1, 1, 1, 1, 1, 1, 1, 1, \ 406 1, 1, 1, 1, 1, 1, 1, 1, \ 407 \ 408 0, 0, 0, 0, 0, 0, 0, 0, \ 409 0, 0, 0, 0, 0, 0, 0, 0, \ 410 0, 0, 0, 0, 0, 0, 0, 0, \ 411 1, 1, 1, 1, 1, 1, 1, 1, \ 412 \ 413 1, 1, 1, 1, 1, 1, 1, 1, \ 414 1, 1, 1, 1, 1, 1, 1, 1, \ 415 1, 1, 1, 1, 1, 1, 1, 1, \ 416 1, 1, 1, 1, 1, 1, 1, 1, \ 417 \ 418 0, 0, 0, 0, 0, 0, 0, 0, \ 419 0, 0, 0, 0, 0, 0, 0, 0, \ 420 1, 1} 421 422 /* If defined, an initializer for a vector of integers, containing the 423 numbers of hard registers in the order in which GCC should 424 prefer to use them (from most preferred to least). */ 425 #define REG_ALLOC_ORDER \ 426 { \ 427 /* General registers. */ \ 428 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \ 429 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \ 430 /* Extension core registers. */ \ 431 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 432 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ 433 /* VR regs. */ \ 434 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 435 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 436 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ 437 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \ 438 124, 125, 126, 127, \ 439 /* DMA registers. */ \ 440 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \ 441 142, 143, \ 442 /* Register not used for general use. */ \ 443 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 444 SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \ 445 } 446 447 /* Use different register alloc ordering for Thumb. */ 448 #define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order () 449 450 /* Tell IRA to use the order we define rather than messing it up with its 451 own cost calculations. */ 452 #define HONOR_REG_ALLOC_ORDER 1 453 454 /* Internal macros to classify a register number as to whether it's a 455 general purpose register for compact insns (r0-r3,r12-r15), or 456 stack pointer (r28). */ 457 458 #define COMPACT_GP_REG_P(REGNO) \ 459 (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15)) 460 #define SP_REG_P(REGNO) ((REGNO) == 28) 461 462 463 464 /* Register classes and constants. */ 465 466 /* Define the classes of registers for register constraints in the 467 machine description. Also define ranges of constants. 468 469 One of the classes must always be named ALL_REGS and include all hard regs. 470 If there is more than one class, another class must be named NO_REGS 471 and contain no registers. 472 473 The name GENERAL_REGS must be the name of a class (or an alias for 474 another name such as ALL_REGS). This is the class of registers 475 that is allowed by "g" or "r" in a register constraint. 476 Also, registers outside this class are allocated only when 477 instructions express preferences for them. 478 479 The classes must be numbered in nondecreasing order; that is, 480 a larger-numbered class must never be contained completely 481 in a smaller-numbered class. 482 483 For any two classes, it is very desirable that there be another 484 class that represents their union. 485 486 It is important that any condition codes have class NO_REGS. 487 See `register_operand'. */ 488 489 enum reg_class 490 { 491 NO_REGS, 492 R0_REGS, /* 'x' */ 493 R0R1_CD_REGS, /* 'Rsd' */ 494 R0R3_CD_REGS, /* 'Rcd' */ 495 ARCOMPACT16_REGS, /* 'q' */ 496 SIBCALL_REGS, /* "Rsc" */ 497 AC16_H_REGS, /* 'h' */ 498 DOUBLE_REGS, /* 'D' */ 499 GENERAL_REGS, /* 'r' */ 500 SIMD_VR_REGS, /* 'v' */ 501 SIMD_DMA_CONFIG_REGS, /* 'd' */ 502 ALL_REGS, 503 LIM_REG_CLASSES 504 }; 505 506 #define N_REG_CLASSES (int) LIM_REG_CLASSES 507 508 /* Give names of register classes as strings for dump file. */ 509 #define REG_CLASS_NAMES \ 510 { \ 511 "NO_REGS", \ 512 "R0_REGS", \ 513 "R0R1_CD_REGS", \ 514 "R0R3_CD_REGS", \ 515 "ARCOMPACT16_REGS", \ 516 "SIBCALL_REGS", \ 517 "AC16_H_REGS", \ 518 "DOUBLE_REGS", \ 519 "GENERAL_REGS", \ 520 "SIMD_VR_REGS", \ 521 "SIMD_DMA_CONFIG_REGS", \ 522 "ALL_REGS" \ 523 } 524 525 /* Define which registers fit in which classes. 526 This is an initializer for a vector of HARD_REG_SET 527 of length N_REG_CLASSES. */ 528 529 #define REG_CLASS_CONTENTS \ 530 { \ 531 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* NO_REGS. */\ 532 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x'. */ \ 533 {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd'. */ \ 534 {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd'. */ \ 535 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q'. */ \ 536 {0x00001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsc'. */ \ 537 {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h'. */ \ 538 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D'. */ \ 539 {0xffffffff, 0x8fffffff, 0x00000000, 0x00000000, 0x00030000}, /* 'r'. */ \ 540 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'v'. */ \ 541 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'd'. */ \ 542 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* ALL_REGS. */\ 543 } 544 545 /* Local macros to mark the first and last regs of different classes. */ 546 #define ARC_FIRST_SIMD_VR_REG 64 547 #define ARC_LAST_SIMD_VR_REG 127 548 549 #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128 550 #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128 551 #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136 552 #define ARC_LAST_SIMD_DMA_CONFIG_REG 143 553 554 /* ARCv2 double-register accumulator. */ 555 #define ACC_REG_FIRST 58 556 #define ACC_REG_LAST 59 557 #define ACCL_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST + 1 : ACC_REG_FIRST) 558 #define ACCH_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST : ACC_REG_FIRST + 1) 559 560 /* The same information, inverted: 561 Return the class number of the smallest class containing 562 reg number REGNO. This could be a conditional expression 563 or could index an array. */ 564 565 extern enum reg_class arc_regno_reg_class[]; 566 567 #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO]) 568 569 /* The class value for valid index registers. An index register is 570 one used in an address where its value is either multiplied by 571 a scale factor or added to another register (as well as added to a 572 displacement). */ 573 574 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS) 575 576 /* The class value for valid base registers. A base register is one used in 577 an address which is the register value plus a displacement. */ 578 579 #define BASE_REG_CLASS GENERAL_REGS 580 581 /* These assume that REGNO is a hard or pseudo reg number. 582 They give nonzero only if REGNO is a hard reg of the suitable class 583 or a pseudo reg currently allocated to a suitable hard reg. 584 Since they use reg_renumber, they are safe only once reg_renumber 585 has been allocated, which happens in local-alloc.c. */ 586 #define REGNO_OK_FOR_BASE_P(REGNO) \ 587 ((REGNO) < 29 \ 588 || ((REGNO) == ARG_POINTER_REGNUM) \ 589 || ((REGNO) == FRAME_POINTER_REGNUM) \ 590 || ((REGNO) == PCL_REG) \ 591 || ((unsigned) reg_renumber[REGNO] < 29) \ 592 || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ 593 || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ 594 || (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG)) 595 596 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) 597 598 /* Given an rtx X being reloaded into a reg required to be 599 in class CLASS, return the class of reg to actually use. 600 In general this is just CLASS; but on some machines 601 in some cases it is preferable to use a more restrictive class. */ 602 603 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 604 arc_preferred_reload_class((X), (CLASS)) 605 606 extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class); 607 608 /* Return the maximum number of consecutive registers 609 needed to represent mode MODE in a register of class CLASS. */ 610 611 #define CLASS_MAX_NREGS(CLASS, MODE) \ 612 (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \ 613 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 614 615 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200) 616 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \ 617 ((unsigned) (((X) >> (SHIFT)) + 0x100) \ 618 < 0x200 - ((unsigned) (OFFSET) >> (SHIFT))) 619 #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000) 620 #define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000) 621 #define LARGE_INT(X) \ 622 (((X) < 0) \ 623 ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ 624 : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff) 625 #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8) 626 #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20) 627 #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40) 628 #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80) 629 #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100) 630 #define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800) 631 #define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000) 632 #define IS_ONE(X) ((X) == 1) 633 #define IS_ZERO(X) ((X) == 0) 634 635 /* Stack layout and stack pointer usage. */ 636 637 /* Define this macro if pushing a word onto the stack moves the stack 638 pointer to a smaller address. */ 639 #define STACK_GROWS_DOWNWARD 1 640 641 /* Define this if the nominal address of the stack frame 642 is at the high-address end of the local variables; 643 that is, each additional local variable allocated 644 goes at a more negative offset in the frame. */ 645 #define FRAME_GROWS_DOWNWARD 1 646 647 /* Offset from the stack pointer register to the first location at which 648 outgoing arguments are placed. */ 649 #define STACK_POINTER_OFFSET (0) 650 651 /* Offset of first parameter from the argument pointer register value. */ 652 #define FIRST_PARM_OFFSET(FNDECL) (0) 653 654 /* A C expression whose value is RTL representing the address in a 655 stack frame where the pointer to the caller's frame is stored. 656 Assume that FRAMEADDR is an RTL expression for the address of the 657 stack frame itself. 658 659 If you don't define this macro, the default is to return the value 660 of FRAMEADDR--that is, the stack frame address is also the address 661 of the stack word that points to the previous frame. */ 662 /* ??? unfinished */ 663 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/ 664 665 /* A C expression whose value is RTL representing the value of the 666 return address for the frame COUNT steps up from the current frame. 667 FRAMEADDR is the frame pointer of the COUNT frame, or the frame 668 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' 669 is defined. */ 670 /* The current return address is in r31. The return address of anything 671 farther back is at [%fp,4]. */ 672 673 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 674 arc_return_addr_rtx(COUNT,FRAME) 675 676 /* Register to use for pushing function arguments. */ 677 #define STACK_POINTER_REGNUM 28 678 679 /* Base register for access to local variables of the function. */ 680 #define FRAME_POINTER_REGNUM 145 681 #define HARD_FRAME_POINTER_REGNUM 27 682 683 /* Base register for access to arguments of the function. This register 684 will be eliminated into either fp or sp. */ 685 #define ARG_POINTER_REGNUM 144 686 687 #define RETURN_ADDR_REGNUM 31 688 689 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */ 690 /* Register in which static-chain is passed to a function. This must 691 not be a register used by the prologue. */ 692 #define STATIC_CHAIN_REGNUM 11 693 694 /* Function argument passing. */ 695 696 /* If defined, the maximum amount of space required for outgoing 697 arguments will be computed and placed into the variable 698 `crtl->outgoing_args_size'. No space will be pushed 699 onto the stack for each call; instead, the function prologue should 700 increase the stack frame size by this amount. */ 701 #define ACCUMULATE_OUTGOING_ARGS 1 702 703 /* Define a data type for recording info about an argument list 704 during the scan of that argument list. This data type should 705 hold all necessary information about the function itself 706 and about the args processed so far, enough to enable macros 707 such as FUNCTION_ARG to determine where the next arg should go. */ 708 #define CUMULATIVE_ARGS int 709 710 /* Initialize a variable CUM of type CUMULATIVE_ARGS 711 for a call to a function whose data type is FNTYPE. 712 For a library call, FNTYPE is 0. */ 713 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \ 714 ((CUM) = 0) 715 716 /* The number of registers used for parameter passing. Local to this file. */ 717 #define MAX_ARC_PARM_REGS (TARGET_RF16 ? 4 : 8) 718 719 /* 1 if N is a possible register number for function argument passing. */ 720 #define FUNCTION_ARG_REGNO_P(N) \ 721 ((unsigned) (N) < MAX_ARC_PARM_REGS) 722 723 /* The ROUND_ADVANCE* macros are local to this file. */ 724 /* Round SIZE up to a word boundary. */ 725 #define ROUND_ADVANCE(SIZE) \ 726 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 727 728 /* Round arg MODE/TYPE up to the next word boundary. */ 729 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 730 ((MODE) == BLKmode \ 731 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 732 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) 733 734 #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY 735 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 736 /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT. 737 ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */ 738 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \ 739 ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\ 740 + 1) 741 742 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 743 a reg. This includes arguments that have to be passed by reference as the 744 pointer to them is passed in a reg if one is available (and that is what 745 we're given). 746 When passing arguments NAMED is always 1. When receiving arguments NAMED 747 is 1 for each argument except the last in a stdarg/varargs function. In 748 a stdarg function we want to treat the last named arg as named. In a 749 varargs function we want to treat the last named arg (which is 750 `__builtin_va_alist') as unnamed. 751 This macro is only used in this file. */ 752 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 753 ((CUM) < MAX_ARC_PARM_REGS) 754 755 756 /* Function results. */ 757 758 /* Define how to find the value returned by a library function 759 assuming the value has mode MODE. */ 760 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 761 762 /* 1 if N is a possible register number for a function value 763 as seen by the caller. */ 764 /* ??? What about r1 in DI/DF values. */ 765 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 766 767 /* Tell GCC to use RETURN_IN_MEMORY. */ 768 #define DEFAULT_PCC_STRUCT_RETURN 0 769 770 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 771 the stack pointer does not matter. The value is tested only in 772 functions that have frame pointers. 773 No definition is equivalent to always zero. */ 774 #define EXIT_IGNORE_STACK 0 775 776 #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO)) 777 778 #define EH_USES(REGNO) arc_eh_uses((REGNO)) 779 780 /* Definitions for register eliminations. 781 782 This is an array of structures. Each structure initializes one pair 783 of eliminable registers. The "from" register number is given first, 784 followed by "to". Eliminations of the same "from" register are listed 785 in order of preference. 786 787 We have two registers that can be eliminated on the ARC. First, the 788 argument pointer register can always be eliminated in favor of the stack 789 pointer register or frame pointer register. Secondly, the frame pointer 790 register can often be eliminated in favor of the stack pointer register. 791 */ 792 793 #define ELIMINABLE_REGS \ 794 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 795 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 796 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 797 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 798 799 /* Define the offset between two registers, one to be eliminated, and the other 800 its replacement, at the start of a routine. */ 801 extern int arc_initial_elimination_offset(int from, int to); 802 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 803 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO)) 804 805 /* All the work done in PROFILE_HOOK, but still required. */ 806 #undef FUNCTION_PROFILER 807 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 808 809 #define NO_PROFILE_COUNTERS 1 810 811 /* Trampolines. */ 812 813 /* Length in units of the trampoline for entering a nested function. */ 814 #define TRAMPOLINE_SIZE 16 815 816 /* Alignment required for a trampoline in bits . */ 817 /* For actual data alignment we just need 32, no more than the stack; 818 however, to reduce cache coherency issues, we want to make sure that 819 trampoline instructions always appear the same in any given cache line. */ 820 #define TRAMPOLINE_ALIGNMENT 256 821 822 /* Library calls. */ 823 824 /* Addressing modes, and classification of registers for them. */ 825 826 /* Maximum number of registers that can appear in a valid memory address. */ 827 /* The `ld' insn allows 2, but the `st' insn only allows 1. */ 828 #define MAX_REGS_PER_ADDRESS 1 829 830 /* We have pre inc/dec (load/store with update). */ 831 #define HAVE_PRE_INCREMENT 1 832 #define HAVE_PRE_DECREMENT 1 833 #define HAVE_POST_INCREMENT 1 834 #define HAVE_POST_DECREMENT 1 835 #define HAVE_PRE_MODIFY_DISP 1 836 #define HAVE_POST_MODIFY_DISP 1 837 #define HAVE_PRE_MODIFY_REG 1 838 #define HAVE_POST_MODIFY_REG 1 839 /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires 840 a special predicate for the memory operand of stores, like for the SH. */ 841 842 /* Recognize any constant value that is a valid address. */ 843 #define CONSTANT_ADDRESS_P(X) \ 844 (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \ 845 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 846 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)) 847 848 /* Is the argument a const_int rtx, containing an exact power of 2 */ 849 #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X)) 850 #define IS_POWEROF2_OR_0_P(X) (! ( (X) & ((X) - 1))) 851 852 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 853 and check its validity for a certain class. 854 We have two alternate definitions for each of them. 855 The *_NONSTRICT definition accepts all pseudo regs; the other rejects 856 them unless they have been allocated suitable hard regs. 857 858 Most source files want to accept pseudo regs in the hope that 859 they will get allocated to the class that the insn wants them to be in. 860 Source files for reload pass need to be strict. 861 After reload, it makes no difference, since pseudo regs have 862 been eliminated by then. */ 863 864 /* Nonzero if X is a hard reg that can be used as an index 865 or if it is a pseudo reg. */ 866 #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \ 867 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ 868 || REGNO_OK_FOR_BASE_P (REGNO (X))) 869 870 /* Nonzero if X is a hard reg that can be used as a base reg 871 or if it is a pseudo reg. */ 872 #define REG_OK_FOR_BASE_P_NONSTRICT(X) \ 873 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ 874 || REGNO_OK_FOR_BASE_P (REGNO (X))) 875 876 /* Nonzero if X is a hard reg that can be used as an index. */ 877 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 878 /* Nonzero if X is a hard reg that can be used as a base reg. */ 879 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 880 881 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 882 that is a valid memory address for an instruction. 883 The MODE argument is the machine mode for the MEM expression 884 that wants to use this address. */ 885 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm] 886 but the `st' insn only allows [reg],[reg+shimm],[limm]. 887 The only thing we can do is only allow the most strict case `st' and hope 888 other parts optimize out the restrictions for `ld'. */ 889 890 #define RTX_OK_FOR_BASE_P(X, STRICT) \ 891 (REG_P (X) \ 892 && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X))) 893 894 #define RTX_OK_FOR_INDEX_P(X, STRICT) \ 895 (REG_P (X) \ 896 && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X))) 897 898 /* A C compound statement that attempts to replace X, which is an address 899 that needs reloading, with a valid memory address for an operand of 900 mode MODE. WIN is a C statement label elsewhere in the code. 901 902 We try to get a normal form 903 of the address. That will allow inheritance of the address reloads. */ 904 905 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 906 do { \ 907 if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ 908 goto WIN; \ 909 } while (0) 910 911 /* Reading lp_count for anything but the lp instruction is very slow on the 912 ARC700. */ 913 #define DONT_REALLOC(REGNO,MODE) \ 914 (TARGET_ARC700 && (REGNO) == 60) 915 916 917 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 918 return the mode to be used for the comparison. */ 919 /*extern machine_mode arc_select_cc_mode ();*/ 920 #define SELECT_CC_MODE(OP, X, Y) \ 921 arc_select_cc_mode (OP, X, Y) 922 923 /* Return non-zero if SELECT_CC_MODE will never return MODE for a 924 floating point inequality comparison. */ 925 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 926 927 /* Costs. */ 928 929 /* The cost of a branch insn. */ 930 /* ??? What's the right value here? Branches are certainly more 931 expensive than reg->reg moves. */ 932 #define BRANCH_COST(speed_p, predictable_p) 2 933 934 /* Scc sets the destination to 1 and then conditionally zeroes it. 935 Best case, ORed SCCs can be made into clear - condset - condset. 936 But it could also end up as five insns. So say it costs four on 937 average. 938 These extra instructions - and the second comparison - will also be 939 an extra cost if the first comparison would have been decisive. 940 So get an average saving, with a probability of the first branch 941 beging decisive of p0, we want: 942 p0 * (branch_cost - 4) > (1 - p0) * 5 943 ??? We don't get to see that probability to evaluate, so we can 944 only wildly guess that it might be 50%. 945 ??? The compiler also lacks the notion of branch predictability. */ 946 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 947 (BRANCH_COST (optimize_function_for_speed_p (cfun), \ 948 false) > 9) 949 950 /* Nonzero if access to memory by bytes is slow and undesirable. 951 For RISC chips, it means that access to memory by bytes is no 952 better than access by words when possible, so grab a whole word 953 and maybe make use of that. */ 954 #define SLOW_BYTE_ACCESS 0 955 956 /* Define this macro if it is as good or better to call a constant 957 function address than to call an address kept in a register. */ 958 /* On the ARC, calling through registers is slow. */ 959 #define NO_FUNCTION_CSE 1 960 961 /* Section selection. */ 962 /* WARNING: These section names also appear in dwarfout.c. */ 963 964 #define TEXT_SECTION_ASM_OP "\t.section\t.text" 965 #define DATA_SECTION_ASM_OP "\t.section\t.data" 966 967 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 968 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata" 969 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss" 970 971 /* Expression whose value is a string, including spacing, containing the 972 assembler operation to identify the following data as initialization/termination 973 code. If not defined, GCC will assume such a section does not exist. */ 974 #define INIT_SECTION_ASM_OP "\t.section\t.init" 975 #define FINI_SECTION_ASM_OP "\t.section\t.fini" 976 977 /* Define this macro if jump tables (for tablejump insns) should be 978 output in the text section, along with the assembler instructions. 979 Otherwise, the readonly data section is used. 980 This macro is irrelevant if there is no separate readonly data section. */ 981 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE) 982 983 /* For DWARF. Marginally different than default so output is "prettier" 984 (and consistent with above). */ 985 #define PUSHSECTION_FORMAT "\t%s %s\n" 986 987 /* Tell crtstuff.c we're using ELF. */ 988 #define OBJECT_FORMAT_ELF 989 990 /* PIC */ 991 992 /* The register number of the register used to address a table of static 993 data addresses in memory. In some cases this register is defined by a 994 processor's ``application binary interface'' (ABI). When this macro 995 is defined, RTL is generated for this register once, as with the stack 996 pointer and frame pointer registers. If this macro is not defined, it 997 is up to the machine-dependent files to allocate such a register (if 998 necessary). */ 999 #define PIC_OFFSET_TABLE_REGNUM 26 1000 1001 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 1002 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 1003 is not defined. */ 1004 /* This register is call-saved on the ARC. */ 1005 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 1006 1007 /* A C expression that is nonzero if X is a legitimate immediate 1008 operand on the target machine when generating position independent code. 1009 You can assume that X satisfies CONSTANT_P, so you need not 1010 check this. You can also assume `flag_pic' is true, so you need not 1011 check it either. You need not define this macro if all constants 1012 (including SYMBOL_REF) can be immediate operands when generating 1013 position independent code. */ 1014 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1015 (!arc_raw_symbolic_reference_mentioned_p ((X), true)) 1016 1017 /* PIC and small data don't mix on ARC because they use the same register. */ 1018 #define SDATA_BASE_REGNUM 26 1019 1020 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1021 (flag_pic \ 1022 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 1023 : DW_EH_PE_absptr) 1024 1025 /* Control the assembler format that we output. */ 1026 1027 /* A C string constant describing how to begin a comment in the target 1028 assembler language. The compiler assumes that the comment will 1029 end at the end of the line. */ 1030 /* Gas needs this to be "#" in order to recognize line directives. */ 1031 #define ASM_COMMENT_START "#" 1032 1033 /* Output to assembler file text saying following lines 1034 may contain character constants, extra white space, comments, etc. */ 1035 #undef ASM_APP_ON 1036 #define ASM_APP_ON "" 1037 1038 /* Output to assembler file text saying following lines 1039 no longer contain unusual constructs. */ 1040 #undef ASM_APP_OFF 1041 #define ASM_APP_OFF "" 1042 1043 /* Globalizing directive for a label. */ 1044 #define GLOBAL_ASM_OP "\t.global\t" 1045 1046 /* This is how to output an assembler line defining a `char' constant. */ 1047 #define ASM_OUTPUT_CHAR(FILE, VALUE) \ 1048 ( fprintf (FILE, "\t.byte\t"), \ 1049 output_addr_const (FILE, (VALUE)), \ 1050 fprintf (FILE, "\n")) 1051 1052 /* This is how to output an assembler line defining a `short' constant. */ 1053 #define ASM_OUTPUT_SHORT(FILE, VALUE) \ 1054 ( fprintf (FILE, "\t.hword\t"), \ 1055 output_addr_const (FILE, (VALUE)), \ 1056 fprintf (FILE, "\n")) 1057 1058 /* This is how to output an assembler line defining an `int' constant. 1059 We also handle symbol output here. Code addresses must be right shifted 1060 by 2 because that's how the jump instruction wants them. */ 1061 #define ASM_OUTPUT_INT(FILE, VALUE) \ 1062 do { \ 1063 fprintf (FILE, "\t.word\t"); \ 1064 if (GET_CODE (VALUE) == LABEL_REF) \ 1065 { \ 1066 fprintf (FILE, "%%st(@"); \ 1067 output_addr_const (FILE, (VALUE)); \ 1068 fprintf (FILE, ")"); \ 1069 } \ 1070 else \ 1071 output_addr_const (FILE, (VALUE)); \ 1072 fprintf (FILE, "\n"); \ 1073 } while (0) 1074 1075 /* This is how to output an assembler line defining a `float' constant. */ 1076 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ 1077 { \ 1078 long t; \ 1079 char str[30]; \ 1080 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ 1081 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ 1082 fprintf (FILE, "\t.word\t0x%lx %s %s\n", \ 1083 t, ASM_COMMENT_START, str); \ 1084 } 1085 1086 /* This is how to output an assembler line defining a `double' constant. */ 1087 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ 1088 { \ 1089 long t[2]; \ 1090 char str[30]; \ 1091 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ 1092 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ 1093 fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \ 1094 t[0], ASM_COMMENT_START, str, t[1]); \ 1095 } 1096 1097 /* This is how to output the definition of a user-level label named NAME, 1098 such as the label on a static function or variable NAME. */ 1099 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1100 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1101 1102 #define ASM_NAME_P(NAME) ( NAME[0]=='*') 1103 1104 /* This is how to output a reference to a user-level label named NAME. 1105 `assemble_name' uses this. */ 1106 /* We work around a dwarfout.c deficiency by watching for labels from it and 1107 not adding the '_' prefix. There is a comment in 1108 dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */ 1109 #define ASM_OUTPUT_LABELREF(FILE, NAME1) \ 1110 do { \ 1111 const char *NAME; \ 1112 NAME = (*targetm.strip_name_encoding)(NAME1); \ 1113 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \ 1114 fprintf (FILE, "%s", NAME); \ 1115 else \ 1116 { \ 1117 if (!ASM_NAME_P (NAME1)) \ 1118 fprintf (FILE, "%s", user_label_prefix); \ 1119 fprintf (FILE, "%s", NAME); \ 1120 } \ 1121 } while (0) 1122 1123 /* This is how to output a reference to a symbol_ref / label_ref as 1124 (part of) an operand. To disambiguate from register names like 1125 a1 / a2 / status etc, symbols are preceded by '@'. */ 1126 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ 1127 ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0)) 1128 #define ASM_OUTPUT_LABEL_REF(FILE,STR) \ 1129 do \ 1130 { \ 1131 fputc ('@', file); \ 1132 assemble_name ((FILE), (STR)); \ 1133 } \ 1134 while (0) 1135 1136 /* Store in OUTPUT a string (made with alloca) containing 1137 an assembler-name for a local static variable named NAME. 1138 LABELNO is an integer which is different for each call. */ 1139 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1140 ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1141 sprintf ((OUTPUT), "%s.%u", (NAME), (unsigned int)(LABELNO))) 1142 1143 /* The following macro defines the format used to output the second 1144 operand of the .type assembler directive. Different svr4 assemblers 1145 expect various different forms for this operand. The one given here 1146 is just a default. You may need to override it in your machine- 1147 specific tm.h file (depending upon the particulars of your assembler). */ 1148 1149 #undef TYPE_OPERAND_FMT 1150 #define TYPE_OPERAND_FMT "@%s" 1151 1152 /* A C string containing the appropriate assembler directive to 1153 specify the size of a symbol, without any arguments. On systems 1154 that use ELF, the default (in `config/elfos.h') is `"\t.size\t"'; 1155 on other systems, the default is not to define this macro. */ 1156 #undef SIZE_ASM_OP 1157 #define SIZE_ASM_OP "\t.size\t" 1158 1159 /* Assembler pseudo-op to equate one value with another. */ 1160 /* ??? This is needed because dwarfout.c provides a default definition too 1161 late for defaults.h (which contains the default definition of ASM_OTPUT_DEF 1162 that we use). */ 1163 #ifdef SET_ASM_OP 1164 #undef SET_ASM_OP 1165 #endif 1166 #define SET_ASM_OP "\t.set\t" 1167 1168 extern char rname29[], rname30[]; 1169 extern char rname56[], rname57[], rname58[], rname59[]; 1170 /* How to refer to registers in assembler output. 1171 This sequence is indexed by compiler's hard-register-number (see above). */ 1172 #define REGISTER_NAMES \ 1173 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1174 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1175 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 1176 "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \ 1177 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 1178 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \ 1179 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 1180 rname56,rname57,rname58,rname59,"lp_count", "cc", "limm", "pcl", \ 1181 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \ 1182 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \ 1183 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \ 1184 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \ 1185 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \ 1186 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \ 1187 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \ 1188 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \ 1189 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ 1190 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ 1191 "arg", "frame" \ 1192 } 1193 1194 #define ADDITIONAL_REGISTER_NAMES \ 1195 { \ 1196 {"ilink", 29}, \ 1197 {"r29", 29}, \ 1198 {"r30", 30}, \ 1199 {"r40", 40}, \ 1200 {"r41", 41}, \ 1201 {"r42", 42}, \ 1202 {"r43", 43}, \ 1203 {"r56", 56}, \ 1204 {"r57", 57}, \ 1205 {"r58", 58}, \ 1206 {"r59", 59} \ 1207 } 1208 1209 /* Entry to the insn conditionalizer. */ 1210 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1211 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS) 1212 1213 /* A C expression which evaluates to true if CODE is a valid 1214 punctuation character for use in the `PRINT_OPERAND' macro. */ 1215 extern char arc_punct_chars[]; 1216 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1217 arc_punct_chars[(unsigned char) (CHAR)] 1218 1219 /* Print operand X (an rtx) in assembler syntax to file FILE. 1220 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1221 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1222 #define PRINT_OPERAND(FILE, X, CODE) \ 1223 arc_print_operand (FILE, X, CODE) 1224 1225 /* A C compound statement to output to stdio stream STREAM the 1226 assembler syntax for an instruction operand that is a memory 1227 reference whose address is ADDR. ADDR is an RTL expression. 1228 1229 On some machines, the syntax for a symbolic address depends on 1230 the section that the address refers to. On these machines, 1231 define the macro `ENCODE_SECTION_INFO' to store the information 1232 into the `symbol_ref', and then check for it here. */ 1233 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1234 arc_print_operand_address (FILE, ADDR) 1235 1236 /* This is how to output an element of a case-vector that is absolute. */ 1237 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1238 do { \ 1239 char label[30]; \ 1240 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1241 fprintf (FILE, "\t.word "); \ 1242 assemble_name (FILE, label); \ 1243 fprintf (FILE, "\n"); \ 1244 } while (0) 1245 1246 /* This is how to output an element of a case-vector that is relative. */ 1247 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1248 do { \ 1249 char label[30]; \ 1250 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1251 if (!TARGET_BI_BIH) \ 1252 { \ 1253 switch (GET_MODE (BODY)) \ 1254 { \ 1255 case E_QImode: fprintf (FILE, "\t.byte "); break; \ 1256 case E_HImode: fprintf (FILE, "\t.hword "); break; \ 1257 case E_SImode: fprintf (FILE, "\t.word "); break; \ 1258 default: gcc_unreachable (); \ 1259 } \ 1260 assemble_name (FILE, label); \ 1261 fprintf (FILE, "-"); \ 1262 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 1263 assemble_name (FILE, label); \ 1264 fprintf (FILE, "\n"); \ 1265 } \ 1266 else \ 1267 { \ 1268 switch (GET_MODE (BODY)) \ 1269 { \ 1270 case E_SImode: fprintf (FILE, "\tb\t@"); break; \ 1271 case E_HImode: \ 1272 case E_QImode: fprintf (FILE, "\tb_s\t@"); break; \ 1273 default: gcc_unreachable (); \ 1274 } \ 1275 assemble_name (FILE, label); \ 1276 fprintf(FILE, "\n"); \ 1277 } \ 1278 } while (0) 1279 1280 /* Defined to also emit an .align in elfos.h. We don't want that. */ 1281 #undef ASM_OUTPUT_CASE_LABEL 1282 1283 /* ADDR_DIFF_VECs are in the text section and thus can affect the 1284 current alignment. */ 1285 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 1286 do \ 1287 { \ 1288 if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \ 1289 && ((GET_MODE_SIZE (as_a <scalar_int_mode> \ 1290 (GET_MODE (PATTERN (JUMPTABLE)))) \ 1291 * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \ 1292 & 2)) \ 1293 arc_toggle_unalign (); \ 1294 } \ 1295 while (0) 1296 1297 #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0) 1298 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 1299 (JUMP_ALIGN(LABEL) \ 1300 ? JUMP_ALIGN(LABEL) \ 1301 : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 1302 ? 1 : 0) 1303 /* The desired alignment for the location counter at the beginning 1304 of a loop. */ 1305 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size 1306 optimization. */ 1307 #define LOOP_ALIGN(X) 0 1308 1309 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL)) 1310 1311 /* This is how to output an assembler line 1312 that says to advance the location counter 1313 to a multiple of 2**LOG bytes. */ 1314 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1315 do { \ 1316 if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1317 if ((LOG) > 1) \ 1318 arc_clear_unalign (); \ 1319 } while (0) 1320 1321 /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT) 1322 Define this macro when you need to see the variable's decl in order to 1323 chose what to output. */ 1324 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 1325 arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) 1326 1327 /* Debugging information. */ 1328 1329 /* Generate DBX and DWARF debugging information. */ 1330 #ifdef DBX_DEBUGGING_INFO 1331 #undef DBX_DEBUGGING_INFO 1332 #endif 1333 #define DBX_DEBUGGING_INFO 1334 1335 #ifdef DWARF2_DEBUGGING_INFO 1336 #undef DWARF2_DEBUGGING_INFO 1337 #endif 1338 #define DWARF2_DEBUGGING_INFO 1339 1340 /* Prefer STABS (for now). */ 1341 #undef PREFERRED_DEBUGGING_TYPE 1342 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1343 1344 /* How to renumber registers for dbx and gdb. */ 1345 #define DBX_REGISTER_NUMBER(REGNO) \ 1346 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ 1347 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ 1348 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 58) \ 1349 ? (((REGNO) == 57) \ 1350 ? 58 /* MMED */ \ 1351 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \ 1352 : (REGNO)) 1353 1354 /* Use gcc hard register numbering for eh_frame. */ 1355 #define DWARF_FRAME_REGNUM(REG) (REG) 1356 1357 /* Map register numbers held in the call frame info that gcc has 1358 collected using DWARF_FRAME_REGNUM to those that should be output 1359 in .debug_frame and .eh_frame. */ 1360 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 1361 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ 1362 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ 1363 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 58) \ 1364 ? (((REGNO) == 57) \ 1365 ? 58 /* MMED */ \ 1366 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \ 1367 : (REGNO)) 1368 1369 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31) 1370 1371 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31) 1372 1373 /* Frame info. */ 1374 1375 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 1376 1377 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 1378 1379 /* Turn off splitting of long stabs. */ 1380 #define DBX_CONTIN_LENGTH 0 1381 1382 /* Miscellaneous. */ 1383 1384 /* Specify the machine mode that this machine uses 1385 for the index in the tablejump instruction. 1386 If we have pc relative case vectors, we start the case vector shortening 1387 with QImode. */ 1388 #define CASE_VECTOR_MODE \ 1389 (TARGET_BI_BIH ? SImode \ 1390 : (optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode) 1391 1392 /* Define as C expression which evaluates to nonzero if the tablejump 1393 instruction expects the table to contain offsets from the address of the 1394 table. 1395 Do not define this if the table should contain absolute addresses. */ 1396 #define CASE_VECTOR_PC_RELATIVE \ 1397 (TARGET_CASE_VECTOR_PC_RELATIVE || TARGET_BI_BIH) 1398 1399 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 1400 (TARGET_BI_BIH ? \ 1401 ((MIN_OFFSET) >= -512 && (MAX_OFFSET) <= 508 ? HImode : SImode) \ 1402 : ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 1403 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 1404 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \ 1405 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 1406 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \ 1407 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \ 1408 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \ 1409 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \ 1410 : SImode)) 1411 1412 #define ADDR_VEC_ALIGN(VEC_INSN) \ 1413 (TARGET_BI_BIH ? 0 \ 1414 : exact_log2 (GET_MODE_SIZE (as_a <scalar_int_mode> \ 1415 (GET_MODE (PATTERN (VEC_INSN)))))) 1416 1417 #define INSN_LENGTH_ALIGNMENT(INSN) \ 1418 ((JUMP_TABLE_DATA_P (INSN) \ 1419 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \ 1420 && GET_MODE (PATTERN (INSN)) == QImode) \ 1421 ? 0 : length_unit_log) 1422 1423 /* Define if operations between registers always perform the operation 1424 on the full register even if a narrower mode is specified. */ 1425 #define WORD_REGISTER_OPERATIONS 1 1426 1427 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1428 will either zero-extend or sign-extend. The value of this macro should 1429 be the code that says which one of the two operations is implicitly 1430 done, NIL if none. */ 1431 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1432 1433 1434 /* Max number of bytes we can move from memory to memory 1435 in one reasonably fast instruction. */ 1436 #define MOVE_MAX 4 1437 1438 /* Undo the effects of the cpymem pattern presence on STORE_BY_PIECES_P . */ 1439 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3) 1440 1441 /* Define this to be nonzero if shift instructions ignore all but the 1442 low-order few bits. 1443 */ 1444 #define SHIFT_COUNT_TRUNCATED 1 1445 1446 /* We assume that the store-condition-codes instructions store 0 for false 1447 and some other value for true. This is the value stored for true. */ 1448 #define STORE_FLAG_VALUE 1 1449 1450 /* Specify the machine mode that pointers have. 1451 After generation of rtl, the compiler makes no further distinction 1452 between pointers and any other objects of this machine mode. */ 1453 /* ARCompact has full 32-bit pointers. */ 1454 #define Pmode SImode 1455 1456 /* A function address in a call instruction. */ 1457 #define FUNCTION_MODE SImode 1458 1459 /* Define the information needed to generate branch and scc insns. This is 1460 stored from the compare operation. Note that we can't use "rtx" here 1461 since it hasn't been defined! */ 1462 extern struct rtx_def *arc_compare_op0, *arc_compare_op1; 1463 1464 /* ARC function types. */ 1465 enum arc_function_type { 1466 /* No function should have the unknown type. This value is used to 1467 indicate the that function type has not yet been computed. */ 1468 ARC_FUNCTION_UNKNOWN = 0, 1469 1470 /* The normal function type indicates that the function has the 1471 standard prologue and epilogue. */ 1472 ARC_FUNCTION_NORMAL = 1 << 0, 1473 /* These are interrupt handlers. The name corresponds to the register 1474 name that contains the return address. */ 1475 ARC_FUNCTION_ILINK1 = 1 << 1, 1476 ARC_FUNCTION_ILINK2 = 1 << 2, 1477 /* Fast interrupt is only available on ARCv2 processors. */ 1478 ARC_FUNCTION_FIRQ = 1 << 3, 1479 /* The naked function type indicates that the function does not have 1480 prologue or epilogue, and that no stack frame is available. */ 1481 ARC_FUNCTION_NAKED = 1 << 4 1482 }; 1483 1484 /* Check if a function is an interrupt function. */ 1485 #define ARC_INTERRUPT_P(TYPE) \ 1486 (((TYPE) & (ARC_FUNCTION_ILINK1 | ARC_FUNCTION_ILINK2 \ 1487 | ARC_FUNCTION_FIRQ)) != 0) 1488 1489 /* Check if a function is a fast interrupt function. */ 1490 #define ARC_FAST_INTERRUPT_P(TYPE) (((TYPE) & ARC_FUNCTION_FIRQ) != 0) 1491 1492 /* Check if a function is normal, that is, has standard prologue and 1493 epilogue. */ 1494 #define ARC_NORMAL_P(TYPE) (((TYPE) & ARC_FUNCTION_NORMAL) != 0) 1495 1496 /* Check if a function is naked. */ 1497 #define ARC_NAKED_P(TYPE) (((TYPE) & ARC_FUNCTION_NAKED) != 0) 1498 1499 /* Called by crtstuff.c to make calls to function FUNCTION that are defined in 1500 SECTION_OP, and then to switch back to text section. */ 1501 #undef CRT_CALL_STATIC_FUNCTION 1502 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 1503 asm (SECTION_OP "\n\t" \ 1504 "add r12,pcl,@" USER_LABEL_PREFIX #FUNC "@pcl\n\t" \ 1505 "jl [r12]\n" \ 1506 TEXT_SECTION_ASM_OP); 1507 1508 /* This macro expands to the name of the scratch register r12, used for 1509 temporary calculations according to the ABI. */ 1510 #define ARC_TEMP_SCRATCH_REG "r12" 1511 1512 /* The C++ compiler must use one bit to indicate whether the function 1513 that will be called through a pointer-to-member-function is 1514 virtual. Normally, we assume that the low-order bit of a function 1515 pointer must always be zero. Then, by ensuring that the 1516 vtable_index is odd, we can distinguish which variant of the union 1517 is in use. But, on some platforms function pointers can be odd, 1518 and so this doesn't work. In that case, we use the low-order bit 1519 of the `delta' field, and shift the remainder of the `delta' field 1520 to the left. We needed to do this for A4 because the address was always 1521 shifted and thus could be odd. */ 1522 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ 1523 (ptrmemfunc_vbit_in_pfn) 1524 1525 #define INSN_SETS_ARE_DELAYED(X) \ 1526 (GET_CODE (X) == INSN \ 1527 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1528 && GET_CODE (PATTERN (X)) != USE \ 1529 && GET_CODE (PATTERN (X)) != CLOBBER \ 1530 && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC)) 1531 1532 #define INSN_REFERENCES_ARE_DELAYED(insn) \ 1533 (INSN_SETS_ARE_DELAYED (insn)) 1534 1535 #define CALL_ATTR(X, NAME) \ 1536 ((CALL_P (X) || NONJUMP_INSN_P (X)) \ 1537 && GET_CODE (PATTERN (X)) != USE \ 1538 && GET_CODE (PATTERN (X)) != CLOBBER \ 1539 && get_attr_is_##NAME (X) == IS_##NAME##_YES) \ 1540 1541 #define REVERSE_CONDITION(CODE,MODE) \ 1542 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \ 1543 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \ 1544 || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \ 1545 || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode) \ 1546 ? reverse_condition_maybe_unordered ((CODE)) \ 1547 : reverse_condition ((CODE))) 1548 1549 #define ADJUST_INSN_LENGTH(X, LENGTH) \ 1550 ((LENGTH) \ 1551 = (GET_CODE (PATTERN (X)) == SEQUENCE \ 1552 ? ((LENGTH) \ 1553 + arc_adjust_insn_length ( \ 1554 as_a <rtx_sequence *> (PATTERN (X))->insn (0), \ 1555 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \ 1556 true) \ 1557 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \ 1558 + arc_adjust_insn_length ( \ 1559 as_a <rtx_sequence *> (PATTERN (X))->insn (1), \ 1560 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \ 1561 true) \ 1562 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \ 1563 : arc_adjust_insn_length ((X), (LENGTH), false))) 1564 1565 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`') 1566 1567 #define INIT_EXPANDERS arc_init_expanders () 1568 1569 enum 1570 { 1571 ARC_LRA_PRIORITY_NONE, ARC_LRA_PRIORITY_NONCOMPACT, ARC_LRA_PRIORITY_COMPACT 1572 }; 1573 1574 /* The define_cond_exec construct is rather crude, as we can't have 1575 different ones with different conditions apply to different sets 1576 of instructions. We can't use an attribute test inside the condition, 1577 because that would lead to infinite recursion as the attribute test 1578 needs to recognize the insn. So, instead we have a clause for 1579 the pattern condition of all sfunc patterns which is only relevant for 1580 the predicated varaint. */ 1581 #define SFUNC_CHECK_PREDICABLE \ 1582 (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS) 1583 1584 /* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */ 1585 #define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2) 1586 /* Full ARCv2 multiplication feature macro. */ 1587 #define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2) 1588 /* General MPY feature macro. */ 1589 #define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI) 1590 /* ARC700 MPY feature macro. */ 1591 #define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET)) 1592 /* Any multiplication feature macro. */ 1593 #define TARGET_ANY_MPY \ 1594 (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET) 1595 /* PLUS_DMPY feature macro. */ 1596 #define TARGET_PLUS_DMPY ((arc_mpy_option > 6) && TARGET_HS) 1597 /* PLUS_MACD feature macro. */ 1598 #define TARGET_PLUS_MACD ((arc_mpy_option > 7) && TARGET_HS) 1599 /* PLUS_QMACW feature macro. */ 1600 #define TARGET_PLUS_QMACW ((arc_mpy_option > 8) && TARGET_HS) 1601 1602 /* ARC600 and ARC601 feature macro. */ 1603 #define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601) 1604 /* ARC600, ARC601 and ARC700 feature macro. */ 1605 #define TARGET_ARCOMPACT_FAMILY \ 1606 (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700) 1607 /* Loop count register can be read in very next instruction after has 1608 been written to by an ordinary instruction. */ 1609 #define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY) 1610 1611 /* FPU defines. */ 1612 /* Any FPU support. */ 1613 #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0) 1614 /* Single precision floating point support. */ 1615 #define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0) 1616 /* Double precision floating point support. */ 1617 #define TARGET_FP_DP_BASE ((arc_fpu_build & FPU_DP) != 0) 1618 /* Single precision floating point support with fused operation. */ 1619 #define TARGET_FP_SP_FUSED ((arc_fpu_build & FPU_SF) != 0) 1620 /* Double precision floating point support with fused operation. */ 1621 #define TARGET_FP_DP_FUSED ((arc_fpu_build & FPU_DF) != 0) 1622 /* Single precision floating point conversion instruction support. */ 1623 #define TARGET_FP_SP_CONV ((arc_fpu_build & FPU_SC) != 0) 1624 /* Double precision floating point conversion instruction support. */ 1625 #define TARGET_FP_DP_CONV ((arc_fpu_build & FPU_DC) != 0) 1626 /* Single precision floating point SQRT/DIV instruction support. */ 1627 #define TARGET_FP_SP_SQRT ((arc_fpu_build & FPU_SD) != 0) 1628 /* Double precision floating point SQRT/DIV instruction support. */ 1629 #define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0) 1630 /* Double precision floating point assist instruction support. */ 1631 #define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0) 1632 /* Custom FP instructions used by QuarkSE EM cpu. */ 1633 #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \ 1634 && (arc_fpu_build == FPX_QK)) 1635 /* DBNZ support is available for ARCv2 core3 and newer cpus. */ 1636 #define TARGET_DBNZ (TARGET_V2 && (arc_tune >= ARC_TUNE_CORE_3)) 1637 1638 /* BI/BIH feature macro. */ 1639 #define TARGET_BI_BIH (TARGET_BRANCH_INDEX && TARGET_CODE_DENSITY) 1640 1641 /* The default option for BI/BIH instructions. */ 1642 #define DEFAULT_BRANCH_INDEX 0 1643 1644 #ifndef TARGET_LRA 1645 #define TARGET_LRA arc_lra_p() 1646 #endif 1647 1648 #endif /* GCC_ARC_H */ 1649