1 /* Definitions of target machine GNU compiler. IA-64 version. 2 Copyright (C) 1999-2020 Free Software Foundation, Inc. 3 Contributed by James E. Wilson <wilson@cygnus.com> and 4 David Mosberger <davidm@hpl.hp.com>. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* ??? Look at ABI group documents for list of preprocessor macros and 23 other features required for ABI compliance. */ 24 25 /* ??? Functions containing a non-local goto target save many registers. Why? 26 See for instance execute/920428-2.c. */ 27 28 29 /* Run-time target specifications */ 30 31 /* Target CPU builtins. */ 32 #define TARGET_CPU_CPP_BUILTINS() \ 33 do { \ 34 builtin_assert("cpu=ia64"); \ 35 builtin_assert("machine=ia64"); \ 36 builtin_define("__ia64"); \ 37 builtin_define("__ia64__"); \ 38 builtin_define("__itanium__"); \ 39 if (TARGET_BIG_ENDIAN) \ 40 builtin_define("__BIG_ENDIAN__"); \ 41 builtin_define("__SIZEOF_FPREG__=16"); \ 42 builtin_define("__SIZEOF_FLOAT80__=16");\ 43 builtin_define("__SIZEOF_FLOAT128__=16");\ 44 } while (0) 45 46 #ifndef SUBTARGET_EXTRA_SPECS 47 #define SUBTARGET_EXTRA_SPECS 48 #endif 49 50 #define EXTRA_SPECS \ 51 { "asm_extra", ASM_EXTRA_SPEC }, \ 52 SUBTARGET_EXTRA_SPECS 53 54 #define CC1_SPEC "%(cc1_cpu) " 55 56 #define ASM_EXTRA_SPEC "" 57 58 /* Variables which are this size or smaller are put in the sdata/sbss 59 sections. */ 60 extern unsigned int ia64_section_threshold; 61 62 /* If the assembler supports thread-local storage, assume that the 63 system does as well. If a particular target system has an 64 assembler that supports TLS -- but the rest of the system does not 65 support TLS -- that system should explicit define TARGET_HAVE_TLS 66 to false in its own configuration file. */ 67 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS) 68 #define TARGET_HAVE_TLS true 69 #endif 70 71 #define TARGET_TLS14 (ia64_tls_size == 14) 72 #define TARGET_TLS22 (ia64_tls_size == 22) 73 #define TARGET_TLS64 (ia64_tls_size == 64) 74 75 #define TARGET_HPUX 0 76 #define TARGET_HPUX_LD 0 77 78 #define TARGET_ABI_OPEN_VMS 0 79 80 #ifndef TARGET_ILP32 81 #define TARGET_ILP32 0 82 #endif 83 84 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS 85 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0 86 #endif 87 88 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and 89 TARGET_INLINE_SQRT. */ 90 91 enum ia64_inline_type 92 { 93 INL_NO = 0, 94 INL_MIN_LAT = 1, 95 INL_MAX_THR = 2 96 }; 97 98 /* Default target_flags if no switches are specified */ 99 100 #ifndef TARGET_DEFAULT 101 #define TARGET_DEFAULT (MASK_DWARF2_ASM) 102 #endif 103 104 #ifndef TARGET_CPU_DEFAULT 105 #define TARGET_CPU_DEFAULT 0 106 #endif 107 108 /* Driver configuration */ 109 110 /* A C string constant that tells the GCC driver program options to pass to 111 `cc1'. It can also specify how to translate options you give to GCC into 112 options for GCC to pass to the `cc1'. */ 113 114 #undef CC1_SPEC 115 #define CC1_SPEC "%{G*}" 116 117 /* A C string constant that tells the GCC driver program options to pass to 118 `cc1plus'. It can also specify how to translate options you give to GCC 119 into options for GCC to pass to the `cc1plus'. */ 120 121 /* #define CC1PLUS_SPEC "" */ 122 123 /* Storage Layout */ 124 125 /* Define this macro to have the value 1 if the most significant bit in a byte 126 has the lowest number; otherwise define it to have the value zero. */ 127 128 #define BITS_BIG_ENDIAN 0 129 130 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 131 132 /* Define this macro to have the value 1 if, in a multiword object, the most 133 significant word has the lowest number. */ 134 135 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 136 137 #define UNITS_PER_WORD 8 138 139 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 140 141 /* A C expression whose value is zero if pointers that need to be extended 142 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if 143 they are zero-extended and negative one if there is a ptr_extend operation. 144 145 You need not define this macro if the `POINTER_SIZE' is equal to the width 146 of `Pmode'. */ 147 /* Need this for 32-bit pointers, see hpux.h for setting it. */ 148 /* #define POINTERS_EXTEND_UNSIGNED */ 149 150 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and 151 which has the specified mode and signedness is to be stored in a register. 152 This macro is only called when TYPE is a scalar type. */ 153 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 154 do \ 155 { \ 156 if (GET_MODE_CLASS (MODE) == MODE_INT \ 157 && GET_MODE_SIZE (MODE) < 4) \ 158 (MODE) = SImode; \ 159 } \ 160 while (0) 161 162 #define PARM_BOUNDARY 64 163 164 /* Define this macro if you wish to preserve a certain alignment for the stack 165 pointer. The definition is a C expression for the desired alignment 166 (measured in bits). */ 167 168 #define STACK_BOUNDARY 128 169 170 /* Align frames on double word boundaries */ 171 #ifndef IA64_STACK_ALIGN 172 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) 173 #endif 174 175 #define FUNCTION_BOUNDARY 128 176 177 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word 178 128-bit integers all require 128-bit alignment. */ 179 #define BIGGEST_ALIGNMENT 128 180 181 /* If defined, a C expression to compute the alignment for a static variable. 182 TYPE is the data type, and ALIGN is the alignment that the object 183 would ordinarily have. The value of this macro is used instead of that 184 alignment to align the object. */ 185 186 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 187 (TREE_CODE (TYPE) == ARRAY_TYPE \ 188 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 189 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 190 191 #define STRICT_ALIGNMENT 1 192 193 /* Define this if you wish to imitate the way many other C compilers handle 194 alignment of bitfields and the structures that contain them. 195 The behavior is that the type written for a bit-field (`int', `short', or 196 other integer type) imposes an alignment for the entire structure, as if the 197 structure really did contain an ordinary field of that type. In addition, 198 the bit-field is placed within the structure so that it would fit within such 199 a field, not crossing a boundary for it. */ 200 #define PCC_BITFIELD_TYPE_MATTERS 1 201 202 /* An integer expression for the size in bits of the largest integer machine 203 mode that should actually be used. */ 204 205 /* Allow pairs of registers to be used, which is the intent of the default. */ 206 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 207 208 /* By default, the C++ compiler will use function addresses in the 209 vtable entries. Setting this nonzero tells the compiler to use 210 function descriptors instead. The value of this macro says how 211 many words wide the descriptor is (normally 2). It is assumed 212 that the address of a function descriptor may be treated as a 213 pointer to a function. 214 215 For reasons known only to HP, the vtable entries (as opposed to 216 normal function descriptors) are 16 bytes wide in 32-bit mode as 217 well, even though the 3rd and 4th words are unused. */ 218 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2) 219 220 /* Due to silliness in the HPUX linker, vtable entries must be 221 8-byte aligned even in 32-bit mode. Rather than create multiple 222 ABIs, force this restriction on everyone else too. */ 223 #define TARGET_VTABLE_ENTRY_ALIGN 64 224 225 /* Due to the above, we need extra padding for the data entries below 0 226 to retain the alignment of the descriptors. */ 227 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1) 228 229 /* Layout of Source Language Data Types */ 230 231 #define INT_TYPE_SIZE 32 232 233 #define SHORT_TYPE_SIZE 16 234 235 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 236 237 #define LONG_LONG_TYPE_SIZE 64 238 239 #define FLOAT_TYPE_SIZE 32 240 241 #define DOUBLE_TYPE_SIZE 64 242 243 /* long double is XFmode normally, and TFmode for HPUX. It should be 244 TFmode for VMS as well but we only support up to DFmode now. */ 245 #define LONG_DOUBLE_TYPE_SIZE \ 246 (TARGET_HPUX ? 128 \ 247 : TARGET_ABI_OPEN_VMS ? 64 \ 248 : 80) 249 250 251 #define DEFAULT_SIGNED_CHAR 1 252 253 /* A C expression for a string describing the name of the data type to use for 254 size values. The typedef name `size_t' is defined using the contents of the 255 string. */ 256 /* ??? Needs to be defined for P64 code. */ 257 /* #define SIZE_TYPE */ 258 259 /* A C expression for a string describing the name of the data type to use for 260 the result of subtracting two pointers. The typedef name `ptrdiff_t' is 261 defined using the contents of the string. See `SIZE_TYPE' above for more 262 information. */ 263 /* ??? Needs to be defined for P64 code. */ 264 /* #define PTRDIFF_TYPE */ 265 266 /* A C expression for a string describing the name of the data type to use for 267 wide characters. The typedef name `wchar_t' is defined using the contents 268 of the string. See `SIZE_TYPE' above for more information. */ 269 /* #define WCHAR_TYPE */ 270 271 /* A C expression for the size in bits of the data type for wide characters. 272 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ 273 /* #define WCHAR_TYPE_SIZE */ 274 275 276 /* Register Basics */ 277 278 /* Number of hardware registers known to the compiler. 279 We have 128 general registers, 128 floating point registers, 280 64 predicate registers, 8 branch registers, one frame pointer, 281 and several "application" registers. */ 282 283 #define FIRST_PSEUDO_REGISTER 334 284 285 /* Ranges for the various kinds of registers. */ 286 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) 287 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) 288 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) 289 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159) 290 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) 291 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) 292 #define GENERAL_REGNO_P(REGNO) \ 293 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM) 294 295 #define GR_REG(REGNO) ((REGNO) + 0) 296 #define FR_REG(REGNO) ((REGNO) + 128) 297 #define PR_REG(REGNO) ((REGNO) + 256) 298 #define BR_REG(REGNO) ((REGNO) + 320) 299 #define OUT_REG(REGNO) ((REGNO) + 120) 300 #define IN_REG(REGNO) ((REGNO) + 112) 301 #define LOC_REG(REGNO) ((REGNO) + 32) 302 303 #define AR_CCV_REGNUM 329 304 #define AR_UNAT_REGNUM 330 305 #define AR_PFS_REGNUM 331 306 #define AR_LC_REGNUM 332 307 #define AR_EC_REGNUM 333 308 309 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) 310 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) 311 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) 312 313 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ 314 || (REGNO) == AR_UNAT_REGNUM) 315 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ 316 && (REGNO) < FIRST_PSEUDO_REGISTER) 317 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ 318 && (REGNO) < FIRST_PSEUDO_REGISTER) 319 320 321 /* ??? Don't really need two sets of macros. I like this one better because 322 it is less typing. */ 323 #define R_GR(REGNO) GR_REG (REGNO) 324 #define R_FR(REGNO) FR_REG (REGNO) 325 #define R_PR(REGNO) PR_REG (REGNO) 326 #define R_BR(REGNO) BR_REG (REGNO) 327 328 /* An initializer that says which registers are used for fixed purposes all 329 throughout the compiled code and are therefore not available for general 330 allocation. 331 332 r0: constant 0 333 r1: global pointer (gp) 334 r12: stack pointer (sp) 335 r13: thread pointer (tp) 336 f0: constant 0.0 337 f1: constant 1.0 338 p0: constant true 339 fp: eliminable frame pointer */ 340 341 /* The last 16 stacked regs are reserved for the 8 input and 8 output 342 registers. */ 343 344 #define FIXED_REGISTERS \ 345 { /* General registers. */ \ 346 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ 347 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 348 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 350 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 351 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 352 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 354 /* Floating-point registers. */ \ 355 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 357 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 358 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 359 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 360 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 361 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 363 /* Predicate registers. */ \ 364 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 365 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 368 /* Branch registers. */ \ 369 0, 0, 0, 0, 0, 0, 0, 0, \ 370 /*FP CCV UNAT PFS LC EC */ \ 371 1, 1, 1, 1, 1, 1 \ 372 } 373 374 /* Like `CALL_USED_REGISTERS' but used to overcome a historical 375 problem which makes CALL_USED_REGISTERS *always* include 376 all the FIXED_REGISTERS. Until this problem has been 377 resolved this macro can be used to overcome this situation. 378 In particular, block_propagate() requires this list 379 be accurate, or we can remove registers which should be live. 380 This macro is used in regs_invalidated_by_call. */ 381 382 #define CALL_REALLY_USED_REGISTERS \ 383 { /* General registers. */ \ 384 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \ 385 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 386 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 387 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 389 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 390 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 391 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 392 /* Floating-point registers. */ \ 393 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 394 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 395 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 396 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 397 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 398 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 399 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 400 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 401 /* Predicate registers. */ \ 402 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 404 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 406 /* Branch registers. */ \ 407 1, 0, 0, 0, 0, 0, 1, 1, \ 408 /*FP CCV UNAT PFS LC EC */ \ 409 0, 1, 0, 1, 0, 0 \ 410 } 411 412 413 /* Define this macro if the target machine has register windows. This C 414 expression returns the register number as seen by the called function 415 corresponding to the register number OUT as seen by the calling function. 416 Return OUT if register number OUT is not an outbound register. */ 417 418 #define INCOMING_REGNO(OUT) \ 419 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) 420 421 /* Define this macro if the target machine has register windows. This C 422 expression returns the register number as seen by the calling function 423 corresponding to the register number IN as seen by the called function. 424 Return IN if register number IN is not an inbound register. */ 425 426 #define OUTGOING_REGNO(IN) \ 427 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) 428 429 /* Define this macro if the target machine has register windows. This 430 C expression returns true if the register is call-saved but is in the 431 register window. */ 432 433 #define LOCAL_REGNO(REGNO) \ 434 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) 435 436 /* We define CCImode in ia64-modes.def so we need a selector. */ 437 438 #define SELECT_CC_MODE(OP,X,Y) CCmode 439 440 /* Order of allocation of registers */ 441 442 /* If defined, an initializer for a vector of integers, containing the numbers 443 of hard registers in the order in which GCC should prefer to use them 444 (from most preferred to least). 445 446 If this macro is not defined, registers are used lowest numbered first (all 447 else being equal). 448 449 One use of this macro is on machines where the highest numbered registers 450 must always be saved and the save-multiple-registers instruction supports 451 only sequences of consecutive registers. On such machines, define 452 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered 453 allocatable register first. */ 454 455 /* ??? Should the GR return value registers come before or after the rest 456 of the caller-save GRs? */ 457 458 #define REG_ALLOC_ORDER \ 459 { \ 460 /* Caller-saved general registers. */ \ 461 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ 462 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ 463 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ 464 R_GR (30), R_GR (31), \ 465 /* Output registers. */ \ 466 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ 467 R_GR (126), R_GR (127), \ 468 /* Caller-saved general registers, also used for return values. */ \ 469 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ 470 /* addl caller-saved general registers. */ \ 471 R_GR (2), R_GR (3), \ 472 /* Caller-saved FP registers. */ \ 473 R_FR (6), R_FR (7), \ 474 /* Caller-saved FP registers, used for parameters and return values. */ \ 475 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ 476 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ 477 /* Rotating caller-saved FP registers. */ \ 478 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ 479 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ 480 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ 481 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ 482 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ 483 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ 484 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ 485 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ 486 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ 487 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ 488 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ 489 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ 490 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ 491 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ 492 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ 493 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ 494 R_FR (126), R_FR (127), \ 495 /* Caller-saved predicate registers. */ \ 496 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ 497 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ 498 /* Rotating caller-saved predicate registers. */ \ 499 R_PR (16), R_PR (17), \ 500 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ 501 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ 502 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ 503 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ 504 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ 505 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ 506 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ 507 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ 508 /* Caller-saved branch registers. */ \ 509 R_BR (6), R_BR (7), \ 510 \ 511 /* Stacked callee-saved general registers. */ \ 512 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ 513 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ 514 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ 515 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ 516 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ 517 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ 518 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ 519 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ 520 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ 521 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ 522 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ 523 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ 524 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ 525 R_GR (108), \ 526 /* Input registers. */ \ 527 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ 528 R_GR (118), R_GR (119), \ 529 /* Callee-saved general registers. */ \ 530 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ 531 /* Callee-saved FP registers. */ \ 532 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ 533 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ 534 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ 535 R_FR (30), R_FR (31), \ 536 /* Callee-saved predicate registers. */ \ 537 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ 538 /* Callee-saved branch registers. */ \ 539 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ 540 \ 541 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ 542 R_GR (109), R_GR (110), R_GR (111), \ 543 \ 544 /* Special general registers. */ \ 545 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ 546 /* Special FP registers. */ \ 547 R_FR (0), R_FR (1), \ 548 /* Special predicate registers. */ \ 549 R_PR (0), \ 550 /* Special branch registers. */ \ 551 R_BR (0), \ 552 /* Other fixed registers. */ \ 553 FRAME_POINTER_REGNUM, \ 554 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ 555 AR_EC_REGNUM \ 556 } 557 558 /* How Values Fit in Registers */ 559 560 /* Specify the modes required to caller save a given hard regno. 561 We need to ensure floating pt regs are not saved as DImode. */ 562 563 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 564 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \ 565 : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) 566 567 /* Handling Leaf Functions */ 568 569 /* A C initializer for a vector, indexed by hard register number, which 570 contains 1 for a register that is allowable in a candidate for leaf function 571 treatment. */ 572 /* ??? This might be useful. */ 573 /* #define LEAF_REGISTERS */ 574 575 /* A C expression whose value is the register number to which REGNO should be 576 renumbered, when a function is treated as a leaf function. */ 577 /* ??? This might be useful. */ 578 /* #define LEAF_REG_REMAP(REGNO) */ 579 580 581 /* Register Classes */ 582 583 /* An enumeral type that must be defined with all the register class names as 584 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last 585 register class, followed by one more enumeral value, `LIM_REG_CLASSES', 586 which is not a register class but rather tells how many classes there 587 are. */ 588 /* ??? When compiling without optimization, it is possible for the only use of 589 a pseudo to be a parameter load from the stack with a REG_EQUIV note. 590 Regclass handles this case specially and does not assign any costs to the 591 pseudo. The pseudo then ends up using the last class before ALL_REGS. 592 Thus we must not let either PR_REGS or BR_REGS be the last class. The 593 testcase for this is gcc.c-torture/execute/va-arg-7.c. */ 594 enum reg_class 595 { 596 NO_REGS, 597 PR_REGS, 598 BR_REGS, 599 AR_M_REGS, 600 AR_I_REGS, 601 ADDL_REGS, 602 GR_REGS, 603 FP_REGS, 604 FR_REGS, 605 GR_AND_BR_REGS, 606 GR_AND_FR_REGS, 607 ALL_REGS, 608 LIM_REG_CLASSES 609 }; 610 611 #define GENERAL_REGS GR_REGS 612 613 /* The number of distinct register classes. */ 614 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 615 616 /* An initializer containing the names of the register classes as C string 617 constants. These names are used in writing some of the debugging dumps. */ 618 #define REG_CLASS_NAMES \ 619 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ 620 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \ 621 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } 622 623 /* An initializer containing the contents of the register classes, as integers 624 which are bit masks. The Nth integer specifies the contents of class N. 625 The way the integer MASK is interpreted is that register R is in the class 626 if `MASK & (1 << R)' is 1. */ 627 #define REG_CLASS_CONTENTS \ 628 { \ 629 /* NO_REGS. */ \ 630 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 631 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 632 0x00000000, 0x00000000, 0x0000 }, \ 633 /* PR_REGS. */ \ 634 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 635 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 636 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ 637 /* BR_REGS. */ \ 638 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 639 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 640 0x00000000, 0x00000000, 0x00FF }, \ 641 /* AR_M_REGS. */ \ 642 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 643 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 644 0x00000000, 0x00000000, 0x0600 }, \ 645 /* AR_I_REGS. */ \ 646 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 647 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 648 0x00000000, 0x00000000, 0x3800 }, \ 649 /* ADDL_REGS. */ \ 650 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ 651 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 652 0x00000000, 0x00000000, 0x0000 }, \ 653 /* GR_REGS. */ \ 654 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 655 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 656 0x00000000, 0x00000000, 0x0100 }, \ 657 /* FP_REGS. */ \ 658 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 659 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \ 660 0x00000000, 0x00000000, 0x0000 }, \ 661 /* FR_REGS. */ \ 662 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 663 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 664 0x00000000, 0x00000000, 0x0000 }, \ 665 /* GR_AND_BR_REGS. */ \ 666 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 667 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 668 0x00000000, 0x00000000, 0x01FF }, \ 669 /* GR_AND_FR_REGS. */ \ 670 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 671 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 672 0x00000000, 0x00000000, 0x0100 }, \ 673 /* ALL_REGS. */ \ 674 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 675 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 676 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ 677 } 678 679 /* A C expression whose value is a register class containing hard register 680 REGNO. In general there is more than one such class; choose a class which 681 is "minimal", meaning that no smaller class also contains the register. */ 682 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which 683 may call here with private (invalid) register numbers, such as 684 REG_VOLATILE. */ 685 #define REGNO_REG_CLASS(REGNO) \ 686 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \ 687 : GENERAL_REGNO_P (REGNO) ? GR_REGS \ 688 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \ 689 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \ 690 : PR_REGNO_P (REGNO) ? PR_REGS \ 691 : BR_REGNO_P (REGNO) ? BR_REGS \ 692 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ 693 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ 694 : NO_REGS) 695 696 /* A macro whose definition is the name of the class to which a valid base 697 register must belong. A base register is one used in an address which is 698 the register value plus a displacement. */ 699 #define BASE_REG_CLASS GENERAL_REGS 700 701 /* A macro whose definition is the name of the class to which a valid index 702 register must belong. An index register is one used in an address where its 703 value is either multiplied by a scale factor or added to another register 704 (as well as added to a displacement). This is needed for POST_MODIFY. */ 705 #define INDEX_REG_CLASS GENERAL_REGS 706 707 /* A C expression which is nonzero if register number NUM is suitable for use 708 as a base register in operand addresses. It may be either a suitable hard 709 register or a pseudo register that has been allocated such a hard reg. */ 710 #define REGNO_OK_FOR_BASE_P(REGNO) \ 711 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) 712 713 /* A C expression which is nonzero if register number NUM is suitable for use 714 as an index register in operand addresses. It may be either a suitable hard 715 register or a pseudo register that has been allocated such a hard reg. 716 This is needed for POST_MODIFY. */ 717 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) 718 719 /* You should define this macro to indicate to the reload phase that it may 720 need to allocate at least one register for a reload in addition to the 721 register to contain the data. Specifically, if copying X to a register 722 CLASS in MODE requires an intermediate register, you should define this 723 to return the largest register class all of whose registers can be used 724 as intermediate registers or scratch registers. */ 725 726 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 727 ia64_secondary_reload_class (CLASS, MODE, X) 728 729 /* A C expression for the maximum number of consecutive registers of 730 class CLASS needed to hold a value of mode MODE. 731 This is closely related to TARGET_HARD_REGNO_NREGS. */ 732 733 #define CLASS_MAX_NREGS(CLASS, MODE) \ 734 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ 735 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \ 736 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \ 737 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \ 738 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 739 740 /* Basic Stack Layout */ 741 742 /* Define this macro if pushing a word onto the stack moves the stack pointer 743 to a smaller address. */ 744 #define STACK_GROWS_DOWNWARD 1 745 746 /* Define this macro to nonzero if the addresses of local variable slots 747 are at negative offsets from the frame pointer. */ 748 #define FRAME_GROWS_DOWNWARD 0 749 750 /* Offset from the stack pointer register to the first location at which 751 outgoing arguments are placed. If not specified, the default value of zero 752 is used. This is the proper value for most machines. */ 753 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ 754 #define STACK_POINTER_OFFSET 16 755 756 /* Offset from the argument pointer register to the first argument's address. 757 On some machines it may depend on the data type of the function. */ 758 #define FIRST_PARM_OFFSET(FUNDECL) 0 759 760 /* A C expression whose value is RTL representing the value of the return 761 address for the frame COUNT steps up from the current frame, after the 762 prologue. */ 763 764 /* ??? Frames other than zero would likely require interpreting the frame 765 unwind info, so we don't try to support them. We would also need to define 766 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ 767 768 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 769 ia64_return_addr_rtx (COUNT, FRAME) 770 771 /* A C expression whose value is RTL representing the location of the incoming 772 return address at the beginning of any function, before the prologue. This 773 RTL is either a `REG', indicating that the return value is saved in `REG', 774 or a `MEM' representing a location in the stack. This enables DWARF2 775 unwind info for C++ EH. */ 776 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, BR_REG (0)) 777 778 /* A C expression whose value is an integer giving the offset, in bytes, from 779 the value of the stack pointer register to the top of the stack frame at the 780 beginning of any function, before the prologue. The top of the frame is 781 defined to be the value of the stack pointer in the previous frame, just 782 before the call instruction. */ 783 /* The CFA is past the red zone, not at the entry-point stack 784 pointer. */ 785 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 786 787 /* We shorten debug info by using CFA-16 as DW_AT_frame_base. */ 788 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET) 789 790 791 /* Register That Address the Stack Frame. */ 792 793 /* The register number of the stack pointer register, which must also be a 794 fixed register according to `FIXED_REGISTERS'. On most machines, the 795 hardware determines which register this is. */ 796 797 #define STACK_POINTER_REGNUM 12 798 799 /* The register number of the frame pointer register, which is used to access 800 automatic variables in the stack frame. On some machines, the hardware 801 determines which register this is. On other machines, you can choose any 802 register you wish for this purpose. */ 803 804 #define FRAME_POINTER_REGNUM 328 805 806 /* Base register for access to local variables of the function. */ 807 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79) 808 809 /* The register number of the arg pointer register, which is used to access the 810 function's argument list. */ 811 /* r0 won't otherwise be used, so put the always eliminated argument pointer 812 in it. */ 813 #define ARG_POINTER_REGNUM R_GR(0) 814 815 /* Due to the way varargs and argument spilling happens, the argument 816 pointer is not 16-byte aligned like the stack pointer. */ 817 #define INIT_EXPANDERS \ 818 do { \ 819 ia64_init_expanders (); \ 820 if (crtl->emit.regno_pointer_align) \ 821 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \ 822 } while (0) 823 824 /* Register numbers used for passing a function's static chain pointer. */ 825 /* ??? The ABI sez the static chain should be passed as a normal parameter. */ 826 #define STATIC_CHAIN_REGNUM 15 827 828 /* Eliminating the Frame Pointer and the Arg Pointer */ 829 830 /* If defined, this macro specifies a table of register pairs used to eliminate 831 unneeded registers that point into the stack frame. */ 832 833 #define ELIMINABLE_REGS \ 834 { \ 835 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 836 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 837 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 838 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 839 } 840 841 /* This macro returns the initial difference between the specified pair 842 of registers. */ 843 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 844 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) 845 846 /* Passing Function Arguments on the Stack */ 847 848 /* If defined, the maximum amount of space required for outgoing arguments will 849 be computed and placed into the variable 850 `crtl->outgoing_args_size'. */ 851 852 #define ACCUMULATE_OUTGOING_ARGS 1 853 854 855 /* Function Arguments in Registers */ 856 857 #define MAX_ARGUMENT_SLOTS 8 858 #define MAX_INT_RETURN_SLOTS 4 859 #define GR_ARG_FIRST IN_REG (0) 860 #define GR_RET_FIRST GR_REG (8) 861 #define GR_RET_LAST GR_REG (11) 862 #define FR_ARG_FIRST FR_REG (8) 863 #define FR_RET_FIRST FR_REG (8) 864 #define FR_RET_LAST FR_REG (15) 865 #define AR_ARG_FIRST OUT_REG (0) 866 867 /* A C type for declaring a variable that is used as the first argument of 868 `FUNCTION_ARG' and other related values. For some target machines, the type 869 `int' suffices and can hold the number of bytes of argument so far. */ 870 871 enum ivms_arg_type {I64, FF, FD, FG, FS, FT}; 872 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */ 873 874 typedef struct ia64_args 875 { 876 int words; /* # words of arguments so far */ 877 int int_regs; /* # GR registers used so far */ 878 int fp_regs; /* # FR registers used so far */ 879 int prototype; /* whether function prototyped */ 880 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */ 881 } CUMULATIVE_ARGS; 882 883 /* A C statement (sans semicolon) for initializing the variable CUM for the 884 state at the beginning of the argument list. */ 885 886 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 887 do { \ 888 (CUM).words = 0; \ 889 (CUM).int_regs = 0; \ 890 (CUM).fp_regs = 0; \ 891 (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME); \ 892 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 893 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 894 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 895 } while (0) 896 897 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the 898 arguments for the function being compiled. If this macro is undefined, 899 `INIT_CUMULATIVE_ARGS' is used instead. */ 900 901 /* We set prototype to true so that we never try to return a PARALLEL from 902 function_arg. */ 903 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 904 do { \ 905 (CUM).words = 0; \ 906 (CUM).int_regs = 0; \ 907 (CUM).fp_regs = 0; \ 908 (CUM).prototype = 1; \ 909 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 910 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 911 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 912 } while (0) 913 914 /* A C expression that is nonzero if REGNO is the number of a hard register in 915 which function arguments are sometimes passed. This does *not* include 916 implicit arguments such as the static chain and the structure-value address. 917 On many machines, no registers can be used for this purpose since all 918 function arguments are pushed on the stack. */ 919 #define FUNCTION_ARG_REGNO_P(REGNO) \ 920 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ 921 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) 922 923 924 /* How Large Values are Returned */ 925 926 #define DEFAULT_PCC_STRUCT_RETURN 0 927 928 929 /* Caller-Saves Register Allocation */ 930 931 /* A C expression to determine whether it is worthwhile to consider placing a 932 pseudo-register in a call-clobbered hard register and saving and restoring 933 it around each function call. The expression should be 1 when this is worth 934 doing, and 0 otherwise. 935 936 If you don't define this macro, a default is used which is good on most 937 machines: `4 * CALLS < REFS'. */ 938 /* ??? Investigate. */ 939 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ 940 941 942 /* Function Entry and Exit */ 943 944 /* Define this macro as a C expression that is nonzero if the return 945 instruction or the function epilogue ignores the value of the stack pointer; 946 in other words, if it is safe to delete an instruction to adjust the stack 947 pointer before a return from the function. */ 948 949 #define EXIT_IGNORE_STACK 1 950 951 /* Define this macro as a C expression that is nonzero for registers 952 used by the epilogue or the `return' pattern. */ 953 954 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) 955 956 /* Nonzero for registers used by the exception handling mechanism. */ 957 958 #define EH_USES(REGNO) ia64_eh_uses (REGNO) 959 960 /* Output part N of a function descriptor for DECL. For ia64, both 961 words are emitted with a single relocation, so ignore N > 0. */ 962 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ 963 do { \ 964 if ((PART) == 0) \ 965 { \ 966 if (TARGET_ILP32) \ 967 fputs ("\tdata8.ua @iplt(", FILE); \ 968 else \ 969 fputs ("\tdata16.ua @iplt(", FILE); \ 970 mark_decl_referenced (DECL); \ 971 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ 972 fputs (")\n", FILE); \ 973 if (TARGET_ILP32) \ 974 fputs ("\tdata8.ua 0\n", FILE); \ 975 } \ 976 } while (0) 977 978 /* Generating Code for Profiling. */ 979 980 /* A C statement or compound statement to output to FILE some assembler code to 981 call the profiling subroutine `mcount'. */ 982 983 #undef FUNCTION_PROFILER 984 #define FUNCTION_PROFILER(FILE, LABELNO) \ 985 ia64_output_function_profiler(FILE, LABELNO) 986 987 /* Neither hpux nor linux use profile counters. */ 988 #define NO_PROFILE_COUNTERS 1 989 990 /* Trampolines for Nested Functions. */ 991 992 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of 993 the function containing a non-local goto target. */ 994 995 #define STACK_SAVEAREA_MODE(LEVEL) \ 996 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) 997 998 /* A C expression for the size in bytes of the trampoline, as an integer. */ 999 1000 #define TRAMPOLINE_SIZE 32 1001 1002 /* Alignment required for trampolines, in bits. */ 1003 1004 #define TRAMPOLINE_ALIGNMENT 64 1005 1006 /* Addressing Modes */ 1007 1008 /* Define this macro if the machine supports post-increment addressing. */ 1009 1010 #define HAVE_POST_INCREMENT 1 1011 #define HAVE_POST_DECREMENT 1 1012 #define HAVE_POST_MODIFY_DISP 1 1013 #define HAVE_POST_MODIFY_REG 1 1014 1015 /* A C expression that is 1 if the RTX X is a constant which is a valid 1016 address. */ 1017 1018 #define CONSTANT_ADDRESS_P(X) 0 1019 1020 /* The max number of registers that can appear in a valid memory address. */ 1021 1022 #define MAX_REGS_PER_ADDRESS 2 1023 1024 1025 /* Condition Code Status */ 1026 1027 /* One some machines not all possible comparisons are defined, but you can 1028 convert an invalid comparison into a valid one. */ 1029 /* ??? Investigate. See the alpha definition. */ 1030 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ 1031 1032 1033 /* Describing Relative Costs of Operations */ 1034 1035 /* A C expression for the cost of a branch instruction. A value of 1 is the 1036 default; other values are interpreted relative to that. Used by the 1037 if-conversion code as max instruction count. */ 1038 /* ??? This requires investigation. The primary effect might be how 1039 many additional insn groups we run into, vs how good the dynamic 1040 branch predictor is. */ 1041 1042 #define BRANCH_COST(speed_p, predictable_p) 6 1043 1044 /* Define this macro as a C expression which is nonzero if accessing less than 1045 a word of memory (i.e. a `char' or a `short') is no faster than accessing a 1046 word of memory. */ 1047 1048 #define SLOW_BYTE_ACCESS 1 1049 1050 /* Define this macro if it is as good or better to call a constant function 1051 address than to call an address kept in a register. 1052 1053 Indirect function calls are more expensive that direct function calls, so 1054 don't cse function addresses. */ 1055 1056 #define NO_FUNCTION_CSE 1 1057 1058 1059 /* Dividing the output into sections. */ 1060 1061 /* A C expression whose value is a string containing the assembler operation 1062 that should precede instructions and read-only data. */ 1063 1064 #define TEXT_SECTION_ASM_OP "\t.text" 1065 1066 /* A C expression whose value is a string containing the assembler operation to 1067 identify the following data as writable initialized data. */ 1068 1069 #define DATA_SECTION_ASM_OP "\t.data" 1070 1071 /* If defined, a C expression whose value is a string containing the assembler 1072 operation to identify the following data as uninitialized global data. */ 1073 1074 #define BSS_SECTION_ASM_OP "\t.bss" 1075 1076 #define IA64_DEFAULT_GVALUE 8 1077 1078 /* Position Independent Code. */ 1079 1080 /* The register number of the register used to address a table of static data 1081 addresses in memory. */ 1082 1083 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of 1084 gen_rtx_REG (DImode, 1). */ 1085 1086 /* ??? Should we set flag_pic? Probably need to define 1087 LEGITIMIZE_PIC_OPERAND_P to make that work. */ 1088 1089 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1) 1090 1091 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is 1092 clobbered by calls. */ 1093 1094 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1 1095 1096 1097 /* The Overall Framework of an Assembler File. */ 1098 1099 /* A C string constant describing how to begin a comment in the target 1100 assembler language. The compiler assumes that the comment will end at the 1101 end of the line. */ 1102 1103 #define ASM_COMMENT_START "//" 1104 1105 /* A C string constant for text to be output before each `asm' statement or 1106 group of consecutive ones. */ 1107 1108 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n") 1109 1110 /* A C string constant for text to be output after each `asm' statement or 1111 group of consecutive ones. */ 1112 1113 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n") 1114 1115 /* Output and Generation of Labels. */ 1116 1117 /* A C statement (sans semicolon) to output to the stdio stream STREAM the 1118 assembler definition of a label named NAME. */ 1119 1120 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of 1121 why ia64_asm_output_label exists. */ 1122 1123 extern int ia64_asm_output_label; 1124 #define ASM_OUTPUT_LABEL(STREAM, NAME) \ 1125 do { \ 1126 ia64_asm_output_label = 1; \ 1127 assemble_name (STREAM, NAME); \ 1128 fputs (":\n", STREAM); \ 1129 ia64_asm_output_label = 0; \ 1130 } while (0) 1131 1132 /* Globalizing directive for a label. */ 1133 #define GLOBAL_ASM_OP "\t.global " 1134 1135 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text 1136 necessary for declaring the name of an external symbol named NAME which is 1137 referenced in this compilation but not defined. */ 1138 1139 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 1140 ia64_asm_output_external (FILE, DECL, NAME) 1141 1142 /* A C statement to store into the string STRING a label whose name is made 1143 from the string PREFIX and the number NUM. */ 1144 1145 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 1146 do { \ 1147 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ 1148 } while (0) 1149 1150 /* ??? Not sure if using a ? in the name for Intel as is safe. */ 1151 1152 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu") 1153 1154 /* A C statement to output to the stdio stream STREAM assembler code which 1155 defines (equates) the symbol NAME to have the value VALUE. */ 1156 1157 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 1158 do { \ 1159 assemble_name (STREAM, NAME); \ 1160 fputs (" = ", STREAM); \ 1161 if (ISDIGIT (*VALUE)) \ 1162 ia64_asm_output_label = 1; \ 1163 assemble_name (STREAM, VALUE); \ 1164 fputc ('\n', STREAM); \ 1165 ia64_asm_output_label = 0; \ 1166 } while (0) 1167 1168 1169 /* Macros Controlling Initialization Routines. */ 1170 1171 /* This is handled by sysv4.h. */ 1172 1173 1174 /* Output of Assembler Instructions. */ 1175 1176 /* A C initializer containing the assembler's names for the machine registers, 1177 each one as a C string constant. */ 1178 1179 #define REGISTER_NAMES \ 1180 { \ 1181 /* General registers. */ \ 1182 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 1183 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ 1184 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ 1185 "r30", "r31", \ 1186 /* Local registers. */ \ 1187 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ 1188 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ 1189 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ 1190 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ 1191 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ 1192 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ 1193 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ 1194 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ 1195 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ 1196 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ 1197 /* Input registers. */ \ 1198 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ 1199 /* Output registers. */ \ 1200 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ 1201 /* Floating-point registers. */ \ 1202 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ 1203 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ 1204 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ 1205 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ 1206 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ 1207 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ 1208 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ 1209 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ 1210 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ 1211 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ 1212 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ 1213 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ 1214 "f120","f121","f122","f123","f124","f125","f126","f127", \ 1215 /* Predicate registers. */ \ 1216 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ 1217 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ 1218 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ 1219 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ 1220 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ 1221 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ 1222 "p60", "p61", "p62", "p63", \ 1223 /* Branch registers. */ \ 1224 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ 1225 /* Frame pointer. Application registers. */ \ 1226 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ 1227 } 1228 1229 /* If defined, a C initializer for an array of structures containing a name and 1230 a register number. This macro defines additional names for hard registers, 1231 thus allowing the `asm' option in declarations to refer to registers using 1232 alternate names. */ 1233 1234 #define ADDITIONAL_REGISTER_NAMES \ 1235 { \ 1236 { "gp", R_GR (1) }, \ 1237 { "sp", R_GR (12) }, \ 1238 { "in0", IN_REG (0) }, \ 1239 { "in1", IN_REG (1) }, \ 1240 { "in2", IN_REG (2) }, \ 1241 { "in3", IN_REG (3) }, \ 1242 { "in4", IN_REG (4) }, \ 1243 { "in5", IN_REG (5) }, \ 1244 { "in6", IN_REG (6) }, \ 1245 { "in7", IN_REG (7) }, \ 1246 { "out0", OUT_REG (0) }, \ 1247 { "out1", OUT_REG (1) }, \ 1248 { "out2", OUT_REG (2) }, \ 1249 { "out3", OUT_REG (3) }, \ 1250 { "out4", OUT_REG (4) }, \ 1251 { "out5", OUT_REG (5) }, \ 1252 { "out6", OUT_REG (6) }, \ 1253 { "out7", OUT_REG (7) }, \ 1254 { "loc0", LOC_REG (0) }, \ 1255 { "loc1", LOC_REG (1) }, \ 1256 { "loc2", LOC_REG (2) }, \ 1257 { "loc3", LOC_REG (3) }, \ 1258 { "loc4", LOC_REG (4) }, \ 1259 { "loc5", LOC_REG (5) }, \ 1260 { "loc6", LOC_REG (6) }, \ 1261 { "loc7", LOC_REG (7) }, \ 1262 { "loc8", LOC_REG (8) }, \ 1263 { "loc9", LOC_REG (9) }, \ 1264 { "loc10", LOC_REG (10) }, \ 1265 { "loc11", LOC_REG (11) }, \ 1266 { "loc12", LOC_REG (12) }, \ 1267 { "loc13", LOC_REG (13) }, \ 1268 { "loc14", LOC_REG (14) }, \ 1269 { "loc15", LOC_REG (15) }, \ 1270 { "loc16", LOC_REG (16) }, \ 1271 { "loc17", LOC_REG (17) }, \ 1272 { "loc18", LOC_REG (18) }, \ 1273 { "loc19", LOC_REG (19) }, \ 1274 { "loc20", LOC_REG (20) }, \ 1275 { "loc21", LOC_REG (21) }, \ 1276 { "loc22", LOC_REG (22) }, \ 1277 { "loc23", LOC_REG (23) }, \ 1278 { "loc24", LOC_REG (24) }, \ 1279 { "loc25", LOC_REG (25) }, \ 1280 { "loc26", LOC_REG (26) }, \ 1281 { "loc27", LOC_REG (27) }, \ 1282 { "loc28", LOC_REG (28) }, \ 1283 { "loc29", LOC_REG (29) }, \ 1284 { "loc30", LOC_REG (30) }, \ 1285 { "loc31", LOC_REG (31) }, \ 1286 { "loc32", LOC_REG (32) }, \ 1287 { "loc33", LOC_REG (33) }, \ 1288 { "loc34", LOC_REG (34) }, \ 1289 { "loc35", LOC_REG (35) }, \ 1290 { "loc36", LOC_REG (36) }, \ 1291 { "loc37", LOC_REG (37) }, \ 1292 { "loc38", LOC_REG (38) }, \ 1293 { "loc39", LOC_REG (39) }, \ 1294 { "loc40", LOC_REG (40) }, \ 1295 { "loc41", LOC_REG (41) }, \ 1296 { "loc42", LOC_REG (42) }, \ 1297 { "loc43", LOC_REG (43) }, \ 1298 { "loc44", LOC_REG (44) }, \ 1299 { "loc45", LOC_REG (45) }, \ 1300 { "loc46", LOC_REG (46) }, \ 1301 { "loc47", LOC_REG (47) }, \ 1302 { "loc48", LOC_REG (48) }, \ 1303 { "loc49", LOC_REG (49) }, \ 1304 { "loc50", LOC_REG (50) }, \ 1305 { "loc51", LOC_REG (51) }, \ 1306 { "loc52", LOC_REG (52) }, \ 1307 { "loc53", LOC_REG (53) }, \ 1308 { "loc54", LOC_REG (54) }, \ 1309 { "loc55", LOC_REG (55) }, \ 1310 { "loc56", LOC_REG (56) }, \ 1311 { "loc57", LOC_REG (57) }, \ 1312 { "loc58", LOC_REG (58) }, \ 1313 { "loc59", LOC_REG (59) }, \ 1314 { "loc60", LOC_REG (60) }, \ 1315 { "loc61", LOC_REG (61) }, \ 1316 { "loc62", LOC_REG (62) }, \ 1317 { "loc63", LOC_REG (63) }, \ 1318 { "loc64", LOC_REG (64) }, \ 1319 { "loc65", LOC_REG (65) }, \ 1320 { "loc66", LOC_REG (66) }, \ 1321 { "loc67", LOC_REG (67) }, \ 1322 { "loc68", LOC_REG (68) }, \ 1323 { "loc69", LOC_REG (69) }, \ 1324 { "loc70", LOC_REG (70) }, \ 1325 { "loc71", LOC_REG (71) }, \ 1326 { "loc72", LOC_REG (72) }, \ 1327 { "loc73", LOC_REG (73) }, \ 1328 { "loc74", LOC_REG (74) }, \ 1329 { "loc75", LOC_REG (75) }, \ 1330 { "loc76", LOC_REG (76) }, \ 1331 { "loc77", LOC_REG (77) }, \ 1332 { "loc78", LOC_REG (78) }, \ 1333 { "loc79", LOC_REG (79) }, \ 1334 } 1335 1336 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and 1337 `%I' options of `asm_fprintf' (see `final.c'). */ 1338 1339 #define REGISTER_PREFIX "" 1340 #define LOCAL_LABEL_PREFIX "." 1341 #define USER_LABEL_PREFIX "" 1342 #define IMMEDIATE_PREFIX "" 1343 1344 1345 /* Output of dispatch tables. */ 1346 1347 /* This macro should be provided on machines where the addresses in a dispatch 1348 table are relative to the table's own address. */ 1349 1350 /* ??? Depends on the pointer size. */ 1351 1352 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 1353 do { \ 1354 if (CASE_VECTOR_MODE == SImode) \ 1355 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \ 1356 else \ 1357 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \ 1358 } while (0) 1359 1360 /* Jump tables only need 4 or 8 byte alignment. */ 1361 1362 #define ADDR_VEC_ALIGN(ADDR_VEC) (CASE_VECTOR_MODE == SImode ? 2 : 3) 1363 1364 1365 /* Assembler Commands for Exception Regions. */ 1366 1367 /* Select a format to encode pointers in exception handling data. CODE 1368 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1369 true if the symbol may be affected by dynamic relocations. */ 1370 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1371 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ 1372 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \ 1373 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8)) 1374 1375 /* Handle special EH pointer encodings. Absolute, pc-relative, and 1376 indirect are handled automatically. */ 1377 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 1378 do { \ 1379 const char *reltag = NULL; \ 1380 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ 1381 reltag = "@segrel("; \ 1382 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ 1383 reltag = "@gprel("; \ 1384 if (reltag) \ 1385 { \ 1386 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1387 fputs (reltag, FILE); \ 1388 assemble_name (FILE, XSTR (ADDR, 0)); \ 1389 fputc (')', FILE); \ 1390 goto DONE; \ 1391 } \ 1392 } while (0) 1393 1394 1395 /* Assembler Commands for Alignment. */ 1396 1397 /* ??? Investigate. */ 1398 1399 /* The alignment (log base 2) to put in front of LABEL, which follows 1400 a BARRIER. */ 1401 1402 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ 1403 1404 /* The desired alignment for the location counter at the beginning 1405 of a loop. */ 1406 1407 /* #define LOOP_ALIGN(LABEL) */ 1408 1409 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text 1410 section because it fails put zeros in the bytes that are skipped. */ 1411 1412 #define ASM_NO_SKIP_IN_TEXT 1 1413 1414 /* A C statement to output to the stdio stream STREAM an assembler command to 1415 advance the location counter to a multiple of 2 to the POWER bytes. */ 1416 1417 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 1418 fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) 1419 1420 1421 /* Macros Affecting all Debug Formats. */ 1422 1423 /* This is handled in sysv4.h. */ 1424 1425 1426 /* Specific Options for DBX Output. */ 1427 1428 /* This is handled by dbxelf.h. */ 1429 1430 1431 /* Open ended Hooks for DBX Output. */ 1432 1433 /* Likewise. */ 1434 1435 1436 /* File names in DBX format. */ 1437 1438 /* Likewise. */ 1439 1440 1441 /* Macros for Dwarf Output. */ 1442 1443 /* Define this macro if GCC should produce dwarf version 2 format debugging 1444 output in response to the `-g' option. */ 1445 1446 #define DWARF2_DEBUGGING_INFO 1 1447 1448 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) 1449 1450 /* Use tags for debug info labels, so that they don't break instruction 1451 bundles. This also avoids getting spurious DV warnings from the 1452 assembler. This is similar to (*targetm.asm_out.internal_label), except that we 1453 add brackets around the label. */ 1454 1455 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 1456 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM) 1457 1458 /* Use section-relative relocations for debugging offsets. Unlike other 1459 targets that fake this by putting the section VMA at 0, IA-64 has 1460 proper relocations for them. */ 1461 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, OFFSET, SECTION) \ 1462 do { \ 1463 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1464 fputs ("@secrel(", FILE); \ 1465 assemble_name (FILE, LABEL); \ 1466 if ((OFFSET) != 0) \ 1467 fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC, \ 1468 (HOST_WIDE_INT) (OFFSET)); \ 1469 fputc (')', FILE); \ 1470 } while (0) 1471 1472 /* Emit a PC-relative relocation. */ 1473 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1474 do { \ 1475 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1476 fputs ("@pcrel(", FILE); \ 1477 assemble_name (FILE, LABEL); \ 1478 fputc (')', FILE); \ 1479 } while (0) 1480 1481 /* Register Renaming Parameters. */ 1482 1483 /* A C expression that is nonzero if hard register number REGNO2 can be 1484 considered for use as a rename register for REGNO1 */ 1485 1486 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 1487 ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) 1488 1489 1490 /* Miscellaneous Parameters. */ 1491 1492 /* Flag to mark data that is in the small address area (addressable 1493 via "addl", that is, within a 2MByte offset of 0. */ 1494 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 1495 #define SYMBOL_REF_SMALL_ADDR_P(X) \ 1496 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0) 1497 1498 /* An alias for a machine mode name. This is the machine mode that elements of 1499 a jump-table should have. */ 1500 1501 #define CASE_VECTOR_MODE ptr_mode 1502 1503 /* Define as C expression which evaluates to nonzero if the tablejump 1504 instruction expects the table to contain offsets from the address of the 1505 table. */ 1506 1507 #define CASE_VECTOR_PC_RELATIVE 1 1508 1509 /* Define this macro if operations between registers with integral mode smaller 1510 than a word are always performed on the entire register. */ 1511 1512 #define WORD_REGISTER_OPERATIONS 1 1513 1514 /* Define this macro to be a C expression indicating when insns that read 1515 memory in MODE, an integral mode narrower than a word, set the bits outside 1516 of MODE to be either the sign-extension or the zero-extension of the data 1517 read. */ 1518 1519 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1520 1521 /* The maximum number of bytes that a single instruction can move quickly from 1522 memory to memory. */ 1523 #define MOVE_MAX 8 1524 1525 /* A C expression describing the value returned by a comparison operator with 1526 an integral mode and stored by a store-flag instruction (`sCOND') when the 1527 condition is true. */ 1528 1529 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */ 1530 1531 /* An alias for the machine mode for pointers. */ 1532 1533 /* ??? This would change if we had ILP32 support. */ 1534 1535 #define Pmode DImode 1536 1537 /* An alias for the machine mode used for memory references to functions being 1538 called, in `call' RTL expressions. */ 1539 1540 #define FUNCTION_MODE Pmode 1541 1542 /* A C expression for the maximum number of instructions to execute via 1543 conditional execution instructions instead of a branch. A value of 1544 BRANCH_COST+1 is the default if the machine does not use 1545 cc0, and 1 if it does use cc0. */ 1546 /* ??? Investigate. */ 1547 #define MAX_CONDITIONAL_EXECUTE 12 1548 1549 extern int ia64_final_schedule; 1550 1551 #define TARGET_UNWIND_TABLES_DEFAULT true 1552 1553 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) 1554 1555 /* This function contains machine specific function data. */ 1556 struct GTY(()) machine_function 1557 { 1558 /* The new stack pointer when unwinding from EH. */ 1559 rtx ia64_eh_epilogue_sp; 1560 1561 /* The new bsp value when unwinding from EH. */ 1562 rtx ia64_eh_epilogue_bsp; 1563 1564 /* The GP value save register. */ 1565 rtx ia64_gp_save; 1566 1567 /* The number of varargs registers to save. */ 1568 int n_varargs; 1569 1570 /* The number of the next unwind state to copy. */ 1571 int state_num; 1572 }; 1573 1574 #define DONT_USE_BUILTIN_SETJMP 1575 1576 /* Output any profiling code before the prologue. */ 1577 1578 #undef PROFILE_BEFORE_PROLOGUE 1579 #define PROFILE_BEFORE_PROLOGUE 1 1580 1581 /* Initialize library function table. */ 1582 #undef TARGET_INIT_LIBFUNCS 1583 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs 1584 1585 1586 /* Switch on code for querying unit reservations. */ 1587 #define CPU_UNITS_QUERY 1 1588 1589 /* End of ia64.h */ 1590