1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2020 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 /* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29 #ifndef RS6000_OPTS_H 30 #include "config/rs6000/rs6000-opts.h" 31 #endif 32 33 /* 128-bit floating point precision values. */ 34 #ifndef RS6000_MODES_H 35 #include "config/rs6000/rs6000-modes.h" 36 #endif 37 38 /* Definitions for the object file format. These are set at 39 compile-time. */ 40 41 #define OBJECT_XCOFF 1 42 #define OBJECT_ELF 2 43 #define OBJECT_MACHO 4 44 45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 48 49 #ifndef TARGET_AIX 50 #define TARGET_AIX 0 51 #endif 52 53 #ifndef TARGET_AIX_OS 54 #define TARGET_AIX_OS 0 55 #endif 56 57 /* Turn off TOC support if pc-relative addressing is used. */ 58 #define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL) 59 60 /* On 32-bit systems without a TOC or pc-relative addressing, we need to use 61 ADDIS/ADDI to load up the address of a symbol. */ 62 #define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL) 63 64 /* Control whether function entry points use a "dot" symbol when 65 ABI_AIX. */ 66 #define DOT_SYMBOLS 1 67 68 /* Default string to use for cpu if not specified. */ 69 #ifndef TARGET_CPU_DEFAULT 70 #define TARGET_CPU_DEFAULT ((char *)0) 71 #endif 72 73 /* If configured for PPC405, support PPC405CR Erratum77. */ 74 #ifdef CONFIG_PPC405CR 75 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 76 #else 77 #define PPC405_ERRATUM77 0 78 #endif 79 80 #ifndef SUBTARGET_DRIVER_SELF_SPECS 81 # define SUBTARGET_DRIVER_SELF_SPECS "" 82 #endif 83 84 /* Only for use in the testsuite: -mdejagnu-cpu=<value> filters out all 85 -mcpu= as well as -mtune= options then simply adds -mcpu=<value>, 86 while -mdejagnu-tune=<value> filters out all -mtune= options then 87 simply adds -mtune=<value>. 88 With older versions of Dejagnu the command line arguments you set in 89 RUNTESTFLAGS override those set in the testcases; with these options, 90 the testcase will always win. */ 91 #define DRIVER_SELF_SPECS \ 92 "%{mdejagnu-cpu=*: %<mcpu=* %<mtune=* -mcpu=%*}", \ 93 "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \ 94 "%{mdejagnu-*: %<mdejagnu-*}", \ 95 SUBTARGET_DRIVER_SELF_SPECS 96 97 #if CHECKING_P 98 #define ASM_OPT_ANY "" 99 #else 100 #define ASM_OPT_ANY " -many" 101 #endif 102 103 /* Common ASM definitions used by ASM_SPEC among the various targets for 104 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 105 provide the default assembler options if the user uses -mcpu=native, so if 106 you make changes here, make them also there. PR63177: Do not pass -mpower8 107 to the assembler if -mpower9-vector was also used. */ 108 #define ASM_CPU_SPEC \ 109 "%{mcpu=native: %(asm_cpu_native); \ 110 mcpu=power10: -mpower10; \ 111 mcpu=power9: -mpower9; \ 112 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ 113 mcpu=power7: -mpower7; \ 114 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 115 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 116 mcpu=power5+: -mpower5; \ 117 mcpu=power5: -mpower5; \ 118 mcpu=power4: -mpower4; \ 119 mcpu=power3: -mppc64; \ 120 mcpu=powerpc: -mppc; \ 121 mcpu=powerpc64: -mppc64; \ 122 mcpu=a2: -ma2; \ 123 mcpu=cell: -mcell; \ 124 mcpu=rs64: -mppc64; \ 125 mcpu=401: -mppc; \ 126 mcpu=403: -m403; \ 127 mcpu=405: -m405; \ 128 mcpu=405fp: -m405; \ 129 mcpu=440: -m440; \ 130 mcpu=440fp: -m440; \ 131 mcpu=464: -m440; \ 132 mcpu=464fp: -m440; \ 133 mcpu=476: -m476; \ 134 mcpu=476fp: -m476; \ 135 mcpu=505: -mppc; \ 136 mcpu=601: -m601; \ 137 mcpu=602: -mppc; \ 138 mcpu=603: -mppc; \ 139 mcpu=603e: -mppc; \ 140 mcpu=ec603e: -mppc; \ 141 mcpu=604: -mppc; \ 142 mcpu=604e: -mppc; \ 143 mcpu=620: -mppc64; \ 144 mcpu=630: -mppc64; \ 145 mcpu=740: -mppc; \ 146 mcpu=750: -mppc; \ 147 mcpu=G3: -mppc; \ 148 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 149 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 150 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 151 mcpu=801: -mppc; \ 152 mcpu=821: -mppc; \ 153 mcpu=823: -mppc; \ 154 mcpu=860: -mppc; \ 155 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 156 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 157 mcpu=8540: -me500; \ 158 mcpu=8548: -me500; \ 159 mcpu=e300c2: -me300; \ 160 mcpu=e300c3: -me300; \ 161 mcpu=e500mc: -me500mc; \ 162 mcpu=e500mc64: -me500mc64; \ 163 mcpu=e5500: -me5500; \ 164 mcpu=e6500: -me6500; \ 165 mcpu=titan: -mtitan; \ 166 !mcpu*: %{mpower9-vector: -mpower9; \ 167 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ 168 mvsx: -mpower7; \ 169 mpowerpc64: -mppc64;: %(asm_default)}; \ 170 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ 171 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ 172 ASM_OPT_ANY 173 174 #define CPP_DEFAULT_SPEC "" 175 176 #define ASM_DEFAULT_SPEC "" 177 #define ASM_DEFAULT_EXTRA "" 178 179 /* This macro defines names of additional specifications to put in the specs 180 that can be used in various specifications like CC1_SPEC. Its definition 181 is an initializer with a subgrouping for each command option. 182 183 Each subgrouping contains a string constant, that defines the 184 specification name, and a string constant that used by the GCC driver 185 program. 186 187 Do not define this macro if it does not need to do anything. */ 188 189 #define SUBTARGET_EXTRA_SPECS 190 191 #define EXTRA_SPECS \ 192 { "cpp_default", CPP_DEFAULT_SPEC }, \ 193 { "asm_cpu", ASM_CPU_SPEC }, \ 194 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 195 { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \ 196 { "cc1_cpu", CC1_CPU_SPEC }, \ 197 SUBTARGET_EXTRA_SPECS 198 199 /* -mcpu=native handling only makes sense with compiler running on 200 an PowerPC chip. If changing this condition, also change 201 the condition in driver-rs6000.c. */ 202 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 203 /* In driver-rs6000.c. */ 204 extern const char *host_detect_local_cpu (int argc, const char **argv); 205 #define EXTRA_SPEC_FUNCTIONS \ 206 { "local_cpu_detect", host_detect_local_cpu }, 207 #define HAVE_LOCAL_CPU_DETECT 208 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 209 210 #else 211 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 212 #endif 213 214 #ifndef CC1_CPU_SPEC 215 #ifdef HAVE_LOCAL_CPU_DETECT 216 #define CC1_CPU_SPEC \ 217 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 218 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 219 #else 220 #define CC1_CPU_SPEC "" 221 #endif 222 #endif 223 224 /* Architecture type. */ 225 226 /* Define TARGET_MFCRF if the target assembler does not support the 227 optional field operand for mfcr. */ 228 229 #ifndef HAVE_AS_MFCRF 230 #undef TARGET_MFCRF 231 #define TARGET_MFCRF 0 232 #endif 233 234 #ifndef TARGET_SECURE_PLT 235 #define TARGET_SECURE_PLT 0 236 #endif 237 238 #ifndef TARGET_CMODEL 239 #define TARGET_CMODEL CMODEL_SMALL 240 #endif 241 242 #define TARGET_32BIT (! TARGET_64BIT) 243 244 #ifndef HAVE_AS_TLS 245 #define HAVE_AS_TLS 0 246 #endif 247 248 #ifndef HAVE_AS_PLTSEQ 249 #define HAVE_AS_PLTSEQ 0 250 #endif 251 252 #ifndef TARGET_PLTSEQ 253 #define TARGET_PLTSEQ 0 254 #endif 255 256 #ifndef TARGET_LINK_STACK 257 #define TARGET_LINK_STACK 0 258 #endif 259 260 #ifndef SET_TARGET_LINK_STACK 261 #define SET_TARGET_LINK_STACK(X) do { } while (0) 262 #endif 263 264 #ifndef TARGET_FLOAT128_ENABLE_TYPE 265 #define TARGET_FLOAT128_ENABLE_TYPE 0 266 #endif 267 268 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 269 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 270 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0) 271 272 #ifdef IN_LIBGCC2 273 /* For libgcc2 we make sure this is a compile time constant */ 274 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 275 #undef TARGET_POWERPC64 276 #define TARGET_POWERPC64 1 277 #else 278 #undef TARGET_POWERPC64 279 #define TARGET_POWERPC64 0 280 #endif 281 #else 282 /* The option machinery will define this. */ 283 #endif 284 285 #define TARGET_DEFAULT (MASK_MULTIPLE) 286 287 /* Define generic processor types based upon current deployment. */ 288 #define PROCESSOR_COMMON PROCESSOR_PPC601 289 #define PROCESSOR_POWERPC PROCESSOR_PPC604 290 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 291 292 /* Define the default processor. This is overridden by other tm.h files. */ 293 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 294 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 295 296 /* Specify the dialect of assembler to use. Only new mnemonics are supported 297 starting with GCC 4.8, i.e. just one dialect, but for backwards 298 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 299 defined. */ 300 #define ASSEMBLER_DIALECT 1 301 302 /* Debug support */ 303 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 304 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 305 #define MASK_DEBUG_REG 0x04 /* debug register handling */ 306 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 307 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 308 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 309 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 310 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 311 | MASK_DEBUG_ARG \ 312 | MASK_DEBUG_REG \ 313 | MASK_DEBUG_ADDR \ 314 | MASK_DEBUG_COST \ 315 | MASK_DEBUG_TARGET \ 316 | MASK_DEBUG_BUILTIN) 317 318 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 319 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 320 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 321 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 322 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 323 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 324 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 325 326 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM 327 long double format that uses a pair of doubles, or IEEE 128-bit floating 328 point. KFmode was added as a way to represent IEEE 128-bit floating point, 329 even if the default for long double is the IBM long double format. 330 Similarly IFmode is the IBM long double format even if the default is IEEE 331 128-bit. Don't allow IFmode if -msoft-float. */ 332 #define FLOAT128_IEEE_P(MODE) \ 333 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 334 && ((MODE) == TFmode || (MODE) == TCmode)) \ 335 || ((MODE) == KFmode) || ((MODE) == KCmode)) 336 337 #define FLOAT128_IBM_P(MODE) \ 338 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 339 && ((MODE) == TFmode || (MODE) == TCmode)) \ 340 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) 341 342 /* Helper macros to say whether a 128-bit floating point type can go in a 343 single vector register, or whether it needs paired scalar values. */ 344 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) 345 346 #define FLOAT128_2REG_P(MODE) \ 347 (FLOAT128_IBM_P (MODE) \ 348 || ((MODE) == TDmode) \ 349 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) 350 351 /* Return true for floating point that does not use a vector register. */ 352 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ 353 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) 354 355 /* Describe the vector unit used for arithmetic operations. */ 356 extern enum rs6000_vector rs6000_vector_unit[]; 357 358 #define VECTOR_UNIT_NONE_P(MODE) \ 359 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 360 361 #define VECTOR_UNIT_VSX_P(MODE) \ 362 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 363 364 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 365 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 366 367 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 368 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 369 370 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 371 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 372 (int)VECTOR_VSX, \ 373 (int)VECTOR_P8_VECTOR)) 374 375 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 376 altivec (VMX) or VSX vector instructions. P8 vector support is upwards 377 compatible, so allow it as well, rather than changing all of the uses of the 378 macro. */ 379 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 380 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 381 (int)VECTOR_ALTIVEC, \ 382 (int)VECTOR_P8_VECTOR)) 383 384 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 385 same unit as the vector unit we are using, but we may want to migrate to 386 using VSX style loads even for types handled by altivec. */ 387 extern enum rs6000_vector rs6000_vector_mem[]; 388 389 #define VECTOR_MEM_NONE_P(MODE) \ 390 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 391 392 #define VECTOR_MEM_VSX_P(MODE) \ 393 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 394 395 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ 396 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 397 398 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 399 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 400 401 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 402 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 403 (int)VECTOR_VSX, \ 404 (int)VECTOR_P8_VECTOR)) 405 406 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 407 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 408 (int)VECTOR_ALTIVEC, \ 409 (int)VECTOR_P8_VECTOR)) 410 411 /* Return the alignment of a given vector type, which is set based on the 412 vector unit use. VSX for instance can load 32 or 64 bit aligned words 413 without problems, while Altivec requires 128-bit aligned vectors. */ 414 extern int rs6000_vector_align[]; 415 416 #define VECTOR_ALIGN(MODE) \ 417 ((rs6000_vector_align[(MODE)] != 0) \ 418 ? rs6000_vector_align[(MODE)] \ 419 : (int)GET_MODE_BITSIZE ((MODE))) 420 421 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 422 with scalar instructions. */ 423 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 424 425 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 426 with the ISA 3.0 MFVSRLD instructions. */ 427 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) 428 429 /* Alignment options for fields in structures for sub-targets following 430 AIX-like ABI. 431 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 432 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 433 434 Override the macro definitions when compiling libobjc to avoid undefined 435 reference to rs6000_alignment_flags due to library's use of GCC alignment 436 macros which use the macros below. */ 437 438 #ifndef IN_TARGET_LIBS 439 #define MASK_ALIGN_POWER 0x00000000 440 #define MASK_ALIGN_NATURAL 0x00000001 441 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 442 #else 443 #define TARGET_ALIGN_NATURAL 0 444 #endif 445 446 /* We use values 126..128 to pick the appropriate long double type (IFmode, 447 KFmode, TFmode). */ 448 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) 449 #define TARGET_IEEEQUAD rs6000_ieeequad 450 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 451 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 452 453 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 454 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ 455 #define TARGET_FCFID (TARGET_POWERPC64 \ 456 || TARGET_PPC_GPOPT /* 970/power4 */ \ 457 || TARGET_POPCNTB /* ISA 2.02 */ \ 458 || TARGET_CMPB /* ISA 2.05 */ \ 459 || TARGET_POPCNTD) /* ISA 2.06 */ 460 461 #define TARGET_FCTIDZ TARGET_FCFID 462 #define TARGET_STFIWX TARGET_PPC_GFXOPT 463 #define TARGET_LFIWAX TARGET_CMPB 464 #define TARGET_LFIWZX TARGET_POPCNTD 465 #define TARGET_FCFIDS TARGET_POPCNTD 466 #define TARGET_FCFIDU TARGET_POPCNTD 467 #define TARGET_FCFIDUS TARGET_POPCNTD 468 #define TARGET_FCTIDUZ TARGET_POPCNTD 469 #define TARGET_FCTIWUZ TARGET_POPCNTD 470 #define TARGET_CTZ TARGET_MODULO 471 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) 472 #define TARGET_MADDLD TARGET_MODULO 473 474 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 475 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 476 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 477 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 478 && TARGET_POWERPC64) 479 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 480 && TARGET_POWERPC64) 481 482 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ 483 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT 484 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) 485 486 /* This wants to be set for p8 and newer. On p7, overlapping unaligned 487 loads are slow. */ 488 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX 489 490 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 491 in power7, so conditionalize them on p8 features. TImode syncs need quad 492 memory support. */ 493 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 494 || TARGET_QUAD_MEMORY_ATOMIC \ 495 || TARGET_DIRECT_MOVE) 496 497 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 498 499 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 500 to allocate the SDmode stack slot to get the value into the proper location 501 in the register. */ 502 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 503 504 /* ISA 3.0 has new min/max functions that don't need fast math that are being 505 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct 506 answers if the arguments are not in the normal range. */ 507 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 508 && (TARGET_P9_MINMAX || !flag_trapping_math)) 509 510 /* In switching from using target_flags to using rs6000_isa_flags, the options 511 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 512 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 513 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 514 #define MASK_CMPB OPTION_MASK_CMPB 515 #define MASK_CRYPTO OPTION_MASK_CRYPTO 516 #define MASK_DFP OPTION_MASK_DFP 517 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 518 #define MASK_DLMZB OPTION_MASK_DLMZB 519 #define MASK_EABI OPTION_MASK_EABI 520 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD 521 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW 522 #define MASK_FPRND OPTION_MASK_FPRND 523 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION 524 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 525 #define MASK_HTM OPTION_MASK_HTM 526 #define MASK_ISEL OPTION_MASK_ISEL 527 #define MASK_MFCRF OPTION_MASK_MFCRF 528 #define MASK_MMA OPTION_MASK_MMA 529 #define MASK_MULHW OPTION_MASK_MULHW 530 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE 531 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 532 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 533 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR 534 #define MASK_P9_MISC OPTION_MASK_P9_MISC 535 #define MASK_POPCNTB OPTION_MASK_POPCNTB 536 #define MASK_POPCNTD OPTION_MASK_POPCNTD 537 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 538 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 539 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 540 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 541 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 542 #define MASK_UPDATE OPTION_MASK_UPDATE 543 #define MASK_VSX OPTION_MASK_VSX 544 #define MASK_POWER10 OPTION_MASK_POWER10 545 546 #ifndef IN_LIBGCC2 547 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 548 #endif 549 550 #ifdef TARGET_64BIT 551 #define MASK_64BIT OPTION_MASK_64BIT 552 #endif 553 554 #ifdef TARGET_LITTLE_ENDIAN 555 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 556 #endif 557 558 #ifdef TARGET_REGNAMES 559 #define MASK_REGNAMES OPTION_MASK_REGNAMES 560 #endif 561 562 #ifdef TARGET_PROTOTYPE 563 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 564 #endif 565 566 #ifdef TARGET_MODULO 567 #define RS6000_BTM_MODULO OPTION_MASK_MODULO 568 #endif 569 570 571 /* For power systems, we want to enable Altivec and VSX builtins even if the 572 user did not use -maltivec or -mvsx to allow the builtins to be used inside 573 of #pragma GCC target or the target attribute to change the code level for a 574 given system. */ 575 576 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ 577 || TARGET_PPC_GPOPT /* 970/power4 */ \ 578 || TARGET_POPCNTB /* ISA 2.02 */ \ 579 || TARGET_CMPB /* ISA 2.05 */ \ 580 || TARGET_POPCNTD /* ISA 2.06 */ \ 581 || TARGET_ALTIVEC \ 582 || TARGET_VSX \ 583 || TARGET_HARD_FLOAT) 584 585 /* E500 cores only support plain "sync", not lwsync. */ 586 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 587 || rs6000_cpu == PROCESSOR_PPC8548) 588 589 590 /* Which machine supports the various reciprocal estimate instructions. */ 591 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) 592 593 #define TARGET_FRE (TARGET_HARD_FLOAT \ 594 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 595 596 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 597 && TARGET_PPC_GFXOPT) 598 599 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ 600 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 601 602 /* Macro to say whether we can do optimizations where we need to do parts of 603 the calculation in 64-bit GPRs and then is transfered to the vector 604 registers. */ 605 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ 606 && TARGET_P8_VECTOR \ 607 && TARGET_POWERPC64) 608 609 /* Whether the various reciprocal divide/square root estimate instructions 610 exist, and whether we should automatically generate code for the instruction 611 by default. */ 612 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 613 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 614 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 615 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 616 617 extern unsigned char rs6000_recip_bits[]; 618 619 #define RS6000_RECIP_HAVE_RE_P(MODE) \ 620 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 621 622 #define RS6000_RECIP_AUTO_RE_P(MODE) \ 623 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 624 625 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 626 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 627 628 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 629 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 630 631 /* The default CPU for TARGET_OPTION_OVERRIDE. */ 632 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 633 634 /* Target pragma. */ 635 #define REGISTER_TARGET_PRAGMAS() do { \ 636 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 637 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 638 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 639 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 640 } while (0) 641 642 /* Target #defines. */ 643 #define TARGET_CPU_CPP_BUILTINS() \ 644 rs6000_cpu_cpp_builtins (pfile) 645 646 /* Target CPU versions for D. */ 647 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions 648 649 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 650 we're compiling for. Some configurations may need to override it. */ 651 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 652 do \ 653 { \ 654 if (BYTES_BIG_ENDIAN) \ 655 { \ 656 builtin_define ("__BIG_ENDIAN__"); \ 657 builtin_define ("_BIG_ENDIAN"); \ 658 builtin_assert ("machine=bigendian"); \ 659 } \ 660 else \ 661 { \ 662 builtin_define ("__LITTLE_ENDIAN__"); \ 663 builtin_define ("_LITTLE_ENDIAN"); \ 664 builtin_assert ("machine=littleendian"); \ 665 } \ 666 } \ 667 while (0) 668 669 /* Target machine storage layout. */ 670 671 /* Define this macro if it is advisable to hold scalars in registers 672 in a wider mode than that declared by the program. In such cases, 673 the value is constrained to be within the bounds of the declared 674 type, but kept valid in the wider mode. The signedness of the 675 extension may differ from that of the type. */ 676 677 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 678 if (GET_MODE_CLASS (MODE) == MODE_INT \ 679 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ 680 (MODE) = TARGET_32BIT ? SImode : DImode; 681 682 /* Define this if most significant bit is lowest numbered 683 in instructions that operate on numbered bit-fields. */ 684 /* That is true on RS/6000. */ 685 #define BITS_BIG_ENDIAN 1 686 687 /* Define this if most significant byte of a word is the lowest numbered. */ 688 /* That is true on RS/6000. */ 689 #define BYTES_BIG_ENDIAN 1 690 691 /* Define this if most significant word of a multiword number is lowest 692 numbered. 693 694 For RS/6000 we can decide arbitrarily since there are no machine 695 instructions for them. Might as well be consistent with bits and bytes. */ 696 #define WORDS_BIG_ENDIAN 1 697 698 /* This says that for the IBM long double the larger magnitude double 699 comes first. It's really a two element double array, and arrays 700 don't index differently between little- and big-endian. */ 701 #define LONG_DOUBLE_LARGE_FIRST 1 702 703 #define MAX_BITS_PER_WORD 64 704 705 /* Width of a word, in units (bytes). */ 706 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 707 #ifdef IN_LIBGCC2 708 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 709 #else 710 #define MIN_UNITS_PER_WORD 4 711 #endif 712 #define UNITS_PER_FP_WORD 8 713 #define UNITS_PER_ALTIVEC_WORD 16 714 #define UNITS_PER_VSX_WORD 16 715 716 /* Type used for ptrdiff_t, as a string used in a declaration. */ 717 #define PTRDIFF_TYPE "int" 718 719 /* Type used for size_t, as a string used in a declaration. */ 720 #define SIZE_TYPE "long unsigned int" 721 722 /* Type used for wchar_t, as a string used in a declaration. */ 723 #define WCHAR_TYPE "short unsigned int" 724 725 /* Width of wchar_t in bits. */ 726 #define WCHAR_TYPE_SIZE 16 727 728 /* A C expression for the size in bits of the type `short' on the 729 target machine. If you don't define this, the default is half a 730 word. (If this would be less than one storage unit, it is 731 rounded up to one unit.) */ 732 #define SHORT_TYPE_SIZE 16 733 734 /* A C expression for the size in bits of the type `int' on the 735 target machine. If you don't define this, the default is one 736 word. */ 737 #define INT_TYPE_SIZE 32 738 739 /* A C expression for the size in bits of the type `long' on the 740 target machine. If you don't define this, the default is one 741 word. */ 742 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 743 744 /* A C expression for the size in bits of the type `long long' on the 745 target machine. If you don't define this, the default is two 746 words. */ 747 #define LONG_LONG_TYPE_SIZE 64 748 749 /* A C expression for the size in bits of the type `float' on the 750 target machine. If you don't define this, the default is one 751 word. */ 752 #define FLOAT_TYPE_SIZE 32 753 754 /* A C expression for the size in bits of the type `double' on the 755 target machine. If you don't define this, the default is two 756 words. */ 757 #define DOUBLE_TYPE_SIZE 64 758 759 /* A C expression for the size in bits of the type `long double' on the target 760 machine. If you don't define this, the default is two words. */ 761 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 762 763 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 764 #define WIDEST_HARDWARE_FP_SIZE 64 765 766 /* Width in bits of a pointer. 767 See also the macro `Pmode' defined below. */ 768 extern unsigned rs6000_pointer_size; 769 #define POINTER_SIZE rs6000_pointer_size 770 771 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 772 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 773 774 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 775 #define STACK_BOUNDARY \ 776 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 777 ? 64 : 128) 778 779 /* Allocation boundary (in *bits*) for the code of a function. */ 780 #define FUNCTION_BOUNDARY 32 781 782 /* No data type is required to be aligned rounder than this. Warning, if 783 BIGGEST_ALIGNMENT is changed, then this may be an ABI break. An example 784 of where this can break an ABI is in GLIBC's struct _Unwind_Exception. */ 785 #define BIGGEST_ALIGNMENT 128 786 787 /* Alignment of field after `int : 0' in a structure. */ 788 #define EMPTY_FIELD_BOUNDARY 32 789 790 /* Every structure's size must be a multiple of this. */ 791 #define STRUCTURE_SIZE_BOUNDARY 8 792 793 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 794 #define PCC_BITFIELD_TYPE_MATTERS 1 795 796 enum data_align { align_abi, align_opt, align_both }; 797 798 /* A C expression to compute the alignment for a variables in the 799 local store. TYPE is the data type, and ALIGN is the alignment 800 that the object would ordinarily have. */ 801 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 802 rs6000_data_alignment (TYPE, ALIGN, align_both) 803 804 /* Make arrays of chars word-aligned for the same reasons. */ 805 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 806 rs6000_data_alignment (TYPE, ALIGN, align_opt) 807 808 /* Align vectors to 128 bits. */ 809 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 810 rs6000_data_alignment (TYPE, ALIGN, align_abi) 811 812 /* Nonzero if move instructions will actually fail to work 813 when given unaligned data. */ 814 #define STRICT_ALIGNMENT 0 815 816 /* Standard register usage. */ 817 818 /* Number of actual hardware registers. 819 The hardware registers are assigned numbers for the compiler 820 from 0 to just below FIRST_PSEUDO_REGISTER. 821 All registers that the compiler knows about must be given numbers, 822 even those that are not normally considered general registers. 823 824 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 825 a count register, a link register, and 8 condition register fields, 826 which we view here as separate registers. AltiVec adds 32 vector 827 registers and a VRsave register. 828 829 In addition, the difference between the frame and argument pointers is 830 a function of the number of registers saved, so we need to have a 831 register for AP that will later be eliminated in favor of SP or FP. 832 This is a normal register, but it is fixed. 833 834 We also create a pseudo register for float/int conversions, that will 835 really represent the memory location used. It is represented here as 836 a register, in order to work around problems in allocating stack storage 837 in inline functions. 838 839 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 840 pointer, which is eventually eliminated in favor of SP or FP. */ 841 842 #define FIRST_PSEUDO_REGISTER 111 843 844 /* Use standard DWARF numbering for DWARF debugging information. */ 845 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) 846 847 /* Use gcc hard register numbering for eh_frame. */ 848 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 849 850 /* Map register numbers held in the call frame info that gcc has 851 collected using DWARF_FRAME_REGNUM to those that should be output in 852 .debug_frame and .eh_frame. */ 853 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 854 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1) 855 856 /* 1 for registers that have pervasive standard uses 857 and are not available for the register allocator. 858 859 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 860 as a local register; for all other OS's r2 is the TOC pointer. 861 862 On System V implementations, r13 is fixed and not available for use. */ 863 864 #define FIXED_REGISTERS \ 865 {/* GPRs */ \ 866 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 868 /* FPRs */ \ 869 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 870 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 871 /* VRs */ \ 872 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 873 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 874 /* lr ctr ca ap */ \ 875 0, 0, 1, 1, \ 876 /* cr0..cr7 */ \ 877 0, 0, 0, 0, 0, 0, 0, 0, \ 878 /* vrsave vscr sfp */ \ 879 1, 1, 1 \ 880 } 881 882 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 883 the entire set of `FIXED_REGISTERS' be included. 884 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 885 This macro is optional. If not specified, it defaults to the value 886 of `CALL_USED_REGISTERS'. */ 887 888 #define CALL_REALLY_USED_REGISTERS \ 889 {/* GPRs */ \ 890 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 892 /* FPRs */ \ 893 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 894 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 895 /* VRs */ \ 896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 898 /* lr ctr ca ap */ \ 899 1, 1, 1, 1, \ 900 /* cr0..cr7 */ \ 901 1, 1, 0, 0, 0, 1, 1, 1, \ 902 /* vrsave vscr sfp */ \ 903 0, 0, 0 \ 904 } 905 906 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 907 908 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 909 #define FIRST_SAVED_FP_REGNO (14+32) 910 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 911 912 /* List the order in which to allocate registers. Each register must be 913 listed once, even those in FIXED_REGISTERS. 914 915 We allocate in the following order: 916 fp0 (not saved or used for anything) 917 fp13 - fp2 (not saved; incoming fp arg registers) 918 fp1 (not saved; return value) 919 fp31 - fp14 (saved; order given to save least number) 920 cr7, cr5 (not saved or special) 921 cr6 (not saved, but used for vector operations) 922 cr1 (not saved, but used for FP operations) 923 cr0 (not saved, but used for arithmetic operations) 924 cr4, cr3, cr2 (saved) 925 r9 (not saved; best for TImode) 926 r10, r8-r4 (not saved; highest first for less conflict with params) 927 r3 (not saved; return value register) 928 r11 (not saved; later alloc to help shrink-wrap) 929 r0 (not saved; cannot be base reg) 930 r31 - r13 (saved; order given to save least number) 931 r12 (not saved; if used for DImode or DFmode would use r13) 932 ctr (not saved; when we have the choice ctr is better) 933 lr (saved) 934 r1, r2, ap, ca (fixed) 935 v0 - v1 (not saved or used for anything) 936 v13 - v3 (not saved; incoming vector arg registers) 937 v2 (not saved; incoming vector arg reg; return value) 938 v19 - v14 (not saved or used for anything) 939 v31 - v20 (saved; order given to save least number) 940 vrsave, vscr (fixed) 941 sfp (fixed) 942 */ 943 944 #if FIXED_R2 == 1 945 #define MAYBE_R2_AVAILABLE 946 #define MAYBE_R2_FIXED 2, 947 #else 948 #define MAYBE_R2_AVAILABLE 2, 949 #define MAYBE_R2_FIXED 950 #endif 951 952 #if FIXED_R13 == 1 953 #define EARLY_R12 12, 954 #define LATE_R12 955 #else 956 #define EARLY_R12 957 #define LATE_R12 12, 958 #endif 959 960 #define REG_ALLOC_ORDER \ 961 {32, \ 962 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 963 /* not use fr14 which is a saved register. */ \ 964 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 965 33, \ 966 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 967 50, 49, 48, 47, 46, \ 968 100, 107, 105, 106, 101, 104, 103, 102, \ 969 MAYBE_R2_AVAILABLE \ 970 9, 10, 8, 7, 6, 5, 4, \ 971 3, EARLY_R12 11, 0, \ 972 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 973 18, 17, 16, 15, 14, 13, LATE_R12 \ 974 97, 96, \ 975 1, MAYBE_R2_FIXED 99, 98, \ 976 /* AltiVec registers. */ \ 977 64, 65, \ 978 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ 979 66, \ 980 83, 82, 81, 80, 79, 78, \ 981 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ 982 108, 109, \ 983 110 \ 984 } 985 986 /* True if register is floating-point. */ 987 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 988 989 /* True if register is a condition register. */ 990 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 991 992 /* True if register is a condition register, but not cr0. */ 993 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 994 995 /* True if register is an integer register. */ 996 #define INT_REGNO_P(N) \ 997 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 998 999 /* True if register is the CA register. */ 1000 #define CA_REGNO_P(N) ((N) == CA_REGNO) 1001 1002 /* True if register is an AltiVec register. */ 1003 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1004 1005 /* True if register is a VSX register. */ 1006 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1007 1008 /* Alternate name for any vector register supporting floating point, no matter 1009 which instruction set(s) are available. */ 1010 #define VFLOAT_REGNO_P(N) \ 1011 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1012 1013 /* Alternate name for any vector register supporting integer, no matter which 1014 instruction set(s) are available. */ 1015 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1016 1017 /* Alternate name for any vector register supporting logical operations, no 1018 matter which instruction set(s) are available. Allow GPRs as well as the 1019 vector registers. */ 1020 #define VLOGICAL_REGNO_P(N) \ 1021 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1022 || (TARGET_VSX && FP_REGNO_P (N))) \ 1023 1024 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1025 enough space to account for vectors in FP regs. However, TFmode/TDmode 1026 should not use VSX instructions to do a caller save. */ 1027 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1028 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ 1029 ? (MODE) \ 1030 : TARGET_VSX \ 1031 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1032 && FP_REGNO_P (REGNO) \ 1033 ? V2DFmode \ 1034 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ 1035 ? DFmode \ 1036 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ 1037 ? DImode \ 1038 : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) 1039 1040 #define VSX_VECTOR_MODE(MODE) \ 1041 ((MODE) == V4SFmode \ 1042 || (MODE) == V2DFmode) \ 1043 1044 /* Modes that are not vectors, but require vector alignment. Treat these like 1045 vectors in terms of loads and stores. */ 1046 #define VECTOR_ALIGNMENT_P(MODE) \ 1047 (FLOAT128_VECTOR_P (MODE) || (MODE) == POImode || (MODE) == PXImode) 1048 1049 #define ALTIVEC_VECTOR_MODE(MODE) \ 1050 ((MODE) == V16QImode \ 1051 || (MODE) == V8HImode \ 1052 || (MODE) == V4SFmode \ 1053 || (MODE) == V4SImode \ 1054 || VECTOR_ALIGNMENT_P (MODE)) 1055 1056 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1057 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1058 || (MODE) == V2DImode || (MODE) == V1TImode) 1059 1060 /* Post-reload, we can't use any new AltiVec registers, as we already 1061 emitted the vrsave mask. */ 1062 1063 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1064 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1065 1066 /* Specify the cost of a branch insn; roughly the number of extra insns that 1067 should be added to avoid a branch. 1068 1069 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1070 unscheduled conditional branch. */ 1071 1072 #define BRANCH_COST(speed_p, predictable_p) 3 1073 1074 /* Override BRANCH_COST heuristic which empirically produces worse 1075 performance for removing short circuiting from the logical ops. */ 1076 1077 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1078 1079 /* Specify the registers used for certain standard purposes. 1080 The values of these macros are register numbers. */ 1081 1082 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1083 /* #define PC_REGNUM */ 1084 1085 /* Register to use for pushing function arguments. */ 1086 #define STACK_POINTER_REGNUM 1 1087 1088 /* Base register for access to local variables of the function. */ 1089 #define HARD_FRAME_POINTER_REGNUM 31 1090 1091 /* Base register for access to local variables of the function. */ 1092 #define FRAME_POINTER_REGNUM 110 1093 1094 /* Base register for access to arguments of the function. */ 1095 #define ARG_POINTER_REGNUM 99 1096 1097 /* Place to put static chain when calling a function that requires it. */ 1098 #define STATIC_CHAIN_REGNUM 11 1099 1100 /* Base register for access to thread local storage variables. */ 1101 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) 1102 1103 1104 /* Define the classes of registers for register constraints in the 1105 machine description. Also define ranges of constants. 1106 1107 One of the classes must always be named ALL_REGS and include all hard regs. 1108 If there is more than one class, another class must be named NO_REGS 1109 and contain no registers. 1110 1111 The name GENERAL_REGS must be the name of a class (or an alias for 1112 another name such as ALL_REGS). This is the class of registers 1113 that is allowed by "g" or "r" in a register constraint. 1114 Also, registers outside this class are allocated only when 1115 instructions express preferences for them. 1116 1117 The classes must be numbered in nondecreasing order; that is, 1118 a larger-numbered class must never be contained completely 1119 in a smaller-numbered class. 1120 1121 For any two classes, it is very desirable that there be another 1122 class that represents their union. */ 1123 1124 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1125 condition registers, plus three special registers, CTR, and the link 1126 register. AltiVec adds a vector register class. VSX registers overlap the 1127 FPR registers and the Altivec registers. 1128 1129 However, r0 is special in that it cannot be used as a base register. 1130 So make a class for registers valid as base registers. 1131 1132 Also, cr0 is the only condition code register that can be used in 1133 arithmetic insns, so make a separate class for it. */ 1134 1135 enum reg_class 1136 { 1137 NO_REGS, 1138 BASE_REGS, 1139 GENERAL_REGS, 1140 FLOAT_REGS, 1141 ALTIVEC_REGS, 1142 VSX_REGS, 1143 VRSAVE_REGS, 1144 VSCR_REGS, 1145 GEN_OR_FLOAT_REGS, 1146 GEN_OR_VSX_REGS, 1147 LINK_REGS, 1148 CTR_REGS, 1149 LINK_OR_CTR_REGS, 1150 SPECIAL_REGS, 1151 SPEC_OR_GEN_REGS, 1152 CR0_REGS, 1153 CR_REGS, 1154 NON_FLOAT_REGS, 1155 CA_REGS, 1156 ALL_REGS, 1157 LIM_REG_CLASSES 1158 }; 1159 1160 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1161 1162 /* Give names of register classes as strings for dump file. */ 1163 1164 #define REG_CLASS_NAMES \ 1165 { \ 1166 "NO_REGS", \ 1167 "BASE_REGS", \ 1168 "GENERAL_REGS", \ 1169 "FLOAT_REGS", \ 1170 "ALTIVEC_REGS", \ 1171 "VSX_REGS", \ 1172 "VRSAVE_REGS", \ 1173 "VSCR_REGS", \ 1174 "GEN_OR_FLOAT_REGS", \ 1175 "GEN_OR_VSX_REGS", \ 1176 "LINK_REGS", \ 1177 "CTR_REGS", \ 1178 "LINK_OR_CTR_REGS", \ 1179 "SPECIAL_REGS", \ 1180 "SPEC_OR_GEN_REGS", \ 1181 "CR0_REGS", \ 1182 "CR_REGS", \ 1183 "NON_FLOAT_REGS", \ 1184 "CA_REGS", \ 1185 "ALL_REGS" \ 1186 } 1187 1188 /* Define which registers fit in which classes. 1189 This is an initializer for a vector of HARD_REG_SET 1190 of length N_REG_CLASSES. */ 1191 1192 #define REG_CLASS_CONTENTS \ 1193 { \ 1194 /* NO_REGS. */ \ 1195 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1196 /* BASE_REGS. */ \ 1197 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ 1198 /* GENERAL_REGS. */ \ 1199 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ 1200 /* FLOAT_REGS. */ \ 1201 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ 1202 /* ALTIVEC_REGS. */ \ 1203 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ 1204 /* VSX_REGS. */ \ 1205 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1206 /* VRSAVE_REGS. */ \ 1207 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ 1208 /* VSCR_REGS. */ \ 1209 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ 1210 /* GEN_OR_FLOAT_REGS. */ \ 1211 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ 1212 /* GEN_OR_VSX_REGS. */ \ 1213 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ 1214 /* LINK_REGS. */ \ 1215 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ 1216 /* CTR_REGS. */ \ 1217 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ 1218 /* LINK_OR_CTR_REGS. */ \ 1219 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ 1220 /* SPECIAL_REGS. */ \ 1221 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ 1222 /* SPEC_OR_GEN_REGS. */ \ 1223 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ 1224 /* CR0_REGS. */ \ 1225 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ 1226 /* CR_REGS. */ \ 1227 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ 1228 /* NON_FLOAT_REGS. */ \ 1229 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ 1230 /* CA_REGS. */ \ 1231 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ 1232 /* ALL_REGS. */ \ 1233 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ 1234 } 1235 1236 /* The same information, inverted: 1237 Return the class number of the smallest class containing 1238 reg number REGNO. This could be a conditional expression 1239 or could index an array. */ 1240 1241 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1242 1243 #define REGNO_REG_CLASS(REGNO) \ 1244 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ 1245 rs6000_regno_regclass[(REGNO)]) 1246 1247 /* Register classes for various constraints that are based on the target 1248 switches. */ 1249 enum r6000_reg_class_enum { 1250 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1251 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1252 RS6000_CONSTRAINT_v, /* Altivec registers */ 1253 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1254 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ 1255 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1256 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1257 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ 1258 RS6000_CONSTRAINT_MAX 1259 }; 1260 1261 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1262 1263 /* The class value for index registers, and the one for base regs. */ 1264 #define INDEX_REG_CLASS GENERAL_REGS 1265 #define BASE_REG_CLASS BASE_REGS 1266 1267 /* Return whether a given register class can hold VSX objects. */ 1268 #define VSX_REG_CLASS_P(CLASS) \ 1269 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1270 1271 /* Return whether a given register class targets general purpose registers. */ 1272 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1273 1274 /* Given an rtx X being reloaded into a reg required to be 1275 in class CLASS, return the class of reg to actually use. 1276 In general this is just CLASS; but on some machines 1277 in some cases it is preferable to use a more restrictive class. 1278 1279 On the RS/6000, we have to return NO_REGS when we want to reload a 1280 floating-point CONST_DOUBLE to force it to be copied to memory. 1281 1282 We also don't want to reload integer values into floating-point 1283 registers if we can at all help it. In fact, this can 1284 cause reload to die, if it tries to generate a reload of CTR 1285 into a FP register and discovers it doesn't have the memory location 1286 required. 1287 1288 ??? Would it be a good idea to have reload do the converse, that is 1289 try to reload floating modes into FP registers if possible? 1290 */ 1291 1292 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1293 rs6000_preferred_reload_class_ptr (X, CLASS) 1294 1295 /* Return the register class of a scratch register needed to copy IN into 1296 or out of a register in CLASS in MODE. If it can be done directly, 1297 NO_REGS is returned. */ 1298 1299 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1300 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1301 1302 /* Return the maximum number of consecutive registers 1303 needed to represent mode MODE in a register of class CLASS. 1304 1305 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1306 a single reg is enough for two words, unless we have VSX, where the FP 1307 registers can hold 128 bits. */ 1308 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1309 1310 /* Stack layout; function entry, exit and calling. */ 1311 1312 /* Define this if pushing a word on the stack 1313 makes the stack pointer a smaller address. */ 1314 #define STACK_GROWS_DOWNWARD 1 1315 1316 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1317 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1318 1319 /* Define this to nonzero if the nominal address of the stack frame 1320 is at the high-address end of the local variables; 1321 that is, each additional local variable allocated 1322 goes at a more negative offset in the frame. 1323 1324 On the RS/6000, we grow upwards, from the area after the outgoing 1325 arguments. */ 1326 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1327 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1328 1329 /* Size of the fixed area on the stack */ 1330 #define RS6000_SAVE_AREA \ 1331 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1332 << (TARGET_64BIT ? 1 : 0)) 1333 1334 /* Stack offset for toc save slot. */ 1335 #define RS6000_TOC_SAVE_SLOT \ 1336 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1337 1338 /* Align an address */ 1339 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) 1340 1341 /* Offset within stack frame to start allocating local variables at. 1342 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1343 first local allocated. Otherwise, it is the offset to the BEGINNING 1344 of the first local allocated. 1345 1346 On the RS/6000, the frame pointer is the same as the stack pointer, 1347 except for dynamic allocations. So we start after the fixed area and 1348 outgoing parameter area. 1349 1350 If the function uses dynamic stack space (CALLS_ALLOCA is set), that 1351 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the 1352 sizes of the fixed area and the parameter area must be a multiple of 1353 STACK_BOUNDARY. */ 1354 1355 #define RS6000_STARTING_FRAME_OFFSET \ 1356 (cfun->calls_alloca \ 1357 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ 1358 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ 1359 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1360 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1361 + RS6000_SAVE_AREA)) 1362 1363 /* Offset from the stack pointer register to an item dynamically 1364 allocated on the stack, e.g., by `alloca'. 1365 1366 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1367 length of the outgoing arguments. The default is correct for most 1368 machines. See `function.c' for details. 1369 1370 This value must be a multiple of STACK_BOUNDARY (hard coded in 1371 `emit-rtl.c'). */ 1372 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1373 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ 1374 + STACK_POINTER_OFFSET, \ 1375 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) 1376 1377 /* If we generate an insn to push BYTES bytes, 1378 this says how many the stack pointer really advances by. 1379 On RS/6000, don't define this because there are no push insns. */ 1380 /* #define PUSH_ROUNDING(BYTES) */ 1381 1382 /* Offset of first parameter from the argument pointer register value. 1383 On the RS/6000, we define the argument pointer to the start of the fixed 1384 area. */ 1385 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1386 1387 /* Offset from the argument pointer register value to the top of 1388 stack. This is different from FIRST_PARM_OFFSET because of the 1389 register save area. */ 1390 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1391 1392 /* Define this if stack space is still allocated for a parameter passed 1393 in a register. The value is the number of bytes allocated to this 1394 area. */ 1395 #define REG_PARM_STACK_SPACE(FNDECL) \ 1396 rs6000_reg_parm_stack_space ((FNDECL), false) 1397 1398 /* Define this macro if space guaranteed when compiling a function body 1399 is different to space required when making a call, a situation that 1400 can arise with K&R style function definitions. */ 1401 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1402 rs6000_reg_parm_stack_space ((FNDECL), true) 1403 1404 /* Define this if the above stack space is to be considered part of the 1405 space allocated by the caller. */ 1406 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1407 1408 /* This is the difference between the logical top of stack and the actual sp. 1409 1410 For the RS/6000, sp points past the fixed area. */ 1411 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1412 1413 /* Define this if the maximum size of all the outgoing args is to be 1414 accumulated and pushed during the prologue. The amount can be 1415 found in the variable crtl->outgoing_args_size. */ 1416 #define ACCUMULATE_OUTGOING_ARGS 1 1417 1418 /* Define how to find the value returned by a library function 1419 assuming the value has mode MODE. */ 1420 1421 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1422 1423 /* DRAFT_V4_STRUCT_RET defaults off. */ 1424 #define DRAFT_V4_STRUCT_RET 0 1425 1426 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1427 #define DEFAULT_PCC_STRUCT_RETURN 0 1428 1429 /* Mode of stack savearea. 1430 FUNCTION is VOIDmode because calling convention maintains SP. 1431 BLOCK needs Pmode for SP. 1432 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1433 #define STACK_SAVEAREA_MODE(LEVEL) \ 1434 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1435 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1436 1437 /* Minimum and maximum general purpose registers used to hold arguments. */ 1438 #define GP_ARG_MIN_REG 3 1439 #define GP_ARG_MAX_REG 10 1440 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1441 1442 /* Minimum and maximum floating point registers used to hold arguments. */ 1443 #define FP_ARG_MIN_REG 33 1444 #define FP_ARG_AIX_MAX_REG 45 1445 #define FP_ARG_V4_MAX_REG 40 1446 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1447 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1448 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1449 1450 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1451 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1452 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1453 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1454 1455 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1456 #define AGGR_ARG_NUM_REG 8 1457 1458 /* Return registers */ 1459 #define GP_ARG_RETURN GP_ARG_MIN_REG 1460 #define FP_ARG_RETURN FP_ARG_MIN_REG 1461 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1462 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1463 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1464 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ 1465 ? (ALTIVEC_ARG_RETURN \ 1466 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ 1467 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1468 1469 /* Flags for the call/call_value rtl operations set up by function_arg */ 1470 #define CALL_NORMAL 0x00000000 /* no special processing */ 1471 /* Bits in 0x00000001 are unused. */ 1472 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1473 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1474 #define CALL_LONG 0x00000008 /* always call indirect */ 1475 #define CALL_LIBCALL 0x00000010 /* libcall */ 1476 1477 /* Identify PLT sequence for rs6000_pltseq_template. */ 1478 enum rs6000_pltseq_enum { 1479 RS6000_PLTSEQ_TOCSAVE, 1480 RS6000_PLTSEQ_PLT16_HA, 1481 RS6000_PLTSEQ_PLT16_LO, 1482 RS6000_PLTSEQ_MTCTR, 1483 RS6000_PLTSEQ_PLT_PCREL34 1484 }; 1485 1486 #define IS_V4_FP_ARGS(OP) \ 1487 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0) 1488 1489 /* We don't have prologue and epilogue functions to save/restore 1490 everything for most ABIs. */ 1491 #define WORLD_SAVE_P(INFO) 0 1492 1493 /* 1 if N is a possible register number for a function value 1494 as seen by the caller. 1495 1496 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1497 #define FUNCTION_VALUE_REGNO_P(N) \ 1498 ((N) == GP_ARG_RETURN \ 1499 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ 1500 && TARGET_HARD_FLOAT) \ 1501 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ 1502 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1503 1504 /* 1 if N is a possible register number for function argument passing. 1505 On RS/6000, these are r3-r10 and fp1-fp13. 1506 On AltiVec, v2 - v13 are used for passing vectors. */ 1507 #define FUNCTION_ARG_REGNO_P(N) \ 1508 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ 1509 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ 1510 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1511 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ 1512 && TARGET_HARD_FLOAT)) 1513 1514 /* Define a data type for recording info about an argument list 1515 during the scan of that argument list. This data type should 1516 hold all necessary information about the function itself 1517 and about the args processed so far, enough to enable macros 1518 such as FUNCTION_ARG to determine where the next arg should go. 1519 1520 On the RS/6000, this is a structure. The first element is the number of 1521 total argument words, the second is used to store the next 1522 floating-point register number, and the third says how many more args we 1523 have prototype types for. 1524 1525 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1526 the next available GP register, `fregno' is the next available FP 1527 register, and `words' is the number of words used on the stack. 1528 1529 The varargs/stdarg support requires that this structure's size 1530 be a multiple of sizeof(int). */ 1531 1532 typedef struct rs6000_args 1533 { 1534 int words; /* # words used for passing GP registers */ 1535 int fregno; /* next available FP register */ 1536 int vregno; /* next available AltiVec register */ 1537 int nargs_prototype; /* # args left in the current prototype */ 1538 int prototype; /* Whether a prototype was defined */ 1539 int stdarg; /* Whether function is a stdarg function. */ 1540 int call_cookie; /* Do special things for this call */ 1541 int sysv_gregno; /* next available GP register */ 1542 int intoffset; /* running offset in struct (darwin64) */ 1543 int use_stack; /* any part of struct on stack (darwin64) */ 1544 int floats_in_gpr; /* count of SFmode floats taking up 1545 GPR space (darwin64) */ 1546 int named; /* false for varargs params */ 1547 int escapes; /* if function visible outside tu */ 1548 int libcall; /* If this is a compiler generated call. */ 1549 } CUMULATIVE_ARGS; 1550 1551 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1552 for a call to a function whose data type is FNTYPE. 1553 For a library call, FNTYPE is 0. */ 1554 1555 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1556 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1557 N_NAMED_ARGS, FNDECL, VOIDmode) 1558 1559 /* Similar, but when scanning the definition of a procedure. We always 1560 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1561 1562 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1563 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1564 1000, current_function_decl, VOIDmode) 1565 1566 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1567 1568 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1569 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1570 0, NULL_TREE, MODE) 1571 1572 #define PAD_VARARGS_DOWN \ 1573 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 1574 1575 /* Output assembler code to FILE to increment profiler label # LABELNO 1576 for profiling a function entry. */ 1577 1578 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1579 output_function_profiler ((FILE), (LABELNO)); 1580 1581 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1582 the stack pointer does not matter. No definition is equivalent to 1583 always zero. 1584 1585 On the RS/6000, this is nonzero because we can restore the stack from 1586 its backpointer, which we maintain. */ 1587 #define EXIT_IGNORE_STACK 1 1588 1589 /* Define this macro as a C expression that is nonzero for registers 1590 that are used by the epilogue or the return' pattern. The stack 1591 and frame pointer registers are already be assumed to be used as 1592 needed. */ 1593 1594 #define EPILOGUE_USES(REGNO) \ 1595 ((reload_completed && (REGNO) == LR_REGNO) \ 1596 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1597 || (crtl->calls_eh_return \ 1598 && TARGET_AIX \ 1599 && (REGNO) == 2)) 1600 1601 1602 /* Length in units of the trampoline for entering a nested function. */ 1603 1604 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1605 1606 /* Definitions for __builtin_return_address and __builtin_frame_address. 1607 __builtin_return_address (0) should give link register (LR_REGNO), enable 1608 this. */ 1609 /* This should be uncommented, so that the link register is used, but 1610 currently this would result in unmatched insns and spilling fixed 1611 registers so we'll leave it for another day. When these problems are 1612 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1613 (mrs) */ 1614 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1615 1616 /* Number of bytes into the frame return addresses can be found. See 1617 rs6000_stack_info in rs6000.c for more information on how the different 1618 abi's store the return address. */ 1619 #define RETURN_ADDRESS_OFFSET \ 1620 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1621 1622 /* The current return address is in the link register. The return address 1623 of anything farther back is accessed normally at an offset of 8 from the 1624 frame pointer. */ 1625 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1626 (rs6000_return_addr (COUNT, FRAME)) 1627 1628 1629 /* Definitions for register eliminations. 1630 1631 We have two registers that can be eliminated on the RS/6000. First, the 1632 frame pointer register can often be eliminated in favor of the stack 1633 pointer register. Secondly, the argument pointer register can always be 1634 eliminated; it is replaced with either the stack or frame pointer. 1635 1636 In addition, we use the elimination mechanism to see if r30 is needed 1637 Initially we assume that it isn't. If it is, we spill it. This is done 1638 by making it an eliminable register. We replace it with itself so that 1639 if it isn't needed, then existing uses won't be modified. */ 1640 1641 /* This is an array of structures. Each structure initializes one pair 1642 of eliminable registers. The "from" register number is given first, 1643 followed by "to". Eliminations of the same "from" register are listed 1644 in order of preference. */ 1645 #define ELIMINABLE_REGS \ 1646 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1647 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1648 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1649 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1650 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1651 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1652 1653 /* Define the offset between two registers, one to be eliminated, and the other 1654 its replacement, at the start of a routine. */ 1655 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1656 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1657 1658 /* Addressing modes, and classification of registers for them. */ 1659 1660 #define HAVE_PRE_DECREMENT 1 1661 #define HAVE_PRE_INCREMENT 1 1662 #define HAVE_PRE_MODIFY_DISP 1 1663 #define HAVE_PRE_MODIFY_REG 1 1664 1665 /* Macros to check register numbers against specific register classes. */ 1666 1667 /* These assume that REGNO is a hard or pseudo reg number. 1668 They give nonzero only if REGNO is a hard reg of the suitable class 1669 or a pseudo reg currently allocated to a suitable hard reg. 1670 Since they use reg_renumber, they are safe only once reg_renumber 1671 has been allocated, which happens in reginfo.c during register 1672 allocation. */ 1673 1674 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1675 (HARD_REGISTER_NUM_P (REGNO) \ 1676 ? (REGNO) <= 31 \ 1677 || (REGNO) == ARG_POINTER_REGNUM \ 1678 || (REGNO) == FRAME_POINTER_REGNUM \ 1679 : (reg_renumber[REGNO] >= 0 \ 1680 && (reg_renumber[REGNO] <= 31 \ 1681 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1682 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1683 1684 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1685 (HARD_REGISTER_NUM_P (REGNO) \ 1686 ? ((REGNO) > 0 && (REGNO) <= 31) \ 1687 || (REGNO) == ARG_POINTER_REGNUM \ 1688 || (REGNO) == FRAME_POINTER_REGNUM \ 1689 : (reg_renumber[REGNO] > 0 \ 1690 && (reg_renumber[REGNO] <= 31 \ 1691 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1692 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1693 1694 /* Nonzero if X is a hard reg that can be used as an index 1695 or if it is a pseudo reg in the non-strict case. */ 1696 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1697 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1698 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1699 1700 /* Nonzero if X is a hard reg that can be used as a base reg 1701 or if it is a pseudo reg in the non-strict case. */ 1702 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1703 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1704 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1705 1706 1707 /* Maximum number of registers that can appear in a valid memory address. */ 1708 1709 #define MAX_REGS_PER_ADDRESS 2 1710 1711 /* Recognize any constant value that is a valid address. */ 1712 1713 #define CONSTANT_ADDRESS_P(X) \ 1714 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \ 1715 || CONST_INT_P (X) || GET_CODE (X) == CONST \ 1716 || GET_CODE (X) == HIGH) 1717 1718 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1719 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1720 && EASY_VECTOR_15((n) >> 1) \ 1721 && ((n) & 1) == 0) 1722 1723 #define EASY_VECTOR_MSB(n,mode) \ 1724 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ 1725 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1726 1727 1728 #define FIND_BASE_TERM rs6000_find_base_term 1729 1730 /* The register number of the register used to address a table of 1731 static data addresses in memory. In some cases this register is 1732 defined by a processor's "application binary interface" (ABI). 1733 When this macro is defined, RTL is generated for this register 1734 once, as with the stack pointer and frame pointer registers. If 1735 this macro is not defined, it is up to the machine-dependent files 1736 to allocate such a register (if necessary). */ 1737 1738 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1739 #define PIC_OFFSET_TABLE_REGNUM \ 1740 (TARGET_TOC ? TOC_REGISTER \ 1741 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ 1742 : INVALID_REGNUM) 1743 1744 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1745 1746 /* Define this macro if the register defined by 1747 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1748 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1749 1750 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1751 1752 /* A C expression that is nonzero if X is a legitimate immediate 1753 operand on the target machine when generating position independent 1754 code. You can assume that X satisfies `CONSTANT_P', so you need 1755 not check this. You can also assume FLAG_PIC is true, so you need 1756 not check it either. You need not define this macro if all 1757 constants (including `SYMBOL_REF') can be immediate operands when 1758 generating position independent code. */ 1759 1760 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1761 1762 /* Specify the machine mode that this machine uses 1763 for the index in the tablejump instruction. */ 1764 #define CASE_VECTOR_MODE SImode 1765 1766 /* Define as C expression which evaluates to nonzero if the tablejump 1767 instruction expects the table to contain offsets from the address of the 1768 table. 1769 Do not define this if the table should contain absolute addresses. */ 1770 #define CASE_VECTOR_PC_RELATIVE 1 1771 1772 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1773 #define DEFAULT_SIGNED_CHAR 0 1774 1775 /* An integer expression for the size in bits of the largest integer machine 1776 mode that should actually be used. */ 1777 1778 /* Allow pairs of registers to be used, which is the intent of the default. */ 1779 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1780 1781 /* Max number of bytes we can move from memory to memory 1782 in one reasonably fast instruction. */ 1783 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1784 #define MAX_MOVE_MAX 8 1785 1786 /* Nonzero if access to memory by bytes is no faster than for words. 1787 Also nonzero if doing byte operations (specifically shifts) in registers 1788 is undesirable. */ 1789 #define SLOW_BYTE_ACCESS 1 1790 1791 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1792 will either zero-extend or sign-extend. The value of this macro should 1793 be the code that says which one of the two operations is implicitly 1794 done, UNKNOWN if none. */ 1795 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1796 1797 /* Define if loading short immediate values into registers sign extends. */ 1798 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 1799 1800 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1801 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1802 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) 1803 1804 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of 1805 zero. The hardware instructions added in Power9 and the sequences using 1806 popcount return 32 or 64. */ 1807 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1808 (TARGET_CTZ || TARGET_POPCNTD \ 1809 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ 1810 : ((VALUE) = -1, 2)) 1811 1812 /* Specify the machine mode that pointers have. 1813 After generation of rtl, the compiler makes no further distinction 1814 between pointers and any other objects of this machine mode. */ 1815 extern scalar_int_mode rs6000_pmode; 1816 #define Pmode rs6000_pmode 1817 1818 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1819 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1820 1821 /* Mode of a function address in a call instruction (for indexing purposes). 1822 Doesn't matter on RS/6000. */ 1823 #define FUNCTION_MODE SImode 1824 1825 /* Define this if addresses of constant functions 1826 shouldn't be put through pseudo regs where they can be cse'd. 1827 Desirable on machines where ordinary constants are expensive 1828 but a CALL with constant address is cheap. */ 1829 #define NO_FUNCTION_CSE 1 1830 1831 /* Define this to be nonzero if shift instructions ignore all but the low-order 1832 few bits. 1833 1834 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1835 have been dropped from the PowerPC architecture. */ 1836 #define SHIFT_COUNT_TRUNCATED 0 1837 1838 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 1839 should be adjusted to reflect any required changes. This macro is used when 1840 there is some systematic length adjustment required that would be difficult 1841 to express in the length attribute. 1842 1843 In the PowerPC, we use this to adjust the length of an instruction if one or 1844 more prefixed instructions are generated, using the attribute 1845 num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the 1846 hardware requires that a prefied instruciton does not cross a 64-byte 1847 boundary. This means the compiler has to assume the length of the first 1848 prefixed instruction is 12 bytes instead of 8 bytes. Since the length is 1849 already set for the non-prefixed instruction, we just need to udpate for the 1850 difference. */ 1851 1852 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ 1853 (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH)) 1854 1855 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 1856 COMPARE, return the mode to be used for the comparison. For 1857 floating-point, CCFPmode should be used. CCUNSmode should be used 1858 for unsigned comparisons. CCEQmode should be used when we are 1859 doing an inequality comparison on the result of a 1860 comparison. CCmode should be used in all other cases. */ 1861 1862 #define SELECT_CC_MODE(OP,X,Y) \ 1863 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 1864 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1865 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1866 ? CCEQmode : CCmode)) 1867 1868 /* Can the condition code MODE be safely reversed? This is safe in 1869 all cases on this port, because at present it doesn't use the 1870 trapping FP comparisons (fcmpo). */ 1871 #define REVERSIBLE_CC_MODE(MODE) 1 1872 1873 /* Given a condition code and a mode, return the inverse condition. */ 1874 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1875 1876 1877 /* Target cpu costs. */ 1878 1879 struct processor_costs { 1880 const int mulsi; /* cost of SImode multiplication. */ 1881 const int mulsi_const; /* cost of SImode multiplication by constant. */ 1882 const int mulsi_const9; /* cost of SImode mult by short constant. */ 1883 const int muldi; /* cost of DImode multiplication. */ 1884 const int divsi; /* cost of SImode division. */ 1885 const int divdi; /* cost of DImode division. */ 1886 const int fp; /* cost of simple SFmode and DFmode insns. */ 1887 const int dmul; /* cost of DFmode multiplication (and fmadd). */ 1888 const int sdiv; /* cost of SFmode division (fdivs). */ 1889 const int ddiv; /* cost of DFmode division (fdiv). */ 1890 const int cache_line_size; /* cache line size in bytes. */ 1891 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 1892 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 1893 const int simultaneous_prefetches; /* number of parallel prefetch 1894 operations. */ 1895 const int sfdf_convert; /* cost of SF->DF conversion. */ 1896 }; 1897 1898 extern const struct processor_costs *rs6000_cost; 1899 1900 /* Control the assembler format that we output. */ 1901 1902 /* A C string constant describing how to begin a comment in the target 1903 assembler language. The compiler assumes that the comment will end at 1904 the end of the line. */ 1905 #define ASM_COMMENT_START " #" 1906 1907 /* Flag to say the TOC is initialized */ 1908 extern int toc_initialized; 1909 1910 /* Macro to output a special constant pool entry. Go to WIN if we output 1911 it. Otherwise, it is written the usual way. 1912 1913 On the RS/6000, toc entries are handled this way. */ 1914 1915 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1916 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1917 { \ 1918 output_toc (FILE, X, LABELNO, MODE); \ 1919 goto WIN; \ 1920 } \ 1921 } 1922 1923 #ifdef HAVE_GAS_WEAK 1924 #define RS6000_WEAK 1 1925 #else 1926 #define RS6000_WEAK 0 1927 #endif 1928 1929 #if RS6000_WEAK 1930 /* Used in lieu of ASM_WEAKEN_LABEL. */ 1931 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 1932 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) 1933 #endif 1934 1935 #if HAVE_GAS_WEAKREF 1936 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 1937 do \ 1938 { \ 1939 fputs ("\t.weakref\t", (FILE)); \ 1940 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1941 fputs (", ", (FILE)); \ 1942 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1943 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1944 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1945 { \ 1946 fputs ("\n\t.weakref\t.", (FILE)); \ 1947 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1948 fputs (", .", (FILE)); \ 1949 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1950 } \ 1951 fputc ('\n', (FILE)); \ 1952 } while (0) 1953 #endif 1954 1955 /* This implements the `alias' attribute. */ 1956 #undef ASM_OUTPUT_DEF_FROM_DECLS 1957 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 1958 do \ 1959 { \ 1960 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 1961 const char *name = IDENTIFIER_POINTER (TARGET); \ 1962 if (TREE_CODE (DECL) == FUNCTION_DECL \ 1963 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1964 { \ 1965 if (TREE_PUBLIC (DECL)) \ 1966 { \ 1967 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1968 { \ 1969 fputs ("\t.globl\t.", FILE); \ 1970 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1971 putc ('\n', FILE); \ 1972 } \ 1973 } \ 1974 else if (TARGET_XCOFF) \ 1975 { \ 1976 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1977 { \ 1978 fputs ("\t.lglobl\t.", FILE); \ 1979 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1980 putc ('\n', FILE); \ 1981 fputs ("\t.lglobl\t", FILE); \ 1982 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1983 putc ('\n', FILE); \ 1984 } \ 1985 } \ 1986 fputs ("\t.set\t.", FILE); \ 1987 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1988 fputs (",.", FILE); \ 1989 RS6000_OUTPUT_BASENAME (FILE, name); \ 1990 fputc ('\n', FILE); \ 1991 } \ 1992 ASM_OUTPUT_DEF (FILE, alias, name); \ 1993 } \ 1994 while (0) 1995 1996 #define TARGET_ASM_FILE_START rs6000_file_start 1997 1998 /* Output to assembler file text saying following lines 1999 may contain character constants, extra white space, comments, etc. */ 2000 2001 #define ASM_APP_ON "" 2002 2003 /* Output to assembler file text saying following lines 2004 no longer contain unusual constructs. */ 2005 2006 #define ASM_APP_OFF "" 2007 2008 /* How to refer to registers in assembler output. 2009 This sequence is indexed by compiler's hard-register-number (see above). */ 2010 2011 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2012 2013 #define REGISTER_NAMES \ 2014 { \ 2015 &rs6000_reg_names[ 0][0], /* r0 */ \ 2016 &rs6000_reg_names[ 1][0], /* r1 */ \ 2017 &rs6000_reg_names[ 2][0], /* r2 */ \ 2018 &rs6000_reg_names[ 3][0], /* r3 */ \ 2019 &rs6000_reg_names[ 4][0], /* r4 */ \ 2020 &rs6000_reg_names[ 5][0], /* r5 */ \ 2021 &rs6000_reg_names[ 6][0], /* r6 */ \ 2022 &rs6000_reg_names[ 7][0], /* r7 */ \ 2023 &rs6000_reg_names[ 8][0], /* r8 */ \ 2024 &rs6000_reg_names[ 9][0], /* r9 */ \ 2025 &rs6000_reg_names[10][0], /* r10 */ \ 2026 &rs6000_reg_names[11][0], /* r11 */ \ 2027 &rs6000_reg_names[12][0], /* r12 */ \ 2028 &rs6000_reg_names[13][0], /* r13 */ \ 2029 &rs6000_reg_names[14][0], /* r14 */ \ 2030 &rs6000_reg_names[15][0], /* r15 */ \ 2031 &rs6000_reg_names[16][0], /* r16 */ \ 2032 &rs6000_reg_names[17][0], /* r17 */ \ 2033 &rs6000_reg_names[18][0], /* r18 */ \ 2034 &rs6000_reg_names[19][0], /* r19 */ \ 2035 &rs6000_reg_names[20][0], /* r20 */ \ 2036 &rs6000_reg_names[21][0], /* r21 */ \ 2037 &rs6000_reg_names[22][0], /* r22 */ \ 2038 &rs6000_reg_names[23][0], /* r23 */ \ 2039 &rs6000_reg_names[24][0], /* r24 */ \ 2040 &rs6000_reg_names[25][0], /* r25 */ \ 2041 &rs6000_reg_names[26][0], /* r26 */ \ 2042 &rs6000_reg_names[27][0], /* r27 */ \ 2043 &rs6000_reg_names[28][0], /* r28 */ \ 2044 &rs6000_reg_names[29][0], /* r29 */ \ 2045 &rs6000_reg_names[30][0], /* r30 */ \ 2046 &rs6000_reg_names[31][0], /* r31 */ \ 2047 \ 2048 &rs6000_reg_names[32][0], /* fr0 */ \ 2049 &rs6000_reg_names[33][0], /* fr1 */ \ 2050 &rs6000_reg_names[34][0], /* fr2 */ \ 2051 &rs6000_reg_names[35][0], /* fr3 */ \ 2052 &rs6000_reg_names[36][0], /* fr4 */ \ 2053 &rs6000_reg_names[37][0], /* fr5 */ \ 2054 &rs6000_reg_names[38][0], /* fr6 */ \ 2055 &rs6000_reg_names[39][0], /* fr7 */ \ 2056 &rs6000_reg_names[40][0], /* fr8 */ \ 2057 &rs6000_reg_names[41][0], /* fr9 */ \ 2058 &rs6000_reg_names[42][0], /* fr10 */ \ 2059 &rs6000_reg_names[43][0], /* fr11 */ \ 2060 &rs6000_reg_names[44][0], /* fr12 */ \ 2061 &rs6000_reg_names[45][0], /* fr13 */ \ 2062 &rs6000_reg_names[46][0], /* fr14 */ \ 2063 &rs6000_reg_names[47][0], /* fr15 */ \ 2064 &rs6000_reg_names[48][0], /* fr16 */ \ 2065 &rs6000_reg_names[49][0], /* fr17 */ \ 2066 &rs6000_reg_names[50][0], /* fr18 */ \ 2067 &rs6000_reg_names[51][0], /* fr19 */ \ 2068 &rs6000_reg_names[52][0], /* fr20 */ \ 2069 &rs6000_reg_names[53][0], /* fr21 */ \ 2070 &rs6000_reg_names[54][0], /* fr22 */ \ 2071 &rs6000_reg_names[55][0], /* fr23 */ \ 2072 &rs6000_reg_names[56][0], /* fr24 */ \ 2073 &rs6000_reg_names[57][0], /* fr25 */ \ 2074 &rs6000_reg_names[58][0], /* fr26 */ \ 2075 &rs6000_reg_names[59][0], /* fr27 */ \ 2076 &rs6000_reg_names[60][0], /* fr28 */ \ 2077 &rs6000_reg_names[61][0], /* fr29 */ \ 2078 &rs6000_reg_names[62][0], /* fr30 */ \ 2079 &rs6000_reg_names[63][0], /* fr31 */ \ 2080 \ 2081 &rs6000_reg_names[64][0], /* vr0 */ \ 2082 &rs6000_reg_names[65][0], /* vr1 */ \ 2083 &rs6000_reg_names[66][0], /* vr2 */ \ 2084 &rs6000_reg_names[67][0], /* vr3 */ \ 2085 &rs6000_reg_names[68][0], /* vr4 */ \ 2086 &rs6000_reg_names[69][0], /* vr5 */ \ 2087 &rs6000_reg_names[70][0], /* vr6 */ \ 2088 &rs6000_reg_names[71][0], /* vr7 */ \ 2089 &rs6000_reg_names[72][0], /* vr8 */ \ 2090 &rs6000_reg_names[73][0], /* vr9 */ \ 2091 &rs6000_reg_names[74][0], /* vr10 */ \ 2092 &rs6000_reg_names[75][0], /* vr11 */ \ 2093 &rs6000_reg_names[76][0], /* vr12 */ \ 2094 &rs6000_reg_names[77][0], /* vr13 */ \ 2095 &rs6000_reg_names[78][0], /* vr14 */ \ 2096 &rs6000_reg_names[79][0], /* vr15 */ \ 2097 &rs6000_reg_names[80][0], /* vr16 */ \ 2098 &rs6000_reg_names[81][0], /* vr17 */ \ 2099 &rs6000_reg_names[82][0], /* vr18 */ \ 2100 &rs6000_reg_names[83][0], /* vr19 */ \ 2101 &rs6000_reg_names[84][0], /* vr20 */ \ 2102 &rs6000_reg_names[85][0], /* vr21 */ \ 2103 &rs6000_reg_names[86][0], /* vr22 */ \ 2104 &rs6000_reg_names[87][0], /* vr23 */ \ 2105 &rs6000_reg_names[88][0], /* vr24 */ \ 2106 &rs6000_reg_names[89][0], /* vr25 */ \ 2107 &rs6000_reg_names[90][0], /* vr26 */ \ 2108 &rs6000_reg_names[91][0], /* vr27 */ \ 2109 &rs6000_reg_names[92][0], /* vr28 */ \ 2110 &rs6000_reg_names[93][0], /* vr29 */ \ 2111 &rs6000_reg_names[94][0], /* vr30 */ \ 2112 &rs6000_reg_names[95][0], /* vr31 */ \ 2113 \ 2114 &rs6000_reg_names[96][0], /* lr */ \ 2115 &rs6000_reg_names[97][0], /* ctr */ \ 2116 &rs6000_reg_names[98][0], /* ca */ \ 2117 &rs6000_reg_names[99][0], /* ap */ \ 2118 \ 2119 &rs6000_reg_names[100][0], /* cr0 */ \ 2120 &rs6000_reg_names[101][0], /* cr1 */ \ 2121 &rs6000_reg_names[102][0], /* cr2 */ \ 2122 &rs6000_reg_names[103][0], /* cr3 */ \ 2123 &rs6000_reg_names[104][0], /* cr4 */ \ 2124 &rs6000_reg_names[105][0], /* cr5 */ \ 2125 &rs6000_reg_names[106][0], /* cr6 */ \ 2126 &rs6000_reg_names[107][0], /* cr7 */ \ 2127 \ 2128 &rs6000_reg_names[108][0], /* vrsave */ \ 2129 &rs6000_reg_names[109][0], /* vscr */ \ 2130 \ 2131 &rs6000_reg_names[110][0] /* sfp */ \ 2132 } 2133 2134 /* Table of additional register names to use in user input. */ 2135 2136 #define ADDITIONAL_REGISTER_NAMES \ 2137 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2138 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2139 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2140 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2141 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2142 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2143 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2144 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2145 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2146 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2147 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2148 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2149 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2150 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2151 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2152 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2153 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ 2154 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ 2155 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ 2156 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ 2157 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ 2158 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ 2159 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ 2160 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ 2161 {"vrsave", 108}, {"vscr", 109}, \ 2162 /* no additional names for: lr, ctr, ap */ \ 2163 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ 2164 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ 2165 {"cc", 100},{"sp", 1}, {"toc", 2}, \ 2166 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2167 {"xer", 98}, \ 2168 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2169 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2170 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2171 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2172 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2173 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2174 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2175 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2176 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2177 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ 2178 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ 2179 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ 2180 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ 2181 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ 2182 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ 2183 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ 2184 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ 2185 } 2186 2187 /* This is how to output an element of a case-vector that is relative. */ 2188 2189 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2190 do { char buf[100]; \ 2191 fputs ("\t.long ", FILE); \ 2192 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2193 assemble_name (FILE, buf); \ 2194 putc ('-', FILE); \ 2195 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2196 assemble_name (FILE, buf); \ 2197 putc ('\n', FILE); \ 2198 } while (0) 2199 2200 /* This is how to output an assembler line 2201 that says to advance the location counter 2202 to a multiple of 2**LOG bytes. */ 2203 2204 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2205 if ((LOG) != 0) \ 2206 fprintf (FILE, "\t.align %d\n", (LOG)) 2207 2208 /* How to align the given loop. */ 2209 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2210 2211 /* Alignment guaranteed by __builtin_malloc. */ 2212 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2213 However, specifying the stronger guarantee currently leads to 2214 a regression in SPEC CPU2006 437.leslie3d. The stronger 2215 guarantee should be implemented here once that's fixed. */ 2216 #define MALLOC_ABI_ALIGNMENT (64) 2217 2218 /* Pick up the return address upon entry to a procedure. Used for 2219 dwarf2 unwind information. This also enables the table driven 2220 mechanism. */ 2221 2222 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2223 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2224 2225 /* Describe how we implement __builtin_eh_return. */ 2226 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2227 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2228 2229 /* Print operand X (an rtx) in assembler syntax to file FILE. 2230 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2231 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2232 2233 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2234 2235 /* Define which CODE values are valid. */ 2236 2237 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2238 2239 /* Print a memory address as an operand to reference that memory location. */ 2240 2241 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2242 2243 /* For switching between functions with different target attributes. */ 2244 #define SWITCHABLE_TARGET 1 2245 2246 /* uncomment for disabling the corresponding default options */ 2247 /* #define MACHINE_no_sched_interblock */ 2248 /* #define MACHINE_no_sched_speculative */ 2249 /* #define MACHINE_no_sched_speculative_load */ 2250 2251 /* General flags. */ 2252 extern int frame_pointer_needed; 2253 2254 /* Classification of the builtin functions as to which switches enable the 2255 builtin, and what attributes it should have. We used to use the target 2256 flags macros, but we've run out of bits, so we now map the options into new 2257 settings used here. */ 2258 2259 /* Builtin operand count. */ 2260 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2261 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2262 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2263 #define RS6000_BTC_QUATERNARY 0x00000004 /* normal quaternary 2264 function. */ 2265 #define RS6000_BTC_QUINARY 0x00000005 /* normal quinary function. */ 2266 #define RS6000_BTC_SENARY 0x00000006 /* normal senary function. */ 2267 #define RS6000_BTC_OPND_MASK 0x00000007 /* Mask to isolate operands. */ 2268 2269 /* Builtin attributes. */ 2270 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2271 #define RS6000_BTC_PREDICATE 0x00000008 /* predicate function. */ 2272 #define RS6000_BTC_ABS 0x00000010 /* Altivec/VSX ABS 2273 function. */ 2274 #define RS6000_BTC_DST 0x00000020 /* Altivec DST function. */ 2275 2276 #define RS6000_BTC_TYPE_MASK 0x0000003f /* Mask to isolate types */ 2277 2278 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2279 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor 2280 modifies global state. */ 2281 #define RS6000_BTC_PURE 0x00000200 /* reads global 2282 state/mem and does 2283 not modify global state. */ 2284 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2285 #define RS6000_BTC_QUAD 0x00000800 /* Uses a register quad. */ 2286 #define RS6000_BTC_PAIR 0x00001000 /* Uses a register pair. */ 2287 #define RS6000_BTC_QUADPAIR 0x00001800 /* Uses a quad and a pair. */ 2288 #define RS6000_BTC_ATTR_MASK 0x00001f00 /* Mask of the attributes. */ 2289 2290 /* Miscellaneous information. */ 2291 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2292 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2293 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ 2294 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ 2295 #define RS6000_BTC_GIMPLE 0x10000000 /* function should be expanded 2296 into gimple. */ 2297 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2298 2299 /* Convenience macros to document the instruction type. */ 2300 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2301 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2302 2303 /* Builtin targets. For now, we reuse the masks for those options that are in 2304 target flags, and pick a random bit for ldbl128, which isn't in 2305 target_flags. */ 2306 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2307 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2308 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ 2309 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2310 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2311 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ 2312 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ 2313 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2314 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2315 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2316 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2317 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2318 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2319 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2320 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2321 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2322 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2323 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2324 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ 2325 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ 2326 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ 2327 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ 2328 #define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ 2329 #define RS6000_BTM_P10 MASK_POWER10 2330 2331 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2332 | RS6000_BTM_VSX \ 2333 | RS6000_BTM_P8_VECTOR \ 2334 | RS6000_BTM_P9_VECTOR \ 2335 | RS6000_BTM_P9_MISC \ 2336 | RS6000_BTM_MODULO \ 2337 | RS6000_BTM_CRYPTO \ 2338 | RS6000_BTM_FRE \ 2339 | RS6000_BTM_FRES \ 2340 | RS6000_BTM_FRSQRTE \ 2341 | RS6000_BTM_FRSQRTES \ 2342 | RS6000_BTM_HTM \ 2343 | RS6000_BTM_POPCNTD \ 2344 | RS6000_BTM_CELL \ 2345 | RS6000_BTM_DFP \ 2346 | RS6000_BTM_HARD_FLOAT \ 2347 | RS6000_BTM_LDBL128 \ 2348 | RS6000_BTM_POWERPC64 \ 2349 | RS6000_BTM_FLOAT128 \ 2350 | RS6000_BTM_FLOAT128_HW \ 2351 | RS6000_BTM_MMA \ 2352 | RS6000_BTM_P10) 2353 2354 /* Define builtin enum index. */ 2355 2356 #undef RS6000_BUILTIN_0 2357 #undef RS6000_BUILTIN_1 2358 #undef RS6000_BUILTIN_2 2359 #undef RS6000_BUILTIN_3 2360 #undef RS6000_BUILTIN_A 2361 #undef RS6000_BUILTIN_D 2362 #undef RS6000_BUILTIN_H 2363 #undef RS6000_BUILTIN_M 2364 #undef RS6000_BUILTIN_P 2365 #undef RS6000_BUILTIN_X 2366 2367 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2368 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2369 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2370 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2371 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2372 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2373 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2374 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2375 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2376 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2377 2378 enum rs6000_builtins 2379 { 2380 #include "rs6000-builtin.def" 2381 2382 RS6000_BUILTIN_COUNT 2383 }; 2384 2385 #undef RS6000_BUILTIN_0 2386 #undef RS6000_BUILTIN_1 2387 #undef RS6000_BUILTIN_2 2388 #undef RS6000_BUILTIN_3 2389 #undef RS6000_BUILTIN_A 2390 #undef RS6000_BUILTIN_D 2391 #undef RS6000_BUILTIN_H 2392 #undef RS6000_BUILTIN_M 2393 #undef RS6000_BUILTIN_P 2394 #undef RS6000_BUILTIN_X 2395 2396 /* Mappings for overloaded builtins. */ 2397 struct altivec_builtin_types 2398 { 2399 enum rs6000_builtins code; 2400 enum rs6000_builtins overloaded_code; 2401 signed char ret_type; 2402 signed char op1; 2403 signed char op2; 2404 signed char op3; 2405 }; 2406 extern const struct altivec_builtin_types altivec_overloaded_builtins[]; 2407 2408 enum rs6000_builtin_type_index 2409 { 2410 RS6000_BTI_NOT_OPAQUE, 2411 RS6000_BTI_opaque_V4SI, 2412 RS6000_BTI_V16QI, /* __vector signed char */ 2413 RS6000_BTI_V1TI, 2414 RS6000_BTI_V2DI, 2415 RS6000_BTI_V2DF, 2416 RS6000_BTI_V4HI, 2417 RS6000_BTI_V4SI, 2418 RS6000_BTI_V4SF, 2419 RS6000_BTI_V8HI, 2420 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ 2421 RS6000_BTI_unsigned_V1TI, 2422 RS6000_BTI_unsigned_V8HI, 2423 RS6000_BTI_unsigned_V4SI, 2424 RS6000_BTI_unsigned_V2DI, 2425 RS6000_BTI_bool_char, /* __bool char */ 2426 RS6000_BTI_bool_short, /* __bool short */ 2427 RS6000_BTI_bool_int, /* __bool int */ 2428 RS6000_BTI_bool_long_long, /* __bool long long */ 2429 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 2430 channels of 1, 5, 5, and 5 bits 2431 respectively as packed with the 2432 vpkpx insn. __pixel is only 2433 meaningful as a vector type. 2434 There is no corresponding scalar 2435 __pixel data type.) */ 2436 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2437 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2438 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2439 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2440 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2441 RS6000_BTI_long, /* long_integer_type_node */ 2442 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2443 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2444 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2445 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ 2446 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2447 RS6000_BTI_INTHI, /* intHI_type_node */ 2448 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2449 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ 2450 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2451 RS6000_BTI_INTDI, /* intDI_type_node */ 2452 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2453 RS6000_BTI_INTTI, /* intTI_type_node */ 2454 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2455 RS6000_BTI_float, /* float_type_node */ 2456 RS6000_BTI_double, /* double_type_node */ 2457 RS6000_BTI_long_double, /* long_double_type_node */ 2458 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2459 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2460 RS6000_BTI_void, /* void_type_node */ 2461 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ 2462 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ 2463 RS6000_BTI_const_str, /* pointer to const char * */ 2464 RS6000_BTI_vector_pair, /* unsigned 256-bit types (vector pair). */ 2465 RS6000_BTI_vector_quad, /* unsigned 512-bit types (vector quad). */ 2466 RS6000_BTI_MAX 2467 }; 2468 2469 2470 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2471 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2472 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2473 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2474 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2475 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2476 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2477 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2478 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2479 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2480 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2481 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2482 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2483 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2484 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2485 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2486 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2487 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) 2488 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2489 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2490 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2491 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2492 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2493 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2494 2495 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2496 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2497 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2498 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2499 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2500 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2501 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2502 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2503 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2504 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2505 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2506 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2507 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2508 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2509 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2510 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2511 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2512 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2513 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2514 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2515 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) 2516 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) 2517 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) 2518 #define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair]) 2519 #define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad]) 2520 2521 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2522 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2523 2524 #ifndef USED_FOR_TARGET 2525 extern GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; 2526 extern GTY(()) tree altivec_builtin_mask_for_load; 2527 extern GTY(()) section *toc_section; 2528 2529 /* A C structure for machine-specific, per-function data. 2530 This is added to the cfun structure. */ 2531 typedef struct GTY(()) machine_function 2532 { 2533 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 2534 int ra_needs_full_frame; 2535 /* Flags if __builtin_return_address (0) was used. */ 2536 int ra_need_lr; 2537 /* Cache lr_save_p after expansion of builtin_eh_return. */ 2538 int lr_save_state; 2539 /* Whether we need to save the TOC to the reserved stack location in the 2540 function prologue. */ 2541 bool save_toc_in_prologue; 2542 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 2543 varargs save area. */ 2544 HOST_WIDE_INT varargs_save_offset; 2545 /* Alternative internal arg pointer for -fsplit-stack. */ 2546 rtx split_stack_arg_pointer; 2547 bool split_stack_argp_used; 2548 /* Flag if r2 setup is needed with ELFv2 ABI. */ 2549 bool r2_setup_needed; 2550 /* The number of components we use for separate shrink-wrapping. */ 2551 int n_components; 2552 /* The components already handled by separate shrink-wrapping, which should 2553 not be considered by the prologue and epilogue. */ 2554 bool gpr_is_wrapped_separately[32]; 2555 bool fpr_is_wrapped_separately[32]; 2556 bool lr_is_wrapped_separately; 2557 bool toc_is_wrapped_separately; 2558 } machine_function; 2559 #endif 2560 2561 2562 #define TARGET_SUPPORTS_WIDE_INT 1 2563 2564 #if (GCC_VERSION >= 3000) 2565 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 2566 #endif 2567 2568 /* Whether a given VALUE is a valid 16 or 34-bit signed integer. */ 2569 #define SIGNED_INTEGER_NBIT_P(VALUE, N) \ 2570 IN_RANGE ((VALUE), \ 2571 -(HOST_WIDE_INT_1 << ((N)-1)), \ 2572 (HOST_WIDE_INT_1 << ((N)-1)) - 1) 2573 2574 #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) 2575 #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) 2576 2577 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra 2578 argument that gives a length to validate a range of addresses, to allow for 2579 splitting insns into several insns, each of which has an offsettable 2580 address. */ 2581 #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2582 IN_RANGE ((VALUE), \ 2583 -(HOST_WIDE_INT_1 << 15), \ 2584 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA)) 2585 2586 #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2587 IN_RANGE ((VALUE), \ 2588 -(HOST_WIDE_INT_1 << 33), \ 2589 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA)) 2590 2591 /* Define this if some processing needs to be done before outputting the 2592 assembler code. On the PowerPC, we remember if the current insn is a normal 2593 prefixed insn where we need to emit a 'p' before the insn. */ 2594 #define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \ 2595 do \ 2596 { \ 2597 if (TARGET_PREFIXED) \ 2598 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \ 2599 } \ 2600 while (0) 2601 2602 /* Do anything special before emitting an opcode. We use it to emit a 'p' for 2603 prefixed insns that is set in FINAL_PRESCAN_INSN. */ 2604 #define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \ 2605 do \ 2606 { \ 2607 if (TARGET_PREFIXED) \ 2608 rs6000_asm_output_opcode (STREAM); \ 2609 } \ 2610 while (0) 2611