1;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler 2;; Copyright (C) 2007-2022 Free Software Foundation, Inc. 3 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_c_enum "unspec" [ 21 ;; Va, Vb, Vc builtins 22 UNSPEC_ARC_SIMD_VADDAW 23 UNSPEC_ARC_SIMD_VADDW 24 UNSPEC_ARC_SIMD_VAVB 25 UNSPEC_ARC_SIMD_VAVRB 26 UNSPEC_ARC_SIMD_VDIFAW 27 UNSPEC_ARC_SIMD_VDIFW 28 UNSPEC_ARC_SIMD_VMAXAW 29 UNSPEC_ARC_SIMD_VMAXW 30 UNSPEC_ARC_SIMD_VMINAW 31 UNSPEC_ARC_SIMD_VMINW 32 UNSPEC_ARC_SIMD_VMULAW 33 UNSPEC_ARC_SIMD_VMULFAW 34 UNSPEC_ARC_SIMD_VMULFW 35 UNSPEC_ARC_SIMD_VMULW 36 UNSPEC_ARC_SIMD_VSUBAW 37 UNSPEC_ARC_SIMD_VSUBW 38 UNSPEC_ARC_SIMD_VSUMMW 39 UNSPEC_ARC_SIMD_VAND 40 UNSPEC_ARC_SIMD_VANDAW 41 UNSPEC_ARC_SIMD_VBIC 42 UNSPEC_ARC_SIMD_VBICAW 43 UNSPEC_ARC_SIMD_VOR 44 UNSPEC_ARC_SIMD_VXOR 45 UNSPEC_ARC_SIMD_VXORAW 46 UNSPEC_ARC_SIMD_VEQW 47 UNSPEC_ARC_SIMD_VLEW 48 UNSPEC_ARC_SIMD_VLTW 49 UNSPEC_ARC_SIMD_VNEW 50 UNSPEC_ARC_SIMD_VMR1AW 51 UNSPEC_ARC_SIMD_VMR1W 52 UNSPEC_ARC_SIMD_VMR2AW 53 UNSPEC_ARC_SIMD_VMR2W 54 UNSPEC_ARC_SIMD_VMR3AW 55 UNSPEC_ARC_SIMD_VMR3W 56 UNSPEC_ARC_SIMD_VMR4AW 57 UNSPEC_ARC_SIMD_VMR4W 58 UNSPEC_ARC_SIMD_VMR5AW 59 UNSPEC_ARC_SIMD_VMR5W 60 UNSPEC_ARC_SIMD_VMR6AW 61 UNSPEC_ARC_SIMD_VMR6W 62 UNSPEC_ARC_SIMD_VMR7AW 63 UNSPEC_ARC_SIMD_VMR7W 64 UNSPEC_ARC_SIMD_VMRB 65 UNSPEC_ARC_SIMD_VH264F 66 UNSPEC_ARC_SIMD_VH264FT 67 UNSPEC_ARC_SIMD_VH264FW 68 UNSPEC_ARC_SIMD_VVC1F 69 UNSPEC_ARC_SIMD_VVC1FT 70 ;; Va, Vb, rc/limm builtins 71 UNSPEC_ARC_SIMD_VBADDW 72 UNSPEC_ARC_SIMD_VBMAXW 73 UNSPEC_ARC_SIMD_VBMINW 74 UNSPEC_ARC_SIMD_VBMULAW 75 UNSPEC_ARC_SIMD_VBMULFW 76 UNSPEC_ARC_SIMD_VBMULW 77 UNSPEC_ARC_SIMD_VBRSUBW 78 UNSPEC_ARC_SIMD_VBSUBW 79 80 ;; Va, Vb, Ic builtins 81 UNSPEC_ARC_SIMD_VASRW 82 UNSPEC_ARC_SIMD_VSR8 83 UNSPEC_ARC_SIMD_VSR8AW 84 85 ;; Va, Vb, Ic builtins 86 UNSPEC_ARC_SIMD_VASRRWi 87 UNSPEC_ARC_SIMD_VASRSRWi 88 UNSPEC_ARC_SIMD_VASRWi 89 UNSPEC_ARC_SIMD_VASRPWBi 90 UNSPEC_ARC_SIMD_VASRRPWBi 91 UNSPEC_ARC_SIMD_VSR8AWi 92 UNSPEC_ARC_SIMD_VSR8i 93 94 ;; Va, Vb, u8 (simm) builtins 95 UNSPEC_ARC_SIMD_VMVAW 96 UNSPEC_ARC_SIMD_VMVW 97 UNSPEC_ARC_SIMD_VMVZW 98 UNSPEC_ARC_SIMD_VD6TAPF 99 100 ;; Va, rlimm, u8 (simm) builtins 101 UNSPEC_ARC_SIMD_VMOVAW 102 UNSPEC_ARC_SIMD_VMOVW 103 UNSPEC_ARC_SIMD_VMOVZW 104 105 ;; Va, Vb builtins 106 UNSPEC_ARC_SIMD_VABSAW 107 UNSPEC_ARC_SIMD_VABSW 108 UNSPEC_ARC_SIMD_VADDSUW 109 UNSPEC_ARC_SIMD_VSIGNW 110 UNSPEC_ARC_SIMD_VEXCH1 111 UNSPEC_ARC_SIMD_VEXCH2 112 UNSPEC_ARC_SIMD_VEXCH4 113 UNSPEC_ARC_SIMD_VUPBAW 114 UNSPEC_ARC_SIMD_VUPBW 115 UNSPEC_ARC_SIMD_VUPSBAW 116 UNSPEC_ARC_SIMD_VUPSBW 117 118 UNSPEC_ARC_SIMD_VDIRUN 119 UNSPEC_ARC_SIMD_VDORUN 120 UNSPEC_ARC_SIMD_VDIWR 121 UNSPEC_ARC_SIMD_VDOWR 122 123 UNSPEC_ARC_SIMD_VREC 124 UNSPEC_ARC_SIMD_VRUN 125 UNSPEC_ARC_SIMD_VRECRUN 126 UNSPEC_ARC_SIMD_VENDREC 127 128 UNSPEC_ARC_SIMD_VCAST 129 UNSPEC_ARC_SIMD_VINTI 130 ]) 131 132;; Scheduler descriptions for the simd instructions 133(define_insn_reservation "simd_lat_0_insn" 1 134 (eq_attr "type" "simd_dma, simd_vstore, simd_vcontrol") 135 "issue+simd_unit") 136 137(define_insn_reservation "simd_lat_1_insn" 2 138 (eq_attr "type" "simd_vcompare, simd_vlogic, 139 simd_vmove_else_zero, simd_varith_1cycle") 140 "issue+simd_unit, nothing") 141 142(define_insn_reservation "simd_lat_2_insn" 3 143 (eq_attr "type" "simd_valign, simd_vpermute, 144 simd_vpack, simd_varith_2cycle") 145 "issue+simd_unit, nothing*2") 146 147(define_insn_reservation "simd_lat_3_insn" 4 148 (eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc, 149 simd_vlogic_with_acc, simd_vload128, 150 simd_vmove_with_acc, simd_vspecial_3cycle, 151 simd_varith_with_acc") 152 "issue+simd_unit, nothing*3") 153 154(define_insn_reservation "simd_lat_4_insn" 5 155 (eq_attr "type" "simd_vload, simd_vmove, simd_vspecial_4cycle") 156 "issue+simd_unit, nothing*4") 157 158(define_expand "movv8hi" 159 [(set (match_operand:V8HI 0 "general_operand" "") 160 (match_operand:V8HI 1 "general_operand" ""))] 161 "" 162 " 163{ 164 /* Everything except mem = const or mem = mem can be done easily. */ 165 166 if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM) 167 operands[1] = force_reg (V8HImode, operands[1]); 168}") 169 170;; This pattern should appear before the movv8hi_insn pattern 171(define_insn "vld128_insn" 172 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 173 (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v") 174 (parallel [(match_operand:SI 2 "immediate_operand" "L")]))) 175 (match_operand:SI 3 "immediate_operand" "P"))))] 176 "TARGET_SIMD_SET" 177 "vld128\\t%0,[i%2,%3]" 178 [(set_attr "type" "simd_vload128") 179 (set_attr "length" "4") 180 (set_attr "cond" "nocond")] 181) 182 183(define_insn "vst128_insn" 184 [(set (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v") 185 (parallel [(match_operand:SI 1 "immediate_operand" "L")]))) 186 (match_operand:SI 2 "immediate_operand" "P"))) 187 (match_operand:V8HI 3 "vector_register_operand" "=v"))] 188 "TARGET_SIMD_SET" 189 "vst128\\t%3,[i%1,%2]" 190 [(set_attr "type" "simd_vstore") 191 (set_attr "length" "4") 192 (set_attr "cond" "nocond")] 193) 194 195(define_insn "vst64_insn" 196 [(set (mem:V4HI 197 (plus:SI 198 (zero_extend:SI 199 (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v") 200 (parallel 201 [(match_operand:SI 1 "immediate_operand" "L")]))) 202 (match_operand:SI 2 "immediate_operand" "P"))) 203 (vec_select:V4HI 204 (match_operand:V8HI 3 "vector_register_operand" "=v") 205 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] 206 "TARGET_SIMD_SET" 207 "vst64\\t%3,[i%1,%2]" 208 [(set_attr "type" "simd_vstore") 209 (set_attr "length" "4") 210 (set_attr "cond" "nocond")] 211) 212 213(define_insn "movv8hi_insn" 214 [(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v") 215 (match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))] 216 "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)" 217 "@ 218 vld128r\\t%0,%1 219 vst128r\\t%1,%0 220 vmvzw\\t%0,%1,0xffff" 221 [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero") 222 (set_attr "length" "8,8,4") 223 (set_attr "cond" "nocond, nocond, nocond")]) 224 225(define_insn "movti_insn" 226 [(set (match_operand:TI 0 "vector_register_or_memory_operand" "=v,m,v") 227 (match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))] 228 "" 229 "@ 230 vld128r\\t%0,%1 231 vst128r\\t%1,%0 232 vmvzw\\t%0,%1,0xffff" 233 [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero") 234 (set_attr "length" "8,8,4") 235 (set_attr "cond" "nocond, nocond, nocond")]) 236 237;; V V V Insns 238(define_insn "vaddaw_insn" 239 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 240 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 241 (match_operand:V8HI 2 "vector_register_operand" "v")] 242 UNSPEC_ARC_SIMD_VADDAW))] 243 "TARGET_SIMD_SET" 244 "vaddaw\\t%0,%1,%2" 245 [(set_attr "type" "simd_varith_with_acc") 246 (set_attr "length" "4") 247 (set_attr "cond" "nocond")]) 248 249(define_insn "vaddw_insn" 250 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 251 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 252 (match_operand:V8HI 2 "vector_register_operand" "v")] 253 UNSPEC_ARC_SIMD_VADDW))] 254 "TARGET_SIMD_SET" 255 "vaddw\\t%0,%1,2" 256 [(set_attr "type" "simd_varith_1cycle") 257 (set_attr "length" "4") 258 (set_attr "cond" "nocond")]) 259 260(define_insn "vavb_insn" 261 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 262 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 263 (match_operand:V8HI 2 "vector_register_operand" "v")] 264 UNSPEC_ARC_SIMD_VAVB))] 265 "TARGET_SIMD_SET" 266 "vavb\\t%0,%1,%2" 267 [(set_attr "type" "simd_varith_1cycle") 268 (set_attr "length" "4") 269 (set_attr "cond" "nocond")]) 270 271(define_insn "vavrb_insn" 272 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 273 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 274 (match_operand:V8HI 2 "vector_register_operand" "v")] 275 UNSPEC_ARC_SIMD_VAVRB))] 276 "TARGET_SIMD_SET" 277 "vavrb\\t%0,%1,%2" 278 [(set_attr "type" "simd_varith_1cycle") 279 (set_attr "length" "4") 280 (set_attr "cond" "nocond")]) 281 282(define_insn "vdifaw_insn" 283 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 284 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 285 (match_operand:V8HI 2 "vector_register_operand" "v")] 286 UNSPEC_ARC_SIMD_VDIFAW))] 287 "TARGET_SIMD_SET" 288 "vdifaw\\t%0,%1,%2" 289 [(set_attr "type" "simd_varith_with_acc") 290 (set_attr "length" "4") 291 (set_attr "cond" "nocond")]) 292 293(define_insn "vdifw_insn" 294 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 295 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 296 (match_operand:V8HI 2 "vector_register_operand" "v")] 297 UNSPEC_ARC_SIMD_VDIFW))] 298 "TARGET_SIMD_SET" 299 "vdifw\\t%0,%1,%2" 300 [(set_attr "type" "simd_varith_1cycle") 301 (set_attr "length" "4") 302 (set_attr "cond" "nocond")]) 303 304(define_insn "vmaxaw_insn" 305 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 306 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 307 (match_operand:V8HI 2 "vector_register_operand" "v")] 308 UNSPEC_ARC_SIMD_VMAXAW))] 309 "TARGET_SIMD_SET" 310 "vmaxaw\\t%0,%1,2" 311 [(set_attr "type" "simd_varith_with_acc") 312 (set_attr "length" "4") 313 (set_attr "cond" "nocond")]) 314 315(define_insn "vmaxw_insn" 316 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 317 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 318 (match_operand:V8HI 2 "vector_register_operand" "v")] 319 UNSPEC_ARC_SIMD_VMAXW))] 320 "TARGET_SIMD_SET" 321 "vmaxw\\t%0,%1,%2" 322 [(set_attr "type" "simd_varith_1cycle") 323 (set_attr "length" "4") 324 (set_attr "cond" "nocond")]) 325 326(define_insn "vminaw_insn" 327 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 328 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 329 (match_operand:V8HI 2 "vector_register_operand" "v")] 330 UNSPEC_ARC_SIMD_VMINAW))] 331 "TARGET_SIMD_SET" 332 "vminaw\\t%0,%1,%2" 333 [(set_attr "type" "simd_varith_with_acc") 334 (set_attr "length" "4") 335 (set_attr "cond" "nocond")]) 336 337(define_insn "vminw_insn" 338 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 339 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 340 (match_operand:V8HI 2 "vector_register_operand" "v")] 341 UNSPEC_ARC_SIMD_VMINW))] 342 "TARGET_SIMD_SET" 343 "vminw\\t%0,%1,%2" 344 [(set_attr "type" "simd_varith_1cycle") 345 (set_attr "length" "4") 346 (set_attr "cond" "nocond")]) 347 348(define_insn "vmulaw_insn" 349 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 350 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 351 (match_operand:V8HI 2 "vector_register_operand" "v")] 352 UNSPEC_ARC_SIMD_VMULAW))] 353 "TARGET_SIMD_SET" 354 "vmulaw\\t%0,%1,%2" 355 [(set_attr "type" "simd_varith_with_acc") 356 (set_attr "length" "4") 357 (set_attr "cond" "nocond")]) 358 359(define_insn "vmulfaw_insn" 360 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 361 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 362 (match_operand:V8HI 2 "vector_register_operand" "v")] 363 UNSPEC_ARC_SIMD_VMULFAW))] 364 "TARGET_SIMD_SET" 365 "vmulfaw\\t%0,%1,%2" 366 [(set_attr "type" "simd_varith_with_acc") 367 (set_attr "length" "4") 368 (set_attr "cond" "nocond")]) 369 370(define_insn "vmulfw_insn" 371 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 372 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 373 (match_operand:V8HI 2 "vector_register_operand" "v")] 374 UNSPEC_ARC_SIMD_VMULFW))] 375 "TARGET_SIMD_SET" 376 "vmulfw\\t%0,%1,%2" 377 [(set_attr "type" "simd_varith_2cycle") 378 (set_attr "length" "4") 379 (set_attr "cond" "nocond")]) 380 381(define_insn "vmulw_insn" 382 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 383 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 384 (match_operand:V8HI 2 "vector_register_operand" "v")] 385 UNSPEC_ARC_SIMD_VMULW))] 386 "TARGET_SIMD_SET" 387 "vmulw\\t%0,%1,%2" 388 [(set_attr "type" "simd_varith_2cycle") 389 (set_attr "length" "4") 390 (set_attr "cond" "nocond")]) 391 392(define_insn "vsubaw_insn" 393 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 394 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 395 (match_operand:V8HI 2 "vector_register_operand" "v")] 396 UNSPEC_ARC_SIMD_VSUBAW))] 397 "TARGET_SIMD_SET" 398 "vsubaw\\t%0,%1,%2" 399 [(set_attr "type" "simd_varith_with_acc") 400 (set_attr "length" "4") 401 (set_attr "cond" "nocond")]) 402 403(define_insn "vsubw_insn" 404 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 405 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 406 (match_operand:V8HI 2 "vector_register_operand" "v")] 407 UNSPEC_ARC_SIMD_VSUBW))] 408 "TARGET_SIMD_SET" 409 "vsubw\\t%0,%1,%2" 410 [(set_attr "type" "simd_varith_1cycle") 411 (set_attr "length" "4") 412 (set_attr "cond" "nocond")]) 413 414(define_insn "vsummw_insn" 415 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 416 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 417 (match_operand:V8HI 2 "vector_register_operand" "v")] 418 UNSPEC_ARC_SIMD_VSUMMW))] 419 "TARGET_SIMD_SET" 420 "vsummw\\t%0,%1,%2" 421 [(set_attr "type" "simd_varith_2cycle") 422 (set_attr "length" "4") 423 (set_attr "cond" "nocond")]) 424 425(define_insn "vand_insn" 426 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 427 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 428 (match_operand:V8HI 2 "vector_register_operand" "v")] 429 UNSPEC_ARC_SIMD_VAND))] 430 "TARGET_SIMD_SET" 431 "vand\\t%0,%1,%2" 432 [(set_attr "type" "simd_vlogic") 433 (set_attr "length" "4") 434 (set_attr "cond" "nocond")]) 435 436(define_insn "vandaw_insn" 437 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 438 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 439 (match_operand:V8HI 2 "vector_register_operand" "v")] 440 UNSPEC_ARC_SIMD_VANDAW))] 441 "TARGET_SIMD_SET" 442 "vandaw\\t%0,%1,%2" 443 [(set_attr "type" "simd_vlogic_with_acc") 444 (set_attr "length" "4") 445 (set_attr "cond" "nocond")]) 446 447(define_insn "vbic_insn" 448 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 449 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 450 (match_operand:V8HI 2 "vector_register_operand" "v")] 451 UNSPEC_ARC_SIMD_VBIC))] 452 "TARGET_SIMD_SET" 453 "vbic\\t%0,%1,%2" 454 [(set_attr "type" "simd_vlogic") 455 (set_attr "length" "4") 456 (set_attr "cond" "nocond")]) 457 458(define_insn "vbicaw_insn" 459 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 460 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 461 (match_operand:V8HI 2 "vector_register_operand" "v")] 462 UNSPEC_ARC_SIMD_VBICAW))] 463 "TARGET_SIMD_SET" 464 "vbicaw\\t%0,%1,%2" 465 [(set_attr "type" "simd_vlogic_with_acc") 466 (set_attr "length" "4") 467 (set_attr "cond" "nocond")]) 468 469(define_insn "vor_insn" 470 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 471 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 472 (match_operand:V8HI 2 "vector_register_operand" "v")] 473 UNSPEC_ARC_SIMD_VOR))] 474 "TARGET_SIMD_SET" 475 "vor\\t%0,%1,%2" 476 [(set_attr "type" "simd_vlogic") 477 (set_attr "length" "4") 478 (set_attr "cond" "nocond")]) 479 480(define_insn "vxor_insn" 481 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 482 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 483 (match_operand:V8HI 2 "vector_register_operand" "v")] 484 UNSPEC_ARC_SIMD_VXOR))] 485 "TARGET_SIMD_SET" 486 "vxor\\t%0,%1,%2" 487 [(set_attr "type" "simd_vlogic") 488 (set_attr "length" "4") 489 (set_attr "cond" "nocond")]) 490 491(define_insn "vxoraw_insn" 492 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 493 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 494 (match_operand:V8HI 2 "vector_register_operand" "v")] 495 UNSPEC_ARC_SIMD_VXORAW))] 496 "TARGET_SIMD_SET" 497 "vxoraw\\t%0,%1,%2" 498 [(set_attr "type" "simd_vlogic_with_acc") 499 (set_attr "length" "4") 500 (set_attr "cond" "nocond")]) 501 502(define_insn "veqw_insn" 503 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 504 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 505 (match_operand:V8HI 2 "vector_register_operand" "v")] 506 UNSPEC_ARC_SIMD_VEQW))] 507 "TARGET_SIMD_SET" 508 "veqw\\t%0,%1,%2" 509 [(set_attr "type" "simd_vcompare") 510 (set_attr "length" "4") 511 (set_attr "cond" "nocond")]) 512 513(define_insn "vlew_insn" 514 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 515 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 516 (match_operand:V8HI 2 "vector_register_operand" "v")] 517 UNSPEC_ARC_SIMD_VLEW))] 518 "TARGET_SIMD_SET" 519 "vlew\\t%0,%1,%2" 520 [(set_attr "type" "simd_vcompare") 521 (set_attr "length" "4") 522 (set_attr "cond" "nocond")]) 523 524(define_insn "vltw_insn" 525 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 526 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 527 (match_operand:V8HI 2 "vector_register_operand" "v")] 528 UNSPEC_ARC_SIMD_VLTW))] 529 "TARGET_SIMD_SET" 530 "vltw\\t%0,%1,%2" 531 [(set_attr "type" "simd_vcompare") 532 (set_attr "length" "4") 533 (set_attr "cond" "nocond")]) 534 535(define_insn "vnew_insn" 536 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 537 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 538 (match_operand:V8HI 2 "vector_register_operand" "v")] 539 UNSPEC_ARC_SIMD_VNEW))] 540 "TARGET_SIMD_SET" 541 "vnew\\t%0,%1,%2" 542 [(set_attr "type" "simd_vcompare") 543 (set_attr "length" "4") 544 (set_attr "cond" "nocond")]) 545 546(define_insn "vmr1aw_insn" 547 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 548 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 549 (match_operand:V8HI 2 "vector_register_operand" "v")] 550 UNSPEC_ARC_SIMD_VMR1AW))] 551 "TARGET_SIMD_SET" 552 "vmr1aw\\t%0,%1,%2" 553 [(set_attr "type" "simd_valign_with_acc") 554 (set_attr "length" "4") 555 (set_attr "cond" "nocond")]) 556 557(define_insn "vmr1w_insn" 558 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 559 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 560 (match_operand:V8HI 2 "vector_register_operand" "v")] 561 UNSPEC_ARC_SIMD_VMR1W))] 562 "TARGET_SIMD_SET" 563 "vmr1w\\t%0,%1,%2" 564 [(set_attr "type" "simd_valign") 565 (set_attr "length" "4") 566 (set_attr "cond" "nocond")]) 567 568(define_insn "vmr2aw_insn" 569 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 570 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 571 (match_operand:V8HI 2 "vector_register_operand" "v")] 572 UNSPEC_ARC_SIMD_VMR2AW))] 573 "TARGET_SIMD_SET" 574 "vmr2aw\\t%0,%1,%2" 575 [(set_attr "type" "simd_valign_with_acc") 576 (set_attr "length" "4") 577 (set_attr "cond" "nocond")]) 578 579(define_insn "vmr2w_insn" 580 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 581 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 582 (match_operand:V8HI 2 "vector_register_operand" "v")] 583 UNSPEC_ARC_SIMD_VMR2W))] 584 "TARGET_SIMD_SET" 585 "vmr2w\\t%0,%1,%2" 586 [(set_attr "type" "simd_valign") 587 (set_attr "length" "4") 588 (set_attr "cond" "nocond")]) 589 590(define_insn "vmr3aw_insn" 591 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 592 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 593 (match_operand:V8HI 2 "vector_register_operand" "v")] 594 UNSPEC_ARC_SIMD_VMR3AW))] 595 "TARGET_SIMD_SET" 596 "vmr3aw\\t%0,%1,%2" 597 [(set_attr "type" "simd_valign_with_acc") 598 (set_attr "length" "4") 599 (set_attr "cond" "nocond")]) 600 601(define_insn "vmr3w_insn" 602 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 603 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 604 (match_operand:V8HI 2 "vector_register_operand" "v")] 605 UNSPEC_ARC_SIMD_VMR3W))] 606 "TARGET_SIMD_SET" 607 "vmr3w\\t%0,%1,%2" 608 [(set_attr "type" "simd_valign") 609 (set_attr "length" "4") 610 (set_attr "cond" "nocond")]) 611 612(define_insn "vmr4aw_insn" 613 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 614 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 615 (match_operand:V8HI 2 "vector_register_operand" "v")] 616 UNSPEC_ARC_SIMD_VMR4AW))] 617 "TARGET_SIMD_SET" 618 "vmr4aw\\t%0,%1,%2" 619 [(set_attr "type" "simd_valign_with_acc") 620 (set_attr "length" "4") 621 (set_attr "cond" "nocond")]) 622 623(define_insn "vmr4w_insn" 624 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 625 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 626 (match_operand:V8HI 2 "vector_register_operand" "v")] 627 UNSPEC_ARC_SIMD_VMR4W))] 628 "TARGET_SIMD_SET" 629 "vmr4w\\t%0,%1,%2" 630 [(set_attr "type" "simd_valign") 631 (set_attr "length" "4") 632 (set_attr "cond" "nocond")]) 633 634(define_insn "vmr5aw_insn" 635 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 636 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 637 (match_operand:V8HI 2 "vector_register_operand" "v")] 638 UNSPEC_ARC_SIMD_VMR5AW))] 639 "TARGET_SIMD_SET" 640 "vmr5aw\\t%0,%1,%2" 641 [(set_attr "type" "simd_valign_with_acc") 642 (set_attr "length" "4") 643 (set_attr "cond" "nocond")]) 644 645(define_insn "vmr5w_insn" 646 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 647 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 648 (match_operand:V8HI 2 "vector_register_operand" "v")] 649 UNSPEC_ARC_SIMD_VMR5W))] 650 "TARGET_SIMD_SET" 651 "vmr5w\\t%0,%1,%2" 652 [(set_attr "type" "simd_valign") 653 (set_attr "length" "4") 654 (set_attr "cond" "nocond")]) 655 656(define_insn "vmr6aw_insn" 657 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 658 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 659 (match_operand:V8HI 2 "vector_register_operand" "v")] 660 UNSPEC_ARC_SIMD_VMR6AW))] 661 "TARGET_SIMD_SET" 662 "vmr6aw\\t%0,%1,%2" 663 [(set_attr "type" "simd_valign_with_acc") 664 (set_attr "length" "4") 665 (set_attr "cond" "nocond")]) 666 667(define_insn "vmr6w_insn" 668 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 669 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 670 (match_operand:V8HI 2 "vector_register_operand" "v")] 671 UNSPEC_ARC_SIMD_VMR6W))] 672 "TARGET_SIMD_SET" 673 "vmr6w\\t%0,%1,%2" 674 [(set_attr "type" "simd_valign") 675 (set_attr "length" "4") 676 (set_attr "cond" "nocond")]) 677 678(define_insn "vmr7aw_insn" 679 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 680 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 681 (match_operand:V8HI 2 "vector_register_operand" "v")] 682 UNSPEC_ARC_SIMD_VMR7AW))] 683 "TARGET_SIMD_SET" 684 "vmr7aw\\t%0,%1,%2" 685 [(set_attr "type" "simd_valign_with_acc") 686 (set_attr "length" "4") 687 (set_attr "cond" "nocond")]) 688 689(define_insn "vmr7w_insn" 690 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 691 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 692 (match_operand:V8HI 2 "vector_register_operand" "v")] 693 UNSPEC_ARC_SIMD_VMR7W))] 694 "TARGET_SIMD_SET" 695 "vmr7w\\t%0,%1,%2" 696 [(set_attr "type" "simd_valign") 697 (set_attr "length" "4") 698 (set_attr "cond" "nocond")]) 699 700(define_insn "vmrb_insn" 701 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 702 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 703 (match_operand:V8HI 2 "vector_register_operand" "v")] 704 UNSPEC_ARC_SIMD_VMRB))] 705 "TARGET_SIMD_SET" 706 "vmrb\\t%0,%1,%2" 707 [(set_attr "type" "simd_valign") 708 (set_attr "length" "4") 709 (set_attr "cond" "nocond")]) 710 711(define_insn "vh264f_insn" 712 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 713 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 714 (match_operand:V8HI 2 "vector_register_operand" "v")] 715 UNSPEC_ARC_SIMD_VH264F))] 716 "TARGET_SIMD_SET" 717 "vh264f\\t%0,%1,%2" 718 [(set_attr "type" "simd_vspecial_3cycle") 719 (set_attr "length" "4") 720 (set_attr "cond" "nocond")]) 721 722(define_insn "vh264ft_insn" 723 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 724 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 725 (match_operand:V8HI 2 "vector_register_operand" "v")] 726 UNSPEC_ARC_SIMD_VH264FT))] 727 "TARGET_SIMD_SET" 728 "vh264ft\\t%0,%1,%2" 729 [(set_attr "type" "simd_vspecial_3cycle") 730 (set_attr "length" "4") 731 (set_attr "cond" "nocond")]) 732 733(define_insn "vh264fw_insn" 734 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 735 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 736 (match_operand:V8HI 2 "vector_register_operand" "v")] 737 UNSPEC_ARC_SIMD_VH264FW))] 738 "TARGET_SIMD_SET" 739 "vh264fw\\t%0,%1,%2" 740 [(set_attr "type" "simd_vspecial_3cycle") 741 (set_attr "length" "4") 742 (set_attr "cond" "nocond")]) 743 744(define_insn "vvc1f_insn" 745 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 746 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 747 (match_operand:V8HI 2 "vector_register_operand" "v")] 748 UNSPEC_ARC_SIMD_VVC1F))] 749 "TARGET_SIMD_SET" 750 "vvc1f\\t%0,%1,%2" 751 [(set_attr "type" "simd_vspecial_3cycle") 752 (set_attr "length" "4") 753 (set_attr "cond" "nocond")]) 754 755(define_insn "vvc1ft_insn" 756 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 757 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 758 (match_operand:V8HI 2 "vector_register_operand" "v")] 759 UNSPEC_ARC_SIMD_VVC1FT))] 760 "TARGET_SIMD_SET" 761 "vvc1ft\\t%0,%1,%2" 762 [(set_attr "type" "simd_vspecial_3cycle") 763 (set_attr "length" "4") 764 (set_attr "cond" "nocond")]) 765 766 767 768;;--- 769;; V V r/limm Insns 770(define_insn "vbaddw_insn" 771 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 772 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 773 (match_operand:SI 2 "nonmemory_operand" "r")] 774 UNSPEC_ARC_SIMD_VBADDW))] 775 "TARGET_SIMD_SET" 776 "vbaddw\\t%0,%1,%2" 777 [(set_attr "type" "simd_varith_1cycle") 778 (set_attr "length" "4") 779 (set_attr "cond" "nocond")]) 780 781(define_insn "vbmaxw_insn" 782 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 783 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 784 (match_operand:SI 2 "nonmemory_operand" "r")] 785 UNSPEC_ARC_SIMD_VBMAXW))] 786 "TARGET_SIMD_SET" 787 "vbmaxw\\t%0,%1,%2" 788 [(set_attr "type" "simd_varith_1cycle") 789 (set_attr "length" "4") 790 (set_attr "cond" "nocond")]) 791 792(define_insn "vbminw_insn" 793 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 794 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 795 (match_operand:SI 2 "nonmemory_operand" "r")] 796 UNSPEC_ARC_SIMD_VBMINW))] 797 "TARGET_SIMD_SET" 798 "vbminw\\t%0,%1,%2" 799 [(set_attr "type" "simd_varith_1cycle") 800 (set_attr "length" "4") 801 (set_attr "cond" "nocond")]) 802 803(define_insn "vbmulaw_insn" 804 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 805 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 806 (match_operand:SI 2 "nonmemory_operand" "r")] 807 UNSPEC_ARC_SIMD_VBMULAW))] 808 "TARGET_SIMD_SET" 809 "vbmulaw\\t%0,%1,%2" 810 [(set_attr "type" "simd_varith_with_acc") 811 (set_attr "length" "4") 812 (set_attr "cond" "nocond")]) 813 814(define_insn "vbmulfw_insn" 815 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 816 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 817 (match_operand:SI 2 "nonmemory_operand" "r")] 818 UNSPEC_ARC_SIMD_VBMULFW))] 819 "TARGET_SIMD_SET" 820 "vbmulfw\\t%0,%1,%2" 821 [(set_attr "type" "simd_varith_2cycle") 822 (set_attr "length" "4") 823 (set_attr "cond" "nocond")]) 824 825(define_insn "vbmulw_insn" 826 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 827 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 828 (match_operand:SI 2 "nonmemory_operand" "r")] 829 UNSPEC_ARC_SIMD_VBMULW))] 830 "TARGET_SIMD_SET" 831 "vbmulw\\t%0,%1,%2" 832 [(set_attr "type" "simd_varith_2cycle") 833 (set_attr "length" "4") 834 (set_attr "cond" "nocond")]) 835 836(define_insn "vbrsubw_insn" 837 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 838 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 839 (match_operand:SI 2 "nonmemory_operand" "r")] 840 UNSPEC_ARC_SIMD_VBRSUBW))] 841 "TARGET_SIMD_SET" 842 "vbrsubw\\t%0,%1,%2" 843 [(set_attr "type" "simd_varith_1cycle") 844 (set_attr "length" "4") 845 (set_attr "cond" "nocond")]) 846 847(define_insn "vbsubw_insn" 848 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 849 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 850 (match_operand:SI 2 "nonmemory_operand" "r")] 851 UNSPEC_ARC_SIMD_VBSUBW))] 852 "TARGET_SIMD_SET" 853 "vbsubw\\t%0,%1,%2" 854 [(set_attr "type" "simd_varith_1cycle") 855 (set_attr "length" "4") 856 (set_attr "cond" "nocond")]) 857; Va, Vb, Ic instructions 858 859; Va, Vb, u6 instructions 860(define_insn "vasrrwi_insn" 861 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 862 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 863 (match_operand:SI 2 "immediate_operand" "L")] 864 UNSPEC_ARC_SIMD_VASRRWi))] 865 "TARGET_SIMD_SET" 866 "vasrrwi\\t%0,%1,%2" 867 [(set_attr "type" "simd_varith_2cycle") 868 (set_attr "length" "4") 869 (set_attr "cond" "nocond")]) 870 871(define_insn "vasrsrwi_insn" 872 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 873 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 874 (match_operand:SI 2 "immediate_operand" "L")] 875 UNSPEC_ARC_SIMD_VASRSRWi))] 876 "TARGET_SIMD_SET" 877 "vasrsrwi\\t%0,%1,%2" 878 [(set_attr "type" "simd_varith_2cycle") 879 (set_attr "length" "4") 880 (set_attr "cond" "nocond")]) 881 882(define_insn "vasrwi_insn" 883 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 884 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 885 (match_operand:SI 2 "immediate_operand" "L")] 886 UNSPEC_ARC_SIMD_VASRWi))] 887 "TARGET_SIMD_SET" 888 "vasrwi\\t%0,%1,%2" 889 [(set_attr "type" "simd_varith_1cycle") 890 (set_attr "length" "4") 891 (set_attr "cond" "nocond")]) 892 893(define_insn "vasrpwbi_insn" 894 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 895 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 896 (match_operand:SI 2 "immediate_operand" "L")] 897 UNSPEC_ARC_SIMD_VASRPWBi))] 898 "TARGET_SIMD_SET" 899 "vasrpwbi\\t%0,%1,%2" 900 [(set_attr "type" "simd_vpack") 901 (set_attr "length" "4") 902 (set_attr "cond" "nocond")]) 903 904(define_insn "vasrrpwbi_insn" 905 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 906 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 907 (match_operand:SI 2 "immediate_operand" "L")] 908 UNSPEC_ARC_SIMD_VASRRPWBi))] 909 "TARGET_SIMD_SET" 910 "vasrrpwbi\\t%0,%1,%2" 911 [(set_attr "type" "simd_vpack") 912 (set_attr "length" "4") 913 (set_attr "cond" "nocond")]) 914 915(define_insn "vsr8awi_insn" 916 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 917 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 918 (match_operand:SI 2 "immediate_operand" "L")] 919 UNSPEC_ARC_SIMD_VSR8AWi))] 920 "TARGET_SIMD_SET" 921 "vsr8awi\\t%0,%1,%2" 922 [(set_attr "type" "simd_valign_with_acc") 923 (set_attr "length" "4") 924 (set_attr "cond" "nocond")]) 925 926(define_insn "vsr8i_insn" 927 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 928 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 929 (match_operand:SI 2 "immediate_operand" "L")] 930 UNSPEC_ARC_SIMD_VSR8i))] 931 "TARGET_SIMD_SET" 932 "vsr8i\\t%0,%1,%2" 933 [(set_attr "type" "simd_valign") 934 (set_attr "length" "4") 935 (set_attr "cond" "nocond")]) 936 937;; Va, Vb, u8 (simm) insns 938 939(define_insn "vmvaw_insn" 940 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 941 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 942 (match_operand:SI 2 "immediate_operand" "P")] 943 UNSPEC_ARC_SIMD_VMVAW))] 944 "TARGET_SIMD_SET" 945 "vmvaw\\t%0,%1,%2" 946 [(set_attr "type" "simd_vmove_with_acc") 947 (set_attr "length" "4") 948 (set_attr "cond" "nocond")]) 949 950(define_insn "vmvw_insn" 951 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 952 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 953 (match_operand:SI 2 "immediate_operand" "P")] 954 UNSPEC_ARC_SIMD_VMVW))] 955 "TARGET_SIMD_SET" 956 "vmvw\\t%0,%1,%2" 957 [(set_attr "type" "simd_vmove") 958 (set_attr "length" "4") 959 (set_attr "cond" "nocond")]) 960 961(define_insn "vmvzw_insn" 962 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 963 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 964 (match_operand:SI 2 "immediate_operand" "P")] 965 UNSPEC_ARC_SIMD_VMVZW))] 966 "TARGET_SIMD_SET" 967 "vmvzw\\t%0,%1,%2" 968 [(set_attr "type" "simd_vmove_else_zero") 969 (set_attr "length" "4") 970 (set_attr "cond" "nocond")]) 971 972(define_insn "vd6tapf_insn" 973 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 974 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 975 (match_operand:SI 2 "immediate_operand" "P")] 976 UNSPEC_ARC_SIMD_VD6TAPF))] 977 "TARGET_SIMD_SET" 978 "vd6tapf\\t%0,%1,%2" 979 [(set_attr "type" "simd_vspecial_4cycle") 980 (set_attr "length" "4") 981 (set_attr "cond" "nocond")]) 982 983;; Va, rlimm, u8 (simm) insns 984(define_insn "vmovaw_insn" 985 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 986 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") 987 (match_operand:SI 2 "immediate_operand" "P")] 988 UNSPEC_ARC_SIMD_VMOVAW))] 989 "TARGET_SIMD_SET" 990 "vmovaw\\t%0,%1,%2" 991 [(set_attr "type" "simd_vmove_with_acc") 992 (set_attr "length" "4") 993 (set_attr "cond" "nocond")]) 994 995(define_insn "vmovw_insn" 996 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 997 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") 998 (match_operand:SI 2 "immediate_operand" "P")] 999 UNSPEC_ARC_SIMD_VMOVW))] 1000 "TARGET_SIMD_SET" 1001 "vmovw\\t%0,%1,%2" 1002 [(set_attr "type" "simd_vmove") 1003 (set_attr "length" "4") 1004 (set_attr "cond" "nocond")]) 1005 1006(define_insn "vmovzw_insn" 1007 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1008 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") 1009 (match_operand:SI 2 "immediate_operand" "P")] 1010 UNSPEC_ARC_SIMD_VMOVZW))] 1011 "TARGET_SIMD_SET" 1012 "vmovzw\\t%0,%1,%2" 1013 [(set_attr "type" "simd_vmove_else_zero") 1014 (set_attr "length" "4") 1015 (set_attr "cond" "nocond")]) 1016 1017;; Va, rlimm, Ic insns 1018(define_insn "vsr8_insn" 1019 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1020 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 1021 (match_operand:SI 2 "immediate_operand" "K") 1022 (match_operand:V8HI 3 "vector_register_operand" "v")] 1023 UNSPEC_ARC_SIMD_VSR8))] 1024 "TARGET_SIMD_SET" 1025 "vsr8\\t%0,%1,i%2" 1026 [(set_attr "type" "simd_valign") 1027 (set_attr "length" "4") 1028 (set_attr "cond" "nocond")]) 1029 1030(define_insn "vasrw_insn" 1031 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1032 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 1033 (match_operand:SI 2 "immediate_operand" "K") 1034 (match_operand:V8HI 3 "vector_register_operand" "v")] 1035 UNSPEC_ARC_SIMD_VASRW))] 1036 "TARGET_SIMD_SET" 1037 "vasrw\\t%0,%1,i%2" 1038 [(set_attr "type" "simd_varith_1cycle") 1039 (set_attr "length" "4") 1040 (set_attr "cond" "nocond")]) 1041 1042(define_insn "vsr8aw_insn" 1043 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1044 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") 1045 (match_operand:SI 2 "immediate_operand" "K") 1046 (match_operand:V8HI 3 "vector_register_operand" "v")] 1047 UNSPEC_ARC_SIMD_VSR8AW))] 1048 "TARGET_SIMD_SET" 1049 "vsr8aw\\t%0,%1,i%2" 1050 [(set_attr "type" "simd_valign_with_acc") 1051 (set_attr "length" "4") 1052 (set_attr "cond" "nocond")]) 1053 1054;; Va, Vb insns 1055(define_insn "vabsaw_insn" 1056 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1057 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1058 UNSPEC_ARC_SIMD_VABSAW))] 1059 "TARGET_SIMD_SET" 1060 "vabsaw\\t%0,%1" 1061 [(set_attr "type" "simd_varith_with_acc") 1062 (set_attr "length" "4") 1063 (set_attr "cond" "nocond")]) 1064 1065(define_insn "vabsw_insn" 1066 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1067 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1068 UNSPEC_ARC_SIMD_VABSW))] 1069 "TARGET_SIMD_SET" 1070 "vabsw\\t%0,%1" 1071 [(set_attr "type" "simd_varith_1cycle") 1072 (set_attr "length" "4") 1073 (set_attr "cond" "nocond")]) 1074 1075(define_insn "vaddsuw_insn" 1076 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1077 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1078 UNSPEC_ARC_SIMD_VADDSUW))] 1079 "TARGET_SIMD_SET" 1080 "vaddsuw\\t%0,%1" 1081 [(set_attr "type" "simd_varith_1cycle") 1082 (set_attr "length" "4") 1083 (set_attr "cond" "nocond")]) 1084 1085(define_insn "vsignw_insn" 1086 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1087 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1088 UNSPEC_ARC_SIMD_VSIGNW))] 1089 "TARGET_SIMD_SET" 1090 "vsignw\\t%0,%1" 1091 [(set_attr "type" "simd_varith_1cycle") 1092 (set_attr "length" "4") 1093 (set_attr "cond" "nocond")]) 1094 1095(define_insn "vexch1_insn" 1096 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1097 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1098 UNSPEC_ARC_SIMD_VEXCH1))] 1099 "TARGET_SIMD_SET" 1100 "vexch1\\t%0,%1" 1101 [(set_attr "type" "simd_vpermute") 1102 (set_attr "length" "4") 1103 (set_attr "cond" "nocond")]) 1104 1105(define_insn "vexch2_insn" 1106 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1107 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1108 UNSPEC_ARC_SIMD_VEXCH2))] 1109 "TARGET_SIMD_SET" 1110 "vexch2\\t%0,%1" 1111 [(set_attr "type" "simd_vpermute") 1112 (set_attr "length" "4") 1113 (set_attr "cond" "nocond")]) 1114 1115(define_insn "vexch4_insn" 1116 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1117 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1118 UNSPEC_ARC_SIMD_VEXCH4))] 1119 "TARGET_SIMD_SET" 1120 "vexch4\\t%0,%1" 1121 [(set_attr "type" "simd_vpermute") 1122 (set_attr "length" "4") 1123 (set_attr "cond" "nocond")]) 1124 1125(define_insn "vupbaw_insn" 1126 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1127 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1128 UNSPEC_ARC_SIMD_VUPBAW))] 1129 "TARGET_SIMD_SET" 1130 "vupbaw\\t%0,%1" 1131 [(set_attr "type" "simd_vpack_with_acc") 1132 (set_attr "length" "4") 1133 (set_attr "cond" "nocond")]) 1134 1135(define_insn "vupbw_insn" 1136 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1137 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1138 UNSPEC_ARC_SIMD_VUPBW))] 1139 "TARGET_SIMD_SET" 1140 "vupbw\\t%0,%1" 1141 [(set_attr "type" "simd_vpack") 1142 (set_attr "length" "4") 1143 (set_attr "cond" "nocond")]) 1144 1145(define_insn "vupsbaw_insn" 1146 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1147 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1148 UNSPEC_ARC_SIMD_VUPSBAW))] 1149 "TARGET_SIMD_SET" 1150 "vupsbaw\\t%0,%1" 1151 [(set_attr "type" "simd_vpack_with_acc") 1152 (set_attr "length" "4") 1153 (set_attr "cond" "nocond")]) 1154 1155(define_insn "vupsbw_insn" 1156 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1157 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] 1158 UNSPEC_ARC_SIMD_VUPSBW))] 1159 "TARGET_SIMD_SET" 1160 "vupsbw\\t%0,%1" 1161 [(set_attr "type" "simd_vpack") 1162 (set_attr "length" "4") 1163 (set_attr "cond" "nocond")]) 1164 1165; DMA setup instructions 1166(define_insn "vdirun_insn" 1167 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d") 1168 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r") 1169 (match_operand:SI 2 "nonmemory_operand" "r")] 1170 UNSPEC_ARC_SIMD_VDIRUN))] 1171 "TARGET_SIMD_SET" 1172 "vdirun\\t%1,%2" 1173 [(set_attr "type" "simd_dma") 1174 (set_attr "length" "4") 1175 (set_attr "cond" "nocond")]) 1176 1177(define_insn "vdorun_insn" 1178 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d") 1179 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r") 1180 (match_operand:SI 2 "nonmemory_operand" "r")] 1181 UNSPEC_ARC_SIMD_VDORUN))] 1182 "TARGET_SIMD_SET" 1183 "vdorun\\t%1,%2" 1184 [(set_attr "type" "simd_dma") 1185 (set_attr "length" "4") 1186 (set_attr "cond" "nocond")]) 1187 1188(define_insn "vdiwr_insn" 1189 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d") 1190 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] 1191 UNSPEC_ARC_SIMD_VDIWR))] 1192 "TARGET_SIMD_SET" 1193 "vdiwr\\t%0,%1" 1194 [(set_attr "type" "simd_dma") 1195 (set_attr "length" "4,8") 1196 (set_attr "cond" "nocond,nocond")]) 1197 1198(define_insn "vdowr_insn" 1199 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d") 1200 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] 1201 UNSPEC_ARC_SIMD_VDOWR))] 1202 "TARGET_SIMD_SET" 1203 "vdowr\\t%0,%1" 1204 [(set_attr "type" "simd_dma") 1205 (set_attr "length" "4,8") 1206 (set_attr "cond" "nocond,nocond")]) 1207 1208;; vector record and run instructions 1209(define_insn "vrec_insn" 1210 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] 1211 UNSPEC_ARC_SIMD_VREC)] 1212 "TARGET_SIMD_SET" 1213 "vrec\\t%0" 1214 [(set_attr "type" "simd_vcontrol") 1215 (set_attr "length" "4") 1216 (set_attr "cond" "nocond")]) 1217 1218(define_insn "vrun_insn" 1219 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] 1220 UNSPEC_ARC_SIMD_VRUN)] 1221 "TARGET_SIMD_SET" 1222 "vrun\\t%0" 1223 [(set_attr "type" "simd_vcontrol") 1224 (set_attr "length" "4") 1225 (set_attr "cond" "nocond")]) 1226 1227(define_insn "vrecrun_insn" 1228 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] 1229 UNSPEC_ARC_SIMD_VRECRUN)] 1230 "TARGET_SIMD_SET" 1231 "vrecrun\\t%0" 1232 [(set_attr "type" "simd_vcontrol") 1233 (set_attr "length" "4") 1234 (set_attr "cond" "nocond")]) 1235 1236(define_insn "vendrec_insn" 1237 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] 1238 UNSPEC_ARC_SIMD_VENDREC)] 1239 "TARGET_SIMD_SET" 1240 "vendrec\\t%0" 1241 [(set_attr "type" "simd_vcontrol") 1242 (set_attr "length" "4") 1243 (set_attr "cond" "nocond")]) 1244 1245(define_insn "vld32wh_insn" 1246 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1247 (vec_concat:V8HI 1248 (zero_extend:V4HI 1249 (mem:V4QI 1250 (plus:SI 1251 (match_operand:SI 1 "immediate_operand" "P") 1252 (zero_extend:SI 1253 (vec_select:HI 1254 (match_operand:V8HI 2 "vector_register_operand" "v") 1255 (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) 1256 (vec_select:V4HI 1257 (match_dup 0) 1258 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]) 1259 )))] 1260 "TARGET_SIMD_SET" 1261 "vld32wh\\t%0,[i%3,%1]" 1262 [(set_attr "type" "simd_vload") 1263 (set_attr "length" "4") 1264 (set_attr "cond" "nocond")]) 1265 1266(define_insn "vld32wl_insn" 1267 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1268 (vec_concat:V8HI 1269 (vec_select:V4HI 1270 (match_dup 0) 1271 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])) 1272 (zero_extend:V4HI 1273 (mem:V4QI 1274 (plus:SI 1275 (match_operand:SI 1 "immediate_operand" "P") 1276 (zero_extend:SI 1277 (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v") 1278 (parallel 1279 [(match_operand:SI 3 "immediate_operand" "L")])) 1280 ))))))] 1281 "TARGET_SIMD_SET" 1282 "vld32wl\\t%0,[i%3,%1]" 1283 [(set_attr "type" "simd_vload") 1284 (set_attr "length" "4") 1285 (set_attr "cond" "nocond")]) 1286 1287(define_insn "vld64w_insn" 1288 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1289 (zero_extend:V8HI 1290 (mem:V4HI 1291 (plus:SI 1292 (zero_extend:SI 1293 (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v") 1294 (parallel [(match_operand:SI 2 "immediate_operand" "L")]))) 1295 (match_operand:SI 3 "immediate_operand" "P")))))] 1296 "TARGET_SIMD_SET" 1297 "vld64w\\t%0,[i%2,%3]" 1298 [(set_attr "type" "simd_vload") 1299 (set_attr "length" "4") 1300 (set_attr "cond" "nocond")] 1301) 1302 1303(define_insn "vld64_insn" 1304 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1305 (vec_concat:V8HI 1306 (vec_select:V4HI 1307 (match_dup 0) 1308 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])) 1309 (mem:V4HI 1310 (plus:SI 1311 (match_operand:SI 1 "immediate_operand" "P") 1312 (zero_extend:SI 1313 (vec_select:HI 1314 (match_operand:V8HI 2 "vector_register_operand" "v") 1315 (parallel [(match_operand:SI 3 "immediate_operand" "L")])) 1316 )))))] 1317 "TARGET_SIMD_SET" 1318 "vld64\\t%0,[i%3,%1]" 1319 [(set_attr "type" "simd_vload") 1320 (set_attr "length" "4") 1321 (set_attr "cond" "nocond")]) 1322 1323(define_insn "vld32_insn" 1324 [(set (match_operand:V8HI 0 "vector_register_operand" "=v") 1325 (vec_concat:V8HI 1326 (vec_select:V4HI 1327 (match_dup 0) 1328 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])) 1329 (vec_concat:V4HI 1330 (vec_select:V2HI 1331 (match_dup 0) 1332 (parallel [(const_int 2) (const_int 3)])) 1333 (mem:V2HI 1334 (plus:SI 1335 (match_operand:SI 1 "immediate_operand" "P") 1336 (zero_extend:SI 1337 (vec_select:HI 1338 (match_operand:V8HI 2 "vector_register_operand" "v") 1339 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))))] 1340 "TARGET_SIMD_SET" 1341 "vld32\\t%0,[i%3,%1]" 1342 [(set_attr "type" "simd_vload") 1343 (set_attr "length" "4") 1344 (set_attr "cond" "nocond")]) 1345 1346(define_insn "vst16_n_insn" 1347 [(set (mem:HI 1348 (plus:SI 1349 (match_operand:SI 0 "immediate_operand" "P") 1350 (zero_extend:SI 1351 (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v") 1352 (parallel [(match_operand:SI 2 "immediate_operand" "L")]))))) 1353 (vec_select:HI (match_operand:V8HI 3 "vector_register_operand" "v") 1354 (parallel [(match_operand:SI 4 "immediate_operand" "L")])))] 1355 "TARGET_SIMD_SET" 1356 "vst16_%4\\t%3,[i%2,%0]" 1357 [(set_attr "type" "simd_vstore") 1358 (set_attr "length" "4") 1359 (set_attr "cond" "nocond")]) 1360 1361(define_insn "vst32_n_insn" 1362 [(set (mem:SI 1363 (plus:SI 1364 (match_operand:SI 0 "immediate_operand" "P") 1365 (zero_extend:SI 1366 (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v") 1367 (parallel [(match_operand:SI 2 "immediate_operand" "L")]))))) 1368 (vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")] 1369 UNSPEC_ARC_SIMD_VCAST) 1370 (parallel [(match_operand:SI 4 "immediate_operand" "L")])))] 1371 "TARGET_SIMD_SET" 1372 "vst32_%4\\t%3,[i%2,%0]" 1373 [(set_attr "type" "simd_vstore") 1374 (set_attr "length" "4") 1375 (set_attr "cond" "nocond")]) 1376 1377;; SIMD unit interrupt 1378(define_insn "vinti_insn" 1379 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "L")] 1380 UNSPEC_ARC_SIMD_VINTI)] 1381 "TARGET_SIMD_SET" 1382 "vinti\\t%0" 1383 [(set_attr "type" "simd_vcontrol") 1384 (set_attr "length" "4") 1385 (set_attr "cond" "nocond")]) 1386 1387;; New ARCv2 SIMD extensions 1388 1389;;64-bit vectors of halwords and words 1390(define_mode_iterator VWH [V4HI V2SI]) 1391 1392;;double element vectors 1393(define_mode_iterator VDV [V2HI V2SI]) 1394(define_mode_attr V_addsub [(V2HI "HI") (V2SI "SI")]) 1395(define_mode_attr V_addsub_suffix [(V2HI "2h") (V2SI "")]) 1396 1397;;all vectors 1398(define_mode_iterator VCT [(V2HI "TARGET_PLUS_DMPY") 1399 (V4HI "TARGET_PLUS_QMACW") 1400 (V2SI "TARGET_PLUS_QMACW")]) 1401(define_mode_attr V_suffix [(V2HI "2h") (V4HI "4h") (V2SI "2")]) 1402 1403(define_code_iterator EMUVEC [(mult "TARGET_MPYW") 1404 (div "TARGET_DIVREM") 1405 smax smin]) 1406 1407(define_code_attr voptab [(mult "mul") 1408 (div "div") 1409 (smin "smin") 1410 (smax "smax")]) 1411 1412;; Widening operations. 1413(define_code_iterator SE [sign_extend zero_extend]) 1414(define_code_attr V_US [(sign_extend "s") (zero_extend "u")]) 1415(define_code_attr V_US_suffix [(sign_extend "") (zero_extend "u")]) 1416 1417 1418;; Move patterns 1419(define_expand "movv2hi" 1420 [(set (match_operand:V2HI 0 "move_dest_operand" "") 1421 (match_operand:V2HI 1 "general_operand" ""))] 1422 "" 1423 "{ 1424 if (prepare_move_operands (operands, V2HImode)) 1425 DONE; 1426 }") 1427 1428(define_insn_and_split "*movv2hi_insn" 1429 [(set (match_operand:V2HI 0 "move_dest_operand" "=r,r,r,m") 1430 (match_operand:V2HI 1 "general_operand" "i,r,m,r"))] 1431 "(register_operand (operands[0], V2HImode) 1432 || register_operand (operands[1], V2HImode))" 1433 "@ 1434 # 1435 mov%?\\t%0,%1 1436 ld%U1%V1\\t%0,%1 1437 st%U0%V0\\t%1,%0" 1438 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR" 1439 [(set (match_dup 0) (match_dup 2))] 1440 { 1441 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16; 1442 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF; 1443 1444 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); 1445 operands[2] = GEN_INT (trunc_int_for_mode (intval, SImode)); 1446 } 1447 [(set_attr "type" "move,move,load,store") 1448 (set_attr "predicable" "yes,yes,no,no") 1449 (set_attr "iscompact" "false,false,false,false") 1450 ]) 1451 1452(define_expand "movmisalignv2hi" 1453 [(set (match_operand:V2HI 0 "general_operand" "") 1454 (match_operand:V2HI 1 "general_operand" ""))] 1455 "unaligned_access" 1456 "{ 1457 if (prepare_move_operands (operands, V2HImode)) 1458 DONE; 1459 }") 1460 1461(define_expand "mov<mode>" 1462 [(set (match_operand:VWH 0 "move_dest_operand" "") 1463 (match_operand:VWH 1 "general_operand" ""))] 1464 "" 1465 "{ 1466 if (prepare_move_operands (operands, <MODE>mode)) 1467 DONE; 1468 }") 1469 1470(define_insn_and_split "*mov<mode>_insn" 1471 [(set (match_operand:VWH 0 "move_dest_operand" "=r,r,r,m") 1472 (match_operand:VWH 1 "general_operand" "i,r,m,r"))] 1473 "(register_operand (operands[0], <MODE>mode) 1474 || register_operand (operands[1], <MODE>mode))" 1475 "@ 1476 # 1477 vadd2\\t%0,%1,0 1478 ldd%U1%V1\\t%0,%1 1479 std%U0%V0\\t%1,%0" 1480 "&& reload_completed && arc_split_move_p (operands)" 1481 [(const_int 0)] 1482 { 1483 arc_split_move (operands); 1484 DONE; 1485 } 1486 [(set_attr "type" "move,move,load,store") 1487 (set_attr "length" "16,8,16,16")]) 1488 1489(define_expand "movmisalign<mode>" 1490 [(set (match_operand:VWH 0 "general_operand" "") 1491 (match_operand:VWH 1 "general_operand" ""))] 1492 "unaligned_access" 1493 "{ 1494 if (prepare_move_operands (operands, <MODE>mode)) 1495 DONE; 1496 }") 1497 1498(define_insn "bswapv2hi2" 1499 [(set (match_operand:V2HI 0 "register_operand" "=r,r") 1500 (bswap:V2HI (match_operand:V2HI 1 "nonmemory_operand" "r,i")))] 1501 "TARGET_V2 && TARGET_SWAP" 1502 "swape\\t%0,%1" 1503 [(set_attr "length" "4,8") 1504 (set_attr "type" "two_cycle_core")]) 1505 1506;; Simple arithmetic insns 1507(define_insn "add<mode>3" 1508 [(set (match_operand:VCT 0 "register_operand" "=r,r") 1509 (plus:VCT (match_operand:VCT 1 "register_operand" "0,r") 1510 (match_operand:VCT 2 "register_operand" "r,r")))] 1511 "TARGET_PLUS_DMPY" 1512 "vadd<V_suffix>%?\\t%0,%1,%2" 1513 [(set_attr "length" "4") 1514 (set_attr "type" "multi") 1515 (set_attr "predicable" "yes,no") 1516 (set_attr "cond" "canuse,nocond")]) 1517 1518(define_insn "sub<mode>3" 1519 [(set (match_operand:VCT 0 "register_operand" "=r,r") 1520 (minus:VCT (match_operand:VCT 1 "register_operand" "0,r") 1521 (match_operand:VCT 2 "register_operand" "r,r")))] 1522 "TARGET_PLUS_DMPY" 1523 "vsub<V_suffix>%?\\t%0,%1,%2" 1524 [(set_attr "length" "4") 1525 (set_attr "type" "multi") 1526 (set_attr "predicable" "yes,no") 1527 (set_attr "cond" "canuse,nocond")]) 1528 1529;; Combined arithmetic ops 1530(define_insn "addsub<mode>3" 1531 [(set (match_operand:VDV 0 "register_operand" "=r,r") 1532 (vec_concat:VDV 1533 (plus:<V_addsub> 1534 (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r") 1535 (parallel [(const_int 0)])) 1536 (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r") 1537 (parallel [(const_int 0)]))) 1538 (minus:<V_addsub> 1539 (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)])) 1540 (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))] 1541 "TARGET_PLUS_DMPY" 1542 "vaddsub<V_addsub_suffix>%?\\t%0,%1,%2" 1543 [(set_attr "length" "4") 1544 (set_attr "type" "multi") 1545 (set_attr "predicable" "yes,no") 1546 (set_attr "cond" "canuse,nocond")]) 1547 1548(define_insn "subadd<mode>3" 1549 [(set (match_operand:VDV 0 "register_operand" "=r,r") 1550 (vec_concat:VDV 1551 (minus:<V_addsub> 1552 (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r") 1553 (parallel [(const_int 0)])) 1554 (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r") 1555 (parallel [(const_int 0)]))) 1556 (plus:<V_addsub> 1557 (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)])) 1558 (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))] 1559 "TARGET_PLUS_DMPY" 1560 "vsubadd<V_addsub_suffix>%?\\t%0,%1,%2" 1561 [(set_attr "length" "4") 1562 (set_attr "type" "multi") 1563 (set_attr "predicable" "yes,no") 1564 (set_attr "cond" "canuse,nocond")]) 1565 1566(define_insn "addsubv4hi3" 1567 [(set (match_operand:V4HI 0 "even_register_operand" "=r,r") 1568 (vec_concat:V4HI 1569 (vec_concat:V2HI 1570 (plus:HI 1571 (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r") 1572 (parallel [(const_int 0)])) 1573 (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r") 1574 (parallel [(const_int 0)]))) 1575 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) 1576 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))) 1577 (vec_concat:V2HI 1578 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])) 1579 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))) 1580 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])) 1581 (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))) 1582 ))] 1583 "TARGET_PLUS_QMACW" 1584 "vaddsub4h%?\\t%0,%1,%2" 1585 [(set_attr "length" "4") 1586 (set_attr "type" "multi") 1587 (set_attr "predicable" "yes,no") 1588 (set_attr "cond" "canuse,nocond")]) 1589 1590(define_insn "subaddv4hi3" 1591 [(set (match_operand:V4HI 0 "even_register_operand" "=r,r") 1592 (vec_concat:V4HI 1593 (vec_concat:V2HI 1594 (minus:HI 1595 (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r") 1596 (parallel [(const_int 0)])) 1597 (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r") 1598 (parallel [(const_int 0)]))) 1599 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])) 1600 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))) 1601 (vec_concat:V2HI 1602 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])) 1603 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))) 1604 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])) 1605 (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))) 1606 ))] 1607 "TARGET_PLUS_QMACW" 1608 "vsubadd4h%?\\t%0,%1,%2" 1609 [(set_attr "length" "4") 1610 (set_attr "type" "multi") 1611 (set_attr "predicable" "yes,no") 1612 (set_attr "cond" "canuse,nocond")]) 1613 1614;; Multiplication 1615(define_insn "dmpyh<V_US_suffix>" 1616 [(set (match_operand:SI 0 "register_operand" "=r,r") 1617 (plus:SI 1618 (mult:SI 1619 (SE:SI 1620 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,r") 1621 (parallel [(const_int 0)]))) 1622 (SE:SI 1623 (vec_select:HI (match_operand:V2HI 2 "register_operand" "r,r") 1624 (parallel [(const_int 0)])))) 1625 (mult:SI 1626 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) 1627 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))) 1628 (set (reg:DI ARCV2_ACC) 1629 (zero_extend:DI 1630 (plus:SI 1631 (mult:SI 1632 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 0)]))) 1633 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))) 1634 (mult:SI 1635 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) 1636 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))))] 1637 "TARGET_PLUS_DMPY" 1638 "dmpyh<V_US_suffix>%?\\t%0,%1,%2" 1639 [(set_attr "length" "4") 1640 (set_attr "type" "multi") 1641 (set_attr "predicable" "yes,no") 1642 (set_attr "cond" "canuse,nocond")]) 1643 1644;; We can use dmac as well here. To be investigated which version 1645;; brings more. 1646(define_expand "sdot_prodv2hi" 1647 [(match_operand:SI 0 "register_operand" "") 1648 (match_operand:V2HI 1 "register_operand" "") 1649 (match_operand:V2HI 2 "register_operand" "") 1650 (match_operand:SI 3 "register_operand" "")] 1651 "TARGET_PLUS_DMPY" 1652{ 1653 rtx t = gen_reg_rtx (SImode); 1654 emit_insn (gen_dmpyh (t, operands[1], operands[2])); 1655 emit_insn (gen_addsi3 (operands[0], operands[3], t)); 1656 DONE; 1657}) 1658 1659(define_expand "udot_prodv2hi" 1660 [(match_operand:SI 0 "register_operand" "") 1661 (match_operand:V2HI 1 "register_operand" "") 1662 (match_operand:V2HI 2 "register_operand" "") 1663 (match_operand:SI 3 "register_operand" "")] 1664 "TARGET_PLUS_DMPY" 1665{ 1666 rtx t = gen_reg_rtx (SImode); 1667 emit_insn (gen_dmpyhu (t, operands[1], operands[2])); 1668 emit_insn (gen_addsi3 (operands[0], operands[3], t)); 1669 DONE; 1670}) 1671 1672(define_expand "sdot_prodv4hi" 1673 [(match_operand:V2SI 0 "register_operand" "") 1674 (match_operand:V4HI 1 "register_operand" "") 1675 (match_operand:V4HI 2 "register_operand" "") 1676 (match_operand:V2SI 3 "register_operand" "")] 1677 "TARGET_PLUS_MACD" 1678{ 1679 rtx acc_reg = gen_rtx_REG (V2SImode, ACC_REG_FIRST); 1680 rtx op1_low = gen_lowpart (V2HImode, operands[1]); 1681 rtx op1_high = gen_highpart (V2HImode, operands[1]); 1682 rtx op2_low = gen_lowpart (V2HImode, operands[2]); 1683 rtx op2_high = gen_highpart (V2HImode, operands[2]); 1684 1685 emit_move_insn (acc_reg, operands[3]); 1686 emit_insn (gen_arc_vec_smac_v2hiv2si_zero (op1_low, op2_low)); 1687 emit_insn (gen_arc_vec_smac_v2hiv2si (operands[0], op1_high, op2_high)); 1688 DONE; 1689}) 1690 1691(define_expand "udot_prodv4hi" 1692 [(match_operand:V2SI 0 "register_operand" "") 1693 (match_operand:V4HI 1 "register_operand" "") 1694 (match_operand:V4HI 2 "register_operand" "") 1695 (match_operand:V2SI 3 "register_operand" "")] 1696 "TARGET_PLUS_MACD" 1697{ 1698 rtx acc_reg = gen_rtx_REG (V2SImode, ACC_REG_FIRST); 1699 rtx op1_low = gen_lowpart (V2HImode, operands[1]); 1700 rtx op1_high = gen_highpart (V2HImode, operands[1]); 1701 rtx op2_low = gen_lowpart (V2HImode, operands[2]); 1702 rtx op2_high = gen_highpart (V2HImode, operands[2]); 1703 1704 emit_move_insn (acc_reg, operands[3]); 1705 emit_insn (gen_arc_vec_umac_v2hiv2si_zero (op1_low, op2_low)); 1706 emit_insn (gen_arc_vec_umac_v2hiv2si (operands[0], op1_high, op2_high)); 1707 DONE; 1708}) 1709 1710(define_insn "arc_vec_<V_US>mult_lo_v4hi" 1711 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") 1712 (mult:V2SI (SE:V2SI (vec_select:V2HI 1713 (match_operand:V4HI 1 "even_register_operand" "0,r") 1714 (parallel [(const_int 0) (const_int 1)]))) 1715 (SE:V2SI (vec_select:V2HI 1716 (match_operand:V4HI 2 "even_register_operand" "r,r") 1717 (parallel [(const_int 0) (const_int 1)]))))) 1718 (set (reg:V2SI ARCV2_ACC) 1719 (mult:V2SI (SE:V2SI 1720 (vec_select:V2HI (match_dup 1) 1721 (parallel [(const_int 0) (const_int 1)]))) 1722 (SE:V2SI 1723 (vec_select:V2HI (match_dup 2) 1724 (parallel [(const_int 0) (const_int 1)]))))) 1725 ] 1726 "TARGET_PLUS_MACD" 1727 "vmpy2h<V_US_suffix>%?\\t%0,%1,%2" 1728 [(set_attr "length" "4") 1729 (set_attr "type" "multi") 1730 (set_attr "predicable" "yes,no") 1731 (set_attr "cond" "canuse,nocond")]) 1732 1733(define_insn "arc_vec_<V_US>multacc_lo_v4hi" 1734 [(set (reg:V2SI ARCV2_ACC) 1735 (mult:V2SI (SE:V2SI (vec_select:V2HI 1736 (match_operand:V4HI 0 "even_register_operand" "r") 1737 (parallel [(const_int 0) (const_int 1)]))) 1738 (SE:V2SI (vec_select:V2HI 1739 (match_operand:V4HI 1 "even_register_operand" "r") 1740 (parallel [(const_int 0) (const_int 1)]))))) 1741 ] 1742 "TARGET_PLUS_MACD" 1743 "vmpy2h<V_US_suffix>%?\\t0,%0,%1" 1744 [(set_attr "length" "4") 1745 (set_attr "type" "multi") 1746 (set_attr "predicable" "no") 1747 (set_attr "cond" "nocond")]) 1748 1749(define_expand "vec_widen_<V_US>mult_lo_v4hi" 1750 [(set (match_operand:V2SI 0 "even_register_operand" "") 1751 (mult:V2SI (SE:V2SI (vec_select:V2HI 1752 (match_operand:V4HI 1 "even_register_operand" "") 1753 (parallel [(const_int 0) (const_int 1)]))) 1754 (SE:V2SI (vec_select:V2HI 1755 (match_operand:V4HI 2 "even_register_operand" "") 1756 (parallel [(const_int 0) (const_int 1)])))))] 1757 "TARGET_PLUS_QMACW" 1758 { 1759 emit_insn (gen_arc_vec_<V_US>mult_lo_v4hi (operands[0], 1760 operands[1], 1761 operands[2])); 1762 DONE; 1763 } 1764) 1765 1766(define_insn "arc_vec_<V_US>mult_hi_v4hi" 1767 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") 1768 (mult:V2SI (SE:V2SI (vec_select:V2HI 1769 (match_operand:V4HI 1 "even_register_operand" "0,r") 1770 (parallel [(const_int 2) (const_int 3)]))) 1771 (SE:V2SI (vec_select:V2HI 1772 (match_operand:V4HI 2 "even_register_operand" "r,r") 1773 (parallel [(const_int 2) (const_int 3)]))))) 1774 (set (reg:V2SI ARCV2_ACC) 1775 (mult:V2SI (SE:V2SI 1776 (vec_select:V2HI (match_dup 1) 1777 (parallel [(const_int 2) (const_int 3)]))) 1778 (SE:V2SI 1779 (vec_select:V2HI (match_dup 2) 1780 (parallel [(const_int 2) (const_int 3)]))))) 1781 ] 1782 "TARGET_PLUS_QMACW" 1783 "vmpy2h<V_US_suffix>%?\\t%0,%R1,%R2" 1784 [(set_attr "length" "4") 1785 (set_attr "type" "multi") 1786 (set_attr "predicable" "yes,no") 1787 (set_attr "cond" "canuse,nocond")]) 1788 1789(define_expand "vec_widen_<V_US>mult_hi_v4hi" 1790 [(set (match_operand:V2SI 0 "even_register_operand") 1791 (mult:V2SI (SE:V2SI (vec_select:V2HI 1792 (match_operand:V4HI 1 "even_register_operand") 1793 (parallel [(const_int 2) (const_int 3)]))) 1794 (SE:V2SI (vec_select:V2HI 1795 (match_operand:V4HI 2 "even_register_operand") 1796 (parallel [(const_int 2) (const_int 3)])))))] 1797 "TARGET_PLUS_QMACW" 1798 { 1799 emit_insn (gen_arc_vec_<V_US>mult_hi_v4hi (operands[0], 1800 operands[1], 1801 operands[2])); 1802 DONE; 1803 } 1804) 1805 1806(define_insn "arc_vec_<V_US>mac_v2hiv2si" 1807 [(set (match_operand:V2SI 0 "even_register_operand" "=r,Ral,r") 1808 (plus:V2SI 1809 (mult:V2SI 1810 (SE:V2SI (match_operand:V2HI 1 "register_operand" "0, r,r")) 1811 (SE:V2SI (match_operand:V2HI 2 "register_operand" "r, r,r"))) 1812 (reg:V2SI ARCV2_ACC))) 1813 (set (reg:V2SI ARCV2_ACC) 1814 (plus:V2SI 1815 (mult:V2SI (SE:V2SI (match_dup 1)) 1816 (SE:V2SI (match_dup 2))) 1817 (reg:V2SI ARCV2_ACC))) 1818 ] 1819 "TARGET_PLUS_MACD" 1820 "@ 1821 vmac2h<V_US_suffix>%?\\t%0,%1,%2 1822 vmac2h<V_US_suffix>%?\\t0,%1,%2 1823 vmac2h<V_US_suffix>%?\\t%0,%1,%2" 1824 [(set_attr "length" "4") 1825 (set_attr "type" "multi") 1826 (set_attr "predicable" "yes,no,no")]) 1827 1828(define_insn "arc_vec_<V_US>mac_v2hiv2si_zero" 1829 [(set (reg:V2SI ARCV2_ACC) 1830 (plus:V2SI 1831 (mult:V2SI (SE:V2SI (match_operand:V2HI 0 "register_operand" "r")) 1832 (SE:V2SI (match_operand:V2HI 1 "register_operand" "r"))) 1833 (reg:V2SI ARCV2_ACC)))] 1834 "TARGET_PLUS_MACD" 1835 "vmac2h<V_US_suffix>%?\\t0,%0,%1" 1836 [(set_attr "length" "4") 1837 (set_attr "type" "multi")]) 1838 1839;; Builtins 1840(define_insn "dmach" 1841 [(set (match_operand:SI 0 "register_operand" "=r,r") 1842 (unspec:SI [(match_operand:V2HI 1 "register_operand" "0,r") 1843 (match_operand:V2HI 2 "register_operand" "r,r") 1844 (reg:DI ARCV2_ACC)] 1845 UNSPEC_ARC_DMACH)) 1846 (clobber (reg:DI ARCV2_ACC))] 1847 "TARGET_PLUS_DMPY" 1848 "dmach%?\\t%0,%1,%2" 1849 [(set_attr "length" "4") 1850 (set_attr "type" "multi") 1851 (set_attr "predicable" "yes,no") 1852 (set_attr "cond" "canuse,nocond")]) 1853 1854(define_insn "dmachu" 1855 [(set (match_operand:SI 0 "register_operand" "=r,r") 1856 (unspec:SI [(match_operand:V2HI 1 "register_operand" "0,r") 1857 (match_operand:V2HI 2 "register_operand" "r,r") 1858 (reg:DI ARCV2_ACC)] 1859 UNSPEC_ARC_DMACHU)) 1860 (clobber (reg:DI ARCV2_ACC))] 1861 "TARGET_PLUS_DMPY" 1862 "dmachu%?\\t%0,%1,%2" 1863 [(set_attr "length" "4") 1864 (set_attr "type" "multi") 1865 (set_attr "predicable" "yes,no") 1866 (set_attr "cond" "canuse,nocond")]) 1867 1868(define_insn "dmacwh" 1869 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 1870 (unspec:DI [(match_operand:V2SI 1 "even_register_operand" "0,r") 1871 (match_operand:V2HI 2 "register_operand" "r,r") 1872 (reg:DI ARCV2_ACC)] 1873 UNSPEC_ARC_DMACWH)) 1874 (clobber (reg:DI ARCV2_ACC))] 1875 "TARGET_PLUS_QMACW" 1876 "dmacwh%?\\t%0,%1,%2" 1877 [(set_attr "length" "4") 1878 (set_attr "type" "multi") 1879 (set_attr "predicable" "yes,no") 1880 (set_attr "cond" "canuse,nocond")]) 1881 1882(define_insn "dmacwhu" 1883 [(set (match_operand:DI 0 "register_operand" "=r,r") 1884 (unspec:DI [(match_operand:V2SI 1 "even_register_operand" "0,r") 1885 (match_operand:V2HI 2 "register_operand" "r,r") 1886 (reg:DI ARCV2_ACC)] 1887 UNSPEC_ARC_DMACWHU)) 1888 (clobber (reg:DI ARCV2_ACC))] 1889 "TARGET_PLUS_QMACW" 1890 "dmacwhu%?\\t%0,%1,%2" 1891 [(set_attr "length" "4") 1892 (set_attr "type" "multi") 1893 (set_attr "predicable" "yes,no") 1894 (set_attr "cond" "canuse,nocond")]) 1895 1896(define_insn "vmac2h" 1897 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") 1898 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r") 1899 (match_operand:V2HI 2 "register_operand" "r,r") 1900 (reg:DI ARCV2_ACC)] 1901 UNSPEC_ARC_VMAC2H)) 1902 (clobber (reg:DI ARCV2_ACC))] 1903 "TARGET_PLUS_MACD" 1904 "vmac2h%?\\t%0,%1,%2" 1905 [(set_attr "length" "4") 1906 (set_attr "type" "multi") 1907 (set_attr "predicable" "yes,no") 1908 (set_attr "cond" "canuse,nocond")]) 1909 1910(define_insn "vmac2hu" 1911 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") 1912 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r") 1913 (match_operand:V2HI 2 "register_operand" "r,r") 1914 (reg:DI ARCV2_ACC)] 1915 UNSPEC_ARC_VMAC2HU)) 1916 (clobber (reg:DI ARCV2_ACC))] 1917 "TARGET_PLUS_MACD" 1918 "vmac2hu%?\\t%0,%1,%2" 1919 [(set_attr "length" "4") 1920 (set_attr "type" "multi") 1921 (set_attr "predicable" "yes,no") 1922 (set_attr "cond" "canuse,nocond")]) 1923 1924(define_insn "vmpy2h" 1925 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") 1926 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r") 1927 (match_operand:V2HI 2 "register_operand" "r,r")] 1928 UNSPEC_ARC_VMPY2H)) 1929 (clobber (reg:DI ARCV2_ACC))] 1930 "TARGET_PLUS_MACD" 1931 "vmpy2h%?\\t%0,%1,%2" 1932 [(set_attr "length" "4") 1933 (set_attr "type" "multi") 1934 (set_attr "predicable" "yes,no") 1935 (set_attr "cond" "canuse,nocond")]) 1936 1937(define_insn "vmpy2hu" 1938 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") 1939 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r") 1940 (match_operand:V2HI 2 "register_operand" "r,r")] 1941 UNSPEC_ARC_VMPY2HU)) 1942 (clobber (reg:DI ARCV2_ACC))] 1943 "TARGET_PLUS_MACD" 1944 "vmpy2hu%?\\t%0,%1,%2" 1945 [(set_attr "length" "4") 1946 (set_attr "type" "multi") 1947 (set_attr "predicable" "yes,no") 1948 (set_attr "cond" "canuse,nocond")]) 1949 1950(define_insn "qmach" 1951 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 1952 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r") 1953 (match_operand:V4HI 2 "even_register_operand" "r,r") 1954 (reg:DI ARCV2_ACC)] 1955 UNSPEC_ARC_QMACH)) 1956 (clobber (reg:DI ARCV2_ACC))] 1957 "TARGET_PLUS_QMACW" 1958 "qmach%?\\t%0,%1,%2" 1959 [(set_attr "length" "4") 1960 (set_attr "type" "multi") 1961 (set_attr "predicable" "yes,no") 1962 (set_attr "cond" "canuse,nocond")]) 1963 1964(define_insn "qmachu" 1965 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 1966 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r") 1967 (match_operand:V4HI 2 "even_register_operand" "r,r") 1968 (reg:DI ARCV2_ACC)] 1969 UNSPEC_ARC_QMACHU)) 1970 (clobber (reg:DI ARCV2_ACC))] 1971 "TARGET_PLUS_QMACW" 1972 "qmachu%?\\t%0,%1,%2" 1973 [(set_attr "length" "4") 1974 (set_attr "type" "multi") 1975 (set_attr "predicable" "yes,no") 1976 (set_attr "cond" "canuse,nocond")]) 1977 1978(define_insn "qmpyh" 1979 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 1980 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r") 1981 (match_operand:V4HI 2 "even_register_operand" "r,r")] 1982 UNSPEC_ARC_QMPYH)) 1983 (clobber (reg:DI ARCV2_ACC))] 1984 "TARGET_PLUS_QMACW" 1985 "qmpyh%?\\t%0,%1,%2" 1986 [(set_attr "length" "4") 1987 (set_attr "type" "multi") 1988 (set_attr "predicable" "yes,no") 1989 (set_attr "cond" "canuse,nocond")]) 1990 1991(define_insn "qmpyhu" 1992 [(set (match_operand:DI 0 "even_register_operand" "=r,r") 1993 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r") 1994 (match_operand:V4HI 2 "even_register_operand" "r,r")] 1995 UNSPEC_ARC_QMPYHU)) 1996 (clobber (reg:DI ARCV2_ACC))] 1997 "TARGET_PLUS_QMACW" 1998 "qmpyhu%?\\t%0,%1,%2" 1999 [(set_attr "length" "4") 2000 (set_attr "type" "multi") 2001 (set_attr "predicable" "yes,no") 2002 (set_attr "cond" "canuse,nocond")]) 2003 2004;; Emulated vector instructions. 2005(define_insn_and_split "<voptab>v2si3" 2006 [(set (match_operand:V2SI 0 "register_operand" "=r") 2007 (EMUVEC:V2SI (match_operand:V2SI 1 "register_operand" "r") 2008 (match_operand:V2SI 2 "nonmemory_operand" "ri")))] 2009 "" 2010 "#" 2011 "reload_completed" 2012 [(const_int 0)] 2013 { 2014 rtx high_dest = gen_highpart (SImode, operands[0]); 2015 rtx low_dest = gen_lowpart (SImode, operands[0]); 2016 rtx high_op1 = gen_highpart (SImode, operands[1]); 2017 rtx low_op1 = gen_lowpart (SImode, operands[1]); 2018 rtx high_op2 = gen_highpart (SImode, operands[2]); 2019 rtx low_op2 = gen_lowpart (SImode, operands[2]); 2020 emit_insn (gen_<voptab>si3 (low_dest, low_op1, low_op2)); 2021 emit_insn (gen_<voptab>si3 (high_dest, high_op1, high_op2)); 2022 DONE; 2023 } 2024 [(set_attr "length" "12") 2025 (set_attr "type" "multi")]) 2026 2027(define_expand "neg<mode>2" 2028 [(set (match_operand:VCT 0 "register_operand") 2029 (neg:VCT (match_operand:VCT 1 "register_operand")))] 2030 "TARGET_PLUS_DMPY" 2031 "") 2032 2033(define_insn "*neg<mode>2" 2034 [(set (match_operand:VCT 0 "register_operand" "=r") 2035 (neg:VCT (match_operand:VCT 1 "register_operand" "r")))] 2036 "TARGET_PLUS_DMPY" 2037 "vsub<V_suffix>\\t%0,0,%1" 2038 [(set_attr "length" "8") 2039 (set_attr "type" "multi")]) 2040 2041(define_insn "reduc_plus_scal_v4hi" 2042 [(set (match_operand:HI 0 "even_register_operand" "=r") 2043 (unspec:HI [(match_operand:V4HI 1 "even_register_operand" "r")] 2044 UNSPEC_ARC_QMPYH)) 2045 (clobber (reg:DI ARCV2_ACC))] 2046 "TARGET_PLUS_QMACW" 2047 "qmpyh\\t%0,%1,1" 2048 [(set_attr "length" "4") 2049 (set_attr "type" "multi")]) 2050 2051(define_insn "reduc_plus_scal_v2si" 2052 [(set (match_operand:SI 0 "even_register_operand" "=r") 2053 (unspec:SI [(match_operand:V2SI 1 "even_register_operand" "r")] 2054 UNSPEC_ARC_DMPYWH)) 2055 (clobber (reg:DI ARCV2_ACC))] 2056 "TARGET_PLUS_DMPY" 2057 "dmpywh\\t%0,%1,1" 2058 [(set_attr "length" "4") 2059 (set_attr "type" "multi")]) 2060 2061(define_insn_and_split "vec_duplicatev2si" 2062 [(set (match_operand:V2SI 0 "register_operand" "=r") 2063 (vec_duplicate:V2SI 2064 (match_operand:SI 1 "nonmemory_operand" "ri")))] 2065 "" 2066 "#" 2067 "reload_completed" 2068 [(const_int 0)] 2069 { 2070 rtx high_dest = gen_highpart (SImode, operands[0]); 2071 rtx low_dest = gen_lowpart (SImode, operands[0]); 2072 emit_move_insn (high_dest, operands[1]); 2073 emit_move_insn (low_dest, operands[1]); 2074 DONE; 2075 } 2076 [(set_attr "length" "8") 2077 (set_attr "type" "multi")]) 2078 2079(define_insn_and_split "vec_duplicatev4hi" 2080 [(set (match_operand:V4HI 0 "register_operand" "=r") 2081 (vec_duplicate:V4HI 2082 (match_operand:HI 1 "nonmemory_operand" "ri")))] 2083 "TARGET_BARREL_SHIFTER" 2084 "#" 2085 "reload_completed" 2086 [(const_int 0)] 2087 { 2088 rtx high_dest = gen_highpart (SImode, operands[0]); 2089 rtx low_dest = gen_lowpart (SImode, operands[0]); 2090 rtx tmp = gen_lowpart (SImode, operands[1]); 2091 emit_insn (gen_rtx_SET (high_dest, 2092 gen_rtx_ASHIFT (SImode, tmp, GEN_INT (16)))); 2093 emit_insn (gen_rtx_SET (low_dest, 2094 gen_rtx_IOR (SImode, high_dest, tmp))); 2095 emit_move_insn (high_dest, low_dest); 2096 DONE; 2097 } 2098 [(set_attr "length" "12") 2099 (set_attr "type" "multi")]) 2100