1;; Predicate definitions for POWER and PowerPC. 2;; Copyright (C) 2005-2022 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Return 1 for anything except PARALLEL. 21(define_predicate "any_operand" 22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem")) 23 24;; Return 1 for any PARALLEL. 25(define_predicate "any_parallel_operand" 26 (match_code "parallel")) 27 28;; Return 1 if op is COUNT register. 29(define_predicate "count_register_operand" 30 (and (match_code "reg") 31 (match_test "REGNO (op) == CTR_REGNO 32 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) 33 34;; Return 1 if op is a SUBREG that is used to look at a SFmode value as 35;; and integer or vice versa. 36;; 37;; In the normal case where SFmode is in a floating point/vector register, it 38;; is stored as a DFmode and has a different format. If we don't transform the 39;; value, things that use logical operations on the values will get the wrong 40;; value. 41;; 42;; If we don't have 64-bit and direct move, this conversion will be done by 43;; store and load, instead of by fiddling with the bits within the register. 44(define_predicate "sf_subreg_operand" 45 (match_code "subreg") 46{ 47 rtx inner_reg = SUBREG_REG (op); 48 machine_mode inner_mode = GET_MODE (inner_reg); 49 50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg)) 51 return 0; 52 53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT) 54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode)) 55 { 56 if (INT_REGNO_P (REGNO (inner_reg))) 57 return 0; 58 59 return 1; 60 } 61 return 0; 62}) 63 64;; Return 1 if op is an Altivec register. 65(define_predicate "altivec_register_operand" 66 (match_operand 0 "register_operand") 67{ 68 if (SUBREG_P (op)) 69 { 70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 71 return 0; 72 73 op = SUBREG_REG (op); 74 } 75 76 if (!REG_P (op)) 77 return 0; 78 79 if (!HARD_REGISTER_P (op)) 80 return 1; 81 82 return ALTIVEC_REGNO_P (REGNO (op)); 83}) 84 85;; Return 1 if op is a VSX register. 86(define_predicate "vsx_register_operand" 87 (match_operand 0 "register_operand") 88{ 89 if (SUBREG_P (op)) 90 { 91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 92 return 0; 93 94 op = SUBREG_REG (op); 95 } 96 97 if (!REG_P (op)) 98 return 0; 99 100 if (!HARD_REGISTER_P (op)) 101 return 1; 102 103 return VSX_REGNO_P (REGNO (op)); 104}) 105 106;; Like vsx_register_operand, but allow SF SUBREGS 107(define_predicate "vsx_reg_sfsubreg_ok" 108 (match_operand 0 "register_operand") 109{ 110 if (SUBREG_P (op)) 111 op = SUBREG_REG (op); 112 113 if (!REG_P (op)) 114 return 0; 115 116 if (!HARD_REGISTER_P (op)) 117 return 1; 118 119 return VSX_REGNO_P (REGNO (op)); 120}) 121 122;; Return 1 if op is a vector register that operates on floating point vectors 123;; (either altivec or VSX). 124(define_predicate "vfloat_operand" 125 (match_operand 0 "register_operand") 126{ 127 if (SUBREG_P (op)) 128 { 129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 130 return 0; 131 132 op = SUBREG_REG (op); 133 } 134 135 if (!REG_P (op)) 136 return 0; 137 138 if (!HARD_REGISTER_P (op)) 139 return 1; 140 141 return VFLOAT_REGNO_P (REGNO (op)); 142}) 143 144;; Return 1 if op is a vector register that operates on integer vectors 145;; (only altivec, VSX doesn't support integer vectors) 146(define_predicate "vint_operand" 147 (match_operand 0 "register_operand") 148{ 149 if (SUBREG_P (op)) 150 { 151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 152 return 0; 153 154 op = SUBREG_REG (op); 155 } 156 157 if (!REG_P (op)) 158 return 0; 159 160 if (!HARD_REGISTER_P (op)) 161 return 1; 162 163 return VINT_REGNO_P (REGNO (op)); 164}) 165 166;; Return 1 if op is a vector register to do logical operations on (and, or, 167;; xor, etc.) 168(define_predicate "vlogical_operand" 169 (match_operand 0 "register_operand") 170{ 171 if (SUBREG_P (op)) 172 { 173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 174 return 0; 175 176 op = SUBREG_REG (op); 177 } 178 179 180 if (!REG_P (op)) 181 return 0; 182 183 if (!HARD_REGISTER_P (op)) 184 return 1; 185 186 return VLOGICAL_REGNO_P (REGNO (op)); 187}) 188 189;; Return 1 if op is the carry register. 190(define_predicate "ca_operand" 191 (match_operand 0 "register_operand") 192{ 193 if (SUBREG_P (op)) 194 op = SUBREG_REG (op); 195 196 if (!REG_P (op)) 197 return 0; 198 199 return CA_REGNO_P (REGNO (op)); 200}) 201 202;; Return 1 if operand is constant zero (scalars and vectors). 203(define_predicate "zero_constant" 204 (and (match_code "const_int,const_double,const_wide_int,const_vector") 205 (match_test "op == CONST0_RTX (mode)"))) 206 207;; Return 1 if operand is constant -1 (scalars and vectors). 208(define_predicate "all_ones_constant" 209 (and (match_code "const_int,const_double,const_wide_int,const_vector") 210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)"))) 211 212;; Return 1 if op is a signed 5-bit constant integer. 213(define_predicate "s5bit_cint_operand" 214 (and (match_code "const_int") 215 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) 216 217;; Return 1 if op is an unsigned 1-bit constant integer. 218(define_predicate "u1bit_cint_operand" 219 (and (match_code "const_int") 220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1"))) 221 222;; Return 1 if op is a unsigned 3-bit constant integer. 223(define_predicate "u3bit_cint_operand" 224 (and (match_code "const_int") 225 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) 226 227;; Return 1 if op is a unsigned 5-bit constant integer. 228(define_predicate "u5bit_cint_operand" 229 (and (match_code "const_int") 230 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) 231 232;; Return 1 if op is a unsigned 6-bit constant integer. 233(define_predicate "u6bit_cint_operand" 234 (and (match_code "const_int") 235 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63"))) 236 237;; Return 1 if op is an unsigned 7-bit constant integer. 238(define_predicate "u7bit_cint_operand" 239 (and (match_code "const_int") 240 (match_test "IN_RANGE (INTVAL (op), 0, 127)"))) 241 242;; Return 1 if op is a unsigned 8-bit constant integer. 243(define_predicate "u8bit_cint_operand" 244 (and (match_code "const_int") 245 (match_test "IN_RANGE (INTVAL (op), 0, 255)"))) 246 247;; Return 1 if op is a signed 8-bit constant integer. 248;; Integer multiplication complete more quickly 249(define_predicate "s8bit_cint_operand" 250 (and (match_code "const_int") 251 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) 252 253;; Return 1 if op is a unsigned 10-bit constant integer. 254(define_predicate "u10bit_cint_operand" 255 (and (match_code "const_int") 256 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) 257 258;; Return 1 if op is a constant integer that can fit in a D field. 259(define_predicate "short_cint_operand" 260 (and (match_code "const_int") 261 (match_test "satisfies_constraint_I (op)"))) 262 263;; Return 1 if op is a constant integer that can fit in an unsigned D field. 264(define_predicate "u_short_cint_operand" 265 (and (match_code "const_int") 266 (match_test "satisfies_constraint_K (op)"))) 267 268;; Return 1 if op is a constant integer that is a signed 16-bit constant 269;; shifted left 16 bits 270(define_predicate "upper16_cint_operand" 271 (and (match_code "const_int") 272 (match_test "satisfies_constraint_L (op)"))) 273 274;; Return 1 if op is a constant integer that cannot fit in a signed D field. 275(define_predicate "non_short_cint_operand" 276 (and (match_code "const_int") 277 (match_test "(unsigned HOST_WIDE_INT) 278 (INTVAL (op) + 0x8000) >= 0x10000"))) 279 280;; Return 1 if op is a 32-bit constant signed integer 281(define_predicate "s32bit_cint_operand" 282 (and (match_code "const_int") 283 (match_test "(0x80000000 + UINTVAL (op)) >> 32 == 0"))) 284 285;; Return 1 if op is a constant 32-bit unsigned 286(define_predicate "c32bit_cint_operand" 287 (and (match_code "const_int") 288 (match_test "((UINTVAL (op) >> 32) == 0)"))) 289 290;; Return 1 if op is a positive constant integer that is an exact power of 2. 291(define_predicate "exact_log2_cint_operand" 292 (and (match_code "const_int") 293 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) 294 295;; Match op = 0 or op = 1. 296(define_predicate "const_0_to_1_operand" 297 (and (match_code "const_int") 298 (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) 299 300;; Match op = -1, op = 0, or op = 1. 301(define_predicate "const_m1_to_1_operand" 302 (and (match_code "const_int") 303 (match_test "IN_RANGE (INTVAL (op), -1, 1)"))) 304 305;; Match op = 0..3. 306(define_predicate "const_0_to_3_operand" 307 (and (match_code "const_int") 308 (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) 309 310;; Match op = 2 or op = 3. 311(define_predicate "const_2_to_3_operand" 312 (and (match_code "const_int") 313 (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) 314 315;; Match op = 0..7. 316(define_predicate "const_0_to_7_operand" 317 (and (match_code "const_int") 318 (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) 319 320;; Match op = 0..11 321(define_predicate "const_0_to_12_operand" 322 (and (match_code "const_int") 323 (match_test "IN_RANGE (INTVAL (op), 0, 12)"))) 324 325;; Match op = 0..15 326(define_predicate "const_0_to_15_operand" 327 (and (match_code "const_int") 328 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 329 330;; Return 1 if op is a 34-bit constant integer. 331(define_predicate "cint34_operand" 332 (match_code "const_int") 333{ 334 if (!TARGET_PREFIXED) 335 return 0; 336 337 return SIGNED_INTEGER_34BIT_P (INTVAL (op)); 338}) 339 340;; Return 1 if op is a register that is not special. 341;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where 342;; you need to be careful in moving a SFmode to SImode and vice versa due to 343;; the fact that SFmode is represented as DFmode in the VSX registers. 344(define_predicate "gpc_reg_operand" 345 (match_operand 0 "register_operand") 346{ 347 if (SUBREG_P (op)) 348 { 349 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 350 return 0; 351 352 op = SUBREG_REG (op); 353 } 354 355 if (!REG_P (op)) 356 return 0; 357 358 if (!HARD_REGISTER_P (op)) 359 return 1; 360 361 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op))) 362 return 1; 363 364 if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) 365 return 1; 366 367 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); 368}) 369 370;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't 371;; allow floating point or vector registers. Since vector registers are not 372;; allowed, we don't have to reject SFmode/SImode subregs. 373(define_predicate "int_reg_operand" 374 (match_operand 0 "register_operand") 375{ 376 if (SUBREG_P (op)) 377 { 378 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 379 return 0; 380 381 op = SUBREG_REG (op); 382 } 383 384 if (!REG_P (op)) 385 return 0; 386 387 if (!HARD_REGISTER_P (op)) 388 return 1; 389 390 return INT_REGNO_P (REGNO (op)); 391}) 392 393;; Like int_reg_operand, but don't return true for pseudo registers 394;; We don't have to check for SF SUBREGS because pseudo registers 395;; are not allowed, and SF SUBREGs are ok within GPR registers. 396(define_predicate "int_reg_operand_not_pseudo" 397 (match_operand 0 "register_operand") 398{ 399 if (SUBREG_P (op)) 400 op = SUBREG_REG (op); 401 402 if (!REG_P (op)) 403 return 0; 404 405 if (!HARD_REGISTER_P (op)) 406 return 0; 407 408 return INT_REGNO_P (REGNO (op)); 409}) 410 411;; Like int_reg_operand, but only return true for base registers 412(define_predicate "base_reg_operand" 413 (match_operand 0 "int_reg_operand") 414{ 415 if (SUBREG_P (op)) 416 op = SUBREG_REG (op); 417 418 if (!REG_P (op)) 419 return 0; 420 421 return (REGNO (op) != FIRST_GPR_REGNO); 422}) 423 424 425;; Return true if this is a traditional floating point register 426(define_predicate "fpr_reg_operand" 427 (match_code "reg,subreg") 428{ 429 HOST_WIDE_INT r; 430 431 if (SUBREG_P (op)) 432 op = SUBREG_REG (op); 433 434 if (!REG_P (op)) 435 return 0; 436 437 r = REGNO (op); 438 if (!HARD_REGISTER_NUM_P (r)) 439 return 1; 440 441 return FP_REGNO_P (r); 442}) 443 444;; Return 1 if op is a general purpose register that is an even register 445;; which suitable for a load/store quad operation 446;; Subregs are not allowed here because when they are combine can 447;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to 448;; think the innermost reg needs reloading, in TImode instead of 449;; PTImode. So reload will choose a reg in TImode which has no 450;; requirement that the reg be even. 451(define_predicate "quad_int_reg_operand" 452 (match_code "reg") 453{ 454 HOST_WIDE_INT r; 455 456 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) 457 return 0; 458 459 r = REGNO (op); 460 if (!HARD_REGISTER_NUM_P (r)) 461 return 1; 462 463 return (INT_REGNO_P (r) && ((r & 1) == 0)); 464}) 465 466;; Return 1 if op is a register that is a condition register field. 467(define_predicate "cc_reg_operand" 468 (match_operand 0 "register_operand") 469{ 470 if (SUBREG_P (op)) 471 op = SUBREG_REG (op); 472 473 if (!REG_P (op)) 474 return 0; 475 476 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 477 return 1; 478 479 return CR_REGNO_P (REGNO (op)); 480}) 481 482;; Return 1 if op is a register that is a condition register field not cr0. 483(define_predicate "cc_reg_not_cr0_operand" 484 (match_operand 0 "register_operand") 485{ 486 if (SUBREG_P (op)) 487 op = SUBREG_REG (op); 488 489 if (!REG_P (op)) 490 return 0; 491 492 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 493 return 1; 494 495 return CR_REGNO_NOT_CR0_P (REGNO (op)); 496}) 497 498;; Return 1 if op is a constant integer valid for D field 499;; or non-special register. 500(define_predicate "reg_or_short_operand" 501 (if_then_else (match_code "const_int") 502 (match_operand 0 "short_cint_operand") 503 (match_operand 0 "gpc_reg_operand"))) 504 505;; Return 1 if op is a constant integer valid for DS field 506;; or non-special register. 507(define_predicate "reg_or_aligned_short_operand" 508 (if_then_else (match_code "const_int") 509 (and (match_operand 0 "short_cint_operand") 510 (match_test "!(INTVAL (op) & 3)")) 511 (match_operand 0 "gpc_reg_operand"))) 512 513;; Return 1 if op is a constant integer whose high-order 16 bits are zero 514;; or non-special register. 515(define_predicate "reg_or_u_short_operand" 516 (if_then_else (match_code "const_int") 517 (match_operand 0 "u_short_cint_operand") 518 (match_operand 0 "gpc_reg_operand"))) 519 520;; Return 1 if op is any constant integer or a non-special register. 521(define_predicate "reg_or_cint_operand" 522 (ior (match_code "const_int") 523 (match_operand 0 "gpc_reg_operand"))) 524 525;; Return 1 if op is constant zero or a non-special register. 526(define_predicate "reg_or_zero_operand" 527 (ior (match_operand 0 "zero_constant") 528 (match_operand 0 "gpc_reg_operand"))) 529 530;; Return 1 if op is a constant integer valid for addition with addis, addi. 531(define_predicate "add_cint_operand" 532 (and (match_code "const_int") 533 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) 534 + (mode == SImode ? 0x80000000 : 0x80008000)) 535 < (unsigned HOST_WIDE_INT) 0x100000000ll"))) 536 537;; Return 1 if op is a constant integer valid for addition 538;; or non-special register. 539(define_predicate "reg_or_add_cint_operand" 540 (if_then_else (match_code "const_int") 541 (match_operand 0 "add_cint_operand") 542 (match_operand 0 "gpc_reg_operand"))) 543 544;; Return 1 if op is a constant integer valid for subtraction 545;; or non-special register. 546(define_predicate "reg_or_sub_cint_operand" 547 (if_then_else (match_code "const_int") 548 (match_test "(unsigned HOST_WIDE_INT) 549 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) 550 < (unsigned HOST_WIDE_INT) 0x100000000ll") 551 (match_operand 0 "gpc_reg_operand"))) 552 553;; Return 1 if op is any 32-bit unsigned constant integer 554;; or non-special register. 555(define_predicate "reg_or_logical_cint_operand" 556 (if_then_else (match_code "const_int") 557 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 558 && INTVAL (op) >= 0) 559 || ((INTVAL (op) & GET_MODE_MASK (mode) 560 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") 561 (match_operand 0 "gpc_reg_operand"))) 562 563;; Like reg_or_logical_cint_operand, but allow vsx registers 564(define_predicate "vsx_reg_or_cint_operand" 565 (ior (match_operand 0 "vsx_register_operand") 566 (match_operand 0 "reg_or_logical_cint_operand"))) 567 568;; Return 1 if operand is a CONST_DOUBLE that can be set in a register 569;; with no more than one instruction per word. 570(define_predicate "easy_fp_constant" 571 (match_code "const_double") 572{ 573 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode)); 574 575 /* Consider all constants with -msoft-float to be easy when regs are 576 32-bit and thus can be loaded with a maximum of 2 insns. For 577 64-bit avoid long dependent insn sequences. */ 578 if (TARGET_SOFT_FLOAT) 579 { 580 if (!TARGET_POWERPC64) 581 return 1; 582 583 int size = GET_MODE_SIZE (mode); 584 if (size < 8) 585 return 1; 586 587 int load_from_mem_insns = 2; 588 if (size > 8) 589 load_from_mem_insns++; 590 if (TARGET_CMODEL != CMODEL_SMALL) 591 load_from_mem_insns++; 592 if (num_insns_constant (op, mode) <= load_from_mem_insns) 593 return 1; 594 } 595 596 /* 0.0D is not all zero bits. */ 597 if (DECIMAL_FLOAT_MODE_P (mode)) 598 return 0; 599 600 /* The constant 0.0 is easy under VSX. */ 601 if (TARGET_VSX && op == CONST0_RTX (mode)) 602 return 1; 603 604 /* Constants that can be generated with ISA 3.1 instructions are easy. */ 605 vec_const_128bit_type vsx_const; 606 if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) 607 { 608 if (constant_generates_lxvkq (&vsx_const)) 609 return true; 610 611 if (constant_generates_xxspltiw (&vsx_const)) 612 return true; 613 614 if (constant_generates_xxspltidp (&vsx_const)) 615 return true; 616 } 617 618 /* Otherwise consider floating point constants hard, so that the 619 constant gets pushed to memory during the early RTL phases. This 620 has the advantage that double precision constants that can be 621 represented in single precision without a loss of precision will 622 use single precision loads. */ 623 return 0; 624}) 625 626;; Return 1 if the operand is a 64-bit floating point scalar constant or a 627;; vector constant that can be loaded to a VSX register with one prefixed 628;; instruction, such as XXSPLTIDP or XXSPLTIW. 629;; 630;; In addition regular constants, we also recognize constants formed with the 631;; VEC_DUPLICATE insn from scalar constants. 632;; 633;; We don't handle scalar integer constants here because the assumption is the 634;; normal integer constants will be loaded into GPR registers. For the 635;; constants that need to be loaded into vector registers, the instructions 636;; don't work well with TImode variables assigned a constant. This is because 637;; the 64-bit scalar constants are splatted into both halves of the register. 638 639(define_predicate "vsx_prefixed_constant" 640 (match_code "const_double,const_vector,vec_duplicate") 641{ 642 /* If we can generate the constant with a few Altivec instructions, don't 643 generate a prefixed instruction. */ 644 if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode)) 645 return false; 646 647 /* Do we have prefixed instructions and are VSX registers available? Is the 648 constant recognized? */ 649 if (!TARGET_PREFIXED || !TARGET_VSX) 650 return false; 651 652 vec_const_128bit_type vsx_const; 653 if (!vec_const_128bit_to_bytes (op, mode, &vsx_const)) 654 return false; 655 656 if (constant_generates_xxspltiw (&vsx_const)) 657 return true; 658 659 if (constant_generates_xxspltidp (&vsx_const)) 660 return true; 661 662 return false; 663}) 664 665;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded 666;; via the LXVKQ instruction. 667 668(define_predicate "easy_vector_constant_ieee128" 669 (match_code "const_vector,const_double") 670{ 671 vec_const_128bit_type vsx_const; 672 673 /* Can we generate the LXVKQ instruction? */ 674 if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 675 || !TARGET_VSX) 676 return false; 677 678 return (vec_const_128bit_to_bytes (op, mode, &vsx_const) 679 && constant_generates_lxvkq (&vsx_const) != 0); 680}) 681 682;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB 683;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. 684 685(define_predicate "xxspltib_constant_split" 686 (match_code "const_vector,vec_duplicate,const_int") 687{ 688 int value = 256; 689 int num_insns = -1; 690 691 if (!xxspltib_constant_p (op, mode, &num_insns, &value)) 692 return false; 693 694 return num_insns > 1; 695}) 696 697 698;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB 699;; instruction. 700 701(define_predicate "xxspltib_constant_nosplit" 702 (match_code "const_vector,vec_duplicate,const_int") 703{ 704 int value = 256; 705 int num_insns = -1; 706 707 if (!xxspltib_constant_p (op, mode, &num_insns, &value)) 708 return false; 709 710 return num_insns == 1; 711}) 712 713;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a 714;; vector register without using memory. 715(define_predicate "easy_vector_constant" 716 (match_code "const_vector") 717{ 718 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) 719 { 720 int value = 256; 721 int num_insns = -1; 722 723 if (zero_constant (op, mode) || all_ones_constant (op, mode)) 724 return true; 725 726 /* Constants that can be generated with ISA 3.1 instructions are 727 easy. */ 728 vec_const_128bit_type vsx_const; 729 if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) 730 { 731 if (constant_generates_lxvkq (&vsx_const)) 732 return true; 733 734 if (constant_generates_xxspltiw (&vsx_const)) 735 return true; 736 737 if (constant_generates_xxspltidp (&vsx_const)) 738 return true; 739 } 740 741 if (TARGET_P9_VECTOR 742 && xxspltib_constant_p (op, mode, &num_insns, &value)) 743 return true; 744 745 return easy_altivec_constant (op, mode); 746 } 747 748 return false; 749}) 750 751;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. 752(define_predicate "easy_vector_constant_add_self" 753 (and (match_code "const_vector") 754 (and (match_test "TARGET_ALTIVEC") 755 (match_test "easy_altivec_constant (op, mode)"))) 756{ 757 HOST_WIDE_INT val; 758 int elt; 759 if (mode == V2DImode || mode == V2DFmode) 760 return 0; 761 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 762 val = const_vector_elt_as_int (op, elt); 763 val = ((val & 0xff) ^ 0x80) - 0x80; 764 return EASY_VECTOR_15_ADD_SELF (val); 765}) 766 767;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. 768(define_predicate "easy_vector_constant_msb" 769 (and (match_code "const_vector") 770 (and (match_test "TARGET_ALTIVEC") 771 (match_test "easy_altivec_constant (op, mode)") 772 (match_test "vspltis_shifted (op) == 0"))) 773{ 774 HOST_WIDE_INT val; 775 int elt, sz = easy_altivec_constant (op, mode); 776 machine_mode inner = GET_MODE_INNER (mode); 777 int isz = GET_MODE_SIZE (inner); 778 if (mode == V2DImode || mode == V2DFmode) 779 return 0; 780 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 781 if (isz < sz) 782 { 783 if (const_vector_elt_as_int (op, elt) != 0) 784 return 0; 785 elt += (BYTES_BIG_ENDIAN ? -1 : 1) * (sz - isz) / isz; 786 } 787 else if (isz > sz) 788 inner = smallest_int_mode_for_size (sz * BITS_PER_UNIT); 789 val = const_vector_elt_as_int (op, elt); 790 return EASY_VECTOR_MSB (val, inner); 791}) 792 793;; Return true if this is an easy altivec constant that we form 794;; by using VSLDOI. 795(define_predicate "easy_vector_constant_vsldoi" 796 (and (match_code "const_vector") 797 (and (match_test "TARGET_ALTIVEC") 798 (and (match_test "easy_altivec_constant (op, mode)") 799 (match_test "vspltis_shifted (op) != 0"))))) 800 801;; Return 1 if operand is a vector int register or is either a vector constant 802;; of all 0 bits of a vector constant of all 1 bits. 803(define_predicate "vector_int_reg_or_same_bit" 804 (match_code "reg,subreg,const_vector") 805{ 806 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) 807 return 0; 808 809 else if (REG_P (op) || SUBREG_P (op)) 810 return vint_operand (op, mode); 811 812 else 813 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode); 814}) 815 816;; Return 1 if operand is 0.0. 817(define_predicate "zero_fp_constant" 818 (and (match_code "const_double") 819 (match_test "SCALAR_FLOAT_MODE_P (mode) 820 && op == CONST0_RTX (mode)"))) 821 822;; Return 1 if the operand is in volatile memory. Note that during the 823;; RTL generation phase, memory_operand does not return TRUE for volatile 824;; memory references. So this function allows us to recognize volatile 825;; references where it's safe. 826(define_predicate "volatile_mem_operand" 827 (and (match_code "mem") 828 (match_test "MEM_VOLATILE_P (op)") 829 (if_then_else (match_test "reload_completed") 830 (match_operand 0 "memory_operand") 831 (match_test "memory_address_p (mode, XEXP (op, 0))")))) 832 833;; Return 1 if the operand is a volatile or non-volatile memory operand. 834(define_predicate "any_memory_operand" 835 (ior (match_operand 0 "memory_operand") 836 (match_operand 0 "volatile_mem_operand"))) 837 838;; Return 1 if the operand is an offsettable memory operand. 839(define_predicate "offsettable_mem_operand" 840 (and (match_operand 0 "any_memory_operand") 841 (match_test "offsettable_nonstrict_memref_p (op)"))) 842 843;; Return 1 if the operand is a simple offsettable memory operand 844;; that does not include pre-increment, post-increment, etc. 845(define_predicate "simple_offsettable_mem_operand" 846 (match_operand 0 "offsettable_mem_operand") 847{ 848 rtx addr = XEXP (op, 0); 849 850 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 851 return 0; 852 853 if (!CONSTANT_P (XEXP (addr, 1))) 854 return 0; 855 856 return base_reg_operand (XEXP (addr, 0), Pmode); 857}) 858 859;; Return 1 if the operand is suitable for load/store quad memory. 860;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). 861(define_predicate "quad_memory_operand" 862 (match_code "mem") 863{ 864 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) 865 return false; 866 867 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128) 868 return false; 869 870 return quad_address_p (XEXP (op, 0), mode, false); 871}) 872 873;; Return 1 if the operand is suitable for load/store to vector registers with 874;; d-form addressing (register+offset), which was added in ISA 3.0. 875;; Unlike quad_memory_operand, we do not have to check for alignment. 876(define_predicate "vsx_quad_dform_memory_operand" 877 (match_code "mem") 878{ 879 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) 880 return false; 881 882 return quad_address_p (XEXP (op, 0), mode, false); 883}) 884 885;; Return 1 if the operand is an indexed or indirect memory operand. 886(define_predicate "indexed_or_indirect_operand" 887 (match_code "mem") 888{ 889 op = XEXP (op, 0); 890 if (VECTOR_MEM_ALTIVEC_P (mode) 891 && GET_CODE (op) == AND 892 && CONST_INT_P (XEXP (op, 1)) 893 && INTVAL (XEXP (op, 1)) == -16) 894 op = XEXP (op, 0); 895 896 return indexed_or_indirect_address (op, mode); 897}) 898 899;; Like indexed_or_indirect_operand, but also allow a GPR register if direct 900;; moves are supported. 901(define_predicate "reg_or_indexed_operand" 902 (match_code "mem,reg,subreg") 903{ 904 if (MEM_P (op)) 905 return indexed_or_indirect_operand (op, mode); 906 else if (TARGET_DIRECT_MOVE) 907 return register_operand (op, mode); 908 return 909 0; 910}) 911 912;; Return 1 if the operand is an indexed or indirect memory operand with an 913;; AND -16 in it, used to recognize when we need to switch to Altivec loads 914;; to realign loops instead of VSX (altivec silently ignores the bottom bits, 915;; while VSX uses the full address and traps) 916(define_predicate "altivec_indexed_or_indirect_operand" 917 (match_code "mem") 918{ 919 op = XEXP (op, 0); 920 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) 921 && GET_CODE (op) == AND 922 && CONST_INT_P (XEXP (op, 1)) 923 && INTVAL (XEXP (op, 1)) == -16) 924 return indexed_or_indirect_address (XEXP (op, 0), mode); 925 926 return 0; 927}) 928 929;; Return 1 if the operand is an indexed or indirect address. 930(define_special_predicate "indexed_or_indirect_address" 931 (and (match_test "REG_P (op) 932 || (GET_CODE (op) == PLUS 933 /* Omit testing REG_P (XEXP (op, 0)). */ 934 && REG_P (XEXP (op, 1)))") 935 (match_operand 0 "address_operand"))) 936 937;; Return 1 if the operand is an index-form address. 938(define_special_predicate "indexed_address" 939 (match_test "(GET_CODE (op) == PLUS 940 && REG_P (XEXP (op, 0)) 941 && REG_P (XEXP (op, 1)))")) 942 943;; Return 1 if the operand is a MEM with an update-form address. This may 944;; also include update-indexed form. 945(define_special_predicate "update_address_mem" 946 (match_test "(MEM_P (op) 947 && (GET_CODE (XEXP (op, 0)) == PRE_INC 948 || GET_CODE (XEXP (op, 0)) == PRE_DEC 949 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) 950 951;; Anything that matches memory_operand but does not update the address. 952(define_predicate "non_update_memory_operand" 953 (match_code "mem") 954{ 955 if (update_address_mem (op, mode)) 956 return 0; 957 return memory_operand (op, mode); 958}) 959 960;; Return 1 if the operand is a MEM with an indexed-form address. 961(define_special_predicate "indexed_address_mem" 962 (match_test "(MEM_P (op) 963 && (indexed_address (XEXP (op, 0), mode) 964 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY 965 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))")) 966 967;; Return 1 if the operand is either a non-special register or can be used 968;; as the operand of a `mode' add insn. 969(define_predicate "add_operand" 970 (if_then_else (match_code "const_int") 971 (match_test "satisfies_constraint_I (op) 972 || satisfies_constraint_L (op) 973 || satisfies_constraint_eI (op)") 974 (match_operand 0 "gpc_reg_operand"))) 975 976;; Return 1 if the operand is either a non-special register, or 0, or -1. 977(define_predicate "adde_operand" 978 (if_then_else (match_code "const_int") 979 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1") 980 (match_operand 0 "gpc_reg_operand"))) 981 982;; Return 1 if OP is a constant but not a valid add_operand. 983(define_predicate "non_add_cint_operand" 984 (and (match_code "const_int") 985 (not (match_operand 0 "add_operand")))) 986 987;; Return 1 if the operand is a constant that can be used as the operand 988;; of an AND, OR or XOR. 989(define_predicate "logical_const_operand" 990 (match_code "const_int") 991{ 992 HOST_WIDE_INT opl; 993 994 opl = INTVAL (op) & GET_MODE_MASK (mode); 995 996 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 997 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); 998}) 999 1000;; Return 1 if the operand is a non-special register or a constant that 1001;; can be used as the operand of an AND, OR or XOR. 1002(define_predicate "logical_operand" 1003 (ior (match_operand 0 "gpc_reg_operand") 1004 (match_operand 0 "logical_const_operand"))) 1005 1006;; Return 1 if op is a constant that is not a logical operand, but could 1007;; be split into one. 1008(define_predicate "non_logical_cint_operand" 1009 (and (match_code "const_int,const_wide_int") 1010 (and (not (match_operand 0 "logical_operand")) 1011 (match_operand 0 "reg_or_logical_cint_operand")))) 1012 1013;; Return 1 if the operand is either a non-special register or a 1014;; constant that can be used as the operand of a logical AND. 1015(define_predicate "and_operand" 1016 (ior (and (match_code "const_int") 1017 (match_test "rs6000_is_valid_and_mask (op, mode)")) 1018 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 1019 (match_operand 0 "gpc_reg_operand") 1020 (match_operand 0 "logical_operand")))) 1021 1022;; Return 1 if the operand is either a logical operand or a short cint operand. 1023(define_predicate "scc_eq_operand" 1024 (ior (match_operand 0 "logical_operand") 1025 (match_operand 0 "short_cint_operand"))) 1026 1027;; Return 1 if the operand is a general non-special register or memory operand. 1028(define_predicate "reg_or_mem_operand" 1029 (ior (match_operand 0 "gpc_reg_operand") 1030 (match_operand 0 "any_memory_operand") 1031 (and (match_code "mem") 1032 (match_test "macho_lo_sum_memory_operand (op, mode)")))) 1033 1034;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. 1035(define_predicate "zero_reg_mem_operand" 1036 (ior (and (match_test "TARGET_VSX") 1037 (match_operand 0 "zero_fp_constant")) 1038 (match_operand 0 "reg_or_mem_operand"))) 1039 1040;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit 1041;; data types inside of a vector that scalar instructions operate on 1042(define_predicate "vsx_scalar_64bit" 1043 (match_code "const_int") 1044{ 1045 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT); 1046}) 1047 1048;; Return 1 if the operand is a general register or memory operand without 1049;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC 1050;; lwa instruction. 1051(define_predicate "lwa_operand" 1052 (match_code "reg,subreg,mem") 1053{ 1054 rtx inner, addr, offset; 1055 1056 inner = op; 1057 if (reload_completed && SUBREG_P (inner)) 1058 inner = SUBREG_REG (inner); 1059 1060 if (gpc_reg_operand (inner, mode)) 1061 return true; 1062 if (!any_memory_operand (inner, mode)) 1063 return false; 1064 1065 addr = XEXP (inner, 0); 1066 1067 /* The LWA instruction uses the DS-form instruction format which requires 1068 that the bottom two bits of the offset must be 0. The prefixed PLWA does 1069 not have this restriction. While the actual load from memory is 32-bits, 1070 we pass in DImode here to test for using a DS instruction. */ 1071 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS)) 1072 return true; 1073 1074 if (GET_CODE (addr) == PRE_INC 1075 || GET_CODE (addr) == PRE_DEC 1076 || (GET_CODE (addr) == PRE_MODIFY 1077 && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) 1078 return false; 1079 if (GET_CODE (addr) == LO_SUM 1080 && REG_P (XEXP (addr, 0)) 1081 && GET_CODE (XEXP (addr, 1)) == CONST) 1082 addr = XEXP (XEXP (addr, 1), 0); 1083 if (GET_CODE (addr) != PLUS) 1084 return true; 1085 offset = XEXP (addr, 1); 1086 if (!CONST_INT_P (offset)) 1087 return true; 1088 return INTVAL (offset) % 4 == 0; 1089}) 1090 1091;; Return 1 if the operand is a memory operand that has a valid address for 1092;; a DS-form instruction. I.e. the address has to be either just a register, 1093;; or register + const where the two low order bits of const are zero. 1094(define_predicate "ds_form_mem_operand" 1095 (match_code "subreg,mem") 1096{ 1097 if (!any_memory_operand (op, mode)) 1098 return false; 1099 1100 rtx addr = XEXP (op, 0); 1101 1102 return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS; 1103}) 1104 1105;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. 1106(define_predicate "symbol_ref_operand" 1107 (and (match_code "symbol_ref") 1108 (match_test "(mode == VOIDmode || GET_MODE (op) == mode) 1109 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) 1110 1111;; Return 1 if op is an operand that can be loaded via the GOT. 1112;; or non-special register field no cr0 1113(define_predicate "got_operand" 1114 (match_code "symbol_ref,const,label_ref")) 1115 1116;; Return 1 if op is a simple reference that can be loaded via the GOT, 1117;; excluding labels involving addition. 1118(define_predicate "got_no_const_operand" 1119 (match_code "symbol_ref,label_ref")) 1120 1121;; Return 1 if op is a SYMBOL_REF for a TLS symbol. 1122(define_predicate "rs6000_tls_symbol_ref" 1123 (and (match_code "symbol_ref") 1124 (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) 1125 1126;; Return 1 for the CONST_INT or UNSPEC second CALL operand. 1127;; Prevents unwanted substitution of the unspec got_reg arg. 1128(define_predicate "unspec_tls" 1129 (match_code "const_int,unspec") 1130{ 1131 if (CONST_INT_P (op)) 1132 return 1; 1133 if (XINT (op, 1) == UNSPEC_TLSGD) 1134 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx; 1135 if (XINT (op, 1) == UNSPEC_TLSLD) 1136 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx; 1137 return 0; 1138}) 1139 1140;; Return 1 if the operand, used inside a MEM, is a valid first argument 1141;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. 1142(define_predicate "call_operand" 1143 (if_then_else (match_code "reg") 1144 (match_test "REGNO (op) == LR_REGNO 1145 || REGNO (op) == CTR_REGNO 1146 || !HARD_REGISTER_P (op)") 1147 (match_code "symbol_ref"))) 1148 1149;; Return 1 if the operand, used inside a MEM, is a valid first argument 1150;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR. 1151(define_predicate "indirect_call_operand" 1152 (match_code "reg,unspec") 1153{ 1154 if (REG_P (op)) 1155 return (REGNO (op) == LR_REGNO 1156 || REGNO (op) == CTR_REGNO); 1157 if (GET_CODE (op) == UNSPEC) 1158 { 1159 if (XINT (op, 1) != UNSPEC_PLTSEQ) 1160 return false; 1161 op = XVECEXP (op, 0, 0); 1162 return REG_P (op) && REGNO (op) == CTR_REGNO; 1163 } 1164 return false; 1165}) 1166 1167;; Return 1 if the operand is a SYMBOL_REF for a function known to be in 1168;; this file. 1169(define_predicate "current_file_function_operand" 1170 (and (match_code "symbol_ref") 1171 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) 1172 && (SYMBOL_REF_LOCAL_P (op) 1173 || (op == XEXP (DECL_RTL (current_function_decl), 0) 1174 && !decl_replaceable_p (current_function_decl, 1175 opt_for_fn (current_function_decl, 1176 flag_semantic_interposition)))) 1177 && !((DEFAULT_ABI == ABI_AIX 1178 || DEFAULT_ABI == ABI_ELFv2) 1179 && (SYMBOL_REF_EXTERNAL_P (op) 1180 || SYMBOL_REF_WEAK (op))) 1181 && !(DEFAULT_ABI == ABI_ELFv2 1182 && SYMBOL_REF_DECL (op) != NULL 1183 && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL 1184 && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op)) 1185 != rs6000_pcrel_p ()))"))) 1186 1187;; Return 1 if this operand is a valid input for a move insn. 1188(define_predicate "input_operand" 1189 (match_code "symbol_ref,const,reg,subreg,mem, 1190 const_double,const_wide_int,const_vector,const_int") 1191{ 1192 /* Memory is always valid. */ 1193 if (any_memory_operand (op, mode)) 1194 return 1; 1195 1196 /* For floating-point, easy constants are valid. */ 1197 if (SCALAR_FLOAT_MODE_P (mode) 1198 && easy_fp_constant (op, mode)) 1199 return 1; 1200 1201 /* Allow any integer constant. */ 1202 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op)) 1203 return 1; 1204 1205 /* Allow easy vector constants. */ 1206 if (GET_CODE (op) == CONST_VECTOR 1207 && easy_vector_constant (op, mode)) 1208 return 1; 1209 1210 /* For floating-point or multi-word mode, the only remaining valid type 1211 is a register. */ 1212 if (SCALAR_FLOAT_MODE_P (mode) 1213 || GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1214 return register_operand (op, mode); 1215 1216 /* We don't allow moving the carry bit around. */ 1217 if (ca_operand (op, mode)) 1218 return 0; 1219 1220 /* The only cases left are integral modes one word or smaller (we 1221 do not get called for MODE_CC values). These can be in any 1222 register. */ 1223 if (register_operand (op, mode)) 1224 return 1; 1225 1226 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region 1227 to be valid. */ 1228 if (DEFAULT_ABI == ABI_V4 1229 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST) 1230 && small_data_operand (op, Pmode)) 1231 return 1; 1232 1233 return 0; 1234}) 1235 1236;; Return 1 if this operand is a valid input for a vsx_splat insn. 1237(define_predicate "splat_input_operand" 1238 (match_code "reg,subreg,mem") 1239{ 1240 machine_mode vmode; 1241 1242 if (mode == DFmode) 1243 vmode = V2DFmode; 1244 else if (mode == DImode) 1245 vmode = V2DImode; 1246 else if (mode == SImode && TARGET_P9_VECTOR) 1247 vmode = V4SImode; 1248 else if (mode == SFmode && TARGET_P9_VECTOR) 1249 vmode = V4SFmode; 1250 else 1251 return false; 1252 1253 if (MEM_P (op)) 1254 { 1255 rtx addr = XEXP (op, 0); 1256 1257 if (! volatile_ok && MEM_VOLATILE_P (op)) 1258 return 0; 1259 1260 if (lra_in_progress || reload_completed) 1261 return indexed_or_indirect_address (addr, vmode); 1262 else 1263 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op)); 1264 } 1265 return gpc_reg_operand (op, mode); 1266}) 1267 1268;; Return 1 if this operand is valid for a MMA assemble accumulator insn. 1269(define_special_predicate "mma_assemble_input_operand" 1270 (match_test "(mode == V16QImode 1271 && (vsx_register_operand (op, mode) 1272 || (MEM_P (op) 1273 && (indexed_or_indirect_address (XEXP (op, 0), mode) 1274 || quad_address_p (XEXP (op, 0), mode, false)))))")) 1275 1276;; Return 1 if this operand is valid for an MMA disassemble insn. 1277(define_predicate "mma_disassemble_output_operand" 1278 (match_code "reg,subreg,mem") 1279{ 1280 if (MEM_P (op)) 1281 { 1282 rtx addr = XEXP (op, 0); 1283 return indexed_or_indirect_address (addr, mode) 1284 || quad_address_p (addr, mode, false); 1285 } 1286 1287 if (SUBREG_P (op)) 1288 op = SUBREG_REG (op); 1289 1290 return vsx_register_operand (op, mode); 1291}) 1292 1293;; Return true if operand is an operator used in rotate-and-mask instructions. 1294(define_predicate "rotate_mask_operator" 1295 (match_code "rotate,ashift,lshiftrt")) 1296 1297;; Return true if operand is boolean operator. 1298(define_predicate "boolean_operator" 1299 (match_code "and,ior,xor")) 1300 1301;; Return true if operand is OR-form of boolean operator. 1302(define_predicate "boolean_or_operator" 1303 (match_code "ior,xor")) 1304 1305;; Return true if operand is an equality operator. 1306(define_special_predicate "equality_operator" 1307 (match_code "eq,ne")) 1308 1309;; Return 1 if OP is a comparison operation that is valid for a branch 1310;; instruction. We check the opcode against the mode of the CC value. 1311;; validate_condition_mode is an assertion. 1312(define_predicate "branch_comparison_operator" 1313 (and (match_operand 0 "comparison_operator") 1314 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") 1315 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode") 1316 (if_then_else (match_test "flag_finite_math_only") 1317 (match_code "lt,le,gt,ge,eq,ne,unordered,ordered") 1318 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered")) 1319 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne")) 1320 (match_test "validate_condition_mode (GET_CODE (op), 1321 GET_MODE (XEXP (op, 0))), 1322 1"))) 1323 1324;; Return 1 if OP is a comparison that needs an extra instruction to do (a 1325;; crlogical or an extra branch). 1326(define_predicate "extra_insn_branch_comparison_operator" 1327 (and (match_operand 0 "comparison_operator") 1328 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode") 1329 (match_code "ltgt,le,ge,unlt,ungt,uneq") 1330 (match_test "validate_condition_mode (GET_CODE (op), 1331 GET_MODE (XEXP (op, 0))), 1332 1"))) 1333 1334;; Return 1 if OP is an unsigned comparison operator. 1335(define_predicate "unsigned_comparison_operator" 1336 (match_code "ltu,gtu,leu,geu")) 1337 1338;; Return 1 if OP is a signed comparison operator. 1339(define_predicate "signed_comparison_operator" 1340 (match_code "lt,gt,le,ge")) 1341 1342;; Return 1 if OP is a signed comparison or an equality operator. 1343(define_predicate "signed_or_equality_comparison_operator" 1344 (ior (match_operand 0 "equality_operator") 1345 (match_operand 0 "signed_comparison_operator"))) 1346 1347;; Return 1 if OP is an unsigned comparison or an equality operator. 1348(define_predicate "unsigned_or_equality_comparison_operator" 1349 (ior (match_operand 0 "equality_operator") 1350 (match_operand 0 "unsigned_comparison_operator"))) 1351 1352;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- 1353;; it must be a positive comparison. 1354(define_predicate "scc_comparison_operator" 1355 (and (match_operand 0 "branch_comparison_operator") 1356 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1357 1358;; Return 1 if OP is a comparison operation whose inverse would be valid for 1359;; an SCC insn. 1360(define_predicate "scc_rev_comparison_operator" 1361 (and (match_operand 0 "branch_comparison_operator") 1362 (match_code "ne,le,ge,leu,geu,ordered"))) 1363 1364;; Return 1 if OP is a comparison operator suitable for floating point 1365;; vector/scalar comparisons that generate a -1/0 mask. 1366(define_predicate "fpmask_comparison_operator" 1367 (match_code "eq,gt,ge")) 1368 1369;; Return 1 if OP is a comparison operator suitable for vector/scalar 1370;; comparisons that generate a 0/-1 mask (i.e. the inverse of 1371;; fpmask_comparison_operator). 1372(define_predicate "invert_fpmask_comparison_operator" 1373 (match_code "ne,unlt,unle")) 1374 1375;; Return 1 if OP is a comparison operation suitable for integer vector/scalar 1376;; comparisons that generate a -1/0 mask. 1377(define_predicate "vecint_comparison_operator" 1378 (match_code "eq,gt,gtu")) 1379 1380;; Return 1 if OP is a comparison operation that is valid for a branch 1381;; insn, which is true if the corresponding bit in the CC register is set. 1382(define_predicate "branch_positive_comparison_operator" 1383 (and (match_operand 0 "branch_comparison_operator") 1384 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1385 1386;; Return 1 if OP is valid for a save_world call in prologue, known to be 1387;; a PARLLEL. 1388(define_predicate "save_world_operation" 1389 (match_code "parallel") 1390{ 1391 int index; 1392 int i; 1393 rtx elt; 1394 int count = XVECLEN (op, 0); 1395 1396 if (count != 54) 1397 return 0; 1398 1399 index = 0; 1400 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1401 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1402 return 0; 1403 1404 for (i=1; i <= 18; i++) 1405 { 1406 elt = XVECEXP (op, 0, index++); 1407 if (GET_CODE (elt) != SET 1408 || !MEM_P (SET_DEST (elt)) 1409 || !memory_operand (SET_DEST (elt), DFmode) 1410 || !REG_P (SET_SRC (elt)) 1411 || GET_MODE (SET_SRC (elt)) != DFmode) 1412 return 0; 1413 } 1414 1415 for (i=1; i <= 12; i++) 1416 { 1417 elt = XVECEXP (op, 0, index++); 1418 if (GET_CODE (elt) != SET 1419 || !MEM_P (SET_DEST (elt)) 1420 || !REG_P (SET_SRC (elt)) 1421 || GET_MODE (SET_SRC (elt)) != V4SImode) 1422 return 0; 1423 } 1424 1425 for (i=1; i <= 19; i++) 1426 { 1427 elt = XVECEXP (op, 0, index++); 1428 if (GET_CODE (elt) != SET 1429 || !MEM_P (SET_DEST (elt)) 1430 || !memory_operand (SET_DEST (elt), Pmode) 1431 || !REG_P (SET_SRC (elt)) 1432 || GET_MODE (SET_SRC (elt)) != Pmode) 1433 return 0; 1434 } 1435 1436 elt = XVECEXP (op, 0, index++); 1437 if (GET_CODE (elt) != SET 1438 || !MEM_P (SET_DEST (elt)) 1439 || !memory_operand (SET_DEST (elt), Pmode) 1440 || !REG_P (SET_SRC (elt)) 1441 || REGNO (SET_SRC (elt)) != CR2_REGNO 1442 || GET_MODE (SET_SRC (elt)) != Pmode) 1443 return 0; 1444 1445 if (GET_CODE (XVECEXP (op, 0, index++)) != SET 1446 || GET_CODE (XVECEXP (op, 0, index++)) != SET) 1447 return 0; 1448 return 1; 1449}) 1450 1451;; Return 1 if OP is valid for a restore_world call in epilogue, known to be 1452;; a PARLLEL. 1453(define_predicate "restore_world_operation" 1454 (match_code "parallel") 1455{ 1456 int index; 1457 int i; 1458 rtx elt; 1459 int count = XVECLEN (op, 0); 1460 1461 if (count != 58) 1462 return 0; 1463 1464 index = 0; 1465 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN 1466 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1467 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 1468 return 0; 1469 1470 elt = XVECEXP (op, 0, index++); 1471 if (GET_CODE (elt) != SET 1472 || !MEM_P (SET_SRC (elt)) 1473 || !memory_operand (SET_SRC (elt), Pmode) 1474 || !REG_P (SET_DEST (elt)) 1475 || REGNO (SET_DEST (elt)) != CR2_REGNO 1476 || GET_MODE (SET_DEST (elt)) != Pmode) 1477 return 0; 1478 1479 for (i=1; i <= 19; i++) 1480 { 1481 elt = XVECEXP (op, 0, index++); 1482 if (GET_CODE (elt) != SET 1483 || !MEM_P (SET_SRC (elt)) 1484 || !memory_operand (SET_SRC (elt), Pmode) 1485 || !REG_P (SET_DEST (elt)) 1486 || GET_MODE (SET_DEST (elt)) != Pmode) 1487 return 0; 1488 } 1489 1490 for (i=1; i <= 12; i++) 1491 { 1492 elt = XVECEXP (op, 0, index++); 1493 if (GET_CODE (elt) != SET 1494 || !MEM_P (SET_SRC (elt)) 1495 || !REG_P (SET_DEST (elt)) 1496 || GET_MODE (SET_DEST (elt)) != V4SImode) 1497 return 0; 1498 } 1499 1500 for (i=1; i <= 18; i++) 1501 { 1502 elt = XVECEXP (op, 0, index++); 1503 if (GET_CODE (elt) != SET 1504 || !MEM_P (SET_SRC (elt)) 1505 || !memory_operand (SET_SRC (elt), DFmode) 1506 || !REG_P (SET_DEST (elt)) 1507 || GET_MODE (SET_DEST (elt)) != DFmode) 1508 return 0; 1509 } 1510 1511 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1512 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1513 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1514 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1515 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1516 return 0; 1517 return 1; 1518}) 1519 1520;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. 1521(define_predicate "vrsave_operation" 1522 (match_code "parallel") 1523{ 1524 int count = XVECLEN (op, 0); 1525 unsigned int dest_regno, src_regno; 1526 int i; 1527 1528 if (count <= 1 1529 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1530 || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) 1531 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE 1532 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) 1533 return 0; 1534 1535 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1536 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); 1537 1538 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) 1539 return 0; 1540 1541 for (i = 1; i < count; i++) 1542 { 1543 rtx elt = XVECEXP (op, 0, i); 1544 1545 if (GET_CODE (elt) != CLOBBER 1546 && GET_CODE (elt) != SET) 1547 return 0; 1548 } 1549 1550 return 1; 1551}) 1552 1553;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. 1554(define_predicate "mfcr_operation" 1555 (match_code "parallel") 1556{ 1557 int count = XVECLEN (op, 0); 1558 int i; 1559 1560 /* Perform a quick check so we don't blow up below. */ 1561 if (count < 1 1562 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1563 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1564 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1565 return 0; 1566 1567 for (i = 0; i < count; i++) 1568 { 1569 rtx exp = XVECEXP (op, 0, i); 1570 rtx unspec; 1571 int maskval; 1572 rtx src_reg; 1573 1574 src_reg = XVECEXP (SET_SRC (exp), 0, 0); 1575 1576 if (!REG_P (src_reg) 1577 || GET_MODE (src_reg) != CCmode 1578 || ! CR_REGNO_P (REGNO (src_reg))) 1579 return 0; 1580 1581 if (GET_CODE (exp) != SET 1582 || !REG_P (SET_DEST (exp)) 1583 || GET_MODE (SET_DEST (exp)) != SImode 1584 || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) 1585 return 0; 1586 unspec = SET_SRC (exp); 1587 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); 1588 1589 if (GET_CODE (unspec) != UNSPEC 1590 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR 1591 || XVECLEN (unspec, 0) != 2 1592 || XVECEXP (unspec, 0, 0) != src_reg 1593 || !CONST_INT_P (XVECEXP (unspec, 0, 1)) 1594 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1595 return 0; 1596 } 1597 return 1; 1598}) 1599 1600;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. 1601(define_predicate "mtcrf_operation" 1602 (match_code "parallel") 1603{ 1604 int count = XVECLEN (op, 0); 1605 int i; 1606 rtx src_reg; 1607 1608 /* Perform a quick check so we don't blow up below. */ 1609 if (count < 1 1610 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1611 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1612 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1613 return 0; 1614 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); 1615 1616 if (!REG_P (src_reg) 1617 || GET_MODE (src_reg) != SImode 1618 || ! INT_REGNO_P (REGNO (src_reg))) 1619 return 0; 1620 1621 for (i = 0; i < count; i++) 1622 { 1623 rtx exp = XVECEXP (op, 0, i); 1624 rtx unspec; 1625 int maskval; 1626 1627 if (GET_CODE (exp) != SET 1628 || !REG_P (SET_DEST (exp)) 1629 || GET_MODE (SET_DEST (exp)) != CCmode 1630 || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) 1631 return 0; 1632 unspec = SET_SRC (exp); 1633 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); 1634 1635 if (GET_CODE (unspec) != UNSPEC 1636 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR 1637 || XVECLEN (unspec, 0) != 2 1638 || XVECEXP (unspec, 0, 0) != src_reg 1639 || !CONST_INT_P (XVECEXP (unspec, 0, 1)) 1640 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1641 return 0; 1642 } 1643 return 1; 1644}) 1645 1646;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. 1647(define_predicate "crsave_operation" 1648 (match_code "parallel") 1649{ 1650 int count = XVECLEN (op, 0); 1651 int i; 1652 1653 for (i = 1; i < count; i++) 1654 { 1655 rtx exp = XVECEXP (op, 0, i); 1656 1657 if (GET_CODE (exp) != USE 1658 || !REG_P (XEXP (exp, 0)) 1659 || GET_MODE (XEXP (exp, 0)) != CCmode 1660 || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) 1661 return 0; 1662 } 1663 return 1; 1664}) 1665 1666;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. 1667(define_predicate "lmw_operation" 1668 (match_code "parallel") 1669{ 1670 int count = XVECLEN (op, 0); 1671 unsigned int dest_regno; 1672 rtx src_addr; 1673 unsigned int base_regno; 1674 HOST_WIDE_INT offset; 1675 int i; 1676 1677 /* Perform a quick check so we don't blow up below. */ 1678 if (count <= 1 1679 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1680 || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) 1681 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0)))) 1682 return 0; 1683 1684 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1685 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1686 1687 if (dest_regno > 31 1688 || count != 32 - (int) dest_regno) 1689 return 0; 1690 1691 if (legitimate_indirect_address_p (src_addr, 0)) 1692 { 1693 offset = 0; 1694 base_regno = REGNO (src_addr); 1695 if (base_regno == 0) 1696 return 0; 1697 } 1698 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false)) 1699 { 1700 offset = INTVAL (XEXP (src_addr, 1)); 1701 base_regno = REGNO (XEXP (src_addr, 0)); 1702 } 1703 else 1704 return 0; 1705 1706 for (i = 0; i < count; i++) 1707 { 1708 rtx elt = XVECEXP (op, 0, i); 1709 rtx newaddr; 1710 rtx addr_reg; 1711 HOST_WIDE_INT newoffset; 1712 1713 if (GET_CODE (elt) != SET 1714 || !REG_P (SET_DEST (elt)) 1715 || GET_MODE (SET_DEST (elt)) != SImode 1716 || REGNO (SET_DEST (elt)) != dest_regno + i 1717 || !MEM_P (SET_SRC (elt)) 1718 || GET_MODE (SET_SRC (elt)) != SImode) 1719 return 0; 1720 newaddr = XEXP (SET_SRC (elt), 0); 1721 if (legitimate_indirect_address_p (newaddr, 0)) 1722 { 1723 newoffset = 0; 1724 addr_reg = newaddr; 1725 } 1726 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1727 { 1728 addr_reg = XEXP (newaddr, 0); 1729 newoffset = INTVAL (XEXP (newaddr, 1)); 1730 } 1731 else 1732 return 0; 1733 if (REGNO (addr_reg) != base_regno 1734 || newoffset != offset + 4 * i) 1735 return 0; 1736 } 1737 1738 return 1; 1739}) 1740 1741;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. 1742(define_predicate "stmw_operation" 1743 (match_code "parallel") 1744{ 1745 int count = XVECLEN (op, 0); 1746 unsigned int src_regno; 1747 rtx dest_addr; 1748 unsigned int base_regno; 1749 HOST_WIDE_INT offset; 1750 int i; 1751 1752 /* Perform a quick check so we don't blow up below. */ 1753 if (count <= 1 1754 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1755 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0))) 1756 || !REG_P (SET_SRC (XVECEXP (op, 0, 0)))) 1757 return 0; 1758 1759 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1760 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1761 1762 if (src_regno > 31 1763 || count != 32 - (int) src_regno) 1764 return 0; 1765 1766 if (legitimate_indirect_address_p (dest_addr, 0)) 1767 { 1768 offset = 0; 1769 base_regno = REGNO (dest_addr); 1770 if (base_regno == 0) 1771 return 0; 1772 } 1773 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false)) 1774 { 1775 offset = INTVAL (XEXP (dest_addr, 1)); 1776 base_regno = REGNO (XEXP (dest_addr, 0)); 1777 } 1778 else 1779 return 0; 1780 1781 for (i = 0; i < count; i++) 1782 { 1783 rtx elt = XVECEXP (op, 0, i); 1784 rtx newaddr; 1785 rtx addr_reg; 1786 HOST_WIDE_INT newoffset; 1787 1788 if (GET_CODE (elt) != SET 1789 || !REG_P (SET_SRC (elt)) 1790 || GET_MODE (SET_SRC (elt)) != SImode 1791 || REGNO (SET_SRC (elt)) != src_regno + i 1792 || !MEM_P (SET_DEST (elt)) 1793 || GET_MODE (SET_DEST (elt)) != SImode) 1794 return 0; 1795 newaddr = XEXP (SET_DEST (elt), 0); 1796 if (legitimate_indirect_address_p (newaddr, 0)) 1797 { 1798 newoffset = 0; 1799 addr_reg = newaddr; 1800 } 1801 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1802 { 1803 addr_reg = XEXP (newaddr, 0); 1804 newoffset = INTVAL (XEXP (newaddr, 1)); 1805 } 1806 else 1807 return 0; 1808 if (REGNO (addr_reg) != base_regno 1809 || newoffset != offset + 4 * i) 1810 return 0; 1811 } 1812 1813 return 1; 1814}) 1815 1816;; Return 1 if OP is a stack tie operand. 1817(define_predicate "tie_operand" 1818 (match_code "parallel") 1819{ 1820 return (GET_CODE (XVECEXP (op, 0, 0)) == SET 1821 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0)) 1822 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode 1823 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx); 1824}) 1825 1826;; Match a small code model toc reference (or medium and large 1827;; model toc references before reload). 1828(define_predicate "small_toc_ref" 1829 (match_code "unspec,plus") 1830{ 1831 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode)) 1832 op = XEXP (op, 0); 1833 1834 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; 1835}) 1836 1837 1838;; Match the first insn (addis) in fusing the combination of addis and loads to 1839;; GPR registers on power8. 1840(define_predicate "fusion_gpr_addis" 1841 (match_code "const_int,high,plus") 1842{ 1843 HOST_WIDE_INT value; 1844 rtx int_const; 1845 1846 if (GET_CODE (op) == HIGH) 1847 return 1; 1848 1849 if (CONST_INT_P (op)) 1850 int_const = op; 1851 1852 else if (GET_CODE (op) == PLUS 1853 && base_reg_operand (XEXP (op, 0), Pmode) 1854 && CONST_INT_P (XEXP (op, 1))) 1855 int_const = XEXP (op, 1); 1856 1857 else 1858 return 0; 1859 1860 value = INTVAL (int_const); 1861 if ((value & (HOST_WIDE_INT)0xffff) != 0) 1862 return 0; 1863 1864 if ((value & (HOST_WIDE_INT)0xffff0000) == 0) 1865 return 0; 1866 1867 /* Power8 only does the fusion if the top 12 bits of the addis value are all 1868 1's or 0's. */ 1869 return (IN_RANGE (value >> 16, -16, 15)); 1870}) 1871 1872;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis 1873;; and loads to GPR registers on power8. 1874(define_predicate "fusion_gpr_mem_load" 1875 (match_code "mem,sign_extend,zero_extend") 1876{ 1877 rtx addr, base, offset; 1878 1879 /* Handle sign/zero extend. */ 1880 if (GET_CODE (op) == ZERO_EXTEND 1881 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) 1882 { 1883 op = XEXP (op, 0); 1884 mode = GET_MODE (op); 1885 } 1886 1887 if (!MEM_P (op)) 1888 return 0; 1889 1890 switch (mode) 1891 { 1892 case E_QImode: 1893 case E_HImode: 1894 case E_SImode: 1895 break; 1896 1897 case E_DImode: 1898 if (!TARGET_POWERPC64) 1899 return 0; 1900 break; 1901 1902 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they 1903 are not common. */ 1904 default: 1905 return 0; 1906 } 1907 1908 addr = XEXP (op, 0); 1909 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1910 return 0; 1911 1912 base = XEXP (addr, 0); 1913 if (!base_reg_operand (base, GET_MODE (base))) 1914 return 0; 1915 1916 offset = XEXP (addr, 1); 1917 1918 if (GET_CODE (addr) == PLUS) 1919 return satisfies_constraint_I (offset); 1920 1921 else if (GET_CODE (addr) == LO_SUM) 1922 { 1923 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1924 return small_toc_ref (offset, GET_MODE (offset)); 1925 1926 else if (TARGET_ELF && !TARGET_POWERPC64) 1927 return CONSTANT_P (offset); 1928 } 1929 1930 return 0; 1931}) 1932 1933;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the 1934;; memory field with both the addis and the memory offset. Sign extension 1935;; is not handled here, since lha and lwa are not fused. 1936(define_predicate "fusion_addis_mem_combo_load" 1937 (match_code "mem,zero_extend") 1938{ 1939 rtx addr, base, offset; 1940 1941 /* Handle zero extend. */ 1942 if (GET_CODE (op) == ZERO_EXTEND) 1943 { 1944 op = XEXP (op, 0); 1945 mode = GET_MODE (op); 1946 } 1947 1948 if (!MEM_P (op)) 1949 return 0; 1950 1951 switch (mode) 1952 { 1953 case E_QImode: 1954 case E_HImode: 1955 case E_SImode: 1956 break; 1957 1958 /* Do not fuse 64-bit DImode in 32-bit since it splits into two 1959 separate instructions. */ 1960 case E_DImode: 1961 if (!TARGET_POWERPC64) 1962 return 0; 1963 break; 1964 1965 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they 1966 are not common. */ 1967 default: 1968 return 0; 1969 } 1970 1971 addr = XEXP (op, 0); 1972 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1973 return 0; 1974 1975 base = XEXP (addr, 0); 1976 if (!fusion_gpr_addis (base, GET_MODE (base))) 1977 return 0; 1978 1979 offset = XEXP (addr, 1); 1980 if (GET_CODE (addr) == PLUS) 1981 return satisfies_constraint_I (offset); 1982 1983 else if (GET_CODE (addr) == LO_SUM) 1984 { 1985 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1986 return small_toc_ref (offset, GET_MODE (offset)); 1987 1988 else if (TARGET_ELF && !TARGET_POWERPC64) 1989 return CONSTANT_P (offset); 1990 } 1991 1992 return 0; 1993}) 1994 1995 1996;; Return true if the operand is a PC-relative address of a local symbol or a 1997;; label that can be used directly in a memory operation. 1998(define_predicate "pcrel_local_address" 1999 (match_code "label_ref,symbol_ref,const") 2000{ 2001 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT); 2002 return iform == INSN_FORM_PCREL_LOCAL; 2003}) 2004 2005;; Return true if the operand is a PC-relative external symbol whose address 2006;; can be loaded into a register. 2007(define_predicate "pcrel_external_address" 2008 (match_code "symbol_ref,const") 2009{ 2010 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT); 2011 return iform == INSN_FORM_PCREL_EXTERNAL; 2012}) 2013 2014;; Return true if the address is PC-relative and the symbol is either local or 2015;; external. 2016(define_predicate "pcrel_local_or_external_address" 2017 (ior (match_operand 0 "pcrel_local_address") 2018 (match_operand 0 "pcrel_external_address"))) 2019 2020;; Return true if the operand is a memory address that uses a prefixed address. 2021(define_predicate "prefixed_memory" 2022 (match_code "mem") 2023{ 2024 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT); 2025}) 2026 2027;; Return true if the operand is a valid memory operand with a D-form 2028;; address that could be merged with the load of a PC-relative external address 2029;; with the PCREL_OPT optimization. We don't check here whether or not the 2030;; offset needs to be used in a DS-FORM (bottom 2 bits 0) or DQ-FORM (bottom 4 2031;; bits 0) instruction. 2032(define_predicate "d_form_memory" 2033 (match_code "mem") 2034{ 2035 if (!memory_operand (op, mode)) 2036 return false; 2037 2038 rtx addr = XEXP (op, 0); 2039 2040 if (REG_P (addr)) 2041 return true; 2042 if (SUBREG_P (addr) && REG_P (SUBREG_REG (addr))) 2043 return true; 2044 2045 return !indexed_address (addr, mode); 2046}) 2047 2048;; Return 1 if this operand is valid as the index for vec_set. 2049(define_predicate "vec_set_index_operand" 2050 (if_then_else (match_test "TARGET_VSX") 2051 (match_operand 0 "reg_or_cint_operand") 2052 (match_operand 0 "const_int_operand"))) 2053 2054;; Return true if the operand is a valid Mach-O pic address. 2055;; 2056(define_predicate "macho_pic_address" 2057 (match_code "const,unspec") 2058{ 2059 if (GET_CODE (op) == CONST) 2060 op = XEXP (op, 0); 2061 2062 if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_MACHOPIC_OFFSET) 2063 return CONSTANT_P (XVECEXP (op, 0, 0)); 2064 else 2065 return false; 2066}) 2067