1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* CPU data header for fr30. 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6 Copyright (C) 1996-2020 Free Software Foundation, Inc. 7 8 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24 */ 25 26 #ifndef FR30_CPU_H 27 #define FR30_CPU_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define CGEN_ARCH fr30 34 35 /* Given symbol S, return fr30_cgen_<S>. */ 36 #define CGEN_SYM(s) fr30##_cgen_##s 37 38 39 /* Selected cpu families. */ 40 #define HAVE_CPU_FR30BF 41 42 #define CGEN_INSN_LSB0_P 0 43 44 /* Minimum size of any insn (in bytes). */ 45 #define CGEN_MIN_INSN_SIZE 2 46 47 /* Maximum size of any insn (in bytes). */ 48 #define CGEN_MAX_INSN_SIZE 6 49 50 #define CGEN_INT_INSN_P 0 51 52 /* Maximum number of syntax elements in an instruction. */ 53 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 54 55 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 56 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 57 we can't hash on everything up to the space. */ 58 #define CGEN_MNEMONIC_OPERANDS 59 60 /* Maximum number of fields in an instruction. */ 61 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 62 63 /* Enums. */ 64 65 /* Enum declaration for insn op1 enums. */ 66 typedef enum insn_op1 { 67 OP1_0, OP1_1, OP1_2, OP1_3 68 , OP1_4, OP1_5, OP1_6, OP1_7 69 , OP1_8, OP1_9, OP1_A, OP1_B 70 , OP1_C, OP1_D, OP1_E, OP1_F 71 } INSN_OP1; 72 73 /* Enum declaration for insn op2 enums. */ 74 typedef enum insn_op2 { 75 OP2_0, OP2_1, OP2_2, OP2_3 76 , OP2_4, OP2_5, OP2_6, OP2_7 77 , OP2_8, OP2_9, OP2_A, OP2_B 78 , OP2_C, OP2_D, OP2_E, OP2_F 79 } INSN_OP2; 80 81 /* Enum declaration for insn op3 enums. */ 82 typedef enum insn_op3 { 83 OP3_0, OP3_1, OP3_2, OP3_3 84 , OP3_4, OP3_5, OP3_6, OP3_7 85 , OP3_8, OP3_9, OP3_A, OP3_B 86 , OP3_C, OP3_D, OP3_E, OP3_F 87 } INSN_OP3; 88 89 /* Enum declaration for insn op4 enums. */ 90 typedef enum insn_op4 { 91 OP4_0 92 } INSN_OP4; 93 94 /* Enum declaration for insn op5 enums. */ 95 typedef enum insn_op5 { 96 OP5_0, OP5_1 97 } INSN_OP5; 98 99 /* Enum declaration for insn cc enums. */ 100 typedef enum insn_cc { 101 CC_RA, CC_NO, CC_EQ, CC_NE 102 , CC_C, CC_NC, CC_N, CC_P 103 , CC_V, CC_NV, CC_LT, CC_GE 104 , CC_LE, CC_GT, CC_LS, CC_HI 105 } INSN_CC; 106 107 /* Enum declaration for . */ 108 typedef enum gr_names { 109 H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 110 , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 111 , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 112 , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 113 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 114 } GR_NAMES; 115 116 /* Enum declaration for . */ 117 typedef enum cr_names { 118 H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 119 , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 120 , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 121 , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 122 } CR_NAMES; 123 124 /* Enum declaration for . */ 125 typedef enum dr_names { 126 H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP 127 , H_DR_MDH, H_DR_MDL 128 } DR_NAMES; 129 130 /* Attributes. */ 131 132 /* Enum declaration for machine type selection. */ 133 typedef enum mach_attr { 134 MACH_BASE, MACH_FR30, MACH_MAX 135 } MACH_ATTR; 136 137 /* Enum declaration for instruction set selection. */ 138 typedef enum isa_attr { 139 ISA_FR30, ISA_MAX 140 } ISA_ATTR; 141 142 /* Number of architecture variants. */ 143 #define MAX_ISAS 1 144 #define MAX_MACHS ((int) MACH_MAX) 145 146 /* Ifield support. */ 147 148 /* Ifield attribute indices. */ 149 150 /* Enum declaration for cgen_ifld attrs. */ 151 typedef enum cgen_ifld_attr { 152 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 153 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 154 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 155 } CGEN_IFLD_ATTR; 156 157 /* Number of non-boolean elements in cgen_ifld_attr. */ 158 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 159 160 /* cgen_ifld attribute accessor macros. */ 161 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 162 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 163 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 164 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 165 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 166 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 167 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 168 169 /* Enum declaration for fr30 ifield types. */ 170 typedef enum ifield_type { 171 FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 172 , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC 173 , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1 174 , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ 175 , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4 176 , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4 177 , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6 178 , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10 179 , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9 180 , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST 181 , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX 182 } IFIELD_TYPE; 183 184 #define MAX_IFLD ((int) FR30_F_MAX) 185 186 /* Hardware attribute indices. */ 187 188 /* Enum declaration for cgen_hw attrs. */ 189 typedef enum cgen_hw_attr { 190 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 191 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 192 } CGEN_HW_ATTR; 193 194 /* Number of non-boolean elements in cgen_hw_attr. */ 195 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 196 197 /* cgen_hw attribute accessor macros. */ 198 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 199 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 200 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 201 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 202 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 203 204 /* Enum declaration for fr30 hardware types. */ 205 typedef enum cgen_hw_type { 206 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 207 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR 208 , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 209 , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT 210 , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT 211 , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR 212 , HW_H_ILM, HW_MAX 213 } CGEN_HW_TYPE; 214 215 #define MAX_HW ((int) HW_MAX) 216 217 /* Operand attribute indices. */ 218 219 /* Enum declaration for cgen_operand attrs. */ 220 typedef enum cgen_operand_attr { 221 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 222 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 223 , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 224 , CGEN_OPERAND_END_NBOOLS 225 } CGEN_OPERAND_ATTR; 226 227 /* Number of non-boolean elements in cgen_operand_attr. */ 228 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 229 230 /* cgen_operand attribute accessor macros. */ 231 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 232 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 233 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 234 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 235 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 236 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 237 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 238 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 239 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 240 #define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) 241 242 /* Enum declaration for fr30 operand types. */ 243 typedef enum cgen_operand_type { 244 FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC 245 , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 246 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 247 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8 248 , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 249 , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 250 , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9 251 , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD 252 , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC 253 , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT 254 , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT 255 , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR 256 , FR30_OPERAND_ILM, FR30_OPERAND_MAX 257 } CGEN_OPERAND_TYPE; 258 259 /* Number of operands types. */ 260 #define MAX_OPERANDS 49 261 262 /* Maximum number of operands referenced by any insn. */ 263 #define MAX_OPERAND_INSTANCES 8 264 265 /* Insn attribute indices. */ 266 267 /* Enum declaration for cgen_insn attrs. */ 268 typedef enum cgen_insn_attr { 269 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 270 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 271 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS 272 , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 273 } CGEN_INSN_ATTR; 274 275 /* Number of non-boolean elements in cgen_insn_attr. */ 276 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 277 278 /* cgen_insn attribute accessor macros. */ 279 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 280 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 281 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 282 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 283 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 284 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 285 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 286 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 287 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 288 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 289 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 290 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) 291 292 /* cgen.h uses things we just defined. */ 293 #include "opcode/cgen.h" 294 295 extern const struct cgen_ifld fr30_cgen_ifld_table[]; 296 297 /* Attributes. */ 298 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[]; 299 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[]; 300 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[]; 301 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; 302 303 /* Hardware decls. */ 304 305 extern CGEN_KEYWORD fr30_cgen_opval_gr_names; 306 extern CGEN_KEYWORD fr30_cgen_opval_cr_names; 307 extern CGEN_KEYWORD fr30_cgen_opval_dr_names; 308 extern CGEN_KEYWORD fr30_cgen_opval_h_ps; 309 extern CGEN_KEYWORD fr30_cgen_opval_h_r13; 310 extern CGEN_KEYWORD fr30_cgen_opval_h_r14; 311 extern CGEN_KEYWORD fr30_cgen_opval_h_r15; 312 313 extern const CGEN_HW_ENTRY fr30_cgen_hw_table[]; 314 315 316 317 #ifdef __cplusplus 318 } 319 #endif 320 321 #endif /* FR30_CPU_H */ 322