1//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp
2# mach: bfin
3# sim: --environment operating
4
5#include "test.h"
6.include "testutils.inc"
7start
8
9/////////////////////////////////////////////////////////////////////////////
10///////////////////////// Include Files         /////////////////////////////
11/////////////////////////////////////////////////////////////////////////////
12
13include(std.inc)
14include(selfcheck.inc)
15include(symtable.inc)
16include(mmrs.inc)
17
18/////////////////////////////////////////////////////////////////////////////
19///////////////////////// Defines               /////////////////////////////
20/////////////////////////////////////////////////////////////////////////////
21
22#ifndef USER_CODE_SPACE
23#define USER_CODE_SPACE  CODE_ADDR_1   //
24#endif
25#ifndef STACKSIZE
26#define STACKSIZE        0x00000010
27#endif
28#ifndef ITABLE
29#define ITABLE           CODE_ADDR_2   //
30#endif
31
32/////////////////////////////////////////////////////////////////////////////
33///////////////////////// RESET ISR             /////////////////////////////
34/////////////////////////////////////////////////////////////////////////////
35
36 RST_ISR :
37
38    // Initialize Dregs
39INIT_R_REGS(0);
40
41    // Initialize Pregs
42INIT_P_REGS(0);
43
44    // Initialize ILBM Registers
45INIT_I_REGS(0);
46INIT_M_REGS(0);
47INIT_L_REGS(0);
48INIT_B_REGS(0);
49
50    // Initialize the Address of the Checkreg data segment
51    // **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
52CHECK_INIT_DEF(p5); //CHECK_INIT(p5,   0x00BFFFFC);
53
54    // Setup User Stack
55LD32_LABEL(sp, USTACK);
56USP = SP;
57
58    // Setup Kernel Stack
59LD32_LABEL(sp, KSTACK);
60
61    // Setup Frame Pointer
62FP = SP;
63
64    // Setup Event Vector Table
65LD32(p0, EVT0);
66
67LD32_LABEL(r0, EMU_ISR);    // Emulation Handler (Int0)
68    [ P0 ++ ] = R0;
69LD32_LABEL(r0, RST_ISR);    // Reset Handler (Int1)
70    [ P0 ++ ] = R0;
71LD32_LABEL(r0, NMI_ISR);    // NMI Handler (Int2)
72    [ P0 ++ ] = R0;
73LD32_LABEL(r0, EXC_ISR);    // Exception Handler (Int3)
74    [ P0 ++ ] = R0;
75    [ P0 ++ ] = R0;                // IVT4 not used
76LD32_LABEL(r0, HWE_ISR);    // HW Error Handler (Int5)
77    [ P0 ++ ] = R0;
78LD32_LABEL(r0, TMR_ISR);    // Timer Handler (Int6)
79    [ P0 ++ ] = R0;
80LD32_LABEL(r0, IGV7_ISR);   // IVG7 Handler
81    [ P0 ++ ] = R0;
82LD32_LABEL(r0, IGV8_ISR);   // IVG8 Handler
83    [ P0 ++ ] = R0;
84LD32_LABEL(r0, IGV9_ISR);   // IVG9 Handler
85    [ P0 ++ ] = R0;
86LD32_LABEL(r0, IGV10_ISR);  // IVG10 Handler
87    [ P0 ++ ] = R0;
88LD32_LABEL(r0, IGV11_ISR);  // IVG11 Handler
89    [ P0 ++ ] = R0;
90LD32_LABEL(r0, IGV12_ISR);  // IVG12 Handler
91    [ P0 ++ ] = R0;
92LD32_LABEL(r0, IGV13_ISR);  // IVG13 Handler
93    [ P0 ++ ] = R0;
94LD32_LABEL(r0, IGV14_ISR);  // IVG14 Handler
95    [ P0 ++ ] = R0;
96LD32_LABEL(r0, IGV15_ISR);  // IVG15 Handler
97    [ P0 ++ ] = R0;
98
99    // Setup the EVT_OVERRIDE MMR
100    R0 = 0;
101LD32(p0, EVT_OVERRIDE);
102    [ P0 ] = R0;
103
104    // Setup Interrupt Mask
105    R0 = -1;
106LD32(p0, IMASK);
107    [ P0 ] = R0;
108
109    // Return to Supervisor Code
110RAISE 15;
111NOP;
112
113LD32_LABEL(r0, USER_CODE);
114RETI = R0;
115RTI;
116
117.dw 0xFFFF
118.dw 0xFFFF
119.dw 0xFFFF
120.dw 0xFFFF
121.dw 0xFFFF
122.dw 0xFFFF
123.dw 0xFFFF
124
125/////////////////////////////////////////////////////////////////////////////
126
127
128/////////////////////////////////////////////////////////////////////////////
129///////////////////////// EMU ISR               /////////////////////////////
130/////////////////////////////////////////////////////////////////////////////
131
132 EMU_ISR :
133
134RTE;
135
136.dw 0xFFFF
137.dw 0xFFFF
138.dw 0xFFFF
139.dw 0xFFFF
140.dw 0xFFFF
141.dw 0xFFFF
142.dw 0xFFFF
143
144/////////////////////////////////////////////////////////////////////////////
145///////////////////////// NMI ISR               /////////////////////////////
146/////////////////////////////////////////////////////////////////////////////
147
148 NMI_ISR :
149
150RTN;
151
152.dw 0xFFFF
153.dw 0xFFFF
154.dw 0xFFFF
155.dw 0xFFFF
156.dw 0xFFFF
157.dw 0xFFFF
158.dw 0xFFFF
159
160/////////////////////////////////////////////////////////////////////////////
161///////////////////////// EXC ISR               /////////////////////////////
162/////////////////////////////////////////////////////////////////////////////
163
164 EXC_ISR :
165
166RTX;
167
168.dw 0xFFFF
169.dw 0xFFFF
170.dw 0xFFFF
171.dw 0xFFFF
172.dw 0xFFFF
173.dw 0xFFFF
174.dw 0xFFFF
175
176/////////////////////////////////////////////////////////////////////////////
177///////////////////////// HWE ISR               /////////////////////////////
178/////////////////////////////////////////////////////////////////////////////
179
180 HWE_ISR :
181
182RTI;
183
184.dw 0xFFFF
185.dw 0xFFFF
186.dw 0xFFFF
187.dw 0xFFFF
188.dw 0xFFFF
189.dw 0xFFFF
190.dw 0xFFFF
191
192/////////////////////////////////////////////////////////////////////////////
193///////////////////////// TMR ISR               /////////////////////////////
194/////////////////////////////////////////////////////////////////////////////
195
196 TMR_ISR :
197
198RTI;
199
200.dw 0xFFFF
201.dw 0xFFFF
202.dw 0xFFFF
203.dw 0xFFFF
204.dw 0xFFFF
205.dw 0xFFFF
206.dw 0xFFFF
207
208/////////////////////////////////////////////////////////////////////////////
209///////////////////////// IGV7 ISR              /////////////////////////////
210/////////////////////////////////////////////////////////////////////////////
211
212 IGV7_ISR :
213
214RTI;
215
216.dw 0xFFFF
217.dw 0xFFFF
218.dw 0xFFFF
219.dw 0xFFFF
220.dw 0xFFFF
221.dw 0xFFFF
222.dw 0xFFFF
223
224/////////////////////////////////////////////////////////////////////////////
225///////////////////////// IGV8 ISR              /////////////////////////////
226/////////////////////////////////////////////////////////////////////////////
227
228 IGV8_ISR :
229
230RTI;
231
232.dw 0xFFFF
233.dw 0xFFFF
234.dw 0xFFFF
235.dw 0xFFFF
236.dw 0xFFFF
237.dw 0xFFFF
238.dw 0xFFFF
239
240/////////////////////////////////////////////////////////////////////////////
241///////////////////////// IGV9 ISR              /////////////////////////////
242/////////////////////////////////////////////////////////////////////////////
243
244 IGV9_ISR :
245
246RTI;
247
248.dw 0xFFFF
249.dw 0xFFFF
250.dw 0xFFFF
251.dw 0xFFFF
252.dw 0xFFFF
253.dw 0xFFFF
254.dw 0xFFFF
255
256/////////////////////////////////////////////////////////////////////////////
257///////////////////////// IGV10 ISR             /////////////////////////////
258/////////////////////////////////////////////////////////////////////////////
259
260 IGV10_ISR :
261
262RTI;
263
264.dw 0xFFFF
265.dw 0xFFFF
266.dw 0xFFFF
267.dw 0xFFFF
268.dw 0xFFFF
269.dw 0xFFFF
270.dw 0xFFFF
271
272/////////////////////////////////////////////////////////////////////////////
273///////////////////////// IGV11 ISR             /////////////////////////////
274/////////////////////////////////////////////////////////////////////////////
275
276 IGV11_ISR :
277
278RTI;
279
280.dw 0xFFFF
281.dw 0xFFFF
282.dw 0xFFFF
283.dw 0xFFFF
284.dw 0xFFFF
285.dw 0xFFFF
286.dw 0xFFFF
287
288/////////////////////////////////////////////////////////////////////////////
289///////////////////////// IGV12 ISR             /////////////////////////////
290/////////////////////////////////////////////////////////////////////////////
291
292 IGV12_ISR :
293
294RTI;
295
296.dw 0xFFFF
297.dw 0xFFFF
298.dw 0xFFFF
299.dw 0xFFFF
300.dw 0xFFFF
301.dw 0xFFFF
302.dw 0xFFFF
303
304/////////////////////////////////////////////////////////////////////////////
305///////////////////////// IGV13 ISR             /////////////////////////////
306/////////////////////////////////////////////////////////////////////////////
307
308 IGV13_ISR :
309
310RTI;
311
312.dw 0xFFFF
313.dw 0xFFFF
314.dw 0xFFFF
315.dw 0xFFFF
316.dw 0xFFFF
317.dw 0xFFFF
318.dw 0xFFFF
319
320/////////////////////////////////////////////////////////////////////////////
321///////////////////////// IGV14 ISR             /////////////////////////////
322/////////////////////////////////////////////////////////////////////////////
323
324 IGV14_ISR :
325
326RTI;
327
328.dw 0xFFFF
329.dw 0xFFFF
330.dw 0xFFFF
331.dw 0xFFFF
332.dw 0xFFFF
333.dw 0xFFFF
334.dw 0xFFFF
335
336/////////////////////////////////////////////////////////////////////////////
337///////////////////////// IGV15 ISR             /////////////////////////////
338/////////////////////////////////////////////////////////////////////////////
339
340 IGV15_ISR :
341
342    P0 = 0x1 (Z);
343    P1 = 0x2 (Z);
344    P2 = 0x3 (Z);
345    P3 = 0x4 (Z);
346    P4 = 0x5 (Z);
347
348/////////////////////////////////////////////////////////////////////////////
349// Loop 0 (with Kill WB)
350/////////////////////////////////////////////////////////////////////////////
351
352    // Kill Valid Dcr in WB
353LSETUP ( L0T , L0T ) LC0 = P0;
354EXCPT 0x5;
355L0T:R0 += 5;
356
357    // Kill Valid Dcr in EX3
358LSETUP ( L1T , L1B ) LC0 = P0;
359EXCPT 0x5;
360L1T:R0 += 5;
361L1B:R1 += 4;
362
363    // Kill Valid Dcr in EX2
364LSETUP ( L2T , L2B ) LC0 = P0;
365EXCPT 0x5;
366L2T:R0 += 5;
367    R1 += 4;
368L2B:R2 += 3;
369
370    // Kill Valid Dcr in EX1
371LSETUP ( L3T , L3B ) LC0 = P0;
372EXCPT 0x5;
373L3T:R0 += 5;
374    R1 += 4;
375    R2 += 3;
376L3B:R3 += 2;
377
378    // Kill Valid Dcr in AC
379LSETUP ( L4T , L4B ) LC0 = P0;
380EXCPT 0x5;
381L4T:R0 += 5;
382    R1 += 4;
383    R2 += 3;
384    R3 += 2;
385L4B:R4 += 1;
386
387    // Kill Valid Dcr in WB, EX3
388LSETUP ( L5T , L5T ) LC0 = P1;
389EXCPT 0x5;
390L5T:R1 += 5;
391
392    // Kill Valid Dcr in EX3, EX2
393LSETUP ( L6T , L6T ) LC0 = P1;
394EXCPT 0x5;
395NOP;
396L6T:R2 += 5;
397
398    // Kill Valid Dcr in EX2, EX1
399LSETUP ( L7T , L7T ) LC0 = P1;
400EXCPT 0x5;
401NOP;
402NOP;
403L7T:R3 += 5;
404
405    // Kill Valid Dcr in EX1, AC
406LSETUP ( L8T , L8T ) LC0 = P1;
407EXCPT 0x5;
408NOP;
409NOP;
410NOP;
411L8T:R4 += 5;
412
413    // Kill Valid Dcr in WB, EX3, EX2
414LSETUP ( L9T , L9T ) LC0 = P2;
415EXCPT 0x5;
416L9T:R5 += 5;
417
418    // Kill Valid Dcr in EX3, EX2, EX1
419LSETUP ( LAT , LAT ) LC0 = P2;
420EXCPT 0x5;
421NOP;
422LAT:
423	R6 += 6;
424
425    // Kill Valid Dcr in EX2, EX1, AC
426LSETUP ( LBT , LBT ) LC0 = P2;
427EXCPT 0x5;
428NOP;
429NOP;
430LBT:
431	R5 += 5;
432
433    // Kill Valid Dcr in WB, EX3, EX2, EX1
434LSETUP ( LCT , LCT ) LC0 = P3;
435EXCPT 0x5;
436LCT:
437	R7 += 7;
438
439    // Kill Valid Dcr in EX3, EX2, EX1, AC
440LSETUP ( LDT , LDT ) LC0 = P3;
441EXCPT 0x5;
442NOP;
443LDT:
444	R0 += 7;
445
446    // Kill Valid Dcr in WB, EX3, EX2, EX1, AC
447LSETUP ( LET , LET ) LC0 = P4;
448EXCPT 0x5;
449LET:
450	R1 += 1;
451
452    // Kill Valid Dcr in WB, EX2
453LSETUP ( LFT , LFB ) LC0 = P1;
454LFT:
455	EXCPT 0x5;
456LFB:
457	R1 += 2;
458
459    // Kill Valid Dcr in WB, EX1
460LSETUP ( LGT , LGB ) LC0 = P1;
461LGT:
462	R2 += 3;
463EXCPT 0x5;
464LGB:
465	R1 += 2;
466
467    // Kill Valid Dcr in WB, AC
468LSETUP ( LHT , LHB ) LC0 = P1;
469LHT:
470	R2 += 3;
471    R3 += 4;
472EXCPT 0x5;
473LHB:
474	R1 += 2;
475
476    // Kill Valid Dcr in EX3, EX1
477LSETUP ( LIT , LIB ) LC0 = P1;
478EXCPT 0x5;
479LIT:
480	R2 += 1;
481LIB:
482	R1 += 2;
483
484    // Kill Valid Dcr in EX3, AC
485LSETUP ( LJT , LJB ) LC0 = P1;
486LJT:
487	EXCPT 0x5;
488    R2 += 1;
489LJB:
490	R1 += 2;
491
492    // Kill Valid Dcr in EX2, AC
493LSETUP ( LKT , LKB ) LC0 = P1;
494EXCPT 0x5;
495NOP;
496LKT:
497	R2 += 1;
498LKB:
499	R1 += 2;
500
501    // Kill Valid Dcr in WB, EX2, AC
502LSETUP ( LLT , LLB ) LC0 = P2;
503LLT:
504	EXCPT 0x5;
505LLB:
506	R2 += 2;
507
508
509/////////////////////////////////////////////////////////////////////////////
510// Loop 1 (with Kill WB)
511/////////////////////////////////////////////////////////////////////////////
512
513    // Kill Valid Dcr in WB
514LSETUP ( M0T , M0T ) LC1 = P0;
515EXCPT 0x5;
516M0T:R0 += 5;
517
518    // Kill Valid Dcr in EX3
519LSETUP ( M1T , M1B ) LC1 = P0;
520EXCPT 0x5;
521M1T:R0 += 5;
522M1B:R1 += 4;
523
524    // Kill Valid Dcr in EX2
525LSETUP ( M2T , M2B ) LC1 = P0;
526EXCPT 0x5;
527M2T:R0 += 5;
528    R1 += 4;
529M2B:R2 += 3;
530
531    // Kill Valid Dcr in EX1
532LSETUP ( M3T , M3B ) LC1 = P0;
533EXCPT 0x5;
534M3T:R0 += 5;
535    R1 += 4;
536    R2 += 3;
537M3B:R3 += 2;
538
539    // Kill Valid Dcr in AC
540LSETUP ( M4T , M4B ) LC1 = P0;
541EXCPT 0x5;
542M4T:R0 += 5;
543    R1 += 4;
544    R2 += 3;
545    R3 += 2;
546M4B:R4 += 1;
547
548    // Kill Valid Dcr in WB, EX3
549LSETUP ( M5T , M5T ) LC1 = P1;
550EXCPT 0x5;
551M5T:R1 += 5;
552
553    // Kill Valid Dcr in EX3, EX2
554LSETUP ( M6T , M6T ) LC1 = P1;
555EXCPT 0x5;
556NOP;
557M6T:R2 += 5;
558
559    // Kill Valid Dcr in EX2, EX1
560LSETUP ( M7T , M7T ) LC1 = P1;
561EXCPT 0x5;
562NOP;
563NOP;
564M7T:R3 += 5;
565
566    // Kill Valid Dcr in EX1, AC
567LSETUP ( M8T , M8T ) LC1 = P1;
568EXCPT 0x5;
569NOP;
570NOP;
571NOP;
572M8T:R4 += 5;
573
574    // Kill Valid Dcr in WB, EX3, EX2
575LSETUP ( M9T , M9T ) LC1 = P2;
576EXCPT 0x5;
577M9T:R5 += 5;
578
579    // Kill Valid Dcr in EX3, EX2, EX1
580LSETUP ( MAT , MAT ) LC1 = P2;
581EXCPT 0x5;
582NOP;
583MAT:
584	R6 += 6;
585
586    // Kill Valid Dcr in EX2, EX1, AC
587LSETUP ( MBT , MBT ) LC1 = P2;
588EXCPT 0x5;
589NOP;
590NOP;
591MBT:
592	R5 += 5;
593
594    // Kill Valid Dcr in WB, EX3, EX2, EX1
595LSETUP ( MCT , MCT ) LC1 = P3;
596EXCPT 0x5;
597MCT:
598	R7 += 7;
599
600    // Kill Valid Dcr in EX3, EX2, EX1, AC
601LSETUP ( MDT , MDT ) LC1 = P3;
602EXCPT 0x5;
603NOP;
604MDT:
605	R0 += 7;
606
607    // Kill Valid Dcr in WB, EX3, EX2, EX1, AC
608LSETUP ( MET , MET ) LC1 = P4;
609EXCPT 0x5;
610MET:
611	R1 += 1;
612
613    // Kill Valid Dcr in WB, EX2
614LSETUP ( MFT , MFB ) LC1 = P1;
615MFT:
616	EXCPT 0x5;
617MFB:
618	R1 += 2;
619
620    // Kill Valid Dcr in WB, EX1
621LSETUP ( MGT , MGB ) LC1 = P1;
622MGT:
623	R2 += 3;
624EXCPT 0x5;
625MGB:
626	R1 += 2;
627
628    // Kill Valid Dcr in WB, AC
629LSETUP ( MHT , MHB ) LC1 = P1;
630MHT:
631	R2 += 3;
632    R3 += 4;
633EXCPT 0x5;
634MHB:
635	R1 += 2;
636
637    // Kill Valid Dcr in EX3, EX1
638LSETUP ( MIT , MIB ) LC1 = P1;
639EXCPT 0x5;
640MIT:
641	R2 += 1;
642MIB:
643	R1 += 2;
644
645    // Kill Valid Dcr in EX3, AC
646LSETUP ( MJT , MJB ) LC1 = P1;
647MJT:
648	EXCPT 0x5;
649    R2 += 1;
650MJB:
651	R1 += 2;
652
653    // Kill Valid Dcr in EX2, AC
654LSETUP ( MKT , MKB ) LC1 = P1;
655EXCPT 0x5;
656NOP;
657MKT:
658	R2 += 1;
659MKB:
660	R1 += 2;
661
662    // Kill Valid Dcr in WB, EX2, AC
663LSETUP ( MLT , MLB ) LC1 = P2;
664MLT:
665	EXCPT 0x5;
666MLB:
667	R2 += 2;
668
669/////////////////////////////////////////////////////////////////////////////
670// Loop 0 (with Kill EX3)
671/////////////////////////////////////////////////////////////////////////////
672
673    // Kill Valid Dcr in EX3
674LSETUP ( N1T , N1T ) LC0 = P0;
675CSYNC;
676N1T:R0 += 5;
677
678    // Kill Valid Dcr in EX2
679LSETUP ( N2T , N2B ) LC0 = P0;
680CSYNC;
681N2T:R0 += 5;
682N2B:R2 += 3;
683
684    // Kill Valid Dcr in EX1
685LSETUP ( N3T , N3B ) LC0 = P0;
686CSYNC;
687N3T:R0 += 5;
688    R2 += 3;
689N3B:R3 += 2;
690
691    // Kill Valid Dcr in AC
692LSETUP ( N4T , N4B ) LC0 = P0;
693CSYNC;
694N4T:R0 += 5;
695    R2 += 3;
696    R3 += 2;
697N4B:R4 += 1;
698
699    // Kill Valid Dcr in EX3, EX2
700LSETUP ( N6T , N6T ) LC0 = P1;
701CSYNC;
702N6T:R2 += 5;
703
704    // Kill Valid Dcr in EX2, EX1
705LSETUP ( N7T , N7T ) LC0 = P1;
706CSYNC;
707NOP;
708N7T:R3 += 5;
709
710    // Kill Valid Dcr in EX1, AC
711LSETUP ( N8T , N8T ) LC0 = P1;
712CSYNC;
713NOP;
714NOP;
715N8T:R4 += 5;
716
717    // Kill Valid Dcr in EX3, EX2, EX1
718LSETUP ( NAT , NAT ) LC0 = P2;
719CSYNC;
720NAT:
721	R6 += 6;
722
723    // Kill Valid Dcr in EX2, EX1, AC
724LSETUP ( NBT , NBT ) LC0 = P2;
725CSYNC;
726NOP;
727NBT:
728	R5 += 5;
729
730    // Kill Valid Dcr in EX3, EX2, EX1, AC
731LSETUP ( NDT , NDT ) LC0 = P3;
732CSYNC;
733NDT:
734	R0 += 7;
735
736    // Kill Valid Dcr in EX3, EX1
737LSETUP ( NIT , NIB ) LC0 = P1;
738NIT:
739	CSYNC;
740NIB:
741	R1 += 2;
742
743    // Kill Valid Dcr in EX3, AC
744LSETUP ( NJT , NJB ) LC0 = P1;
745NJT:
746	R2 += 1;
747CSYNC;
748NJB:
749	R1 += 2;
750
751    // Kill Valid Dcr in EX2, AC
752LSETUP ( NKT , NKB ) LC0 = P1;
753CSYNC;
754NKT:
755	R2 += 1;
756NKB:
757	R1 += 2;
758
759/////////////////////////////////////////////////////////////////////////////
760// Loop 1 (with Kill EX3)
761/////////////////////////////////////////////////////////////////////////////
762
763    // Kill Valid Dcr in EX3
764LSETUP ( O1T , O1T ) LC1 = P0;
765CSYNC;
766O1T:R0 += 5;
767
768    // Kill Valid Dcr in EX2
769LSETUP ( O2T , O2B ) LC1 = P0;
770CSYNC;
771O2T:R0 += 5;
772O2B:R2 += 3;
773
774    // Kill Valid Dcr in EX1
775LSETUP ( O3T , O3B ) LC1 = P0;
776CSYNC;
777O3T:R0 += 5;
778    R2 += 3;
779O3B:R3 += 2;
780
781    // Kill Valid Dcr in AC
782LSETUP ( O4T , O4B ) LC1 = P0;
783CSYNC;
784O4T:R0 += 5;
785    R2 += 3;
786    R3 += 2;
787O4B:R4 += 1;
788
789    // Kill Valid Dcr in EX3, EX2
790LSETUP ( O6T , O6T ) LC1 = P1;
791CSYNC;
792O6T:R2 += 5;
793
794    // Kill Valid Dcr in EX2, EX1
795LSETUP ( O7T , O7T ) LC1 = P1;
796CSYNC;
797NOP;
798O7T:R3 += 5;
799
800    // Kill Valid Dcr in EX1, AC
801LSETUP ( O8T , O8T ) LC1 = P1;
802CSYNC;
803NOP;
804NOP;
805O8T:R4 += 5;
806
807    // Kill Valid Dcr in EX3, EX2, EX1
808LSETUP ( OAT , OAT ) LC1 = P2;
809CSYNC;
810OAT:
811	R6 += 6;
812
813    // Kill Valid Dcr in EX2, EX1, AC
814LSETUP ( OBT , OBT ) LC1 = P2;
815CSYNC;
816NOP;
817OBT:
818	R5 += 5;
819
820    // Kill Valid Dcr in EX3, EX2, EX1, AC
821LSETUP ( ODT , ODT ) LC1 = P3;
822CSYNC;
823ODT:
824	R0 += 7;
825
826    // Kill Valid Dcr in EX3, EX1
827LSETUP ( OIT , OIB ) LC1 = P1;
828OIT:
829	CSYNC;
830OIB:
831	R1 += 2;
832
833    // Kill Valid Dcr in EX3, AC
834LSETUP ( OJT , OJB ) LC1 = P1;
835OJT:
836	R2 += 1;
837CSYNC;
838OJB:
839	R1 += 2;
840
841    // Kill Valid Dcr in EX2, AC
842LSETUP ( OKT , OKB ) LC1 = P1;
843CSYNC;
844OKT:
845	R2 += 1;
846OKB:
847	R1 += 2;
848
849/////////////////////////////////////////////////////////////////////////////
850// Loop 0 (with Kill AC)
851/////////////////////////////////////////////////////////////////////////////
852
853    // Kill Valid Dcr in AC
854LSETUP ( P4T , P4T ) LC0 = P0;
855JUMP.S 2;
856P4T:R0 += 5;
857
858/////////////////////////////////////////////////////////////////////////////
859// Loop 1 (with Kill AC)
860/////////////////////////////////////////////////////////////////////////////
861
862    // Kill Valid Dcr in AC
863LSETUP ( Q4T , Q4T ) LC1 = P0;
864JUMP.S 2;
865Q4T:R0 += 5;
866
867NOP;
868NOP;
869RTI;
870
871.dw 0xFFFF
872.dw 0xFFFF
873.dw 0xFFFF
874.dw 0xFFFF
875.dw 0xFFFF
876.dw 0xFFFF
877.dw 0xFFFF
878
879/////////////////////////////////////////////////////////////////////////////
880///////////////////////// USER CODE             /////////////////////////////
881/////////////////////////////////////////////////////////////////////////////
882
883
884 USER_CODE :
885
886NOP;
887NOP;
888NOP;
889NOP;
890dbg_pass;        // Call Endtest Macro
891
892/////////////////////////////////////////////////////////////////////////////
893///////////////////////// DATA MEMRORY          /////////////////////////////
894/////////////////////////////////////////////////////////////////////////////
895
896.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
897.dd 0xdeadbeef;
898.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
899.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
900.dd 0x02020202;
901.dd 0x03030303;
902.dd 0x04040404;
903
904// Define Kernal Stack
905.data
906    .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
907     KSTACK :
908
909    .space (STACKSIZE);
910     USTACK :
911
912/////////////////////////////////////////////////////////////////////////////
913///////////////////////// END OF TEST           /////////////////////////////
914/////////////////////////////////////////////////////////////////////////////
915