1# Hitachi H8 testcase 'mac' 2# mach(): h8300s h8sx 3# as(h8300): --defsym sim_cpu=0 4# as(h8300h): --defsym sim_cpu=1 5# as(h8300s): --defsym sim_cpu=2 6# as(h8sx): --defsym sim_cpu=3 7# ld(h8300h): -m h8300helf 8# ld(h8300s): -m h8300self 9# ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 .data 14src1: .word 0 15src2: .word 0 16 17array: .word 0x7fff 18 .word 0x7fff 19 .word 0x7fff 20 .word 0x7fff 21 .word 0x7fff 22 .word 0x7fff 23 .word 0x7fff 24 .word 0x7fff 25 .word 0x7fff 26 .word 0x7fff 27 .word 0x7fff 28 .word 0x7fff 29 .word 0x7fff 30 .word 0x7fff 31 .word 0x7fff 32 .word 0x7fff 33 34 start 35 36.if (sim_cpu) 37_clrmac: 38 set_grs_a5a5 39 set_ccr_zero 40 clrmac 41 test_cc_clear 42 test_grs_a5a5 43 ;; Now see if the mac is actually clear... 44 stmac mach, er0 45 test_zero_set 46 test_neg_clear 47 test_ovf_clear 48 test_h_gr32 0 er0 49 stmac macl, er1 50 test_zero_set 51 test_neg_clear 52 test_ovf_clear 53 test_h_gr32 0 er1 54 55ld_stmac: 56 set_grs_a5a5 57 sub.l er2, er2 58 set_ccr_zero 59 ldmac er1, macl 60 stmac macl, er2 61 test_ovf_clear 62 test_carry_clear 63 ;; neg and zero are undefined 64 test_h_gr32 0xa5a5a5a5 er2 65 66 sub.l er2, er2 67 set_ccr_zero 68 ldmac er1, mach 69 stmac mach, er2 70 test_ovf_clear 71 test_carry_clear 72 ;; neg and zero are undefined 73 test_h_gr32 0x0001a5 er2 74 75 test_gr_a5a5 0 ; Make sure other general regs not disturbed 76 test_gr_a5a5 1 77 test_gr_a5a5 3 78 test_gr_a5a5 4 79 test_gr_a5a5 5 80 test_gr_a5a5 6 81 test_gr_a5a5 7 82 83mac_2x2: 84 set_grs_a5a5 85 mov.w #2, r1 86 mov.w r1, @src1 87 mov.w #2, r2 88 mov.w r2, @src2 89 mov #src1, er1 90 mov #src2, er2 91 set_ccr_zero 92 clrmac 93 mac @er1+, @er2+ 94 test_cc_clear 95 96 test_h_gr32 0xa5a5a5a5 er0 97 test_h_gr32 src1+2 er1 98 test_h_gr32 src2+2 er2 99 test_h_gr32 0xa5a5a5a5 er3 100 test_h_gr32 0xa5a5a5a5 er4 101 test_h_gr32 0xa5a5a5a5 er5 102 test_h_gr32 0xa5a5a5a5 er6 103 test_h_gr32 0xa5a5a5a5 er7 104 105 stmac macl, er0 106 test_zero_clear 107 test_neg_clear 108 test_ovf_clear 109 test_h_gr32 4 er0 110 111 stmac mach, er0 112 test_zero_clear 113 test_neg_clear 114 test_ovf_clear 115 test_h_gr32 0 er0 116 117mac_same_reg_2x4: 118 ;; Use same reg for src and dst. Should be incremented twice, 119 ;; and fetch values from consecutive locations. 120 set_grs_a5a5 121 mov.w #2, r1 122 mov.w r1, @src1 123 mov.w #4, r2 124 mov.w r2, @src2 125 mov #src1, er1 126 127 set_ccr_zero 128 clrmac 129 mac @er1+, @er1+ ; same register for src and dst 130 test_cc_clear 131 132 test_h_gr32 0xa5a5a5a5 er0 133 test_h_gr32 src1+4 er1 134 test_h_gr32 0xa5a50004 er2 135 test_h_gr32 0xa5a5a5a5 er3 136 test_h_gr32 0xa5a5a5a5 er4 137 test_h_gr32 0xa5a5a5a5 er5 138 test_h_gr32 0xa5a5a5a5 er6 139 test_h_gr32 0xa5a5a5a5 er7 140 141 stmac macl, er0 142 test_zero_clear 143 test_neg_clear 144 test_ovf_clear 145 test_h_gr32 8 er0 146 147 stmac mach, er0 148 test_zero_clear 149 test_neg_clear 150 test_ovf_clear 151 test_h_gr32 0 er0 152 153mac_0x0: 154 set_grs_a5a5 155 mov.w #0, r1 156 mov.w r1, @src1 157 mov.w #0, r2 158 mov.w r2, @src2 159 mov #src1, er1 160 mov #src2, er2 161 set_ccr_zero 162 clrmac 163 mac @er1+, @er2+ 164 test_cc_clear 165 166 test_h_gr32 0xa5a5a5a5 er0 167 test_h_gr32 src1+2 er1 168 test_h_gr32 src2+2 er2 169 test_h_gr32 0xa5a5a5a5 er3 170 test_h_gr32 0xa5a5a5a5 er4 171 test_h_gr32 0xa5a5a5a5 er5 172 test_h_gr32 0xa5a5a5a5 er6 173 test_h_gr32 0xa5a5a5a5 er7 174 175 stmac macl, er0 176 test_zero_set ; zero flag is set 177 test_neg_clear 178 test_ovf_clear 179 test_h_gr32 0 er0 ; result is zero 180 181 stmac mach, er0 182 test_zero_set 183 test_neg_clear 184 test_ovf_clear 185 test_h_gr32 0 er0 186 187mac_neg2x2: 188 set_grs_a5a5 189 mov.w #-2, r1 190 mov.w r1, @src1 191 mov.w #2, r2 192 mov.w r2, @src2 193 mov #src1, er1 194 mov #src2, er2 195 set_ccr_zero 196 clrmac 197 mac @er1+, @er2+ 198 test_cc_clear 199 200 test_h_gr32 0xa5a5a5a5 er0 201 test_h_gr32 src1+2 er1 202 test_h_gr32 src2+2 er2 203 test_h_gr32 0xa5a5a5a5 er3 204 test_h_gr32 0xa5a5a5a5 er4 205 test_h_gr32 0xa5a5a5a5 er5 206 test_h_gr32 0xa5a5a5a5 er6 207 test_h_gr32 0xa5a5a5a5 er7 208 209 stmac macl, er0 210 test_zero_clear 211 test_neg_set ; neg flag is set 212 test_ovf_clear 213 test_h_gr32 -4 er0 ; result is negative 214 215 stmac mach, er0 216 test_zero_clear 217 test_neg_set 218 test_ovf_clear 219 test_h_gr32 -1 er0 ; negative sign extend 220 221mac_array: 222 ;; Use same reg for src and dst, pointing to an array of shorts 223 set_grs_a5a5 224 mov #array, er1 225 226 set_ccr_zero 227 clrmac 228 mac @er1+, @er1+ ; same register for src and dst 229 mac @er1+, @er1+ ; repeat 8 times 230 mac @er1+, @er1+ 231 mac @er1+, @er1+ 232 mac @er1+, @er1+ 233 mac @er1+, @er1+ 234 mac @er1+, @er1+ 235 mac @er1+, @er1+ 236 test_cc_clear 237 238 test_h_gr32 0xa5a5a5a5 er0 239 test_h_gr32 array+32 er1 240 test_h_gr32 0xa5a5a5a5 er2 241 test_h_gr32 0xa5a5a5a5 er3 242 test_h_gr32 0xa5a5a5a5 er4 243 test_h_gr32 0xa5a5a5a5 er5 244 test_h_gr32 0xa5a5a5a5 er6 245 test_h_gr32 0xa5a5a5a5 er7 246 247 stmac macl, er0 248 test_zero_clear 249 test_neg_clear 250 test_ovf_clear 251 test_h_gr32 0xfff80008 er0 252 253 stmac mach, er0 254 test_zero_clear 255 test_neg_clear 256 test_ovf_clear 257 test_h_gr32 1 er0 ; result is greater than 32 bits 258 259.endif 260 261 pass 262 263 exit 0 264