1*df5d72efSjmcneill /* $NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $ */ 2c2c35168Smatt 3c2c35168Smatt /*- 4c2c35168Smatt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5c2c35168Smatt * All rights reserved. 6c2c35168Smatt * 7c2c35168Smatt * This code is derived from software contributed to The NetBSD Foundation 8c2c35168Smatt * by Matt Thomas 9c2c35168Smatt * 10c2c35168Smatt * Redistribution and use in source and binary forms, with or without 11c2c35168Smatt * modification, are permitted provided that the following conditions 12c2c35168Smatt * are met: 13c2c35168Smatt * 1. Redistributions of source code must retain the above copyright 14c2c35168Smatt * notice, this list of conditions and the following disclaimer. 15c2c35168Smatt * 2. Redistributions in binary form must reproduce the above copyright 16c2c35168Smatt * notice, this list of conditions and the following disclaimer in the 17c2c35168Smatt * documentation and/or other materials provided with the distribution. 18c2c35168Smatt * 19c2c35168Smatt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20c2c35168Smatt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21c2c35168Smatt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22c2c35168Smatt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23c2c35168Smatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24c2c35168Smatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25c2c35168Smatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26c2c35168Smatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27c2c35168Smatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28c2c35168Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29c2c35168Smatt * POSSIBILITY OF SUCH DAMAGE. 30c2c35168Smatt */ 31c2c35168Smatt 32c2c35168Smatt #include <sys/cdefs.h> 33*df5d72efSjmcneill __KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $"); 34c2c35168Smatt 35c2c35168Smatt #include <sys/param.h> 36c2c35168Smatt #include <sys/bus.h> 37c2c35168Smatt #include <sys/cpu.h> 38c2c35168Smatt #include <sys/device.h> 3996c39f56Smatt #include <sys/atomic.h> 40c2c35168Smatt 41c3d10eb6Smatt #include <arm/locore.h> 42c3d10eb6Smatt 43c2c35168Smatt #include <arm/cortex/mpcore_var.h> 44c2c35168Smatt #include <arm/cortex/pl310_reg.h> 45162b9739Smatt #include <arm/cortex/pl310_var.h> 46c2c35168Smatt 47c2c35168Smatt static int arml2cc_match(device_t, cfdata_t, void *); 48c2c35168Smatt static void arml2cc_attach(device_t, device_t, void *); 49c2c35168Smatt 50c2c35168Smatt #define L2CC_BASE 0x2000 51c2c35168Smatt #define L2CC_SIZE 0x1000 52c2c35168Smatt 53c2c35168Smatt struct arml2cc_softc { 54c2c35168Smatt device_t sc_dev; 55c2c35168Smatt bus_space_tag_t sc_memt; 56c2c35168Smatt bus_space_handle_t sc_memh; 5796c39f56Smatt kmutex_t sc_lock; 5896c39f56Smatt uint32_t sc_waymask; 5996c39f56Smatt struct evcnt sc_ev_inv __aligned(8); 6096c39f56Smatt struct evcnt sc_ev_wb; 6196c39f56Smatt struct evcnt sc_ev_wbinv; 6296c39f56Smatt bool sc_enabled; 63c2c35168Smatt }; 64c2c35168Smatt 6596c39f56Smatt __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_inv.ev_count) % 8 == 0); 6696c39f56Smatt __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wb.ev_count) % 8 == 0); 6796c39f56Smatt __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wbinv.ev_count) % 8 == 0); 6896c39f56Smatt 69c2c35168Smatt CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc), 70c2c35168Smatt arml2cc_match, arml2cc_attach, NULL, NULL); 71c2c35168Smatt 72374340c0Smatt static inline void arml2cc_disable(struct arml2cc_softc *); 73374340c0Smatt static inline void arml2cc_enable(struct arml2cc_softc *); 7496c39f56Smatt static void arml2cc_sdcache_wb_range(vaddr_t, paddr_t, psize_t); 7596c39f56Smatt static void arml2cc_sdcache_inv_range(vaddr_t, paddr_t, psize_t); 7696c39f56Smatt static void arml2cc_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t); 77162b9739Smatt 7896c39f56Smatt static struct arml2cc_softc *arml2cc_sc; 79c2c35168Smatt 80c2c35168Smatt static inline uint32_t 81c2c35168Smatt arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o) 82c2c35168Smatt { 83c2c35168Smatt return bus_space_read_4(sc->sc_memt, sc->sc_memh, o); 84c2c35168Smatt } 85c2c35168Smatt 86c2c35168Smatt static inline void 87c2c35168Smatt arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v) 88c2c35168Smatt { 89c2c35168Smatt bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v); 90c2c35168Smatt } 91c2c35168Smatt 92c2c35168Smatt 93c2c35168Smatt /* ARGSUSED */ 94c2c35168Smatt static int 95c2c35168Smatt arml2cc_match(device_t parent, cfdata_t cf, void *aux) 96c2c35168Smatt { 97c2c35168Smatt struct mpcore_attach_args * const mpcaa = aux; 98c2c35168Smatt 9996c39f56Smatt if (arml2cc_sc) 100c2c35168Smatt return 0; 101c2c35168Smatt 102*df5d72efSjmcneill if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && 103*df5d72efSjmcneill !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) 104c2c35168Smatt return 0; 105c2c35168Smatt 106c2c35168Smatt if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 107c2c35168Smatt return 0; 108c2c35168Smatt 109c2c35168Smatt /* 110c2c35168Smatt * This isn't present on UP A9s (since CBAR isn't present). 111c2c35168Smatt */ 112c2c35168Smatt uint32_t mpidr = armreg_mpidr_read(); 113c2c35168Smatt if (mpidr == 0 || (mpidr & MPIDR_U)) 114c2c35168Smatt return 0; 115c2c35168Smatt 116c2c35168Smatt return 1; 117c2c35168Smatt } 118c2c35168Smatt 119c2c35168Smatt static const struct { 120c2c35168Smatt uint8_t rev; 121c2c35168Smatt uint8_t str[7]; 122c2c35168Smatt } pl310_revs[] = { 123c2c35168Smatt { 0, " r0p0" }, 124c2c35168Smatt { 2, " r1p0" }, 125c2c35168Smatt { 4, " r2p0" }, 126c2c35168Smatt { 5, " r3p0" }, 127c2c35168Smatt { 6, " r3p1" }, 128ac390955Smatt { 7, " r3p1a" }, 129c2c35168Smatt { 8, " r3p2" }, 130c2c35168Smatt { 9, " r3p3" }, 131c2c35168Smatt }; 132c2c35168Smatt 133c2c35168Smatt static void 134c2c35168Smatt arml2cc_attach(device_t parent, device_t self, void *aux) 135c2c35168Smatt { 136c2c35168Smatt struct arml2cc_softc * const sc = device_private(self); 137c2c35168Smatt struct mpcore_attach_args * const mpcaa = aux; 13896c39f56Smatt const char * const xname = device_xname(self); 139ac390955Smatt prop_dictionary_t dict = device_properties(self); 140ac390955Smatt uint32_t off; 141ac390955Smatt 142*df5d72efSjmcneill aprint_naive("\n"); 143*df5d72efSjmcneill 144ac390955Smatt if (!prop_dictionary_get_uint32(dict, "offset", &off)) { 145*df5d72efSjmcneill if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { 146*df5d72efSjmcneill /* 147*df5d72efSjmcneill * PL310 on Cortex-A5 is external to PERIPHBASE, so 148*df5d72efSjmcneill * "offset" property is required. 149*df5d72efSjmcneill */ 150*df5d72efSjmcneill aprint_normal(": not configured\n"); 151*df5d72efSjmcneill return; 152*df5d72efSjmcneill } 153ac390955Smatt off = L2CC_BASE; 154ac390955Smatt } 155c2c35168Smatt 15696c39f56Smatt arml2cc_sc = sc; 157c2c35168Smatt sc->sc_dev = self; 158c2c35168Smatt sc->sc_memt = mpcaa->mpcaa_memt; 15996c39f56Smatt sc->sc_waymask = __BIT(arm_scache.dcache_ways) - 1; 16096c39f56Smatt 16196c39f56Smatt evcnt_attach_dynamic(&sc->sc_ev_inv, EVCNT_TYPE_MISC, NULL, 16296c39f56Smatt xname, "L2 inv requests"); 16396c39f56Smatt evcnt_attach_dynamic(&sc->sc_ev_wb, EVCNT_TYPE_MISC, NULL, 16496c39f56Smatt xname, "L2 wb requests"); 16596c39f56Smatt evcnt_attach_dynamic(&sc->sc_ev_wbinv, EVCNT_TYPE_MISC, NULL, 16696c39f56Smatt xname, "L2 wbinv requests"); 16796c39f56Smatt 16896c39f56Smatt mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 169c2c35168Smatt 170c2c35168Smatt bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, 171ac390955Smatt off, L2CC_SIZE, &sc->sc_memh); 172c2c35168Smatt 173c2c35168Smatt uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID); 174c2c35168Smatt u_int rev = __SHIFTOUT(id, CACHE_ID_REV); 175c2c35168Smatt 176c2c35168Smatt const char *revstr = ""; 177c2c35168Smatt for (size_t i = 0; i < __arraycount(pl310_revs); i++) { 178c2c35168Smatt if (rev == pl310_revs[i].rev) { 179c2c35168Smatt revstr = pl310_revs[i].str; 180c2c35168Smatt break; 181c2c35168Smatt } 182c2c35168Smatt } 183c2c35168Smatt 18456f0e3eaSmatt const bool enabled_p = arml2cc_read_4(sc, L2C_CTL) != 0; 18556f0e3eaSmatt 186162b9739Smatt aprint_normal(": ARM PL310%s L2 Cache Controller%s\n", 18756f0e3eaSmatt revstr, enabled_p ? "" : " (disabled)"); 188c2c35168Smatt 18956f0e3eaSmatt if (enabled_p) { 1908aa761beSmatt if (device_cfdata(self)->cf_flags & 1) { 191162b9739Smatt arml2cc_disable(sc); 192162b9739Smatt aprint_normal_dev(self, "cache %s\n", 193162b9739Smatt arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 19496c39f56Smatt sc->sc_enabled = false; 19596c39f56Smatt } else { 19696c39f56Smatt cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 19796c39f56Smatt cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 19896c39f56Smatt cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 19996c39f56Smatt sc->sc_enabled = true; 200c2c35168Smatt } 2018aa761beSmatt } else if ((device_cfdata(self)->cf_flags & 1) == 0) { 20296c39f56Smatt if (!enabled_p) { 20396c39f56Smatt arml2cc_enable(sc); 20496c39f56Smatt aprint_normal_dev(self, "cache %s\n", 20596c39f56Smatt arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 20696c39f56Smatt } 20796c39f56Smatt cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 20896c39f56Smatt cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 20996c39f56Smatt cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 21096c39f56Smatt sc->sc_enabled = true; 2118aa761beSmatt } 212c2c35168Smatt 213b395ced9Smatt KASSERTMSG(arm_pcache.dcache_line_size == arm_scache.dcache_line_size, 214b395ced9Smatt "pcache %u scache %u", 215b395ced9Smatt arm_pcache.dcache_line_size, arm_scache.dcache_line_size); 21656f0e3eaSmatt } 21756f0e3eaSmatt 21896c39f56Smatt static inline void 219445568dcSmatt arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val, 220445568dcSmatt bool wait) 22196c39f56Smatt { 22296c39f56Smatt arml2cc_write_4(sc, off, val); 223445568dcSmatt if (wait) { 22496c39f56Smatt while (arml2cc_read_4(sc, off) & 1) { 22596c39f56Smatt /* spin */ 22696c39f56Smatt } 22796c39f56Smatt } 228445568dcSmatt } 22996c39f56Smatt 23096c39f56Smatt static inline void 23196c39f56Smatt arml2cc_cache_way_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t way_mask) 23296c39f56Smatt { 23396c39f56Smatt arml2cc_write_4(sc, off, way_mask); 23496c39f56Smatt while (arml2cc_read_4(sc, off) & way_mask) { 23596c39f56Smatt /* spin */ 23696c39f56Smatt } 23796c39f56Smatt } 23896c39f56Smatt 23996c39f56Smatt static inline void 24096c39f56Smatt arml2cc_cache_sync(struct arml2cc_softc *sc) 24196c39f56Smatt { 242445568dcSmatt arml2cc_cache_op(sc, L2C_CACHE_SYNC, 0, true); 24396c39f56Smatt } 24496c39f56Smatt 24596c39f56Smatt static inline void 246162b9739Smatt arml2cc_disable(struct arml2cc_softc *sc) 247162b9739Smatt { 24896c39f56Smatt mutex_spin_enter(&sc->sc_lock); 249162b9739Smatt 25096c39f56Smatt arml2cc_cache_way_op(sc, L2C_CLEAN_INV_WAY, sc->sc_waymask); 25196c39f56Smatt arml2cc_cache_sync(sc); 25296c39f56Smatt 25396c39f56Smatt arml2cc_write_4(sc, L2C_CTL, 0); // turn it off 25496c39f56Smatt mutex_spin_exit(&sc->sc_lock); 255162b9739Smatt } 256162b9739Smatt 25796c39f56Smatt static inline void 25896c39f56Smatt arml2cc_enable(struct arml2cc_softc *sc) 25996c39f56Smatt { 26096c39f56Smatt mutex_spin_enter(&sc->sc_lock); 261162b9739Smatt 262aa1c874eSmatt arml2cc_cache_way_op(sc, L2C_INV_WAY, sc->sc_waymask); 26396c39f56Smatt arml2cc_cache_sync(sc); 26496c39f56Smatt 265487f016eSmatt arml2cc_write_4(sc, L2C_CTL, 1); // turn it on 266487f016eSmatt 26796c39f56Smatt mutex_spin_exit(&sc->sc_lock); 268162b9739Smatt } 269162b9739Smatt 270162b9739Smatt void 271162b9739Smatt arml2cc_init(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t o) 272162b9739Smatt { 273162b9739Smatt struct arm_cache_info * const info = &arm_scache; 274162b9739Smatt 275162b9739Smatt uint32_t cfg = bus_space_read_4(bst, bsh, o + L2C_CACHE_TYPE); 276162b9739Smatt 277162b9739Smatt info->cache_type = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE); 278162b9739Smatt info->cache_unified = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) == 0; 279162b9739Smatt u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE); 280162b9739Smatt 281162b9739Smatt u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE); 282162b9739Smatt info->dcache_ways = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC); 283162b9739Smatt info->dcache_line_size = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE); 284162b9739Smatt info->dcache_size = info->dcache_ways * d_waysize; 28567b539efSmatt info->dcache_type = CACHE_TYPE_PIPT; 28667b539efSmatt info->icache_type = CACHE_TYPE_PIPT; 287162b9739Smatt 288162b9739Smatt if (info->cache_unified) { 289162b9739Smatt info->icache_ways = info->dcache_ways; 290162b9739Smatt info->icache_line_size = info->dcache_line_size; 291162b9739Smatt info->icache_size = info->dcache_size; 292162b9739Smatt } else { 293162b9739Smatt u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE); 294162b9739Smatt u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE); 295162b9739Smatt info->icache_ways = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC); 296162b9739Smatt info->icache_line_size = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE); 297162b9739Smatt info->icache_size = i_waysize * info->icache_ways; 298162b9739Smatt } 299c2c35168Smatt } 30056f0e3eaSmatt 30156f0e3eaSmatt static void 30296c39f56Smatt arml2cc_cache_range_op(paddr_t pa, psize_t len, bus_size_t cache_op) 30356f0e3eaSmatt { 30496c39f56Smatt struct arml2cc_softc * const sc = arml2cc_sc; 30596c39f56Smatt const size_t line_size = arm_scache.dcache_line_size; 30656f0e3eaSmatt const size_t line_mask = line_size - 1; 30796c39f56Smatt size_t off = pa & line_mask; 30856f0e3eaSmatt if (off) { 30956f0e3eaSmatt len += off; 31096c39f56Smatt pa -= off; 31156f0e3eaSmatt } 31296c39f56Smatt len = roundup2(len, line_size); 31396c39f56Smatt mutex_spin_enter(&sc->sc_lock); 314ecd33720Smatt if (__predict_false(!sc->sc_enabled)) { 315abeffea0Smatt mutex_spin_exit(&sc->sc_lock); 31696c39f56Smatt return; 317abeffea0Smatt } 318ecd33720Smatt for (const paddr_t endpa = pa + len; pa < endpa; pa += line_size) { 319445568dcSmatt arml2cc_cache_op(sc, cache_op, pa, false); 32096c39f56Smatt } 321ecd33720Smatt arml2cc_cache_sync(sc); 32296c39f56Smatt mutex_spin_exit(&sc->sc_lock); 32356f0e3eaSmatt } 32496c39f56Smatt 32596c39f56Smatt static void 32696c39f56Smatt arml2cc_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t len) 32796c39f56Smatt { 32896c39f56Smatt atomic_inc_64(&arml2cc_sc->sc_ev_inv.ev_count); 32996c39f56Smatt arml2cc_cache_range_op(pa, len, L2C_INV_PA); 33096c39f56Smatt } 33196c39f56Smatt 33296c39f56Smatt static void 33396c39f56Smatt arml2cc_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t len) 33496c39f56Smatt { 33596c39f56Smatt atomic_inc_64(&arml2cc_sc->sc_ev_wb.ev_count); 33696c39f56Smatt arml2cc_cache_range_op(pa, len, L2C_CLEAN_PA); 33796c39f56Smatt } 33896c39f56Smatt 33996c39f56Smatt static void 34096c39f56Smatt arml2cc_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t len) 34196c39f56Smatt { 34296c39f56Smatt atomic_inc_64(&arml2cc_sc->sc_ev_wbinv.ev_count); 34396c39f56Smatt arml2cc_cache_range_op(pa, len, L2C_CLEAN_INV_PA); 34496c39f56Smatt } 345