1 /* $NetBSD: tegra_timer.c,v 1.12 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.12 2021/01/27 03:10:19 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/wdog.h>
39
40 #include <dev/sysmon/sysmonvar.h>
41
42 #include <arm/nvidia/tegra_reg.h>
43 #include <arm/nvidia/tegra_timerreg.h>
44 #include <arm/nvidia/tegra_var.h>
45
46 #include <dev/fdt/fdtvar.h>
47
48 #define TEGRA_TIMER_WDOG_PERIOD_DEFAULT 10
49
50 static int tegra_timer_match(device_t, cfdata_t, void *);
51 static void tegra_timer_attach(device_t, device_t, void *);
52
53 struct tegra_timer_softc {
54 device_t sc_dev;
55 bus_space_tag_t sc_bst;
56 bus_space_handle_t sc_bsh;
57
58 struct sysmon_wdog sc_smw;
59 };
60
61 static int tegra_timer_wdt_setmode(struct sysmon_wdog *);
62 static int tegra_timer_wdt_tickle(struct sysmon_wdog *);
63
64 CFATTACH_DECL_NEW(tegra_timer, sizeof(struct tegra_timer_softc),
65 tegra_timer_match, tegra_timer_attach, NULL, NULL);
66
67 #define TIMER_READ(sc, reg) \
68 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
69 #define TIMER_WRITE(sc, reg, val) \
70 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
71 #define TIMER_SET_CLEAR(sc, reg, set, clr) \
72 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
73
74 static const struct device_compatible_entry compat_data[] = {
75 { .compat = "nvidia,tegra210-timer" },
76 { .compat = "nvidia,tegra124-timer" },
77 { .compat = "nvidia,tegra20-timer" },
78 DEVICE_COMPAT_EOL
79 };
80
81 static int
tegra_timer_match(device_t parent,cfdata_t cf,void * aux)82 tegra_timer_match(device_t parent, cfdata_t cf, void *aux)
83 {
84 struct fdt_attach_args * const faa = aux;
85
86 return of_compatible_match(faa->faa_phandle, compat_data);
87 }
88
89 static void
tegra_timer_attach(device_t parent,device_t self,void * aux)90 tegra_timer_attach(device_t parent, device_t self, void *aux)
91 {
92 struct tegra_timer_softc * const sc = device_private(self);
93 struct fdt_attach_args * const faa = aux;
94 bus_addr_t addr;
95 bus_size_t size;
96 int error;
97
98 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
99 aprint_error(": couldn't get registers\n");
100 return;
101 }
102
103 sc->sc_dev = self;
104 sc->sc_bst = faa->faa_bst;
105 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
106 if (error) {
107 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
108 return;
109 }
110
111 aprint_naive("\n");
112 aprint_normal(": Timers\n");
113
114 sc->sc_smw.smw_name = device_xname(self);
115 sc->sc_smw.smw_cookie = sc;
116 sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode;
117 sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle;
118 sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
119
120 aprint_normal_dev(self,
121 "default watchdog period is %u seconds\n",
122 sc->sc_smw.smw_period);
123
124 if (sysmon_wdog_register(&sc->sc_smw) != 0) {
125 aprint_error_dev(self,
126 "couldn't register with sysmon\n");
127 }
128 }
129
130 static int
tegra_timer_wdt_setmode(struct sysmon_wdog * smw)131 tegra_timer_wdt_setmode(struct sysmon_wdog *smw)
132 {
133 struct tegra_timer_softc * const sc = smw->smw_cookie;
134
135 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
136 TIMER_SET_CLEAR(sc, TMR1_PTV_REG, 0, TMR_PTV_EN);
137 } else {
138 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
139 sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
140 } else if (smw->smw_period == 0 || smw->smw_period > 1000) {
141 return EINVAL;
142 } else {
143 sc->sc_smw.smw_period = smw->smw_period;
144 }
145 u_int tval = (sc->sc_smw.smw_period * 1000000) / 2;
146 TIMER_WRITE(sc, TMR1_PTV_REG,
147 TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL));
148 TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
149 }
150
151 return 0;
152 }
153
154 static int
tegra_timer_wdt_tickle(struct sysmon_wdog * smw)155 tegra_timer_wdt_tickle(struct sysmon_wdog *smw)
156 {
157 struct tegra_timer_softc * const sc = smw->smw_cookie;
158
159 TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
160
161 return 0;
162 }
163
164 void
tegra_timer_delay(u_int us)165 tegra_timer_delay(u_int us)
166 {
167 static bool timerus_configured = false;
168 extern struct bus_space arm_generic_bs_tag;
169 bus_space_tag_t bst = &arm_generic_bs_tag;
170 bus_space_handle_t bsh;
171
172 bus_space_subregion(bst, tegra_ppsb_bsh, TEGRA_TIMER_OFFSET,
173 TEGRA_TIMER_SIZE, &bsh);
174
175 if (__predict_false(timerus_configured == false)) {
176 /* clk_m frequency 12 MHz */
177 bus_space_write_4(bst, bsh, TMRUS_USEC_CFG_REG, 0xb);
178 timerus_configured = true;
179 }
180
181 u_int nus = 0;
182 u_int us_prev = bus_space_read_4(bst, bsh, TMRUS_CNTR_1US_REG);
183
184 while (nus < us) {
185 const u_int us_cur = bus_space_read_4(bst, bsh,
186 TMRUS_CNTR_1US_REG);
187 if (us_cur < us_prev) {
188 nus += (0xffffffff - us_prev) + us_cur;
189 } else {
190 nus += (us_cur - us_prev);
191 }
192 us_prev = us_cur;
193 }
194 }
195