1; $NetBSD: arm.asm,v 1.9 2010/04/06 16:20:28 nonaka Exp $ 2; 3; Copyright (c) 2001 The NetBSD Foundation, Inc. 4; All rights reserved. 5; 6; This code is derived from software contributed to The NetBSD Foundation 7; by UCHIYAMA Yasushi. 8; 9; Redistribution and use in source and binary forms, with or without 10; modification, are permitted provided that the following conditions 11; are met: 12; 1. Redistributions of source code must retain the above copyright 13; notice, this list of conditions and the following disclaimer. 14; 2. Redistributions in binary form must reproduce the above copyright 15; notice, this list of conditions and the following disclaimer in the 16; documentation and/or other materials provided with the distribution. 17; 18; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28; POSSIBILITY OF SUCH DAMAGE. 29; 30 31; 32;armasm.exe $(InputPath) 33;arm.obj 34; 35 ; dummy buffer for WritebackDCache 36 EXPORT |dcachesize| [DATA] 37 EXPORT |dcachebuf| [DATA] 38 AREA |.data|, DATA 39|dcachesize| 40 DCD 8192 ; for SA1100 41|dcachebuf| 42 % 65536 ; max D-cache size 43 44 AREA |.text|, CODE, PIC 45 46 ; 47 ; Operation mode ops. 48 ; 49 EXPORT |SetSVCMode| 50|SetSVCMode| PROC 51 mrs r0, cpsr 52 bic r0, r0, #0x1f 53 orr r0, r0, #0x13 54 msr cpsr, r0 55 mov pc, lr 56 ENDP ; |SetSVCMode| 57 EXPORT |SetSystemMode| 58|SetSystemMode| PROC 59 mrs r0, cpsr 60 orr r0, r0, #0x1f 61 msr cpsr, r0 62 mov pc, lr 63 ENDP ; |SetSystemMode| 64 65 ; 66 ; Interrupt ops. 67 ; 68 EXPORT |DI| 69|DI| PROC 70 mrs r0, cpsr 71 orr r0, r0, #0xc0 72 msr cpsr, r0 73 mov pc, lr 74 ENDP ; |DI| 75 EXPORT |EI| 76|EI| PROC 77 mrs r0, cpsr 78 bic r0, r0, #0xc0 79 msr cpsr, r0 80 mov pc, lr 81 ENDP ; |EI| 82 83 ; 84 ; Cache ops. 85 ; 86 EXPORT |InvalidateICache| 87|InvalidateICache| PROC 88 ; c7 (CRn) Cache Control Register 89 ; c5, 0 (CRm, opcode_2) Flush I 90 ; r0 (Rd) ignored 91 mcr p15, 0, r0, c7, c5, 0 92 mov pc, lr 93 ENDP ; |InvalidateICache| 94 95 EXPORT |WritebackDCache| 96|WritebackDCache| PROC 97 ldr r0, [pc, #24] ; dcachebuf 98 ldr r1, [pc, #24] 99 ldr r1, [r1] ; dcache-size 100 add r1, r1, r0 101|wbdc1| 102 ldr r2, [r0], #32 ; line-size is 32byte. 103 teq r1, r0 104 bne |wbdc1| 105 mov pc, lr 106 DCD |dcachebuf| 107 DCD |dcachesize| 108 ENDP ; |WritebackDCache| 109 110 EXPORT |InvalidateDCache| 111|InvalidateDCache| PROC 112 ; c7 (CRn) Cache Control Register 113 ; c6, 0 (CRm, opcode_2) Flush D 114 ; r0 (Rd) ignored 115 mcr p15, 0, r0, c7, c6, 0 116 mov pc, lr 117 ENDP ; |InvalidateDCache| 118 119 EXPORT |WritebackInvalidateDCache| 120|WritebackInvalidateDCache| PROC 121 ldr r0, [pc, #28] ; dcachebuf 122 ldr r1, [pc, #28] 123 ldr r1, [r1] ; dcache-size 124 add r1, r1, r0 125|wbidc1| 126 ldr r2, [r0], #32 127 teq r1, r0 128 bne |wbidc1| 129 mcr p15, 0, r0, c7, c6, 0 130 mov pc, lr 131 DCD |dcachebuf| 132 DCD |dcachesize| 133 ENDP ; |WritebackInvalidateDCache| 134 135 ; 136 ; WriteBuffer ops 137 ; 138 EXPORT |WritebufferFlush| 139|WritebufferFlush| PROC 140 ; c7 (CRn) Cache Control Register 141 ; c10, 4(CRm, opcode_2) Flush D 142 ; r0 (Rd) ignored 143 mcr p15, 0, r0, c7, c10, 4 144 mov pc, lr 145 ENDP ; |WritebufferFlush| 146 147 ; 148 ; TLB ops. 149 ; 150 EXPORT |FlushIDTLB| 151|FlushIDTLB| PROC 152 mcr p15, 0, r0, c8, c7, 0 153 mov pc, lr 154 ENDP ; |FlushIDTLB| 155 156 EXPORT |FlushITLB| 157|FlushITLB| PROC 158 mcr p15, 0, r0, c8, c5, 0 159 mov pc, lr 160 ENDP ; |FlushITLB| 161 162 EXPORT |FlushDTLB| 163|FlushDTLB| PROC 164 mcr p15, 0, r0, c8, c6, 0 165 mov pc, lr 166 ENDP ; |FlushITLB| 167 168 EXPORT |FlushDTLBS| 169|FlushDTLBS| PROC 170 mcr p15, 0, r0, c8, c6, 1 171 mov pc, lr 172 ENDP ; |FlushITLBS| 173 174 ; 175 ; CurrentProgramStatusRegister access. 176 ; 177 EXPORT |GetCPSR| 178|GetCPSR| PROC 179 mrs r0, cpsr 180 mov pc, lr 181 ENDP ; |GetCPSR| 182 183 EXPORT |SetCPSR| 184|SetCPSR| PROC 185 msr cpsr, r0 186 mov pc, lr 187 ENDP ; |SetCPSR| 188 189 ; 190 ; SA-1100 Coprocessor15 access. 191 ; 192; Reg0 ID (R) 193 EXPORT |GetCop15Reg0| 194|GetCop15Reg0| PROC 195 mrc p15, 0, r0, c0, c0, 0 196 ; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping) 197 mov pc, lr 198 ENDP ; |GetCop15Reg0| 199 200; Reg1 Control (R/W) 201 EXPORT |GetCop15Reg1| 202|GetCop15Reg1| PROC 203 mrc p15, 0, r0, c1, c0, 0 204 ; 0xc007327f (||...........|||..||..|..|||||||) 205 ; 0 (1)MMU enabled 206 ; 1 (1)Address fault enabled 207 ; 2 (1)D-cache enabled 208 ; 3 (1)Write-buffer enabled 209 ; 7 (0)little-endian 210 ; 8 (0)MMU protection (System) 211 ; 9 (1)MMU protection (ROM) 212 ; 12 (1)I-cache enabled 213 ; 13 (1)Base address of interrupt vector is 0xffff0000 214 mov pc, lr 215 ENDP ; |GetCop15Reg1| 216 EXPORT |SetCop15Reg1| 217|SetCop15Reg1| PROC 218 mcr p15, 0, r0, c1, c0, 0 219 nop 220 nop 221 nop 222 mov pc, lr 223 ENDP ; |SetCop15Reg1| 224 225; Reg2 Translation table base (R/W) 226 EXPORT |GetCop15Reg2| 227|GetCop15Reg2| PROC 228 mrc p15, 0, r0, c2, c0, 0 229 mov pc, lr 230 ENDP ; |GetCop15Reg2| 231 EXPORT |SetCop15Reg2| 232|SetCop15Reg2| PROC 233 mcr p15, 0, r0, c2, c0, 0 234 mov pc, lr 235 ENDP ; |SetCop15Reg2| 236 237; Reg3 Domain access control (R/W) 238 EXPORT |GetCop15Reg3| 239|GetCop15Reg3| PROC 240 mrc p15, 0, r0, c3, c0, 0 241 mov pc, lr 242 ENDP ; |GetCop15Reg3| 243 EXPORT |SetCop15Reg3| 244|SetCop15Reg3| PROC 245 mcr p15, 0, r0, c3, c0, 0 246 mov pc, lr 247 ENDP ; |SetCop15Reg3| 248 249; Reg5 Fault status (R/W) 250 EXPORT |GetCop15Reg5| 251|GetCop15Reg5| PROC 252 mrc p15, 0, r0, c5, c0, 0 253 mov pc, lr 254 ENDP ; |GetCop15Reg5| 255 256; Reg6 Fault address (R/W) 257 EXPORT |GetCop15Reg6| 258|GetCop15Reg6| PROC 259 mrc p15, 0, r0, c6, c0, 0 260 mov pc, lr 261 ENDP ; |GetCop15Reg6| 262 263; Reg7 Cache operations (W) 264 ; -> Cache ops 265; Reg8 TLB operations (Flush) (W) 266 ; -> TLB ops 267; Reg9 Read buffer operations (W) 268; Reg13 Process ID (R/W) 269 EXPORT |GetCop15Reg13| 270|GetCop15Reg13| PROC 271 mrc p15, 0, r0, c13, c0, 0 272 mov pc, lr 273 ENDP ; |GetCop15Reg13| 274 EXPORT |SetCop15Reg13| 275|SetCop15Reg13| PROC 276 mcr p15, 0, r0, c13, c0, 0 277 mov pc, lr 278 ENDP ; |SetCop15Reg13| 279 280; Reg14 Breakpoint (R/W) 281 EXPORT |GetCop15Reg14| 282|GetCop15Reg14| PROC 283 mrc p15, 0, r0, c14, c0, 0 284 mov pc, lr 285 ENDP ; |GetCop15Reg14| 286; Reg15 Test, clock, and idle (W) 287 288 END 289