1; $NetBSD: arm.asm,v 1.3 2001/07/17 01:43:42 toshii Exp $ 2; 3; Copyright (c) 2001 The NetBSD Foundation, Inc. 4; All rights reserved. 5; 6; This code is derived from software contributed to The NetBSD Foundation 7; by UCHIYAMA Yasushi. 8; 9; Redistribution and use in source and binary forms, with or without 10; modification, are permitted provided that the following conditions 11; are met: 12; 1. Redistributions of source code must retain the above copyright 13; notice, this list of conditions and the following disclaimer. 14; 2. Redistributions in binary form must reproduce the above copyright 15; notice, this list of conditions and the following disclaimer in the 16; documentation and/or other materials provided with the distribution. 17; 3. All advertising materials mentioning features or use of this software 18; must display the following acknowledgement: 19; This product includes software developed by the NetBSD 20; Foundation, Inc. and its contributors. 21; 4. Neither the name of The NetBSD Foundation nor the names of its 22; contributors may be used to endorse or promote products derived 23; from this software without specific prior written permission. 24; 25; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35; POSSIBILITY OF SUCH DAMAGE. 36; 37 38; 39;armasm.exe $(InputPath) 40;arm.obj 41; 42 ; dummy buffer for WritebackDCache 43 EXPORT |dcachebuf| [DATA] 44 AREA |.data|, DATA 45|dcachebuf| 46 % 8192 ; D-cache size 47 48 AREA |.text|, CODE, PIC 49 50 ; 51 ; Operation mode ops. 52 ; 53 EXPORT |SetSVCMode| 54|SetSVCMode| PROC 55 mrs r0, cpsr 56 bic r0, r0, #0x1f 57 orr r0, r0, #0x13 58 msr cpsr, r0 59 mov pc, lr 60 ENDP ; |SetSVCMode| 61 EXPORT |SetSystemMode| 62|SetSystemMode| PROC 63 mrs r0, cpsr 64 orr r0, r0, #0x1f 65 msr cpsr, r0 66 mov pc, lr 67 ENDP ; |SetSystemMode| 68 69 ; 70 ; Interrupt ops. 71 ; 72 EXPORT |DI| 73|DI| PROC 74 mrs r0, cpsr 75 orr r0, r0, #0xc0 76 msr cpsr, r0 77 mov pc, lr 78 ENDP ; |DI| 79 EXPORT |EI| 80|EI| PROC 81 mrs r0, cpsr 82 bic r0, r0, #0xc0 83 msr cpsr, r0 84 mov pc, lr 85 ENDP ; |EI| 86 87 ; 88 ; Cache ops. 89 ; 90 EXPORT |InvalidateICache| 91|InvalidateICache| PROC 92 ; c7 (CRn) Cache Control Register 93 ; c5, 0 (CRm, opcode_2) Flush I 94 ; r0 (Rd) ignored 95 mcr p15, 0, r0, c7, c5, 0 96 mov pc, lr 97 ENDP ; |InvalidateICache| 98 99 EXPORT |WritebackDCache| 100|WritebackDCache| PROC 101 ldr r0, [pc, #16] ; dcachebuf 102 add r1, r0, #8192 ; cache-size is 8Kbyte. 103|wbdc1| 104 ldr r2, [r0], #32 ; line-size is 32byte. 105 teq r1, r0 106 bne |wbdc1| 107 mov pc, lr 108 DCD |dcachebuf| 109 ENDP ; |WritebackDCache| 110 111 EXPORT |InvalidateDCache| 112|InvalidateDCache| PROC 113 ; c7 (CRn) Cache Control Register 114 ; c6, 0 (CRm, opcode_2) Flush D 115 ; r0 (Rd) ignored 116 mcr p15, 0, r0, c7, c6, 0 117 mov pc, lr 118 ENDP ; |InvalidateDCache| 119 120 EXPORT |WritebackInvalidateDCache| 121|WritebackInvalidateDCache| PROC 122 ldr r0, [pc, #20] ; dcachebuf 123 add r1, r0, #8192 124|wbidc1| 125 ldr r2, [r0], #32 126 teq r1, r0 127 bne |wbidc1| 128 mcr p15, 0, r0, c7, c6, 0 129 mov pc, lr 130 DCD |dcachebuf| 131 ENDP ; |WritebackInvalidateDCache| 132 133 ; 134 ; WriteBuffer ops 135 ; 136 EXPORT |WritebufferFlush| 137|WritebufferFlush| PROC 138 ; c7 (CRn) Cache Control Register 139 ; c10, 4(CRm, opcode_2) Flush D 140 ; r0 (Rd) ignored 141 mcr p15, 0, r0, c7, c10, 4 142 mov pc, lr 143 ENDP ; |WritebufferFlush| 144 145 ; 146 ; TLB ops. 147 ; 148 EXPORT |FlushIDTLB| 149|FlushIDTLB| PROC 150 mcr p15, 0, r0, c8, c7, 0 151 mov pc, lr 152 ENDP ; |FlushIDTLB| 153 154 EXPORT |FlushITLB| 155|FlushITLB| PROC 156 mcr p15, 0, r0, c8, c5, 0 157 mov pc, lr 158 ENDP ; |FlushITLB| 159 160 EXPORT |FlushDTLB| 161|FlushDTLB| PROC 162 mcr p15, 0, r0, c8, c6, 0 163 mov pc, lr 164 ENDP ; |FlushITLB| 165 166 EXPORT |FlushDTLBS| 167|FlushDTLBS| PROC 168 mcr p15, 0, r0, c8, c6, 1 169 mov pc, lr 170 ENDP ; |FlushITLBS| 171 172 ; 173 ; CurrentProgramStatusRegister access. 174 ; 175 EXPORT |GetCPSR| 176|GetCPSR| PROC 177 mrs r0, cpsr 178 mov pc, lr 179 ENDP ; |GetCPSR| 180 181 EXPORT |SetCPSR| 182|SetCPSR| PROC 183 msr cpsr, r0 184 mov pc, lr 185 ENDP ; |SetCPSR| 186 187 ; 188 ; SA-1100 Coprocessor15 access. 189 ; 190; Reg0 ID (R) 191 EXPORT |GetCop15Reg0| 192|GetCop15Reg0| PROC 193 mrc p15, 0, r0, c0, c0, 0 194 ; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping) 195 mov pc, lr 196 ENDP ; |GetCop15Reg0| 197 198; Reg1 Control (R/W) 199 EXPORT |GetCop15Reg1| 200|GetCop15Reg1| PROC 201 mrc p15, 0, r0, c1, c0, 0 202 ; 0xc007327f (||...........|||..||..|..|||||||) 203 ; 0 (1)MMU enabled 204 ; 1 (1)Address fault enabled 205 ; 2 (1)D-cache enabled 206 ; 3 (1)Write-buffer enabled 207 ; 7 (0)little-endian 208 ; 8 (0)MMU protection (System) 209 ; 9 (1)MMU protection (ROM) 210 ; 12 (1)I-cache enabled 211 ; 13 (1)Base address of interrupt vector is 0xffff0000 212 mov pc, lr 213 ENDP ; |GetCop15Reg1| 214 EXPORT |SetCop15Reg1| 215|SetCop15Reg1| PROC 216 mcr p15, 0, r0, c1, c0, 0 217 nop 218 nop 219 nop 220 mov pc, lr 221 ENDP ; |SetCop15Reg1| 222 223; Reg2 Translation table base (R/W) 224 EXPORT |GetCop15Reg2| 225|GetCop15Reg2| PROC 226 mrc p15, 0, r0, c2, c0, 0 227 mov pc, lr 228 ENDP ; |GetCop15Reg2| 229 EXPORT |SetCop15Reg2| 230|SetCop15Reg2| PROC 231 mcr p15, 0, r0, c2, c0, 0 232 mov pc, lr 233 ENDP ; |SetCop15Reg2| 234 235; Reg3 Domain access control (R/W) 236 EXPORT |GetCop15Reg3| 237|GetCop15Reg3| PROC 238 mrc p15, 0, r0, c3, c0, 0 239 mov pc, lr 240 ENDP ; |GetCop15Reg3| 241 EXPORT |SetCop15Reg3| 242|SetCop15Reg3| PROC 243 mcr p15, 0, r0, c3, c0, 0 244 mov pc, lr 245 ENDP ; |SetCop15Reg3| 246 247; Reg5 Fault status (R/W) 248 EXPORT |GetCop15Reg5| 249|GetCop15Reg5| PROC 250 mrc p15, 0, r0, c5, c0, 0 251 mov pc, lr 252 ENDP ; |GetCop15Reg5| 253 254; Reg6 Fault address (R/W) 255 EXPORT |GetCop15Reg6| 256|GetCop15Reg6| PROC 257 mrc p15, 0, r0, c6, c0, 0 258 mov pc, lr 259 ENDP ; |GetCop15Reg6| 260 261; Reg7 Cache operations (W) 262 ; -> Cache ops 263; Reg8 TLB operations (Flush) (W) 264 ; -> TLB ops 265; Reg9 Read buffer operations (W) 266; Reg13 Process ID (R/W) 267 EXPORT |GetCop15Reg13| 268|GetCop15Reg13| PROC 269 mrc p15, 0, r0, c13, c0, 0 270 mov pc, lr 271 ENDP ; |GetCop15Reg13| 272 EXPORT |SetCop15Reg13| 273|SetCop15Reg13| PROC 274 mcr p15, 0, r0, c13, c0, 0 275 mov pc, lr 276 ENDP ; |SetCop15Reg13| 277 278; Reg14 Breakpoint (R/W) 279 EXPORT |GetCop15Reg14| 280|GetCop15Reg14| PROC 281 mrc p15, 0, r0, c14, c0, 0 282 mov pc, lr 283 ENDP ; |GetCop15Reg14| 284; Reg15 Test, clock, and idle (W) 285 286 ; FlatJump (kaddr_t bootinfo, kaddr_t pvec, kaddr_t stack 287 ; kaddr_t jump) 288 ; bootinfo boot information block address. 289 ; pvec page vector of kernel. 290 ; stack physical address of stack 291 ; jump physical address of boot function 292 ; *** MMU and pipeline behavier are SA-1100 specific. *** 293 EXPORT |FlatJump| 294|FlatJump| PROC 295 ; disable interrupt 296 mrs r4, cpsr 297 orr r4, r4, #0xc0 298 msr cpsr, r4 299 ; disable MMU, I/D-Cache, Writebuffer. 300 ; interrupt vector address is 0xffff0000 301 ; 32bit exception handler/address range. 302 ldr r4, [pc, #24] 303 ; Disable WB/Cache/MMU 304 mcr p15, 0, r4, c1, c0, 0 305 ; Invalidate I/D-cache. 306 mcr p15, 0, r4, c7, c7, 0 ; Fetch translated fetch 307 ; Invalidate TLB entries. 308 mcr p15, 0, r4, c8, c7, 0 ; Fetch translated decode 309 ; jump to kernel entry physical address. 310 mov pc, r3 ; Fetch translated execute 311 ; NOTREACHED 312 nop ; Fetch nontranslated cache access 313 nop ; Fetch nontranslated writeback 314 mov pc, lr ; Fetch nontranslated 315 DCD 0x00002030 316 ENDP ; |FlatJump| 317; 318; UART test 319; 320 ; boot_func (u_int32_t mapaddr, u_int32_t bootinfo, u_int32_t flags) 321 ; 322 EXPORT |boot_func| 323|boot_func| PROC 324 nop ; Cop15 hazard 325 nop ; Cop15 hazard 326 nop ; Cop15 hazard 327 mov sp, r2 ; set bootloader stack 328; mov r4, r0 329; mov r5, r1 330; bl colorbar 331; mov r0, r4 332; mov r1, r5 333 bl boot 334 nop ; NOTREACHED 335 nop 336 ENDP ; |boot_func| 337 338 EXPORT |colorbar| 339|colorbar| PROC 340 stmea sp!, {r4-r7, lr} 341 adr r4, |$FBADDR| 342 ldr r4, [r4] 343 344 mov r7, #8 345 add r0, r0, r7 346|color_loop| 347 mov r6, r0 348 and r6, r6, #7 349 orr r6, r6, r6, LSL #8 350 orr r6, r6, r6, LSL #16 351 add r5, r4, #0x9600 352|fb_loop| 353 str r6, [r4], #4 354 cmp r4, r5 355 blt |fb_loop| 356 357 subs r7, r7, #1 358 bne |color_loop| 359 360 ldmea sp!, {r4-r7, pc} 361|$FBADDR| 362 DCD 0xc0003000 ; use WindowsCE default. 363 ENDP ; |colorbar| 364 365 EXPORT |boot| 366|boot| PROC 367; 368; UART test code 369; 370; ; print boot_info address (r0) and page_vector start address (r1). 371; mov r4, r0 372; mov r5, r1 373; mov r0, #'I' 374; bl btputc 375; mov r0, r4 376; bl hexdump 377; mov r0, #'P' 378; bl btputc 379; mov r0, r5 380; bl hexdump 381; mov r7, r4 382; mov r2, r5 ; start 383 384 mov r7, r0 ; if enabled above debug print, remove this. 385 mov r2, r1 ; if enabled above debug print, remove this. 386|page_loop| 387 mvn r0, #0 ; ~0 388 cmp r2, r0 389 beq |page_end| ; if (next == ~0) goto page_end 390 391 mov r1, r2 ; p = next 392 ldr r2, [r1] ; next 393 ldr r3, [r1, #4] ; src 394 ldr r4, [r1, #8] ; dst 395 ldr r5, [r1, #12] ; sz 396 397 cmp r3, r0 398 add r6, r4, r5 ; end address 399 bne |page_memcpy4| ; if (src != ~0) goto page_memcpy4 400 401 mov r0, #0 402|page_memset| ; memset (dst, 0, sz) uncached. 403 str r0, [r4], #4 404 cmp r4, r6 405 blt |page_memset| 406 b |page_loop| 407 408|page_memcpy4| ; memcpy (dst, src, sz) uncached. 409 ldr r0, [r3], #4 410 ldr r5, [r3], #4 411 str r0, [r4], #4 412 cmp r4, r6 413 strlt r5, [r4], #4 414 cmplt r4, r6 415 blt |page_memcpy4| 416 417 b |page_loop| 418|page_end| 419 ; 420 ; jump to kernel 421 ; 422; mov r0, #'E' 423; bl btputc 424; ldr r0, [r7] 425; bl hexdump 426; ldr r0, [r7] 427; ldr r0, [r0] 428; bl hexdump 429 430 ; set stack pointer 431 mov r5, #4096 432 add r6, r6, #8192 433 sub r5, r5, #1 434 bic sp, r6, r5 435 436 ; set bootargs 437 ldr r4, [r7] 438 ldr r0, [r7, #4] 439 ldr r1, [r7, #8] 440 ldr r2, [r7, #12] 441 mov pc, r4 442 ; NOTREACHED 443 444|infinite_loop| 445 nop 446 nop 447 nop 448 nop 449 nop 450 b |infinite_loop| 451 ENDP ; |boot| 452 453|btputc| PROC 454 adr r1, |$UARTTXBSY| 455 ldr r1, [r1] 456|btputc_busy| 457 ldr r2, [r1] 458 and r2, r2, #1 459 cmp r2, #1 460 beq |btputc_busy| 461 adr r1, |$UARTTXADR| 462 ldr r1, [r1] 463 str r0, [r1] 464 mov pc, lr 465 ENDP ;|btputc| 466 467|hexdump| PROC 468 stmea sp!, {r4-r5, lr} 469 mov r4, r0 470 mov r0, #0x30 471 bl btputc 472 mov r0, #0x78 473 bl btputc 474 mov r0, r4 475 ; Transmit register address 476 adr r1, |$UARTTXADR| 477 ldr r1, [r1] 478 ; Transmit busy register address 479 adr r2, |$UARTTXBSY| 480 ldr r2, [r2] 481 mov r5, #8 482|hex_loop| 483 mov r3, r0, LSR #28 484 cmp r3, #9 485 addgt r3, r3, #0x41 - 10 486 addle r3, r3, #0x30 487|hex_busyloop| 488 ldr r4, [r2] 489 and r4, r4, #1 490 cmp r4, #1 491 beq |hex_busyloop| 492 str r3, [r1] 493 mov r0, r0, LSL #4 494 subs r5, r5, #1 495 bne |hex_loop| 496 mov r0, #0x0d 497 bl btputc 498 mov r0, #0x0a 499 bl btputc 500 ldmea sp!, {r4-r5, pc} 501 ENDP ;|hexdump| 502 503|$UARTTXADR| 504 DCD 0x80050014 505|$UARTTXBSY| 506 DCD 0x80050020 507 508 EXPORT |boot_func_end| [ DATA ] 509|boot_func_end| DCD 0x0 510 511 END 512