1 /* $NetBSD: cpu.c,v 1.16 2011/06/29 06:13:09 matt Exp $ */
2
3 /*-
4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by NONAKA Kimihiro; by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.16 2011/06/29 06:13:09 matt Exp $");
34
35 #include "opt_ppcparam.h"
36 #include "opt_multiprocessor.h"
37 #include "opt_interrupt.h"
38 #include "opt_altivec.h"
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/device.h>
43
44 #include <dev/ofw/openfirm.h>
45
46 #include <powerpc/openpic.h>
47 #include <powerpc/spr.h>
48 #include <powerpc/oea/spr.h>
49 #include <powerpc/oea/hid.h>
50 #include <powerpc/oea/bat.h>
51 #ifdef ALTIVEC
52 #include <powerpc/altivec.h>
53 #endif
54
55 #ifdef MULTIPROCESSOR
56 #include <arch/powerpc/pic/picvar.h>
57 #include <arch/powerpc/pic/ipivar.h>
58 #include <powerpc/rtas.h>
59 #endif
60
61 #include <machine/autoconf.h>
62 #include <machine/cpu.h>
63 #include <machine/fpu.h>
64 #include <machine/pcb.h>
65 #include <machine/pio.h>
66 #include <machine/trap.h>
67
68 #include "pic_openpic.h"
69
70 #ifndef OPENPIC
71 #if NPIC_OPENPIC > 0
72 #define OPENPIC
73 #endif /* NOPENPIC > 0 */
74 #endif /* OPENPIC */
75
76 static int cpu_match(device_t, cfdata_t, void *);
77 static void cpu_attach(device_t, device_t, void *);
78 void cpu_OFgetspeed(device_t, struct cpu_info *);
79
80 CFATTACH_DECL_NEW(cpu, 0,
81 cpu_match, cpu_attach, NULL, NULL);
82
83 extern struct cfdriver cpu_cd;
84 extern int machine_has_rtas;
85
86 int
cpu_match(device_t parent,cfdata_t cfdata,void * aux)87 cpu_match(device_t parent, cfdata_t cfdata, void *aux)
88 {
89 struct confargs *ca = aux;
90 int *reg = ca->ca_reg;
91 int node;
92
93 if (strcmp(ca->ca_name, cpu_cd.cd_name) != 0)
94 return 0;
95
96 node = OF_finddevice("/cpus");
97 if (node != -1) {
98 for (node = OF_child(node); node != 0; node = OF_peer(node)) {
99 uint32_t cpunum;
100 int l;
101
102 l = OF_getprop(node, "reg", &cpunum, sizeof(cpunum));
103 if (l == 4 && reg[0] == cpunum)
104 return 1;
105 }
106 }
107 if (reg[0] == 0)
108 return 1;
109 return 0;
110 }
111
112 void
cpu_OFgetspeed(device_t self,struct cpu_info * ci)113 cpu_OFgetspeed(device_t self, struct cpu_info *ci)
114 {
115 int node;
116 node = OF_finddevice("/cpus");
117 if (node != -1) {
118 for (node = OF_child(node); node; node = OF_peer(node)) {
119 uint32_t cpunum;
120 int l;
121
122 l = OF_getprop(node, "reg", &cpunum, sizeof(cpunum));
123 if (l == sizeof(uint32_t) && ci->ci_cpuid == cpunum) {
124 uint32_t cf;
125
126 l = OF_getprop(node, "clock-frequency",
127 &cf, sizeof(cf));
128 if (l == sizeof(uint32_t))
129 ci->ci_khz = cf / 1000;
130 break;
131 }
132 }
133 }
134 if (ci->ci_khz)
135 aprint_normal_dev(self, "%u.%02u MHz\n",
136 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100);
137 }
138
139 static void
cpu_print_cache_config(uint32_t size,uint32_t line)140 cpu_print_cache_config(uint32_t size, uint32_t line)
141 {
142 char cbuf[7];
143
144 format_bytes(cbuf, sizeof(cbuf), size);
145 aprint_normal("%s %dB/line", cbuf, line);
146 }
147
148 static void
cpu_OFprintcacheinfo(int node)149 cpu_OFprintcacheinfo(int node)
150 {
151 int l;
152 uint32_t dcache=0, icache=0, dline=0, iline=0;
153
154 OF_getprop(node, "i-cache-size", &icache, sizeof(icache));
155 OF_getprop(node, "d-cache-size", &dcache, sizeof(dcache));
156 OF_getprop(node, "i-cache-line-size", &iline, sizeof(iline));
157 OF_getprop(node, "d-cache-line-size", &dline, sizeof(dline));
158 if (OF_getprop(node, "cache-unified", &l, sizeof(l)) != -1) {
159 aprint_normal("cache ");
160 cpu_print_cache_config(icache, iline);
161 } else {
162 aprint_normal("I-cache ");
163 cpu_print_cache_config(icache, iline);
164 aprint_normal(", D-cache ");
165 cpu_print_cache_config(dcache, dline);
166 }
167 aprint_normal("\n");
168 }
169
170 static void
cpu_OFgetcache(device_t self,struct cpu_info * ci)171 cpu_OFgetcache(device_t self, struct cpu_info *ci)
172 {
173 int node, cpu=-1;
174 char name[32];
175
176 node = OF_finddevice("/cpus");
177 if (node == -1)
178 return;
179
180 for (node = OF_child(node); node; node = OF_peer(node)) {
181 uint32_t cpunum;
182 int l;
183
184 l = OF_getprop(node, "reg", &cpunum, sizeof(cpunum));
185 if (l == sizeof(uint32_t) && ci->ci_cpuid == cpunum) {
186 cpu = node;
187 break;
188 }
189 }
190 if (cpu == -1)
191 return;
192 /* now we have cpu */
193 aprint_normal_dev(self, "L1 ");
194 cpu_OFprintcacheinfo(cpu);
195 for (node = OF_child(cpu); node; node = OF_peer(node)) {
196 if (OF_getprop(node, "name", name, sizeof(name)) != -1) {
197 if (strcmp("l2-cache", name) == 0) {
198 aprint_normal_dev(self, "L2 ");
199 cpu_OFprintcacheinfo(node);
200 } else if (strcmp("l3-cache", name) == 0) {
201 aprint_normal_dev(self, "L3 ");
202 cpu_OFprintcacheinfo(node);
203 }
204 }
205 }
206 }
207
208
209 void
cpu_attach(device_t parent,device_t self,void * aux)210 cpu_attach(device_t parent, device_t self, void *aux)
211 {
212 struct cpu_info *ci;
213 struct confargs *ca = aux;
214 int id = ca->ca_reg[0];
215
216 ci = cpu_attach_common(self, id);
217 if (ci == NULL)
218 return;
219
220 if (id > 0)
221 #ifdef MULTIPROCESSOR
222 cpu_spinup(self, ci);
223 #endif
224
225 if (ci->ci_khz == 0)
226 cpu_OFgetspeed(self, ci);
227
228 cpu_OFgetcache(self, ci);
229 return;
230 }
231
232 #ifdef MULTIPROCESSOR
233
234 extern volatile u_int cpu_spinstart_cpunum;
235 extern volatile u_int cpu_spinstart_ack;
236
237 int
md_setup_trampoline(volatile struct cpu_hatch_data * h,struct cpu_info * ci)238 md_setup_trampoline(volatile struct cpu_hatch_data *h, struct cpu_info *ci)
239 {
240 int i;
241 u_int msr;
242
243 msr = mfmsr();
244 h->hatch_running = -1;
245 cpu_spinstart_cpunum = ci->ci_cpuid;
246 __asm volatile("dcbf 0,%0"::"r"(&cpu_spinstart_cpunum):"memory");
247
248 for (i=0; i < 100000000; i++)
249 if (cpu_spinstart_ack == 0)
250 break;
251 return 1;
252 }
253
254 void
md_presync_timebase(volatile struct cpu_hatch_data * h)255 md_presync_timebase(volatile struct cpu_hatch_data *h)
256 {
257 uint64_t tb;
258 int junk;
259
260 if (machine_has_rtas && rtas_has_func(RTAS_FUNC_FREEZE_TIME_BASE)) {
261 rtas_call(RTAS_FUNC_FREEZE_TIME_BASE, 0, 1, &junk);
262 /* Sync timebase. */
263 tb = mftb();
264
265 h->hatch_tbu = tb >> 32;
266 h->hatch_tbl = tb & 0xffffffff;
267
268 h->hatch_running = 0;
269 }
270 /* otherwise, the machine has no rtas, or if it does, things
271 * are pre-syncd, per PAPR v2.2. I don't have anything without
272 * rtas, so if such a machine exists, someone will have to write
273 * code for it
274 */
275 }
276
277 void
md_start_timebase(volatile struct cpu_hatch_data * h)278 md_start_timebase(volatile struct cpu_hatch_data *h)
279 {
280 int i, junk;
281 /*
282 * wait for secondary spin up (1.5ms @ 604/200MHz)
283 * XXX we cannot use delay() here because timebase is not
284 * running.
285 */
286 for (i = 0; i < 100000; i++)
287 if (h->hatch_running)
288 break;
289
290 /* Start timebase. */
291 if (machine_has_rtas && rtas_has_func(RTAS_FUNC_THAW_TIME_BASE))
292 rtas_call(RTAS_FUNC_THAW_TIME_BASE, 0, 1, &junk);
293 }
294
295 /*
296 * We wait for h->hatch_running to become 0, and then we know that the time is
297 * frozen and h->hatch_tb is correct.
298 */
299
300 void
md_sync_timebase(volatile struct cpu_hatch_data * h)301 md_sync_timebase(volatile struct cpu_hatch_data *h)
302 {
303 /* Sync timebase. */
304 u_int tbu = h->hatch_tbu;
305 u_int tbl = h->hatch_tbl;
306 while (h->hatch_running == -1)
307 ;
308 __asm volatile ("sync; isync");
309 __asm volatile ("mttbl %0" :: "r"(0));
310 __asm volatile ("mttbu %0" :: "r"(tbu));
311 __asm volatile ("mttbl %0" :: "r"(tbl));
312 }
313
314 void
md_setup_interrupts(void)315 md_setup_interrupts(void)
316 {
317 /* do nothing, this is handled in ofwpci */
318 }
319 #endif /* MULTIPROCESSOR */
320