1 /* $NetBSD: ibm405gp.c,v 1.8 2016/10/19 00:08:42 nonaka Exp $ */
2
3 /*
4 * Copyright 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: ibm405gp.c,v 1.8 2016/10/19 00:08:42 nonaka Exp $");
40
41 #include <sys/param.h>
42 #include <sys/device.h>
43 #include <sys/systm.h>
44 #include <sys/extent.h>
45 #include <sys/bus.h>
46
47 #include <dev/pci/pcivar.h>
48
49 #include <powerpc/ibm4xx/ibm405gp.h>
50 #include <powerpc/ibm4xx/pci_machdep.h>
51 #include <powerpc/ibm4xx/dev/pcicreg.h>
52
53 static struct powerpc_bus_space pcicfg_tag = {
54 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
55 IBM405GP_PCIL0_BASE, 0x0, 0x40
56 };
57 static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(1)]
58 __attribute__((aligned(8)));
59 static bus_space_tag_t pcicfg_iot = &pcicfg_tag;
60 static bus_space_handle_t pcicfg_ioh = 0;
61
62 #define PCI0_MEM_BASE 0x80000000
63
64 static struct genppc_pci_chipset genppc_ibm4xx_chipset = {
65 .pc_conf_v = NULL,
66 .pc_attach_hook = ibm4xx_pci_attach_hook,
67 .pc_bus_maxdevs = ibm4xx_pci_bus_maxdevs,
68 .pc_make_tag = ibm4xx_pci_make_tag,
69 .pc_conf_read = ibm4xx_pci_conf_read,
70 .pc_conf_write = ibm4xx_pci_conf_write,
71
72 .pc_intr_v = &genppc_ibm4xx_chipset,
73 .pc_intr_map = genppc_pci_intr_map,
74 .pc_intr_string = genppc_pci_intr_string,
75 .pc_intr_evcnt = genppc_pci_intr_evcnt,
76 .pc_intr_establish = genppc_pci_intr_establish,
77 .pc_intr_disestablish = genppc_pci_intr_disestablish,
78 .pc_intr_setattr = ibm4xx_pci_intr_setattr,
79 .pc_intr_type = genppc_pci_intr_type,
80 .pc_intr_alloc = genppc_pci_intr_alloc,
81 .pc_intr_release = genppc_pci_intr_release,
82 .pc_intx_alloc = genppc_pci_intx_alloc,
83
84 .pc_msi_v = &genppc_ibm4xx_chipset,
85 GENPPC_PCI_MSI_INITIALIZER,
86
87 .pc_msix_v = &genppc_ibm4xx_chipset,
88 GENPPC_PCI_MSIX_INITIALIZER,
89
90 .pc_conf_interrupt = ibm4xx_pci_conf_interrupt,
91 .pc_decompose_tag = ibm4xx_pci_decompose_tag,
92 .pc_conf_hook = ibm4xx_pci_conf_hook,
93 };
94
95 pci_chipset_tag_t
ibm4xx_get_pci_chipset_tag(void)96 ibm4xx_get_pci_chipset_tag(void)
97 {
98 return &genppc_ibm4xx_chipset;
99 }
100
101 static void
setup_pcicfg_window(void)102 setup_pcicfg_window(void)
103 {
104 if (pcicfg_ioh)
105 return;
106 if (bus_space_init(&pcicfg_tag,
107 "pcicfg", ex_storage, sizeof(ex_storage)) ||
108 bus_space_map(pcicfg_iot, 0, 0x40 , 0, &pcicfg_ioh))
109 panic("Cannot map PCI configuration registers");
110 }
111
112 /*
113 * Setup proper Local<->PCI mapping
114 * PCI memory window: 256M @ PCI0MEMBASE with direct memory translation
115 */
116 void
ibm4xx_setup_pci(void)117 ibm4xx_setup_pci(void)
118 {
119 pci_chipset_tag_t pc = &genppc_ibm4xx_chipset;
120 pcitag_t tag;
121
122 setup_pcicfg_window();
123
124 /* Disable all three memory mappers */
125 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0x00000000); /* disabled */
126 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA, 0x00000000); /* disabled */
127 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA, 0x00000000); /* disabled */
128 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0x00000000); /* Can't really disable PTM1. */
129 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS, 0x00000000); /* disabled */
130
131
132 /* Setup memory map #0 */
133 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
134
135 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA, PCI0_MEM_BASE);
136 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA, PCI0_MEM_BASE);
137 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA, 0);
138
139 /* Configure PCI bridge */
140 tag = pci_make_tag(pc, 0, 0, 0);
141 // x = pci_conf_read(pc, tag, PCI0_CMD); /* Read PCI command register */
142 // pci_conf_write(pc, tag, PCI0_CMD, x | MA | ME); /* enable bus mastering and memory space */
143
144 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0xF0000001); /* Enable PTM1 */
145 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA, 0);
146 pci_conf_write(pc, tag, PCIC_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */
147 pci_conf_write(pc, tag, PCIC_PTM2BAR, 0);
148 }
149
150 void
ibm4xx_show_pci_map(void)151 ibm4xx_show_pci_map(void)
152 {
153 pci_chipset_tag_t pc = &genppc_ibm4xx_chipset;
154 paddr_t la, lm, pl, ph;
155 pcitag_t tag;
156
157 setup_pcicfg_window();
158
159 printf("Local -> PCI map\n");
160 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA);
161 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA);
162 pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA);
163 ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA);
164 printf("0: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
165 (lm & 2) ? "":"not ",
166 (lm & 1) ? "enabled":"disabled");
167 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1LA);
168 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA);
169 pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCILA);
170 ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCIHA);
171 printf("1: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
172 (lm & 2) ? "":"not ",
173 (lm & 1) ? "enabled":"disabled");
174 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2LA);
175 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA);
176 pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCILA);
177 ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCIHA);
178 printf("2: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
179 (lm & 2) ? "":"not ",
180 (lm & 1) ? "enabled":"disabled");
181 printf("PCI -> Local map\n");
182
183 tag = pci_make_tag(pc, 0, 0, 0);
184 pl = pci_conf_read(pc, tag, PCIC_PTM1BAR);
185 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA);
186 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS);
187 printf("1: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
188 (lm & 1)?"enabled":"disabled");
189 pl = pci_conf_read(pc, tag, PCIC_PTM2BAR);
190 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2LA);
191 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS);
192 printf("2: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
193 (lm & 1)?"enabled":"disabled");
194 }
195