1 /* $NetBSD: ahcisata_pci.c,v 1.68 2022/10/12 12:50:02 macallan Exp $ */
2
3 /*
4 * Copyright (c) 2006 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.68 2022/10/12 12:50:02 macallan Exp $");
30
31 #ifdef _KERNEL_OPT
32 #include "opt_ahcisata_pci.h"
33 #endif
34
35 #include <sys/types.h>
36 #include <sys/kmem.h>
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/disklabel.h>
41 #include <sys/pmf.h>
42
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcidevs.h>
45 #include <dev/pci/pciidereg.h>
46 #include <dev/pci/pciidevar.h>
47 #include <dev/ic/ahcisatavar.h>
48
49 struct ahci_pci_quirk {
50 pci_vendor_id_t vendor; /* Vendor ID */
51 pci_product_id_t product; /* Product ID */
52 int quirks; /* quirks; same as sc_ahci_quirks */
53 };
54
55 static const struct ahci_pci_quirk ahci_pci_quirks[] = {
56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
65 AHCI_QUIRK_BADPMP },
66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
67 AHCI_QUIRK_BADPMP },
68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
69 AHCI_QUIRK_BADPMP },
70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
71 AHCI_QUIRK_BADPMP },
72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
75 AHCI_QUIRK_BADPMP },
76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
77 AHCI_QUIRK_BADPMP },
78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
79 AHCI_QUIRK_BADPMP },
80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
81 AHCI_QUIRK_BADPMP },
82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
83 AHCI_QUIRK_BADPMP },
84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
85 AHCI_QUIRK_BADPMP },
86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
87 AHCI_QUIRK_BADPMP },
88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
89 AHCI_QUIRK_BADPMP },
90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
91 AHCI_QUIRK_BADPMP },
92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
93 AHCI_QUIRK_BADPMP },
94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
95 AHCI_QUIRK_BADPMP },
96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
99 AHCI_QUIRK_BADPMP },
100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
101 AHCI_QUIRK_BADPMP },
102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
103 AHCI_QUIRK_BADPMP },
104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
105 AHCI_QUIRK_BADPMP },
106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
107 AHCI_QUIRK_BADPMP },
108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
109 AHCI_QUIRK_BADPMP },
110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
111 AHCI_QUIRK_BADPMP },
112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
113 AHCI_QUIRK_BADPMP },
114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
115 AHCI_QUIRK_BADPMP },
116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
117 AHCI_QUIRK_BADPMP },
118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
119 AHCI_QUIRK_BADPMP },
120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
145 AHCI_QUIRK_BADPMP },
146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
147 AHCI_QUIRK_BADPMP },
148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
149 AHCI_QUIRK_BADPMP },
150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
151 AHCI_QUIRK_BADPMP },
152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
153 AHCI_QUIRK_BADPMP },
154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
155 AHCI_QUIRK_BADPMP },
156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
157 AHCI_QUIRK_BADPMP },
158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
159 AHCI_QUIRK_BADPMP },
160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
161 AHCI_QUIRK_BADPMP },
162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
163 AHCI_QUIRK_BADPMP },
164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
165 AHCI_QUIRK_BADPMP },
166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
167 AHCI_QUIRK_BADPMP },
168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
169 AHCI_PCI_QUIRK_FORCE },
170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
173 AHCI_QUIRK_BADPMP },
174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
175 AHCI_PCI_QUIRK_FORCE },
176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
180 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
182 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
184 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
186 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE,
188 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA,
190 AHCI_QUIRK_BADPMP },
191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
192 AHCI_QUIRK_BADPMP },
193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
194 AHCI_PCI_QUIRK_FORCE },
195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
196 AHCI_PCI_QUIRK_FORCE },
197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
198 AHCI_PCI_QUIRK_FORCE },
199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
200 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_EXTRA_DELAY },
201 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
202 AHCI_PCI_QUIRK_FORCE },
203 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
204 AHCI_QUIRK_BADPMP },
205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
206 AHCI_QUIRK_BADPMP },
207
208 /* extra delay */
209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_AHCI,
210 AHCI_QUIRK_EXTRA_DELAY },
211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SER_MO_SATA_AHCI,
212 AHCI_QUIRK_EXTRA_DELAY },
213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BSW_AHCI,
214 AHCI_QUIRK_EXTRA_DELAY },
215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SER_DT_SATA_AHCI,
216 AHCI_QUIRK_EXTRA_DELAY },
217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SATA_AHCI,
218 AHCI_QUIRK_EXTRA_DELAY },
219 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_FCH_SATA_D, AHCI_QUIRK_EXTRA_DELAY },
220
221 #if 0
222 /*
223 * XXX Non-reproducible failures reported. May need extra-delay quirk.
224 */
225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_0,
226 AHCI_QUIRK_EXTRA_DELAY },
227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_1,
228 AHCI_QUIRK_EXTRA_DELAY },
229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_4,
230 AHCI_QUIRK_EXTRA_DELAY },
231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_5,
232 AHCI_QUIRK_EXTRA_DELAY },
233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_6,
234 AHCI_QUIRK_EXTRA_DELAY },
235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_7,
236 AHCI_QUIRK_EXTRA_DELAY },
237 #endif
238 };
239
240 struct ahci_pci_softc {
241 struct ahci_softc ah_sc;
242 pci_chipset_tag_t sc_pc;
243 pcitag_t sc_pcitag;
244 pci_intr_handle_t *sc_pihp;
245 int sc_nintr;
246 void **sc_ih;
247 };
248
249 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
250 static int ahci_pci_match(device_t, cfdata_t, void *);
251 static void ahci_pci_attach(device_t, device_t, void *);
252 static int ahci_pci_detach(device_t, int);
253 static void ahci_pci_childdetached(device_t, device_t);
254 static bool ahci_pci_resume(device_t, const pmf_qual_t *);
255
256
257 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
258 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL,
259 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN);
260
261 #define AHCI_PCI_ABAR_CAVIUM 0x10
262
263 static int
ahci_pci_has_quirk(pci_vendor_id_t vendor,pci_product_id_t product)264 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
265 {
266 int i;
267
268 for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
269 if (vendor == ahci_pci_quirks[i].vendor &&
270 product == ahci_pci_quirks[i].product)
271 return ahci_pci_quirks[i].quirks;
272 return 0;
273 }
274
275 static int
ahci_pci_abar(struct pci_attach_args * pa)276 ahci_pci_abar(struct pci_attach_args *pa)
277 {
278 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) {
279 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI ||
280 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) {
281 return AHCI_PCI_ABAR_CAVIUM;
282 }
283 }
284
285 return AHCI_PCI_ABAR;
286 }
287
288
289 static int
ahci_pci_match(device_t parent,cfdata_t match,void * aux)290 ahci_pci_match(device_t parent, cfdata_t match, void *aux)
291 {
292 struct pci_attach_args *pa = aux;
293 bus_space_tag_t regt;
294 bus_space_handle_t regh;
295 bus_size_t size;
296 int ret = 0;
297 bool force;
298
299 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
300 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
301
302 /* if wrong class and not forced by quirks, don't match */
303 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
304 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
305 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
306 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
307 (force == false))
308 return 0;
309
310 int bar = ahci_pci_abar(pa);
311 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
312 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0)
313 return 0;
314
315 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
316 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
317 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
318 (force == true))
319 ret = 3;
320
321 bus_space_unmap(regt, regh, size);
322 return ret;
323 }
324
325 static int
ahci_pci_intr_establish(struct ahci_softc * sc,int port)326 ahci_pci_intr_establish(struct ahci_softc *sc, int port)
327 {
328 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc;
329 device_t self = sc->sc_atac.atac_dev;
330 char intrbuf[PCI_INTRSTR_LEN];
331 char intr_xname[INTRDEVNAMEBUF];
332 const char *intrstr;
333 int vec;
334 int (*intr_handler)(void *);
335 void *intr_arg;
336
337 KASSERT(psc->sc_pihp != NULL);
338 KASSERT(psc->sc_nintr > 0);
339
340 snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self));
341
342 if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) {
343 /* Only one interrupt, established on vector 0 */
344 intr_handler = ahci_intr;
345 intr_arg = sc;
346 vec = 0;
347
348 if (psc->sc_ih[vec] != NULL) {
349 /* Already established, nothing more to do */
350 goto out;
351 }
352
353 } else {
354 /*
355 * Theoretically AHCI device can have less MSI/MSI-X vectors
356 * than supported ports. Hardware is allowed to revert
357 * to single message MSI, but not required to do so.
358 * So handle the case when it did not revert to single MSI.
359 * In this case last available interrupt vector is used
360 * for port == max vector, and all further ports.
361 * This last vector must use the general interrupt handler,
362 * since it needs to be able to handle several ports.
363 * NOTE: such case was never actually observed yet
364 */
365 if (sc->sc_atac.atac_nchannels > psc->sc_nintr
366 && port >= (psc->sc_nintr - 1)) {
367 intr_handler = ahci_intr;
368 intr_arg = sc;
369 vec = psc->sc_nintr - 1;
370
371 if (psc->sc_ih[vec] != NULL) {
372 /* Already established, nothing more to do */
373 goto out;
374 }
375
376 if (port == vec) {
377 /* Print error once */
378 aprint_error_dev(self,
379 "port %d independent interrupt vector not "
380 "available, sharing with further ports",
381 port);
382 }
383 } else {
384 /* Vector according to port */
385 KASSERT(port < psc->sc_nintr);
386 KASSERT(psc->sc_ih[port] == NULL);
387 intr_handler = ahci_intr_port;
388 intr_arg = &sc->sc_channels[port];
389 vec = port;
390
391 snprintf(intr_xname, sizeof(intr_xname), "%s port%d",
392 device_xname(self), port);
393 }
394 }
395
396 intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf,
397 sizeof(intrbuf));
398 psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc,
399 psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname);
400 if (psc->sc_ih[vec] == NULL) {
401 aprint_error_dev(self, "couldn't establish interrupt");
402 if (intrstr != NULL)
403 aprint_error(" at %s", intrstr);
404 aprint_error("\n");
405 goto fail;
406 }
407 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
408
409 out:
410 return 0;
411
412 fail:
413 return EAGAIN;
414 }
415
416 static void
ahci_pci_attach(device_t parent,device_t self,void * aux)417 ahci_pci_attach(device_t parent, device_t self, void *aux)
418 {
419 struct pci_attach_args *pa = aux;
420 struct ahci_pci_softc *psc = device_private(self);
421 struct ahci_softc *sc = &psc->ah_sc;
422 bool ahci_cap_64bit;
423 bool ahci_bad_64bit;
424 pcireg_t reg;
425
426 sc->sc_atac.atac_dev = self;
427
428 int bar = ahci_pci_abar(pa);
429 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
430 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih,
431 NULL, &sc->sc_ahcis) != 0) {
432 aprint_error_dev(self, "can't map ahci registers\n");
433 return;
434 }
435 psc->sc_pc = pa->pa_pc;
436 psc->sc_pcitag = pa->pa_tag;
437
438 pci_aprint_devinfo(pa, "AHCI disk controller");
439
440 int counts[PCI_INTR_TYPE_SIZE] = {
441 [PCI_INTR_TYPE_INTX] = 1,
442 [PCI_INTR_TYPE_MSI] = 1,
443 [PCI_INTR_TYPE_MSIX] = -1,
444 };
445
446 /* Allocate and establish the interrupt. */
447 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
448 aprint_error_dev(self, "can't allocate handler\n");
449 goto fail;
450 }
451
452 psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])];
453 psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP);
454 sc->sc_intr_establish = ahci_pci_intr_establish;
455
456 sc->sc_dmat = pa->pa_dmat;
457
458 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
459 PCI_PRODUCT(pa->pa_id));
460
461 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
462 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
463
464 if (pci_dma64_available(pa) && ahci_cap_64bit) {
465 if (!ahci_bad_64bit)
466 sc->sc_dmat = pa->pa_dmat64;
467 aprint_verbose_dev(self, "64-bit DMA%s\n",
468 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
469 }
470
471 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
472 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
473 sc->sc_atac_capflags = ATAC_CAP_RAID;
474 } else {
475 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
476 }
477
478 reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);
479 reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
480 pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
481
482 ahci_attach(sc);
483
484 if (!pmf_device_register(self, NULL, ahci_pci_resume))
485 aprint_error_dev(self, "couldn't establish power handler\n");
486
487 return;
488 fail:
489 if (psc->sc_pihp != NULL) {
490 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
491 psc->sc_pihp = NULL;
492 }
493 if (sc->sc_ahcis) {
494 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
495 sc->sc_ahcis = 0;
496 }
497
498 return;
499
500 }
501
502 static void
ahci_pci_childdetached(device_t dv,device_t child)503 ahci_pci_childdetached(device_t dv, device_t child)
504 {
505 struct ahci_pci_softc *psc = device_private(dv);
506 struct ahci_softc *sc = &psc->ah_sc;
507
508 ahci_childdetached(sc, child);
509 }
510
511 static int
ahci_pci_detach(device_t dv,int flags)512 ahci_pci_detach(device_t dv, int flags)
513 {
514 struct ahci_pci_softc *psc;
515 struct ahci_softc *sc;
516 int rv;
517
518 psc = device_private(dv);
519 sc = &psc->ah_sc;
520
521 if ((rv = ahci_detach(sc, flags)))
522 return rv;
523
524 pmf_device_deregister(dv);
525
526 if (psc->sc_ih != NULL) {
527 for (int intr = 0; intr < psc->sc_nintr; intr++) {
528 if (psc->sc_ih[intr] != NULL) {
529 pci_intr_disestablish(psc->sc_pc,
530 psc->sc_ih[intr]);
531 psc->sc_ih[intr] = NULL;
532 }
533 }
534
535 kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr);
536 psc->sc_ih = NULL;
537 }
538
539 if (psc->sc_pihp != NULL) {
540 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
541 psc->sc_pihp = NULL;
542 }
543
544 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
545
546 return 0;
547 }
548
549 static bool
ahci_pci_resume(device_t dv,const pmf_qual_t * qual)550 ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
551 {
552 struct ahci_pci_softc *psc = device_private(dv);
553 struct ahci_softc *sc = &psc->ah_sc;
554 int s;
555
556 s = splbio();
557 ahci_resume(sc);
558 splx(s);
559
560 return true;
561 }
562