1 /* $NetBSD: siisata_pci.c,v 1.23 2022/09/25 17:52:25 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2006 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 /*
29 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch.
30 * All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 #include <sys/cdefs.h>
54 __KERNEL_RCSID(0, "$NetBSD: siisata_pci.c,v 1.23 2022/09/25 17:52:25 thorpej Exp $");
55
56 #include <sys/types.h>
57 #include <sys/param.h>
58 #include <sys/kernel.h>
59 #include <sys/systm.h>
60
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcidevs.h>
63 #include <dev/ic/siisatavar.h>
64
65 struct siisata_pci_softc {
66 struct siisata_softc si_sc;
67 pci_chipset_tag_t sc_pc;
68 pcitag_t sc_pcitag;
69 pci_intr_handle_t *sc_pihp;
70 void *sc_ih;
71 };
72
73 static int siisata_pci_match(device_t, cfdata_t, void *);
74 static void siisata_pci_attach(device_t, device_t, void *);
75 static int siisata_pci_detach(device_t, int);
76 static void siisata_pci_childdetached(device_t, device_t);
77 static bool siisata_pci_resume(device_t, const pmf_qual_t *);
78
79 struct siisata_pci_board {
80 pci_vendor_id_t spb_vend;
81 pci_product_id_t spb_prod;
82 uint16_t spb_port;
83 uint16_t spb_chip;
84 uint8_t sbp_flags;
85 };
86
87 #define SIISATA_BROKEN_MSI 0x01
88
89 static const struct siisata_pci_board siisata_pci_boards[] = {
90 {
91 .spb_vend = PCI_VENDOR_CMDTECH,
92 .spb_prod = PCI_PRODUCT_CMDTECH_3124,
93 .spb_port = 4,
94 .spb_chip = 3124,
95 /*
96 * SiI3124 seems to be PCI/PCI-X chip behind PCI-e bridge,
97 * claims MSI support but interrupts don't work with MSI on.
98 */
99 .sbp_flags = SIISATA_BROKEN_MSI,
100 },
101 {
102 .spb_vend = PCI_VENDOR_CMDTECH,
103 .spb_prod = PCI_PRODUCT_CMDTECH_3132,
104 .spb_port = 2,
105 .spb_chip = 3132,
106 },
107 {
108 .spb_vend = PCI_VENDOR_CMDTECH,
109 .spb_prod = PCI_PRODUCT_CMDTECH_AAR_1220SA,
110 .spb_port = 2,
111 .spb_chip = 3132,
112 },
113 {
114 .spb_vend = PCI_VENDOR_CMDTECH,
115 .spb_prod = PCI_PRODUCT_CMDTECH_3531,
116 .spb_port = 1,
117 .spb_chip = 3531,
118 },
119 };
120
121 CFATTACH_DECL3_NEW(siisata_pci, sizeof(struct siisata_pci_softc),
122 siisata_pci_match, siisata_pci_attach, siisata_pci_detach, NULL,
123 NULL, siisata_pci_childdetached, DVF_DETACH_SHUTDOWN);
124
125 static const struct siisata_pci_board *
siisata_pci_lookup(const struct pci_attach_args * pa)126 siisata_pci_lookup(const struct pci_attach_args * pa)
127 {
128 int i;
129
130 for (i = 0; i < __arraycount(siisata_pci_boards); i++) {
131 if (siisata_pci_boards[i].spb_vend != PCI_VENDOR(pa->pa_id))
132 continue;
133 if (siisata_pci_boards[i].spb_prod == PCI_PRODUCT(pa->pa_id))
134 return &siisata_pci_boards[i];
135 }
136
137 return NULL;
138 }
139
140 static int
siisata_pci_match(device_t parent,cfdata_t match,void * aux)141 siisata_pci_match(device_t parent, cfdata_t match, void *aux)
142 {
143 struct pci_attach_args *pa = aux;
144
145 if (siisata_pci_lookup(pa) != NULL)
146 return 3;
147
148 return 0;
149 }
150
151 static void
siisata_pci_attach(device_t parent,device_t self,void * aux)152 siisata_pci_attach(device_t parent, device_t self, void *aux)
153 {
154 struct pci_attach_args *pa = aux;
155 struct siisata_pci_softc *psc = device_private(self);
156 struct siisata_softc *sc = &psc->si_sc;
157 const char *intrstr;
158 pcireg_t csr, memtype;
159 const struct siisata_pci_board *spbp;
160 bus_space_tag_t memt;
161 bus_space_handle_t memh;
162 uint32_t gcreg;
163 int memh_valid;
164 bus_size_t grsize, prsize;
165 char intrbuf[PCI_INTRSTR_LEN];
166
167 spbp = siisata_pci_lookup(pa);
168 KASSERT(spbp != NULL);
169
170 sc->sc_atac.atac_dev = self;
171
172 psc->sc_pc = pa->pa_pc;
173 psc->sc_pcitag = pa->pa_tag;
174
175 pci_aprint_devinfo(pa, "SATA-II HBA");
176
177 /* map BAR 0, global registers */
178 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0);
179 switch (memtype) {
180 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
181 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
182 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0,
183 memtype, 0, &memt, &memh, NULL, &grsize) == 0);
184 break;
185 default:
186 memh_valid = 0;
187 }
188 if (memh_valid) {
189 sc->sc_grt = memt;
190 sc->sc_grh = memh;
191 sc->sc_grs = grsize;
192 } else {
193 aprint_error_dev(self, "couldn't map global registers\n");
194 return;
195 }
196
197 /* map BAR 1, port registers */
198 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1);
199 switch (memtype) {
200 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
201 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
202 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1,
203 memtype, 0, &memt, &memh, NULL, &prsize) == 0);
204 break;
205 default:
206 memh_valid = 0;
207 }
208 if (memh_valid) {
209 sc->sc_prt = memt;
210 sc->sc_prh = memh;
211 sc->sc_prs = prsize;
212 } else {
213 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
214 aprint_error_dev(self, "couldn't map port registers\n");
215 return;
216 }
217
218 if (pci_dma64_available(pa))
219 sc->sc_dmat = pa->pa_dmat64;
220 else
221 sc->sc_dmat = pa->pa_dmat;
222
223 int counts[PCI_INTR_TYPE_SIZE] = {
224 [PCI_INTR_TYPE_INTX] = 1,
225 [PCI_INTR_TYPE_MSI] = 1,
226 [PCI_INTR_TYPE_MSIX] = 1,
227 };
228 int max_type = PCI_INTR_TYPE_MSIX;
229
230 if (spbp->sbp_flags & SIISATA_BROKEN_MSI) {
231 max_type = PCI_INTR_TYPE_INTX;
232 }
233
234 /* map interrupt */
235 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, max_type) != 0) {
236 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
237 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize);
238 aprint_error_dev(self, "couldn't map interrupt\n");
239 return;
240 }
241 intrstr = pci_intr_string(pa->pa_pc, psc->sc_pihp[0], intrbuf,
242 sizeof(intrbuf));
243 psc->sc_ih = pci_intr_establish_xname(pa->pa_pc, psc->sc_pihp[0],
244 IPL_BIO, siisata_intr, sc, device_xname(self));
245 if (psc->sc_ih == NULL) {
246 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1);
247 psc->sc_pihp = NULL;
248
249 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
250 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize);
251 aprint_error_dev(self, "couldn't establish interrupt at %s\n",
252 intrstr);
253 return;
254 }
255 aprint_normal_dev(self, "interrupting at %s\n",
256 intrstr ? intrstr : "unknown interrupt");
257
258 /* fill in number of ports on this device */
259 sc->sc_atac.atac_nchannels = spbp->spb_port;
260
261 /* set the necessary bits in case the firmware didn't */
262 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
263 csr |= PCI_COMMAND_MASTER_ENABLE;
264 csr |= PCI_COMMAND_MEM_ENABLE;
265 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
266
267 gcreg = GRREAD(sc, GR_GC);
268
269 aprint_verbose_dev(self, "SiI%d, %sGb/s\n",
270 spbp->spb_chip, (gcreg & GR_GC_3GBPS) ? "3.0" : "1.5" );
271 if (spbp->spb_chip == 3124) {
272 short width;
273 short speed;
274 char pcix = 1;
275
276 width = (gcreg & GR_GC_REQ64) ? 64 : 32;
277
278 switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) {
279 case 0:
280 speed = (gcreg & GR_GC_M66EN) ? 66 : 33;
281 pcix = 0;
282 break;
283 case GR_GC_TRDY:
284 speed = 66;
285 break;
286 case GR_GC_STOP:
287 speed = 100;
288 break;
289 case GR_GC_STOP | GR_GC_TRDY:
290 speed = 133;
291 break;
292 default:
293 speed = -1;
294 break;
295 }
296 aprint_verbose_dev(self, "%hd-bit %hdMHz PCI%s\n",
297 width, speed, pcix ? "-X" : "");
298 }
299
300 siisata_attach(sc);
301
302 if (!pmf_device_register(self, NULL, siisata_pci_resume))
303 aprint_error_dev(self, "couldn't establish power handler\n");
304 }
305
306 static int
siisata_pci_detach(device_t dv,int flags)307 siisata_pci_detach(device_t dv, int flags)
308 {
309 struct siisata_pci_softc *psc = device_private(dv);
310 struct siisata_softc *sc = &psc->si_sc;
311 int rv;
312
313 rv = siisata_detach(sc, flags);
314 if (rv)
315 return rv;
316
317 if (psc->sc_ih != NULL) {
318 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
319 psc->sc_ih = NULL;
320 }
321
322 if (psc->sc_pihp != NULL) {
323 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1);
324 psc->sc_pihp = NULL;
325 }
326
327 bus_space_unmap(sc->sc_prt, sc->sc_prh, sc->sc_prs);
328 bus_space_unmap(sc->sc_grt, sc->sc_grh, sc->sc_grs);
329
330 return 0;
331 }
332
333 static void
siisata_pci_childdetached(device_t dv,device_t child)334 siisata_pci_childdetached(device_t dv, device_t child)
335 {
336 struct siisata_pci_softc *psc = device_private(dv);
337 struct siisata_softc *sc = &psc->si_sc;
338
339 siisata_childdetached(sc, child);
340 }
341
342 static bool
siisata_pci_resume(device_t dv,const pmf_qual_t * qual)343 siisata_pci_resume(device_t dv, const pmf_qual_t *qual)
344 {
345 struct siisata_pci_softc *psc = device_private(dv);
346 struct siisata_softc *sc = &psc->si_sc;
347 int s;
348
349 s = splbio();
350 siisata_resume(sc);
351 splx(s);
352
353 return true;
354 }
355