1 /* $NetBSD: ehci.c,v 1.316 2023/07/20 20:00:34 mrg Exp $ */
2
3 /*
4 * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum,
9 * Jeremy Morse (jeremy.morse@gmail.com), Jared D. McNeill
10 * (jmcneill@invisible.ca). Matthew R. Green (mrg@eterna.com.au), and
11 * Nick Hudson .
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
37 *
38 * The EHCI 1.0 spec can be found at
39 * http://www.intel.com/technology/usb/spec.htm
40 * and the USB 2.0 spec at
41 * http://www.usb.org/developers/docs/
42 *
43 */
44
45 /*
46 * TODO:
47 * 1) hold off explorations by companion controllers until ehci has started.
48 *
49 * 2) The hub driver needs to handle and schedule the transaction translator,
50 * to assign place in frame where different devices get to go. See chapter
51 * on hubs in USB 2.0 for details.
52 *
53 * 3) Command failures are not recovered correctly.
54 */
55
56 #include <sys/cdefs.h>
57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.316 2023/07/20 20:00:34 mrg Exp $");
58
59 #include "ohci.h"
60 #include "uhci.h"
61
62 #ifdef _KERNEL_OPT
63 #include "opt_usb.h"
64 #endif
65
66 #include <sys/param.h>
67
68 #include <sys/bus.h>
69 #include <sys/cpu.h>
70 #include <sys/device.h>
71 #include <sys/kernel.h>
72 #include <sys/kmem.h>
73 #include <sys/mutex.h>
74 #include <sys/proc.h>
75 #include <sys/queue.h>
76 #include <sys/select.h>
77 #include <sys/sysctl.h>
78 #include <sys/systm.h>
79 #include <sys/reboot.h>
80
81 #include <machine/endian.h>
82
83 #include <dev/usb/usb.h>
84 #include <dev/usb/usbdi.h>
85 #include <dev/usb/usbdivar.h>
86 #include <dev/usb/usbhist.h>
87 #include <dev/usb/usb_mem.h>
88 #include <dev/usb/usb_quirks.h>
89
90 #include <dev/usb/ehcireg.h>
91 #include <dev/usb/ehcivar.h>
92 #include <dev/usb/usbroothub.h>
93
94 #ifdef USB_DEBUG
95 #ifndef EHCI_DEBUG
96 #define ehcidebug 0
97 #else
98
99 #ifndef EHCI_DEBUG_DEFAULT
100 #define EHCI_DEBUG_DEFAULT 0
101 #endif
102
103 static int ehcidebug = EHCI_DEBUG_DEFAULT;
104
105 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup")
106 {
107 int err;
108 const struct sysctlnode *rnode;
109 const struct sysctlnode *cnode;
110
111 err = sysctl_createv(clog, 0, NULL, &rnode,
112 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci",
113 SYSCTL_DESCR("ehci global controls"),
114 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
115
116 if (err)
117 goto fail;
118
119 /* control debugging printfs */
120 err = sysctl_createv(clog, 0, &rnode, &cnode,
121 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
122 "debug", SYSCTL_DESCR("Enable debugging output"),
123 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL);
124 if (err)
125 goto fail;
126
127 return;
128 fail:
129 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
130 }
131
132 #endif /* EHCI_DEBUG */
133 #endif /* USB_DEBUG */
134
135 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D)
136 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D)
137 #define EHCIHIST_FUNC() USBHIST_FUNC()
138 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug)
139
140 struct ehci_pipe {
141 struct usbd_pipe pipe;
142 int nexttoggle;
143
144 ehci_soft_qh_t *sqh;
145 union {
146 /* Control pipe */
147 struct {
148 usb_dma_t reqdma;
149 } ctrl;
150 /* Interrupt pipe */
151 struct {
152 u_int length;
153 } intr;
154 /* Iso pipe */
155 struct {
156 u_int next_frame;
157 u_int cur_xfers;
158 } isoc;
159 };
160 };
161
162 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t;
163
164 Static usbd_status ehci_open(struct usbd_pipe *);
165 Static void ehci_poll(struct usbd_bus *);
166 Static void ehci_softintr(void *);
167 Static int ehci_intr1(ehci_softc_t *);
168 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *,
169 ex_completeq_t *);
170 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *,
171 ex_completeq_t *);
172 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *,
173 ex_completeq_t *);
174 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *);
175 Static void ehci_intrlist_timeout(void *);
176 Static void ehci_doorbell(void *);
177 Static void ehci_pcd(void *);
178
179 Static struct usbd_xfer *
180 ehci_allocx(struct usbd_bus *, unsigned int);
181 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *);
182
183 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **);
184 Static bool ehci_dying(struct usbd_bus *);
185 Static int ehci_roothub_ctrl(struct usbd_bus *,
186 usb_device_request_t *, void *, int);
187
188 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *);
189 Static usbd_status ehci_root_intr_start(struct usbd_xfer *);
190 Static void ehci_root_intr_abort(struct usbd_xfer *);
191 Static void ehci_root_intr_close(struct usbd_pipe *);
192 Static void ehci_root_intr_done(struct usbd_xfer *);
193
194 Static int ehci_device_ctrl_init(struct usbd_xfer *);
195 Static void ehci_device_ctrl_fini(struct usbd_xfer *);
196 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *);
197 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *);
198 Static void ehci_device_ctrl_abort(struct usbd_xfer *);
199 Static void ehci_device_ctrl_close(struct usbd_pipe *);
200 Static void ehci_device_ctrl_done(struct usbd_xfer *);
201
202 Static int ehci_device_bulk_init(struct usbd_xfer *);
203 Static void ehci_device_bulk_fini(struct usbd_xfer *);
204 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *);
205 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *);
206 Static void ehci_device_bulk_abort(struct usbd_xfer *);
207 Static void ehci_device_bulk_close(struct usbd_pipe *);
208 Static void ehci_device_bulk_done(struct usbd_xfer *);
209
210 Static int ehci_device_intr_init(struct usbd_xfer *);
211 Static void ehci_device_intr_fini(struct usbd_xfer *);
212 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *);
213 Static usbd_status ehci_device_intr_start(struct usbd_xfer *);
214 Static void ehci_device_intr_abort(struct usbd_xfer *);
215 Static void ehci_device_intr_close(struct usbd_pipe *);
216 Static void ehci_device_intr_done(struct usbd_xfer *);
217
218 Static int ehci_device_isoc_init(struct usbd_xfer *);
219 Static void ehci_device_isoc_fini(struct usbd_xfer *);
220 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *);
221 Static void ehci_device_isoc_abort(struct usbd_xfer *);
222 Static void ehci_device_isoc_close(struct usbd_pipe *);
223 Static void ehci_device_isoc_done(struct usbd_xfer *);
224
225 Static int ehci_device_fs_isoc_init(struct usbd_xfer *);
226 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *);
227 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *);
228 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *);
229 Static void ehci_device_fs_isoc_close(struct usbd_pipe *);
230 Static void ehci_device_fs_isoc_done(struct usbd_xfer *);
231
232 Static void ehci_device_clear_toggle(struct usbd_pipe *);
233 Static void ehci_noop(struct usbd_pipe *);
234
235 Static void ehci_disown(ehci_softc_t *, int, int);
236
237 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *);
238 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
239
240 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
241 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
242 Static int ehci_alloc_sqtd_chain(ehci_softc_t *,
243 struct usbd_xfer *, int, int, ehci_soft_qtd_t **);
244 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *);
245
246 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *,
247 int, int, int *, ehci_soft_qtd_t **);
248 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *);
249
250 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *);
251 Static ehci_soft_sitd_t *
252 ehci_alloc_sitd(ehci_softc_t *);
253
254 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *);
255 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *);
256 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *);
257 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *);
258
259 static inline void
ehci_free_itd_locked(ehci_softc_t * sc,ehci_soft_itd_t * itd)260 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd)
261 {
262
263 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list);
264 }
265
266 static inline void
ehci_free_sitd_locked(ehci_softc_t * sc,ehci_soft_sitd_t * sitd)267 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd)
268 {
269
270 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list);
271 }
272
273 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status);
274
275 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
276 int);
277
278 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *,
279 ehci_soft_qh_t *);
280 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
281 ehci_soft_qh_t *);
282 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
283 Static void ehci_sync_hc(ehci_softc_t *);
284
285 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *);
286 Static void ehci_abortx(struct usbd_xfer *);
287
288 #ifdef EHCI_DEBUG
289 Static ehci_softc_t *theehci;
290 void ehci_dump(void);
291 #endif
292
293 #ifdef EHCI_DEBUG
294 Static void ehci_dump_regs(ehci_softc_t *);
295 Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
296 Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
297 Static void ehci_dump_qtd(ehci_qtd_t *);
298 Static void ehci_dump_sqh(ehci_soft_qh_t *);
299 Static void ehci_dump_sitd(struct ehci_soft_itd *);
300 Static void ehci_dump_itds(ehci_soft_itd_t *);
301 Static void ehci_dump_itd(struct ehci_soft_itd *);
302 Static void ehci_dump_exfer(struct ehci_xfer *);
303 #endif
304
305 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
306
307 static inline void
ehci_add_intr_list(ehci_softc_t * sc,struct ehci_xfer * ex)308 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex)
309 {
310
311 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next);
312 }
313
314 static inline void
ehci_del_intr_list(ehci_softc_t * sc,struct ehci_xfer * ex)315 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex)
316 {
317
318 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next);
319 }
320
321 Static const struct usbd_bus_methods ehci_bus_methods = {
322 .ubm_open = ehci_open,
323 .ubm_softint = ehci_softintr,
324 .ubm_dopoll = ehci_poll,
325 .ubm_allocx = ehci_allocx,
326 .ubm_freex = ehci_freex,
327 .ubm_abortx = ehci_abortx,
328 .ubm_dying = ehci_dying,
329 .ubm_getlock = ehci_get_lock,
330 .ubm_rhctrl = ehci_roothub_ctrl,
331 };
332
333 Static const struct usbd_pipe_methods ehci_root_intr_methods = {
334 .upm_transfer = ehci_root_intr_transfer,
335 .upm_start = ehci_root_intr_start,
336 .upm_abort = ehci_root_intr_abort,
337 .upm_close = ehci_root_intr_close,
338 .upm_cleartoggle = ehci_noop,
339 .upm_done = ehci_root_intr_done,
340 };
341
342 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
343 .upm_init = ehci_device_ctrl_init,
344 .upm_fini = ehci_device_ctrl_fini,
345 .upm_transfer = ehci_device_ctrl_transfer,
346 .upm_start = ehci_device_ctrl_start,
347 .upm_abort = ehci_device_ctrl_abort,
348 .upm_close = ehci_device_ctrl_close,
349 .upm_cleartoggle = ehci_noop,
350 .upm_done = ehci_device_ctrl_done,
351 };
352
353 Static const struct usbd_pipe_methods ehci_device_intr_methods = {
354 .upm_init = ehci_device_intr_init,
355 .upm_fini = ehci_device_intr_fini,
356 .upm_transfer = ehci_device_intr_transfer,
357 .upm_start = ehci_device_intr_start,
358 .upm_abort = ehci_device_intr_abort,
359 .upm_close = ehci_device_intr_close,
360 .upm_cleartoggle = ehci_device_clear_toggle,
361 .upm_done = ehci_device_intr_done,
362 };
363
364 Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
365 .upm_init = ehci_device_bulk_init,
366 .upm_fini = ehci_device_bulk_fini,
367 .upm_transfer = ehci_device_bulk_transfer,
368 .upm_start = ehci_device_bulk_start,
369 .upm_abort = ehci_device_bulk_abort,
370 .upm_close = ehci_device_bulk_close,
371 .upm_cleartoggle = ehci_device_clear_toggle,
372 .upm_done = ehci_device_bulk_done,
373 };
374
375 Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
376 .upm_init = ehci_device_isoc_init,
377 .upm_fini = ehci_device_isoc_fini,
378 .upm_transfer = ehci_device_isoc_transfer,
379 .upm_abort = ehci_device_isoc_abort,
380 .upm_close = ehci_device_isoc_close,
381 .upm_cleartoggle = ehci_noop,
382 .upm_done = ehci_device_isoc_done,
383 };
384
385 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = {
386 .upm_init = ehci_device_fs_isoc_init,
387 .upm_fini = ehci_device_fs_isoc_fini,
388 .upm_transfer = ehci_device_fs_isoc_transfer,
389 .upm_abort = ehci_device_fs_isoc_abort,
390 .upm_close = ehci_device_fs_isoc_close,
391 .upm_cleartoggle = ehci_noop,
392 .upm_done = ehci_device_fs_isoc_done,
393 };
394
395 static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
396 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
397 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
398 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
399 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
400 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
401 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
402 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
403 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
404 };
405
406 int
ehci_init(ehci_softc_t * sc)407 ehci_init(ehci_softc_t *sc)
408 {
409 uint32_t vers, hcr;
410 u_int i;
411 int err;
412 ehci_soft_qh_t *sqh;
413 u_int ncomp;
414
415 EHCIHIST_FUNC(); EHCIHIST_CALLED();
416 #ifdef EHCI_DEBUG
417 theehci = sc;
418 #endif
419
420 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE);
421 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
422 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
423 cv_init(&sc->sc_doorbell, "ehcidb");
424
425 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0,
426 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL);
427
428 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
429 ehci_doorbell, sc);
430 KASSERT(sc->sc_doorbell_si != NULL);
431 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
432 ehci_pcd, sc);
433 KASSERT(sc->sc_pcd_si != NULL);
434
435 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
436
437 vers = EREAD2(sc, EHCI_HCIVERSION);
438 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev),
439 vers >> 8, vers & 0xff);
440
441 const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS);
442 DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0);
443 sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams);
444 ncomp = EHCI_HCS_N_CC(hcsparams);
445 if (ncomp != sc->sc_ncomp) {
446 aprint_verbose("%s: wrong number of companions (%d != %d)\n",
447 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp);
448 #if NOHCI == 0 || NUHCI == 0
449 aprint_error("%s: ohci or uhci probably not configured\n",
450 device_xname(sc->sc_dev));
451 #endif
452 if (ncomp < sc->sc_ncomp)
453 sc->sc_ncomp = ncomp;
454 }
455 if (sc->sc_ncomp > 0) {
456 KASSERT(!(sc->sc_flags & EHCIF_ETTF));
457 aprint_normal_dev(sc->sc_dev,
458 "%d companion controller%s, %d port%s%s",
459 sc->sc_ncomp,
460 sc->sc_ncomp!=1 ? "s" : "",
461 EHCI_HCS_N_PCC(hcsparams),
462 EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "",
463 sc->sc_ncomp!=1 ? " each" : "");
464 if (sc->sc_comps[0]) {
465 aprint_normal(":");
466 for (i = 0; i < sc->sc_ncomp; i++)
467 aprint_normal(" %s",
468 device_xname(sc->sc_comps[i]));
469 }
470 aprint_normal("\n");
471
472 mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB);
473 callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE);
474 cv_init(&sc->sc_compcv, "ehciccv");
475 sc->sc_comp_state = CO_EARLY;
476 }
477 sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams);
478 sc->sc_hasppc = EHCI_HCS_PPC(hcsparams);
479
480 const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS);
481 DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0);
482
483 if (EHCI_HCC_64BIT(hccparams)) {
484 /* MUST clear segment register if 64 bit capable. */
485 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
486 }
487
488 if (hccparams & EHCI_HCC_IST_FULLFRAME) {
489 sc->sc_istthreshold = 0;
490 } else {
491 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams);
492 }
493
494 sc->sc_bus.ub_revision = USBREV_2_0;
495 sc->sc_bus.ub_usedma = true;
496 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG;
497
498 /*
499 * The bus attachment code will possibly provide a 64bit DMA
500 * tag which we now limit to the bottom 4G range as
501 *
502 * - that's as much as ehci can address in its QH, TD, iTD, and siTD
503 * structures; and
504 * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything
505 * other than 0.
506 */
507 bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag;
508 sc->sc_dmatag = sc->sc_bus.ub_dmatag;
509 err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX,
510 &ntag, 0);
511 if (err == 0) {
512 sc->sc_dmatag = ntag;
513 aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control"
514 " data structures\n");
515 }
516
517 /* Reset the controller */
518 DPRINTF("resetting", 0, 0, 0, 0);
519 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
520 usb_delay_ms(&sc->sc_bus, 1);
521 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
522 for (i = 0; i < 100; i++) {
523 usb_delay_ms(&sc->sc_bus, 1);
524 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
525 if (!hcr)
526 break;
527 }
528 if (hcr) {
529 aprint_error_dev(sc->sc_dev, "reset timeout\n");
530 err = EIO;
531 goto fail1;
532 }
533 if (sc->sc_vendor_init)
534 sc->sc_vendor_init(sc);
535
536 /* XXX need proper intr scheduling */
537 sc->sc_rand = 96;
538
539 /* frame list size at default, read back what we got and use that */
540 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
541 case 0: sc->sc_flsize = 1024; break;
542 case 1: sc->sc_flsize = 512; break;
543 case 2: sc->sc_flsize = 256; break;
544 case 3:
545 err = EIO;
546 goto fail1;
547 }
548 err = usb_allocmem(sc->sc_dmatag,
549 sc->sc_flsize * sizeof(ehci_link_t),
550 EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma);
551 if (err) {
552 aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n");
553 goto fail1;
554 }
555 DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0);
556 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
557
558 for (i = 0; i < sc->sc_flsize; i++) {
559 sc->sc_flist[i] = EHCI_NULL;
560 }
561
562 const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0);
563 const uint32_t hi32 = BUS_ADDR_HI32(flba);
564 if (hi32 != 0) {
565 aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n",
566 hi32);
567 goto fail2;
568 }
569
570 const uint32_t lo32 = BUS_ADDR_LO32(flba);
571 EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32);
572
573 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
574 KM_SLEEP);
575 LIST_INIT(&sc->sc_freeitds);
576 LIST_INIT(&sc->sc_freesitds);
577 TAILQ_INIT(&sc->sc_intrhead);
578
579 /* Set up the bus struct. */
580 sc->sc_bus.ub_methods = &ehci_bus_methods;
581 sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe);
582
583 sc->sc_eintrs = EHCI_NORMAL_INTRS;
584
585 /*
586 * Allocate the interrupt dummy QHs. These are arranged to give poll
587 * intervals that are powers of 2 times 1ms.
588 */
589 memset(sc->sc_islots, 0, sizeof(sc->sc_islots));
590 for (i = 0; i < EHCI_INTRQHS; i++) {
591 sqh = ehci_alloc_sqh(sc);
592 if (sqh == NULL) {
593 err = ENOMEM;
594 goto fail3;
595 }
596 sc->sc_islots[i].sqh = sqh;
597 }
598 for (i = 0; i < EHCI_INTRQHS; i++) {
599 sqh = sc->sc_islots[i].sqh;
600 if (i == 0) {
601 /* The last (1ms) QH terminates. */
602 sqh->qh.qh_link = EHCI_NULL;
603 sqh->next = NULL;
604 } else {
605 /* Otherwise the next QH has half the poll interval */
606 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
607 sqh->qh.qh_link = htole32(sqh->next->physaddr |
608 EHCI_LINK_QH);
609 }
610 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
611 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
612 sqh->qh.qh_curqtd = EHCI_NULL;
613 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
614 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
615 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
616 sqh->sqtd = NULL;
617 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
618 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
619 }
620 /* Point the frame list at the last level (128ms). */
621 for (i = 0; i < sc->sc_flsize; i++) {
622 int j;
623
624 j = (i & ~(EHCI_MAX_POLLRATE-1)) |
625 revbits[i & (EHCI_MAX_POLLRATE-1)];
626 sc->sc_flist[j] = htole32(EHCI_LINK_QH |
627 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
628 i)].sqh->physaddr);
629 }
630 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t),
631 BUS_DMASYNC_PREWRITE);
632
633 /* Allocate dummy QH that starts the async list. */
634 sqh = ehci_alloc_sqh(sc);
635 if (sqh == NULL) {
636 err = ENOMEM;
637 goto fail3;
638 }
639 /* Fill the QH */
640 sqh->qh.qh_endp =
641 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
642 sqh->qh.qh_link =
643 htole32(sqh->physaddr | EHCI_LINK_QH);
644 sqh->qh.qh_curqtd = EHCI_NULL;
645 sqh->next = NULL;
646 /* Fill the overlay qTD */
647 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
648 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
649 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
650 sqh->sqtd = NULL;
651 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
652 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
653 #ifdef EHCI_DEBUG
654 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
655 ehci_dump_sqh(sqh);
656 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
657 #endif
658
659 /* Point to async list */
660 sc->sc_async_head = sqh;
661 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
662
663 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE);
664
665 /* Turn on controller */
666 EOWRITE4(sc, EHCI_USBCMD,
667 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
668 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
669 EHCI_CMD_ASE |
670 EHCI_CMD_PSE |
671 EHCI_CMD_RS);
672
673 /* Take over port ownership */
674 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
675
676 for (i = 0; i < 100; i++) {
677 usb_delay_ms(&sc->sc_bus, 1);
678 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
679 if (!hcr)
680 break;
681 }
682 if (hcr) {
683 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev));
684 err = EIO;
685 goto fail4;
686 }
687
688 /* Enable interrupts */
689 DPRINTF("enabling interrupts", 0, 0, 0, 0);
690 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
691
692 return 0;
693
694 fail4:
695 ehci_free_sqh(sc, sc->sc_async_head);
696
697 fail3:
698 for (i = 0; i < EHCI_INTRQHS; i++) {
699 sqh = sc->sc_islots[i].sqh;
700 if (sqh)
701 ehci_free_sqh(sc, sqh);
702 }
703
704 kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *));
705
706 fail2:
707 usb_freemem(&sc->sc_fldma);
708
709 fail1:
710 softint_disestablish(sc->sc_doorbell_si);
711 softint_disestablish(sc->sc_pcd_si);
712 mutex_destroy(&sc->sc_rhlock);
713 mutex_destroy(&sc->sc_lock);
714 mutex_destroy(&sc->sc_intr_lock);
715
716 return err;
717 }
718
719 int
ehci_intr(void * v)720 ehci_intr(void *v)
721 {
722 ehci_softc_t *sc = v;
723 int ret = 0;
724
725 EHCIHIST_FUNC(); EHCIHIST_CALLED();
726
727 if (sc == NULL)
728 return 0;
729
730 mutex_spin_enter(&sc->sc_intr_lock);
731
732 if (sc->sc_dying || !device_has_power(sc->sc_dev))
733 goto done;
734
735 /* If we get an interrupt while polling, then just ignore it. */
736 if (sc->sc_bus.ub_usepolling) {
737 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
738
739 if (intrs)
740 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
741 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
742 goto done;
743 }
744
745 ret = ehci_intr1(sc);
746
747 done:
748 mutex_spin_exit(&sc->sc_intr_lock);
749 return ret;
750 }
751
752 Static int
ehci_intr1(ehci_softc_t * sc)753 ehci_intr1(ehci_softc_t *sc)
754 {
755 uint32_t intrs, eintrs;
756
757 EHCIHIST_FUNC(); EHCIHIST_CALLED();
758
759 /* In case the interrupt occurs before initialization has completed. */
760 if (sc == NULL) {
761 #ifdef DIAGNOSTIC
762 printf("ehci_intr1: sc == NULL\n");
763 #endif
764 return 0;
765 }
766
767 KASSERT(mutex_owned(&sc->sc_intr_lock));
768
769 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
770 if (!intrs)
771 return 0;
772
773 eintrs = intrs & sc->sc_eintrs;
774 DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs,
775 EOREAD4(sc, EHCI_USBSTS), eintrs);
776 if (!eintrs)
777 return 0;
778
779 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
780 if (eintrs & EHCI_STS_IAA) {
781 DPRINTF("door bell", 0, 0, 0, 0);
782 kpreempt_disable();
783 KASSERT(sc->sc_doorbell_si != NULL);
784 softint_schedule(sc->sc_doorbell_si);
785 kpreempt_enable();
786 eintrs &= ~EHCI_STS_IAA;
787 }
788 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
789 DPRINTF("INT=%jd ERRINT=%jd",
790 eintrs & EHCI_STS_INT ? 1 : 0,
791 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0);
792 usb_schedsoftintr(&sc->sc_bus);
793 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
794 }
795 if (eintrs & EHCI_STS_HSE) {
796 printf("%s: unrecoverable error, controller halted\n",
797 device_xname(sc->sc_dev));
798 /* XXX what else */
799 }
800 if (eintrs & EHCI_STS_PCD) {
801 kpreempt_disable();
802 KASSERT(sc->sc_pcd_si != NULL);
803 softint_schedule(sc->sc_pcd_si);
804 kpreempt_enable();
805 eintrs &= ~EHCI_STS_PCD;
806 }
807
808 if (eintrs != 0) {
809 /* Block unprocessed interrupts. */
810 sc->sc_eintrs &= ~eintrs;
811 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
812 printf("%s: blocking intrs %#x\n",
813 device_xname(sc->sc_dev), eintrs);
814 }
815
816 return 1;
817 }
818
819 Static void
ehci_doorbell(void * addr)820 ehci_doorbell(void *addr)
821 {
822 ehci_softc_t *sc = addr;
823 EHCIHIST_FUNC(); EHCIHIST_CALLED();
824
825 mutex_enter(&sc->sc_lock);
826 if (sc->sc_doorbelllwp == NULL)
827 DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0);
828 sc->sc_doorbelllwp = NULL;
829 cv_signal(&sc->sc_doorbell);
830 mutex_exit(&sc->sc_lock);
831 }
832
833 Static void
ehci_pcd(void * addr)834 ehci_pcd(void *addr)
835 {
836 ehci_softc_t *sc = addr;
837 struct usbd_xfer *xfer;
838 u_char *p;
839 int i, m;
840
841 EHCIHIST_FUNC(); EHCIHIST_CALLED();
842
843 mutex_enter(&sc->sc_lock);
844 xfer = sc->sc_intrxfer;
845
846 if (xfer == NULL) {
847 /* Just ignore the change. */
848 goto done;
849 }
850 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
851
852 p = xfer->ux_buf;
853 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1);
854 memset(p, 0, xfer->ux_length);
855 for (i = 1; i <= m; i++) {
856 /* Pick out CHANGE bits from the status reg. */
857 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
858 p[i/8] |= 1 << (i%8);
859 if (i % 8 == 7)
860 DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0);
861 }
862 xfer->ux_actlen = xfer->ux_length;
863 xfer->ux_status = USBD_NORMAL_COMPLETION;
864
865 usb_transfer_complete(xfer);
866
867 done:
868 mutex_exit(&sc->sc_lock);
869 }
870
871 Static void
ehci_softintr(void * v)872 ehci_softintr(void *v)
873 {
874 struct usbd_bus *bus = v;
875 ehci_softc_t *sc = EHCI_BUS2SC(bus);
876 struct ehci_xfer *ex, *nextex;
877
878 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
879
880 EHCIHIST_FUNC(); EHCIHIST_CALLED();
881
882 ex_completeq_t cq;
883 TAILQ_INIT(&cq);
884
885 /*
886 * The only explanation I can think of for why EHCI is as brain dead
887 * as UHCI interrupt-wise is that Intel was involved in both.
888 * An interrupt just tells us that something is done, we have no
889 * clue what, so we need to scan through all active transfers. :-(
890 */
891
892 /*
893 * ehci_idone will remove transfer from sc->sc_intrhead if it's
894 * complete and add to our cq list
895 *
896 */
897 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) {
898 switch (ex->ex_type) {
899 case EX_CTRL:
900 case EX_BULK:
901 case EX_INTR:
902 ehci_check_qh_intr(sc, ex, &cq);
903 break;
904 case EX_ISOC:
905 ehci_check_itd_intr(sc, ex, &cq);
906 break;
907 case EX_FS_ISOC:
908 ehci_check_sitd_intr(sc, ex, &cq);
909 break;
910 default:
911 KASSERT(false);
912 }
913
914 }
915
916 /*
917 * We abuse ex_next for the interrupt and complete lists and
918 * interrupt transfers will get re-added here so use
919 * the _SAFE version of TAILQ_FOREACH.
920 */
921 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) {
922 usb_transfer_complete(&ex->ex_xfer);
923 }
924
925 /* Schedule a callout to catch any dropped transactions. */
926 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
927 !TAILQ_EMPTY(&sc->sc_intrhead))
928 callout_reset(&sc->sc_tmo_intrlist,
929 hz, ehci_intrlist_timeout, sc);
930 }
931
932 Static void
ehci_check_qh_intr(ehci_softc_t * sc,struct ehci_xfer * ex,ex_completeq_t * cq)933 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq)
934 {
935 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd;
936 uint32_t status;
937
938 EHCIHIST_FUNC(); EHCIHIST_CALLED();
939
940 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
941
942 if (ex->ex_type == EX_CTRL) {
943 fsqtd = ex->ex_setup;
944 lsqtd = ex->ex_status;
945 } else {
946 fsqtd = ex->ex_sqtdstart;
947 lsqtd = ex->ex_sqtdend;
948 }
949 KASSERTMSG(fsqtd != NULL && lsqtd != NULL,
950 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd);
951
952 /*
953 * If the last TD is still active we need to check whether there
954 * is an error somewhere in the middle, or whether there was a
955 * short packet (SPD and not ACTIVE).
956 */
957 usb_syncmem(&lsqtd->dma,
958 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
959 sizeof(lsqtd->qtd.qtd_status),
960 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
961 status = le32toh(lsqtd->qtd.qtd_status);
962 usb_syncmem(&lsqtd->dma,
963 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
964 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
965 if (status & EHCI_QTD_ACTIVE) {
966 DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0);
967
968 /* last qTD has already been checked */
969 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) {
970 usb_syncmem(&sqtd->dma,
971 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
972 sizeof(sqtd->qtd.qtd_status),
973 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
974 status = le32toh(sqtd->qtd.qtd_status);
975 usb_syncmem(&sqtd->dma,
976 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
977 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
978 /* If there's an active QTD the xfer isn't done. */
979 if (status & EHCI_QTD_ACTIVE)
980 break;
981 /* Any kind of error makes the xfer done. */
982 if (status & EHCI_QTD_HALTED)
983 goto done;
984 /* Handle short packets */
985 if (EHCI_QTD_GET_BYTES(status) != 0) {
986 /*
987 * If we get here for a control transfer then
988 * we need to let the hardware complete the
989 * status phase. That is, we're not done
990 * quite yet.
991 *
992 * Otherwise, we're done.
993 */
994 if (ex->ex_type == EX_CTRL) {
995 break;
996 }
997 goto done;
998 }
999 }
1000 DPRINTFN(10, "ex=%#jx std=%#jx still active",
1001 (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0);
1002 #ifdef EHCI_DEBUG
1003 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0);
1004 ehci_dump_sqtds(ex->ex_sqtdstart);
1005 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0);
1006 #endif
1007 return;
1008 }
1009 done:
1010 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0);
1011 ehci_idone(ex, cq);
1012 }
1013
1014 Static void
ehci_check_itd_intr(ehci_softc_t * sc,struct ehci_xfer * ex,ex_completeq_t * cq)1015 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq)
1016 {
1017 ehci_soft_itd_t *itd;
1018 int i;
1019
1020 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1021
1022 KASSERT(mutex_owned(&sc->sc_lock));
1023
1024 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue))
1025 return;
1026
1027 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL,
1028 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend);
1029
1030 itd = ex->ex_itdend;
1031
1032 /*
1033 * check no active transfers in last itd, meaning we're finished
1034 */
1035
1036 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
1037 sizeof(itd->itd.itd_ctl),
1038 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1039
1040 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1041 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
1042 break;
1043 }
1044
1045 if (i == EHCI_ITD_NUFRAMES) {
1046 goto done; /* All 8 descriptors inactive, it's done */
1047 }
1048
1049 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
1050 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD);
1051
1052 DPRINTFN(10, "ex %#jx itd %#jx still active",
1053 (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0);
1054 return;
1055 done:
1056 DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0);
1057 ehci_idone(ex, cq);
1058 }
1059
1060 void
ehci_check_sitd_intr(ehci_softc_t * sc,struct ehci_xfer * ex,ex_completeq_t * cq)1061 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq)
1062 {
1063 ehci_soft_sitd_t *sitd;
1064
1065 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1066
1067 KASSERT(mutex_owned(&sc->sc_lock));
1068
1069 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue))
1070 return;
1071
1072 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL,
1073 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend);
1074
1075 sitd = ex->ex_sitdend;
1076
1077 /*
1078 * check no active transfers in last sitd, meaning we're finished
1079 */
1080
1081 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1082 sizeof(sitd->sitd.sitd_trans),
1083 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1084
1085 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0);
1086
1087 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1088 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD);
1089
1090 if (active)
1091 return;
1092
1093 DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0);
1094 ehci_idone(ex, cq);
1095 }
1096
1097 Static void
ehci_idone(struct ehci_xfer * ex,ex_completeq_t * cq)1098 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq)
1099 {
1100 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1101 struct usbd_xfer *xfer = &ex->ex_xfer;
1102 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
1103 struct ehci_softc *sc = EHCI_XFER2SC(xfer);
1104 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd;
1105 uint32_t status = 0, nstatus = 0;
1106 int actlen = 0;
1107
1108 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1109
1110 DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0);
1111
1112 /*
1113 * Try to claim this xfer for completion. If it has already
1114 * completed or aborted, drop it on the floor.
1115 */
1116 if (!usbd_xfer_trycomplete(xfer))
1117 return;
1118
1119 #ifdef DIAGNOSTIC
1120 #ifdef EHCI_DEBUG
1121 if (ex->ex_isdone) {
1122 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1123 ehci_dump_exfer(ex);
1124 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1125 }
1126 #endif
1127 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer,
1128 ex->ex_type, xfer->ux_status);
1129 ex->ex_isdone = true;
1130 #endif
1131
1132 DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer,
1133 (uintptr_t)epipe, 0, 0);
1134
1135 /* The transfer is done, compute actual length and status. */
1136 if (ex->ex_type == EX_ISOC) {
1137 /* HS isoc transfer */
1138
1139 struct ehci_soft_itd *itd;
1140 int i, nframes, len, uframes;
1141
1142 nframes = 0;
1143
1144 #ifdef EHCI_DEBUG
1145 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1146 ehci_dump_itds(ex->ex_itdstart);
1147 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1148 #endif
1149
1150 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
1151 uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME);
1152
1153 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) {
1154 usb_syncmem(&itd->dma,
1155 itd->offs + offsetof(ehci_itd_t,itd_ctl),
1156 sizeof(itd->itd.itd_ctl),
1157 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1158
1159 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) {
1160 /*
1161 * XXX - driver didn't fill in the frame full
1162 * of uframes. This leads to scheduling
1163 * inefficiencies, but working around
1164 * this doubles complexity of tracking
1165 * an xfer.
1166 */
1167 if (nframes >= xfer->ux_nframes)
1168 break;
1169
1170 status = le32toh(itd->itd.itd_ctl[i]);
1171 len = EHCI_ITD_GET_LEN(status);
1172 if (EHCI_ITD_GET_STATUS(status) != 0)
1173 len = 0; /*No valid data on error*/
1174
1175 xfer->ux_frlengths[nframes++] = len;
1176 actlen += len;
1177 }
1178 usb_syncmem(&itd->dma,
1179 itd->offs + offsetof(ehci_itd_t,itd_ctl),
1180 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD);
1181
1182 if (nframes >= xfer->ux_nframes)
1183 break;
1184 }
1185
1186 xfer->ux_actlen = actlen;
1187 xfer->ux_status = USBD_NORMAL_COMPLETION;
1188 goto end;
1189 } else if (ex->ex_type == EX_FS_ISOC) {
1190 /* FS isoc transfer */
1191 struct ehci_soft_sitd *sitd;
1192 int nframes, len;
1193
1194 nframes = 0;
1195
1196 for (sitd = ex->ex_sitdstart; sitd != NULL;
1197 sitd = sitd->xfer_next) {
1198 usb_syncmem(&sitd->dma,
1199 sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1200 sizeof(sitd->sitd.sitd_trans),
1201 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1202
1203 /*
1204 * XXX - driver didn't fill in the frame full
1205 * of uframes. This leads to scheduling
1206 * inefficiencies, but working around
1207 * this doubles complexity of tracking
1208 * an xfer.
1209 */
1210 if (nframes >= xfer->ux_nframes)
1211 break;
1212
1213 status = le32toh(sitd->sitd.sitd_trans);
1214 usb_syncmem(&sitd->dma,
1215 sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1216 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD);
1217
1218 len = EHCI_SITD_GET_LEN(status);
1219 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR|
1220 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) {
1221 /* No valid data on error */
1222 len = xfer->ux_frlengths[nframes];
1223 }
1224
1225 /*
1226 * frlengths[i]: # of bytes to send
1227 * len: # of bytes host didn't send
1228 */
1229 xfer->ux_frlengths[nframes] -= len;
1230 /* frlengths[i]: # of bytes host sent */
1231 actlen += xfer->ux_frlengths[nframes++];
1232
1233 if (nframes >= xfer->ux_nframes)
1234 break;
1235 }
1236
1237 xfer->ux_actlen = actlen;
1238 xfer->ux_status = USBD_NORMAL_COMPLETION;
1239 goto end;
1240 }
1241 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR ||
1242 ex->ex_type == EX_BULK);
1243
1244 /* Continue processing xfers using queue heads */
1245 if (ex->ex_type == EX_CTRL) {
1246 fsqtd = ex->ex_setup;
1247 lsqtd = ex->ex_status;
1248 } else {
1249 fsqtd = ex->ex_sqtdstart;
1250 lsqtd = ex->ex_sqtdend;
1251 }
1252 #ifdef EHCI_DEBUG
1253 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1254 ehci_dump_sqtds(fsqtd);
1255 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1256 #endif
1257
1258 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) {
1259 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
1260 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1261 nstatus = le32toh(sqtd->qtd.qtd_status);
1262 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
1263 BUS_DMASYNC_PREREAD);
1264 if (nstatus & EHCI_QTD_ACTIVE)
1265 break;
1266
1267 status = nstatus;
1268 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
1269 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
1270 }
1271
1272 /*
1273 * If there are left over TDs we need to update the toggle.
1274 * The default pipe doesn't need it since control transfers
1275 * start the toggle at 0 every time.
1276 * For a short transfer we need to update the toggle for the missing
1277 * packets within the qTD.
1278 */
1279 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) &&
1280 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) {
1281 DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx",
1282 status, nstatus, 0, 0);
1283 #if 0
1284 ehci_dump_sqh(epipe->sqh);
1285 ehci_dump_sqtds(ex->ex_sqtdstart);
1286 #endif
1287 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus);
1288 }
1289
1290 DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen,
1291 status, 0);
1292 xfer->ux_actlen = actlen;
1293 if (status & EHCI_QTD_HALTED) {
1294 #ifdef EHCI_DEBUG
1295 DPRINTF("halted addr=%jd endpt=0x%02jx",
1296 xfer->ux_pipe->up_dev->ud_addr,
1297 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1298 0, 0);
1299 DPRINTF("cerr=%jd pid=%jd",
1300 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status),
1301 0, 0);
1302 DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd",
1303 status & EHCI_QTD_ACTIVE ? 1 : 0,
1304 status & EHCI_QTD_HALTED ? 1 : 0,
1305 status & EHCI_QTD_BUFERR ? 1 : 0,
1306 status & EHCI_QTD_BABBLE ? 1 : 0);
1307
1308 DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd",
1309 status & EHCI_QTD_XACTERR ? 1 : 0,
1310 status & EHCI_QTD_MISSEDMICRO ? 1 : 0,
1311 status & EHCI_QTD_SPLITXSTATE ? 1 : 0,
1312 status & EHCI_QTD_PINGSTATE ? 1 : 0);
1313
1314 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1315 ehci_dump_sqh(epipe->sqh);
1316 ehci_dump_sqtds(ex->ex_sqtdstart);
1317 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1318 #endif
1319 /* low&full speed has an extra error flag */
1320 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) !=
1321 EHCI_QH_SPEED_HIGH)
1322 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE;
1323 else
1324 status &= EHCI_QTD_STATERRS;
1325 if (status == 0) /* no other errors means a stall */ {
1326 xfer->ux_status = USBD_STALLED;
1327 } else {
1328 xfer->ux_status = USBD_IOERROR; /* more info XXX */
1329 }
1330 /* XXX need to reset TT on missed microframe */
1331 if (status & EHCI_QTD_MISSEDMICRO) {
1332 printf("%s: missed microframe, TT reset not "
1333 "implemented, hub might be inoperational\n",
1334 device_xname(sc->sc_dev));
1335 }
1336 } else {
1337 xfer->ux_status = USBD_NORMAL_COMPLETION;
1338 }
1339
1340 end:
1341
1342 ehci_del_intr_list(sc, ex);
1343 TAILQ_INSERT_TAIL(cq, ex, ex_next);
1344
1345 DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0);
1346 }
1347
1348 Static void
ehci_poll(struct usbd_bus * bus)1349 ehci_poll(struct usbd_bus *bus)
1350 {
1351 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1352
1353 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1354
1355 #ifdef EHCI_DEBUG
1356 static int last;
1357 int new;
1358 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1359 if (new != last) {
1360 DPRINTF("intrs=0x%04jx", new, 0, 0, 0);
1361 last = new;
1362 }
1363 #endif
1364
1365 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) {
1366 mutex_spin_enter(&sc->sc_intr_lock);
1367 ehci_intr1(sc);
1368 mutex_spin_exit(&sc->sc_intr_lock);
1369 }
1370 }
1371
1372 void
ehci_childdet(device_t self,device_t child)1373 ehci_childdet(device_t self, device_t child)
1374 {
1375 struct ehci_softc *sc = device_private(self);
1376
1377 KASSERT(sc->sc_child == child);
1378 sc->sc_child = NULL;
1379 }
1380
1381 int
ehci_detach(struct ehci_softc * sc,int flags)1382 ehci_detach(struct ehci_softc *sc, int flags)
1383 {
1384 int rv = 0;
1385
1386 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1387
1388 if (sc->sc_child != NULL) {
1389 rv = config_detach(sc->sc_child, flags);
1390 if (rv != 0)
1391 return rv;
1392 }
1393
1394 if (sc->sc_ncomp > 0) {
1395 mutex_enter(&sc->sc_complock);
1396 /* XXX try to halt callout instead of waiting */
1397 while (sc->sc_comp_state == CO_SCHED)
1398 cv_wait(&sc->sc_compcv, &sc->sc_complock);
1399 mutex_exit(&sc->sc_complock);
1400
1401 callout_halt(&sc->sc_compcallout, NULL);
1402 callout_destroy(&sc->sc_compcallout);
1403 cv_destroy(&sc->sc_compcv);
1404 mutex_destroy(&sc->sc_complock);
1405 }
1406
1407 callout_halt(&sc->sc_tmo_intrlist, NULL);
1408 callout_destroy(&sc->sc_tmo_intrlist);
1409
1410 /* XXX free other data structures */
1411 if (sc->sc_softitds) {
1412 kmem_free(sc->sc_softitds,
1413 sc->sc_flsize * sizeof(ehci_soft_itd_t *));
1414 }
1415 cv_destroy(&sc->sc_doorbell);
1416
1417 #if 0
1418 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */
1419 softint_disestablish(sc->sc_doorbell_si);
1420 softint_disestablish(sc->sc_pcd_si);
1421 mutex_destroy(&sc->sc_rhlock);
1422 mutex_destroy(&sc->sc_lock);
1423 mutex_destroy(&sc->sc_intr_lock);
1424 #endif
1425
1426 pool_cache_destroy(sc->sc_xferpool);
1427
1428 EOWRITE4(sc, EHCI_CONFIGFLAG, 0);
1429
1430 return rv;
1431 }
1432
1433 int
ehci_activate(device_t self,enum devact act)1434 ehci_activate(device_t self, enum devact act)
1435 {
1436 struct ehci_softc *sc = device_private(self);
1437
1438 switch (act) {
1439 case DVACT_DEACTIVATE:
1440 sc->sc_dying = 1;
1441 return 0;
1442 default:
1443 return EOPNOTSUPP;
1444 }
1445 }
1446
1447 /*
1448 * Handle suspend/resume.
1449 *
1450 * Note that this power handler isn't to be registered directly; the
1451 * bus glue needs to call out to it.
1452 */
1453 bool
ehci_suspend(device_t dv,const pmf_qual_t * qual)1454 ehci_suspend(device_t dv, const pmf_qual_t *qual)
1455 {
1456 ehci_softc_t *sc = device_private(dv);
1457 int i;
1458 uint32_t cmd, hcr;
1459
1460 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1461
1462 mutex_enter(&sc->sc_rhlock);
1463
1464 for (i = 1; i <= sc->sc_noport; i++) {
1465 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1466 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE)
1467 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP);
1468 }
1469
1470 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
1471
1472 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
1473 EOWRITE4(sc, EHCI_USBCMD, cmd);
1474
1475 for (i = 0; i < 100; i++) {
1476 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS);
1477 if (hcr == 0)
1478 break;
1479
1480 usb_delay_ms(&sc->sc_bus, 1);
1481 }
1482 if (hcr != 0)
1483 printf("%s: reset timeout\n", device_xname(dv));
1484
1485 cmd &= ~EHCI_CMD_RS;
1486 EOWRITE4(sc, EHCI_USBCMD, cmd);
1487
1488 for (i = 0; i < 100; i++) {
1489 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1490 if (hcr == EHCI_STS_HCH)
1491 break;
1492
1493 usb_delay_ms(&sc->sc_bus, 1);
1494 }
1495 if (hcr != EHCI_STS_HCH)
1496 printf("%s: config timeout\n", device_xname(dv));
1497
1498 mutex_exit(&sc->sc_rhlock);
1499
1500 return true;
1501 }
1502
1503 bool
ehci_resume(device_t dv,const pmf_qual_t * qual)1504 ehci_resume(device_t dv, const pmf_qual_t *qual)
1505 {
1506 ehci_softc_t *sc = device_private(dv);
1507 int i;
1508 uint32_t cmd, hcr;
1509
1510 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1511
1512 mutex_enter(&sc->sc_rhlock);
1513
1514 /* restore things in case the bios sucks */
1515 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1516 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1517 EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1518 sc->sc_async_head->physaddr | EHCI_LINK_QH);
1519
1520 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE);
1521
1522 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1523
1524 hcr = 0;
1525 for (i = 1; i <= sc->sc_noport; i++) {
1526 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1527 if ((cmd & EHCI_PS_PO) == 0 &&
1528 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
1529 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR);
1530 hcr = 1;
1531 }
1532 }
1533
1534 if (hcr) {
1535 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1536
1537 for (i = 1; i <= sc->sc_noport; i++) {
1538 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1539 if ((cmd & EHCI_PS_PO) == 0 &&
1540 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1541 EOWRITE4(sc, EHCI_PORTSC(i),
1542 cmd & ~EHCI_PS_FPR);
1543 }
1544 }
1545
1546 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1547 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1548
1549 for (i = 0; i < 100; i++) {
1550 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1551 if (hcr != EHCI_STS_HCH)
1552 break;
1553
1554 usb_delay_ms(&sc->sc_bus, 1);
1555 }
1556 if (hcr == EHCI_STS_HCH)
1557 printf("%s: config timeout\n", device_xname(dv));
1558
1559 mutex_exit(&sc->sc_rhlock);
1560
1561 return true;
1562 }
1563
1564 /*
1565 * Shut down the controller when the system is going down.
1566 */
1567 bool
ehci_shutdown(device_t self,int flags)1568 ehci_shutdown(device_t self, int flags)
1569 {
1570 ehci_softc_t *sc = device_private(self);
1571
1572 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1573
1574 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1575 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1576 return true;
1577 }
1578
1579 Static struct usbd_xfer *
ehci_allocx(struct usbd_bus * bus,unsigned int nframes)1580 ehci_allocx(struct usbd_bus *bus, unsigned int nframes)
1581 {
1582 struct ehci_softc *sc = EHCI_BUS2SC(bus);
1583 struct usbd_xfer *xfer;
1584
1585 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
1586 if (xfer != NULL) {
1587 memset(xfer, 0, sizeof(struct ehci_xfer));
1588
1589 #ifdef DIAGNOSTIC
1590 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
1591 ex->ex_isdone = true;
1592 xfer->ux_state = XFER_BUSY;
1593 #endif
1594 }
1595 return xfer;
1596 }
1597
1598 Static void
ehci_freex(struct usbd_bus * bus,struct usbd_xfer * xfer)1599 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1600 {
1601 struct ehci_softc *sc = EHCI_BUS2SC(bus);
1602 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer);
1603
1604 KASSERTMSG(xfer->ux_state == XFER_BUSY ||
1605 xfer->ux_status == USBD_NOT_STARTED,
1606 "xfer %p state %d\n", xfer, xfer->ux_state);
1607 KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED);
1608
1609 #ifdef DIAGNOSTIC
1610 xfer->ux_state = XFER_FREE;
1611 #endif
1612
1613 pool_cache_put(sc->sc_xferpool, xfer);
1614 }
1615
1616 Static bool
ehci_dying(struct usbd_bus * bus)1617 ehci_dying(struct usbd_bus *bus)
1618 {
1619 struct ehci_softc *sc = EHCI_BUS2SC(bus);
1620
1621 return sc->sc_dying;
1622 }
1623
1624 Static void
ehci_get_lock(struct usbd_bus * bus,kmutex_t ** lock)1625 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1626 {
1627 struct ehci_softc *sc = EHCI_BUS2SC(bus);
1628
1629 *lock = &sc->sc_lock;
1630 }
1631
1632 Static void
ehci_device_clear_toggle(struct usbd_pipe * pipe)1633 ehci_device_clear_toggle(struct usbd_pipe *pipe)
1634 {
1635 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
1636
1637 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1638
1639 DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe,
1640 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0);
1641 #ifdef EHCI_DEBUG
1642 if (ehcidebug)
1643 usbd_dump_pipe(pipe);
1644 #endif
1645 epipe->nexttoggle = 0;
1646 }
1647
1648 Static void
ehci_noop(struct usbd_pipe * pipe)1649 ehci_noop(struct usbd_pipe *pipe)
1650 {
1651 }
1652
1653 #ifdef EHCI_DEBUG
1654 /*
1655 * Unused function - this is meant to be called from a kernel
1656 * debugger.
1657 */
1658 void
ehci_dump(void)1659 ehci_dump(void)
1660 {
1661 ehci_softc_t *sc = theehci;
1662 int i;
1663 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1664 EOREAD4(sc, EHCI_USBCMD),
1665 EOREAD4(sc, EHCI_USBSTS),
1666 EOREAD4(sc, EHCI_USBINTR));
1667 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1668 EOREAD4(sc, EHCI_FRINDEX),
1669 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1670 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1671 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1672 for (i = 1; i <= sc->sc_noport; i++)
1673 printf("port %d status=0x%08x\n", i,
1674 EOREAD4(sc, EHCI_PORTSC(i)));
1675 }
1676
1677 Static void
ehci_dump_regs(ehci_softc_t * sc)1678 ehci_dump_regs(ehci_softc_t *sc)
1679 {
1680 int i;
1681
1682 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1683
1684 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx",
1685 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS),
1686 EOREAD4(sc, EHCI_USBINTR), 0);
1687 DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx "
1688 "async = 0x%08jx",
1689 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1690 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1691 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1692 for (i = 1; i <= sc->sc_noport; i += 2) {
1693 if (i == sc->sc_noport) {
1694 DPRINTF("port %jd status = 0x%08jx", i,
1695 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0);
1696 } else {
1697 DPRINTF("port %jd status = 0x%08jx port %jd "
1698 "status = 0x%08jx",
1699 i, EOREAD4(sc, EHCI_PORTSC(i)),
1700 i+1, EOREAD4(sc, EHCI_PORTSC(i+1)));
1701 }
1702 }
1703 }
1704
1705 #define ehci_dump_link(link, type) do { \
1706 DPRINTF(" link 0x%08jx (T = %jd):", \
1707 link, \
1708 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \
1709 if (type) { \
1710 DPRINTF( \
1711 " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\
1712 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \
1713 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \
1714 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \
1715 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \
1716 } \
1717 } while(0)
1718
1719 Static void
ehci_dump_sqtds(ehci_soft_qtd_t * sqtd)1720 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1721 {
1722 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1723 int i;
1724 uint32_t stop = 0;
1725
1726 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1727 ehci_dump_sqtd(sqtd);
1728 usb_syncmem(&sqtd->dma,
1729 sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1730 sizeof(sqtd->qtd),
1731 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1732 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1733 usb_syncmem(&sqtd->dma,
1734 sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1735 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1736 }
1737 if (!stop)
1738 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0);
1739 }
1740
1741 Static void
ehci_dump_sqtd(ehci_soft_qtd_t * sqtd)1742 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1743 {
1744 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1745
1746 usb_syncmem(&sqtd->dma, sqtd->offs,
1747 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1748
1749 DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr,
1750 0, 0);
1751 ehci_dump_qtd(&sqtd->qtd);
1752
1753 usb_syncmem(&sqtd->dma, sqtd->offs,
1754 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1755 }
1756
1757 Static void
ehci_dump_qtd(ehci_qtd_t * qtd)1758 ehci_dump_qtd(ehci_qtd_t *qtd)
1759 {
1760 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1761 uint32_t s = le32toh(qtd->qtd_status);
1762
1763 DPRINTFN(10,
1764 " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx",
1765 qtd->qtd_next, qtd->qtd_altnext, s, 0);
1766 DPRINTFN(10,
1767 " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx",
1768 EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s),
1769 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s));
1770 DPRINTFN(10,
1771 " cerr = %jd pid = %jd stat = %jx",
1772 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s),
1773 0);
1774 DPRINTFN(10,
1775 "active =%jd halted=%jd buferr=%jd babble=%jd",
1776 s & EHCI_QTD_ACTIVE ? 1 : 0,
1777 s & EHCI_QTD_HALTED ? 1 : 0,
1778 s & EHCI_QTD_BUFERR ? 1 : 0,
1779 s & EHCI_QTD_BABBLE ? 1 : 0);
1780 DPRINTFN(10,
1781 "xacterr=%jd missed=%jd split =%jd ping =%jd",
1782 s & EHCI_QTD_XACTERR ? 1 : 0,
1783 s & EHCI_QTD_MISSEDMICRO ? 1 : 0,
1784 s & EHCI_QTD_SPLITXSTATE ? 1 : 0,
1785 s & EHCI_QTD_PINGSTATE ? 1 : 0);
1786 DPRINTFN(10,
1787 "buffer[0] = %#jx buffer[1] = %#jx "
1788 "buffer[2] = %#jx buffer[3] = %#jx",
1789 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]),
1790 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3]));
1791 DPRINTFN(10,
1792 "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0);
1793 }
1794
1795 Static void
ehci_dump_sqh(ehci_soft_qh_t * sqh)1796 ehci_dump_sqh(ehci_soft_qh_t *sqh)
1797 {
1798 ehci_qh_t *qh = &sqh->qh;
1799 ehci_link_t link;
1800 uint32_t endp, endphub;
1801 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1802
1803 usb_syncmem(&sqh->dma, sqh->offs,
1804 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1805
1806 DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0);
1807 link = le32toh(qh->qh_link);
1808 ehci_dump_link(link, true);
1809
1810 endp = le32toh(qh->qh_endp);
1811 DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0);
1812 DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd "
1813 "eps = %jd",
1814 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1815 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp));
1816 DPRINTFN(10, " dtc = %jd hrecl = %jd",
1817 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0);
1818 DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)",
1819 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp),
1820 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp));
1821
1822 endphub = le32toh(qh->qh_endphub);
1823 DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0);
1824 DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx",
1825 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0);
1826 DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd",
1827 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1828 EHCI_QH_GET_MULT(endphub), 0);
1829
1830 link = le32toh(qh->qh_curqtd);
1831 ehci_dump_link(link, false);
1832 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0);
1833 ehci_dump_qtd(&qh->qh_qtd);
1834
1835 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1836 BUS_DMASYNC_PREREAD);
1837 }
1838
1839 Static void
ehci_dump_itds(ehci_soft_itd_t * itd)1840 ehci_dump_itds(ehci_soft_itd_t *itd)
1841 {
1842 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1843 int i;
1844 uint32_t stop = 0;
1845
1846 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) {
1847 ehci_dump_itd(itd);
1848 usb_syncmem(&itd->dma,
1849 itd->offs + offsetof(ehci_itd_t, itd_next),
1850 sizeof(itd->itd),
1851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1852 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE);
1853 usb_syncmem(&itd->dma,
1854 itd->offs + offsetof(ehci_itd_t, itd_next),
1855 sizeof(itd->itd), BUS_DMASYNC_PREREAD);
1856 }
1857 if (!stop)
1858 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0);
1859 }
1860
1861 Static void
ehci_dump_itd(struct ehci_soft_itd * itd)1862 ehci_dump_itd(struct ehci_soft_itd *itd)
1863 {
1864 ehci_isoc_trans_t t;
1865 ehci_isoc_bufr_ptr_t b, b2, b3;
1866 int i;
1867
1868 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1869
1870 DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0);
1871
1872 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1873 t = le32toh(itd->itd.itd_ctl[i]);
1874 DPRINTF("ITDctl %jd: stat = %jx len = %jx",
1875 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0);
1876 DPRINTF(" ioc = %jx pg = %jx offs = %jx",
1877 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t),
1878 EHCI_ITD_GET_OFFS(t), 0);
1879 }
1880 DPRINTF("ITDbufr: ", 0, 0, 0, 0);
1881 for (i = 0; i < EHCI_ITD_NBUFFERS; i++)
1882 DPRINTF(" %jx",
1883 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0);
1884
1885 b = le32toh(itd->itd.itd_bufr[0]);
1886 b2 = le32toh(itd->itd.itd_bufr[1]);
1887 b3 = le32toh(itd->itd.itd_bufr[2]);
1888 DPRINTF(" ep = %jx daddr = %jx dir = %jd",
1889 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0);
1890 DPRINTF(" maxpkt = %jx multi = %jx",
1891 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0);
1892 }
1893
1894 Static void
ehci_dump_sitd(struct ehci_soft_itd * itd)1895 ehci_dump_sitd(struct ehci_soft_itd *itd)
1896 {
1897 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1898
1899 DPRINTF("SITD %#jx next = %p prev = %#jx",
1900 (uintptr_t)itd, (uintptr_t)itd->frame_list.next,
1901 (uintptr_t)itd->frame_list.prev, 0);
1902 DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd",
1903 (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0);
1904 }
1905
1906 Static void
ehci_dump_exfer(struct ehci_xfer * ex)1907 ehci_dump_exfer(struct ehci_xfer *ex)
1908 {
1909 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1910
1911 DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type,
1912 ex->ex_isdone, 0);
1913
1914 switch (ex->ex_type) {
1915 case EX_CTRL:
1916 DPRINTF(" setup = %#jx data = %#jx status = %#jx",
1917 (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data,
1918 (uintptr_t)ex->ex_status, 0);
1919 break;
1920 case EX_BULK:
1921 case EX_INTR:
1922 DPRINTF(" qtdstart = %#jx qtdend = %#jx",
1923 (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend,
1924 0, 0);
1925 break;
1926 case EX_ISOC:
1927 DPRINTF(" itdstart = %#jx itdend = %#jx",
1928 (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0);
1929 break;
1930 case EX_FS_ISOC:
1931 DPRINTF(" sitdstart = %#jx sitdend = %#jx",
1932 (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend,
1933 0, 0);
1934 break;
1935 default:
1936 DPRINTF(" unknown type", 0, 0, 0, 0);
1937 }
1938 }
1939 #endif
1940
1941 Static usbd_status
ehci_open(struct usbd_pipe * pipe)1942 ehci_open(struct usbd_pipe *pipe)
1943 {
1944 struct usbd_device *dev = pipe->up_dev;
1945 ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
1946 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
1947 uint8_t rhaddr = dev->ud_bus->ub_rhaddr;
1948 uint8_t addr = dev->ud_addr;
1949 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1950 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
1951 ehci_soft_qh_t *sqh;
1952 usbd_status err;
1953 int ival, speed, naks;
1954 int hshubaddr, hshubport;
1955
1956 EHCIHIST_FUNC(); EHCIHIST_CALLED();
1957
1958 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr,
1959 ed->bEndpointAddress, rhaddr);
1960
1961 if (dev->ud_myhsport) {
1962 /*
1963 * When directly attached FS/LS device while doing embedded
1964 * transaction translations and we are the hub, set the hub
1965 * address to 0 (us).
1966 */
1967 if (!(sc->sc_flags & EHCIF_ETTF)
1968 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) {
1969 hshubaddr = dev->ud_myhsport->up_parent->ud_addr;
1970 } else {
1971 hshubaddr = 0;
1972 }
1973 hshubport = dev->ud_myhsport->up_portno;
1974 } else {
1975 hshubaddr = 0;
1976 hshubport = 0;
1977 }
1978
1979 if (sc->sc_dying)
1980 return USBD_IOERROR;
1981
1982 /* toggle state needed for bulk endpoints */
1983 epipe->nexttoggle = pipe->up_endpoint->ue_toggle;
1984
1985 if (addr == rhaddr) {
1986 switch (ed->bEndpointAddress) {
1987 case USB_CONTROL_ENDPOINT:
1988 pipe->up_methods = &roothub_ctrl_methods;
1989 break;
1990 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1991 pipe->up_methods = &ehci_root_intr_methods;
1992 break;
1993 default:
1994 DPRINTF("bad bEndpointAddress 0x%02jx",
1995 ed->bEndpointAddress, 0, 0, 0);
1996 return USBD_INVAL;
1997 }
1998 return USBD_NORMAL_COMPLETION;
1999 }
2000
2001 /* XXX All this stuff is only valid for async. */
2002 switch (dev->ud_speed) {
2003 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
2004 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
2005 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
2006 default: panic("ehci_open: bad device speed %d", dev->ud_speed);
2007 }
2008 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) {
2009 DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0,
2010 0);
2011 return USBD_INVAL;
2012 }
2013
2014 /*
2015 * For interrupt transfer, nak throttling must be disabled, but for
2016 * the other transfer type, nak throttling should be enabled from the
2017 * viewpoint that avoids the memory thrashing.
2018 */
2019 naks = (xfertype == UE_INTERRUPT) ? 0
2020 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0);
2021
2022 /* Allocate sqh for everything, save isoc xfers */
2023 if (xfertype != UE_ISOCHRONOUS) {
2024 sqh = ehci_alloc_sqh(sc);
2025 if (sqh == NULL)
2026 return USBD_NOMEM;
2027 /* qh_link filled when the QH is added */
2028 sqh->qh.qh_endp = htole32(
2029 EHCI_QH_SET_ADDR(addr) |
2030 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
2031 EHCI_QH_SET_EPS(speed) |
2032 EHCI_QH_DTC |
2033 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
2034 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
2035 EHCI_QH_CTL : 0) |
2036 EHCI_QH_SET_NRL(naks)
2037 );
2038 sqh->qh.qh_endphub = htole32(
2039 EHCI_QH_SET_MULT(1) |
2040 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0)
2041 );
2042 if (speed != EHCI_QH_SPEED_HIGH)
2043 sqh->qh.qh_endphub |= htole32(
2044 EHCI_QH_SET_PORT(hshubport) |
2045 EHCI_QH_SET_HUBA(hshubaddr) |
2046 (xfertype == UE_INTERRUPT ?
2047 EHCI_QH_SET_CMASK(0x08) : 0)
2048 );
2049 sqh->qh.qh_curqtd = EHCI_NULL;
2050 /* Fill the overlay qTD */
2051 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
2052 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
2053 sqh->qh.qh_qtd.qtd_status = htole32(0);
2054
2055 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
2056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2057 epipe->sqh = sqh;
2058 } else {
2059 sqh = NULL;
2060 } /*xfertype == UE_ISOC*/
2061
2062 switch (xfertype) {
2063 case UE_CONTROL:
2064 /* we can use 64bit DMA for the reqdma buffer */
2065 err = usb_allocmem(sc->sc_bus.ub_dmatag,
2066 sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT,
2067 &epipe->ctrl.reqdma);
2068 #ifdef EHCI_DEBUG
2069 if (err)
2070 printf("ehci_open: usb_allocmem()=%d\n", err);
2071 #endif
2072 if (err)
2073 goto bad;
2074 pipe->up_methods = &ehci_device_ctrl_methods;
2075 mutex_enter(&sc->sc_lock);
2076 ehci_add_qh(sc, sqh, sc->sc_async_head);
2077 mutex_exit(&sc->sc_lock);
2078 break;
2079 case UE_BULK:
2080 pipe->up_methods = &ehci_device_bulk_methods;
2081 mutex_enter(&sc->sc_lock);
2082 ehci_add_qh(sc, sqh, sc->sc_async_head);
2083 mutex_exit(&sc->sc_lock);
2084 break;
2085 case UE_INTERRUPT:
2086 pipe->up_methods = &ehci_device_intr_methods;
2087 ival = pipe->up_interval;
2088 if (ival == USBD_DEFAULT_INTERVAL) {
2089 if (speed == EHCI_QH_SPEED_HIGH) {
2090 if (ed->bInterval > 16) {
2091 /*
2092 * illegal with high-speed, but there
2093 * were documentation bugs in the spec,
2094 * so be generous
2095 */
2096 ival = 256;
2097 } else
2098 ival = (1 << (ed->bInterval - 1)) / 8;
2099 } else
2100 ival = ed->bInterval;
2101 }
2102 err = ehci_device_setintr(sc, sqh, ival);
2103 if (err)
2104 goto bad;
2105 break;
2106 case UE_ISOCHRONOUS:
2107 pipe->up_serialise = false;
2108 if (speed == EHCI_QH_SPEED_HIGH)
2109 pipe->up_methods = &ehci_device_isoc_methods;
2110 else
2111 pipe->up_methods = &ehci_device_fs_isoc_methods;
2112 if (ed->bInterval == 0 || ed->bInterval > 16) {
2113 printf("ehci: opening pipe with invalid bInterval\n");
2114 err = USBD_INVAL;
2115 goto bad;
2116 }
2117 if (UGETW(ed->wMaxPacketSize) == 0) {
2118 printf("ehci: zero length endpoint open request\n");
2119 err = USBD_INVAL;
2120 goto bad;
2121 }
2122 epipe->isoc.next_frame = 0;
2123 epipe->isoc.cur_xfers = 0;
2124 break;
2125 default:
2126 DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0);
2127 err = USBD_INVAL;
2128 goto bad;
2129 }
2130 return USBD_NORMAL_COMPLETION;
2131
2132 bad:
2133 if (sqh != NULL) {
2134 mutex_enter(&sc->sc_lock);
2135 ehci_free_sqh(sc, sqh);
2136 mutex_exit(&sc->sc_lock);
2137 }
2138 return err;
2139 }
2140
2141 /*
2142 * Add an ED to the schedule. Called with USB lock held.
2143 */
2144 Static void
ehci_add_qh(ehci_softc_t * sc,ehci_soft_qh_t * sqh,ehci_soft_qh_t * head)2145 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
2146 {
2147
2148 KASSERT(mutex_owned(&sc->sc_lock));
2149
2150 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2151
2152 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
2153 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE);
2154
2155 sqh->next = head->next;
2156 sqh->qh.qh_link = head->qh.qh_link;
2157
2158 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
2159 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE);
2160
2161 head->next = sqh;
2162 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
2163
2164 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
2165 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE);
2166
2167 #ifdef EHCI_DEBUG
2168 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
2169 ehci_dump_sqh(sqh);
2170 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
2171 #endif
2172 }
2173
2174 /*
2175 * Remove an ED from the schedule. Called with USB lock held.
2176 */
2177 Static void
ehci_rem_qh(ehci_softc_t * sc,ehci_soft_qh_t * sqh,ehci_soft_qh_t * head)2178 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
2179 {
2180 ehci_soft_qh_t *p;
2181
2182 KASSERT(mutex_owned(&sc->sc_lock));
2183
2184 /* XXX */
2185 for (p = head; p != NULL && p->next != sqh; p = p->next)
2186 ;
2187 if (p == NULL)
2188 panic("ehci_rem_qh: ED not found");
2189 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
2190 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE);
2191 p->next = sqh->next;
2192 p->qh.qh_link = sqh->qh.qh_link;
2193 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link),
2194 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE);
2195
2196 ehci_sync_hc(sc);
2197 }
2198
2199 Static void
ehci_set_qh_qtd(ehci_soft_qh_t * sqh,ehci_soft_qtd_t * sqtd)2200 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
2201 {
2202 int i;
2203 uint32_t status;
2204
2205 /* Save toggle bit and ping status. */
2206 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
2207 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2208 status = sqh->qh.qh_qtd.qtd_status &
2209 htole32(EHCI_QTD_TOGGLE_MASK |
2210 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
2211 /* Set HALTED to make hw leave it alone. */
2212 sqh->qh.qh_qtd.qtd_status =
2213 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
2214 usb_syncmem(&sqh->dma,
2215 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2216 sizeof(sqh->qh.qh_qtd.qtd_status),
2217 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2218 sqh->qh.qh_curqtd = 0;
2219 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
2220 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
2221 for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
2222 sqh->qh.qh_qtd.qtd_buffer[i] = 0;
2223 sqh->sqtd = sqtd;
2224 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
2225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2226 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
2227 sqh->qh.qh_qtd.qtd_status = status;
2228 usb_syncmem(&sqh->dma,
2229 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2230 sizeof(sqh->qh.qh_qtd.qtd_status),
2231 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2232 }
2233
2234 /*
2235 * Ensure that the HC has released all references to the QH. We do this
2236 * by asking for a Async Advance Doorbell interrupt and then we wait for
2237 * the interrupt.
2238 * To make this easier we first obtain exclusive use of the doorbell.
2239 *
2240 * Releases the bus lock to sleep while waiting for interrupt.
2241 */
2242 Static void
ehci_sync_hc(ehci_softc_t * sc)2243 ehci_sync_hc(ehci_softc_t *sc)
2244 {
2245 unsigned delta = hz;
2246 unsigned starttime = getticks();
2247 unsigned endtime = starttime + delta;
2248 unsigned now;
2249
2250 KASSERT(mutex_owned(&sc->sc_lock));
2251
2252 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2253
2254 if (sc->sc_dying) {
2255 DPRINTF("dying", 0, 0, 0, 0);
2256 return;
2257 }
2258
2259 /*
2260 * Wait until any concurrent ehci_sync_hc has completed so we
2261 * have exclusive access to the doorbell.
2262 */
2263 while (sc->sc_doorbelllwp)
2264 cv_wait(&sc->sc_doorbell, &sc->sc_lock);
2265 sc->sc_doorbelllwp = curlwp;
2266
2267 /* ask for doorbell */
2268 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
2269 DPRINTF("cmd = 0x%08jx sts = 0x%08jx",
2270 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0);
2271
2272 /*
2273 * Wait for the ehci to ring our doorbell.
2274 */
2275 while (sc->sc_doorbelllwp == curlwp) {
2276 now = getticks();
2277 if (endtime - now > delta) {
2278 sc->sc_doorbelllwp = NULL;
2279 cv_signal(&sc->sc_doorbell);
2280 DPRINTF("doorbell timeout", 0, 0, 0, 0);
2281 #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */
2282 printf("ehci_sync_hc: timed out\n");
2283 #endif
2284 break;
2285 }
2286 (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock,
2287 endtime - now);
2288 }
2289
2290 DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done",
2291 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0);
2292 }
2293
2294 Static void
ehci_remove_itd_chain(ehci_softc_t * sc,struct ehci_soft_itd * itd)2295 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd)
2296 {
2297
2298 KASSERT(mutex_owned(&sc->sc_lock));
2299
2300 for (; itd != NULL; itd = itd->xfer_next) {
2301 struct ehci_soft_itd *prev = itd->frame_list.prev;
2302
2303 /* Unlink itd from hardware chain, or frame array */
2304 if (prev == NULL) { /* We're at the table head */
2305 sc->sc_softitds[itd->slot] = itd->frame_list.next;
2306 sc->sc_flist[itd->slot] = itd->itd.itd_next;
2307 usb_syncmem(&sc->sc_fldma,
2308 sizeof(ehci_link_t) * itd->slot,
2309 sizeof(ehci_link_t),
2310 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2311
2312 if (itd->frame_list.next != NULL)
2313 itd->frame_list.next->frame_list.prev = NULL;
2314 } else {
2315 /* XXX this part is untested... */
2316 prev->itd.itd_next = itd->itd.itd_next;
2317 usb_syncmem(&itd->dma,
2318 itd->offs + offsetof(ehci_itd_t, itd_next),
2319 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE);
2320
2321 prev->frame_list.next = itd->frame_list.next;
2322 if (itd->frame_list.next != NULL)
2323 itd->frame_list.next->frame_list.prev = prev;
2324 }
2325 }
2326 }
2327
2328 Static void
ehci_free_itd_chain(ehci_softc_t * sc,struct ehci_soft_itd * itd)2329 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd)
2330 {
2331 struct ehci_soft_itd *next;
2332
2333 mutex_enter(&sc->sc_lock);
2334 next = NULL;
2335 for (; itd != NULL; itd = next) {
2336 next = itd->xfer_next;
2337 ehci_free_itd_locked(sc, itd);
2338 }
2339 mutex_exit(&sc->sc_lock);
2340 }
2341
2342 Static void
ehci_remove_sitd_chain(ehci_softc_t * sc,struct ehci_soft_sitd * sitd)2343 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd)
2344 {
2345
2346 KASSERT(mutex_owned(&sc->sc_lock));
2347
2348 for (; sitd != NULL; sitd = sitd->xfer_next) {
2349 struct ehci_soft_sitd *prev = sitd->frame_list.prev;
2350
2351 /* Unlink sitd from hardware chain, or frame array */
2352 if (prev == NULL) { /* We're at the table head */
2353 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next;
2354 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next;
2355 usb_syncmem(&sc->sc_fldma,
2356 sizeof(ehci_link_t) * sitd->slot,
2357 sizeof(ehci_link_t),
2358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2359
2360 if (sitd->frame_list.next != NULL)
2361 sitd->frame_list.next->frame_list.prev = NULL;
2362 } else {
2363 /* XXX this part is untested... */
2364 prev->sitd.sitd_next = sitd->sitd.sitd_next;
2365 usb_syncmem(&sitd->dma,
2366 sitd->offs + offsetof(ehci_sitd_t, sitd_next),
2367 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE);
2368
2369 prev->frame_list.next = sitd->frame_list.next;
2370 if (sitd->frame_list.next != NULL)
2371 sitd->frame_list.next->frame_list.prev = prev;
2372 }
2373 }
2374 }
2375
2376 Static void
ehci_free_sitd_chain(ehci_softc_t * sc,struct ehci_soft_sitd * sitd)2377 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd)
2378 {
2379
2380 mutex_enter(&sc->sc_lock);
2381 struct ehci_soft_sitd *next = NULL;
2382 for (; sitd != NULL; sitd = next) {
2383 next = sitd->xfer_next;
2384 ehci_free_sitd_locked(sc, sitd);
2385 }
2386 mutex_exit(&sc->sc_lock);
2387 }
2388
2389 /***********/
2390
2391 static int
ehci_roothub_ctrl_locked(struct usbd_bus * bus,usb_device_request_t * req,void * buf,int buflen)2392 ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req,
2393 void *buf, int buflen)
2394 {
2395 ehci_softc_t *sc = EHCI_BUS2SC(bus);
2396 usb_hub_descriptor_t hubd;
2397 usb_port_status_t ps;
2398 uint16_t len, value, index;
2399 int l, totlen = 0;
2400 int port, i;
2401 uint32_t v;
2402
2403 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2404
2405 KASSERT(mutex_owned(&sc->sc_rhlock));
2406
2407 if (sc->sc_dying)
2408 return -1;
2409
2410 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest,
2411 0, 0);
2412
2413 len = UGETW(req->wLength);
2414 value = UGETW(req->wValue);
2415 index = UGETW(req->wIndex);
2416
2417 #define C(x,y) ((x) | ((y) << 8))
2418 switch (C(req->bRequest, req->bmRequestType)) {
2419 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2420 if (len == 0)
2421 break;
2422 switch (value) {
2423 #define sd ((usb_string_descriptor_t *)buf)
2424 case C(2, UDESC_STRING):
2425 /* Product */
2426 totlen = usb_makestrdesc(sd, len, "EHCI root hub");
2427 break;
2428 #undef sd
2429 default:
2430 /* default from usbroothub */
2431 return buflen;
2432 }
2433 break;
2434
2435 /* Hub requests */
2436 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2437 break;
2438 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2439 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index,
2440 value, 0, 0);
2441 if (index < 1 || index > sc->sc_noport) {
2442 return -1;
2443 }
2444 port = EHCI_PORTSC(index);
2445 v = EOREAD4(sc, port);
2446 DPRINTF("portsc=0x%08jx", v, 0, 0, 0);
2447 v &= ~EHCI_PS_CLEAR;
2448 switch (value) {
2449 case UHF_PORT_ENABLE:
2450 EOWRITE4(sc, port, v &~ EHCI_PS_PE);
2451 break;
2452 case UHF_PORT_SUSPEND:
2453 if (!(v & EHCI_PS_SUSP)) /* not suspended */
2454 break;
2455 v &= ~EHCI_PS_SUSP;
2456 EOWRITE4(sc, port, v | EHCI_PS_FPR);
2457 /* see USB2 spec ch. 7.1.7.7 */
2458 usb_delay_ms(&sc->sc_bus, 20);
2459 EOWRITE4(sc, port, v);
2460 usb_delay_ms(&sc->sc_bus, 2);
2461 #ifdef DEBUG
2462 v = EOREAD4(sc, port);
2463 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP))
2464 printf("ehci: resume failed: %x\n", v);
2465 #endif
2466 break;
2467 case UHF_PORT_POWER:
2468 if (sc->sc_hasppc)
2469 EOWRITE4(sc, port, v &~ EHCI_PS_PP);
2470 break;
2471 case UHF_PORT_TEST:
2472 DPRINTF("clear port test %jd", index, 0, 0, 0);
2473 break;
2474 case UHF_PORT_INDICATOR:
2475 DPRINTF("clear port ind %jd", index, 0, 0, 0);
2476 EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
2477 break;
2478 case UHF_C_PORT_CONNECTION:
2479 EOWRITE4(sc, port, v | EHCI_PS_CSC);
2480 break;
2481 case UHF_C_PORT_ENABLE:
2482 EOWRITE4(sc, port, v | EHCI_PS_PEC);
2483 break;
2484 case UHF_C_PORT_SUSPEND:
2485 /* how? */
2486 break;
2487 case UHF_C_PORT_OVER_CURRENT:
2488 EOWRITE4(sc, port, v | EHCI_PS_OCC);
2489 break;
2490 case UHF_C_PORT_RESET:
2491 sc->sc_isreset[index] = 0;
2492 break;
2493 default:
2494 return -1;
2495 }
2496 #if 0
2497 switch(value) {
2498 case UHF_C_PORT_CONNECTION:
2499 case UHF_C_PORT_ENABLE:
2500 case UHF_C_PORT_SUSPEND:
2501 case UHF_C_PORT_OVER_CURRENT:
2502 case UHF_C_PORT_RESET:
2503 default:
2504 break;
2505 }
2506 #endif
2507 break;
2508 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2509 if (len == 0)
2510 break;
2511 if ((value & 0xff) != 0) {
2512 return -1;
2513 }
2514 totlen = uimin(buflen, sizeof(hubd));
2515 memcpy(&hubd, buf, totlen);
2516 hubd.bNbrPorts = sc->sc_noport;
2517 v = EREAD4(sc, EHCI_HCSPARAMS);
2518 USETW(hubd.wHubCharacteristics,
2519 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
2520 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0));
2521 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
2522 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2523 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2524 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2525 totlen = uimin(totlen, hubd.bDescLength);
2526 memcpy(buf, &hubd, totlen);
2527 break;
2528 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2529 if (len != 4) {
2530 return -1;
2531 }
2532 memset(buf, 0, len); /* ? XXX */
2533 totlen = len;
2534 break;
2535 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2536 DPRINTF("get port status i=%jd", index, 0, 0, 0);
2537 if (index < 1 || index > sc->sc_noport) {
2538 return -1;
2539 }
2540 if (len != 4) {
2541 return -1;
2542 }
2543 v = EOREAD4(sc, EHCI_PORTSC(index));
2544 DPRINTF("port status=0x%04jx", v, 0, 0, 0);
2545
2546 i = UPS_HIGH_SPEED;
2547 if (sc->sc_flags & EHCIF_ETTF) {
2548 /*
2549 * If we are doing embedded transaction translation,
2550 * then directly attached LS/FS devices are reset by
2551 * the EHCI controller itself. PSPD is encoded
2552 * the same way as in USBSTATUS.
2553 */
2554 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;
2555 }
2556 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
2557 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
2558 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
2559 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2560 if (v & EHCI_PS_PR) i |= UPS_RESET;
2561 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
2562 if (sc->sc_vendor_port_status)
2563 i = sc->sc_vendor_port_status(sc, v, i);
2564 USETW(ps.wPortStatus, i);
2565 i = 0;
2566 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2567 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2568 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
2569 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
2570 USETW(ps.wPortChange, i);
2571 totlen = uimin(len, sizeof(ps));
2572 memcpy(buf, &ps, totlen);
2573 break;
2574 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2575 return -1;
2576 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2577 break;
2578 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2579 if (index < 1 || index > sc->sc_noport) {
2580 return -1;
2581 }
2582 port = EHCI_PORTSC(index);
2583 v = EOREAD4(sc, port);
2584 DPRINTF("portsc=0x%08jx", v, 0, 0, 0);
2585 v &= ~EHCI_PS_CLEAR;
2586 switch(value) {
2587 case UHF_PORT_ENABLE:
2588 EOWRITE4(sc, port, v | EHCI_PS_PE);
2589 break;
2590 case UHF_PORT_SUSPEND:
2591 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
2592 break;
2593 case UHF_PORT_RESET:
2594 DPRINTF("reset port %jd", index, 0, 0, 0);
2595 if (EHCI_PS_IS_LOWSPEED(v)
2596 && sc->sc_ncomp > 0
2597 && !(sc->sc_flags & EHCIF_ETTF)) {
2598 /*
2599 * Low speed device on non-ETTF controller or
2600 * unaccompanied controller, give up ownership.
2601 */
2602 ehci_disown(sc, index, 1);
2603 break;
2604 }
2605 /* Start reset sequence. */
2606 v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
2607 EOWRITE4(sc, port, v | EHCI_PS_PR);
2608 /* Wait for reset to complete. */
2609 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
2610 if (sc->sc_dying) {
2611 return -1;
2612 }
2613 /*
2614 * An embedded transaction translator will automatically
2615 * terminate the reset sequence so there's no need to
2616 * it.
2617 */
2618 v = EOREAD4(sc, port);
2619 if (v & EHCI_PS_PR) {
2620 /* Terminate reset sequence. */
2621 EOWRITE4(sc, port, v & ~EHCI_PS_PR);
2622 /* Wait for HC to complete reset. */
2623 usb_delay_ms(&sc->sc_bus,
2624 EHCI_PORT_RESET_COMPLETE);
2625 if (sc->sc_dying) {
2626 return -1;
2627 }
2628 }
2629
2630 v = EOREAD4(sc, port);
2631 DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0);
2632 if (v & EHCI_PS_PR) {
2633 printf("%s: port reset timeout\n",
2634 device_xname(sc->sc_dev));
2635 return USBD_TIMEOUT;
2636 }
2637 if (!(v & EHCI_PS_PE)) {
2638 /* Not a high speed device, give up ownership.*/
2639 ehci_disown(sc, index, 0);
2640 break;
2641 }
2642 sc->sc_isreset[index] = 1;
2643 DPRINTF("ehci port %jd reset, status = 0x%08jx", index,
2644 v, 0, 0);
2645 break;
2646 case UHF_PORT_POWER:
2647 DPRINTF("set port power %jd (has PPC = %jd)", index,
2648 sc->sc_hasppc, 0, 0);
2649 if (sc->sc_hasppc)
2650 EOWRITE4(sc, port, v | EHCI_PS_PP);
2651 break;
2652 case UHF_PORT_TEST:
2653 DPRINTF("set port test %jd", index, 0, 0, 0);
2654 break;
2655 case UHF_PORT_INDICATOR:
2656 DPRINTF("set port ind %jd", index, 0, 0, 0);
2657 EOWRITE4(sc, port, v | EHCI_PS_PIC);
2658 break;
2659 default:
2660 return -1;
2661 }
2662 break;
2663 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2664 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2665 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2666 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2667 break;
2668 default:
2669 /* default from usbroothub */
2670 DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0);
2671
2672 return buflen;
2673 }
2674
2675 DPRINTF("returning %jd", totlen, 0, 0, 0);
2676
2677 return totlen;
2678 }
2679
2680 Static int
ehci_roothub_ctrl(struct usbd_bus * bus,usb_device_request_t * req,void * buf,int buflen)2681 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2682 void *buf, int buflen)
2683 {
2684 struct ehci_softc *sc = EHCI_BUS2SC(bus);
2685 int actlen;
2686
2687 mutex_enter(&sc->sc_rhlock);
2688 actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen);
2689 mutex_exit(&sc->sc_rhlock);
2690
2691 return actlen;
2692 }
2693
2694 /*
2695 * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE.
2696 *
2697 * This pile of garbage below works around the following problem without
2698 * holding boots with no hand-over devices present, while penalising
2699 * boots where the first ehci probe hands off devices with a 5 second
2700 * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem
2701 * for RB_SINGLE, but the same basic issue exists.
2702 *
2703 * The way ehci hand-off works, the companion controller does not get the
2704 * device until after its initial bus explore, so the reference dropped
2705 * after the first explore is not enough. 5 seconds should be enough,
2706 * and EHCI_DISOWN_DELAY_SECONDS can be set to another value.
2707 *
2708 * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set
2709 * if the callback is scheduled. CO_DONE is set when the callout has
2710 * called config_pending_decr().
2711 *
2712 * There's a mutex, a cv and a callout here, and we delay detach if the
2713 * callout has been set.
2714 */
2715 #ifndef EHCI_DISOWN_DELAY_SECONDS
2716 #define EHCI_DISOWN_DELAY_SECONDS 5
2717 #endif
2718 static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS;
2719
2720 static void
ehci_disown_callback(void * arg)2721 ehci_disown_callback(void *arg)
2722 {
2723 ehci_softc_t *sc = arg;
2724
2725 config_pending_decr(sc->sc_dev);
2726
2727 mutex_enter(&sc->sc_complock);
2728 KASSERT(sc->sc_comp_state == CO_SCHED);
2729 sc->sc_comp_state = CO_DONE;
2730 cv_signal(&sc->sc_compcv);
2731 mutex_exit(&sc->sc_complock);
2732 }
2733
2734 static void
ehci_disown_sched_callback(ehci_softc_t * sc)2735 ehci_disown_sched_callback(ehci_softc_t *sc)
2736 {
2737 extern bool root_is_mounted;
2738
2739 mutex_enter(&sc->sc_complock);
2740
2741 if (root_is_mounted ||
2742 (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 ||
2743 sc->sc_comp_state != CO_EARLY) {
2744 mutex_exit(&sc->sc_complock);
2745 return;
2746 }
2747
2748 callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz,
2749 ehci_disown_callback, &sc->sc_dev);
2750 sc->sc_comp_state = CO_SCHED;
2751
2752 mutex_exit(&sc->sc_complock);
2753
2754 config_pending_incr(sc->sc_dev);
2755 aprint_normal_dev(sc->sc_dev,
2756 "delaying %s by %u seconds due to USB owner change.\n",
2757 (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user",
2758 ehci_disown_delay_seconds);
2759 }
2760
2761 Static void
ehci_disown(ehci_softc_t * sc,int index,int lowspeed)2762 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
2763 {
2764 int port;
2765 uint32_t v;
2766
2767 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2768
2769 DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0);
2770 if (sc->sc_npcomp != 0) {
2771 int i = (index-1) / sc->sc_npcomp;
2772 if (i < sc->sc_ncomp) {
2773 ehci_disown_sched_callback(sc);
2774 #ifdef DIAGNOSTIC
2775 printf("%s: handing over %s speed device on "
2776 "port %d to %s\n",
2777 device_xname(sc->sc_dev),
2778 lowspeed ? "low" : "full",
2779 index, sc->sc_comps[i] ?
2780 device_xname(sc->sc_comps[i]) :
2781 "companion controller");
2782 } else {
2783 printf("%s: strange port\n",
2784 device_xname(sc->sc_dev));
2785 #endif
2786 }
2787 } else {
2788 #ifdef DIAGNOSTIC
2789 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev));
2790 #endif
2791 }
2792 port = EHCI_PORTSC(index);
2793 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2794 EOWRITE4(sc, port, v | EHCI_PS_PO);
2795 }
2796
2797 Static usbd_status
ehci_root_intr_transfer(struct usbd_xfer * xfer)2798 ehci_root_intr_transfer(struct usbd_xfer *xfer)
2799 {
2800
2801 /* Pipe isn't running, start first */
2802 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2803 }
2804
2805 Static usbd_status
ehci_root_intr_start(struct usbd_xfer * xfer)2806 ehci_root_intr_start(struct usbd_xfer *xfer)
2807 {
2808 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
2809
2810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
2811
2812 if (sc->sc_dying)
2813 return USBD_IOERROR;
2814
2815 KASSERT(sc->sc_intrxfer == NULL);
2816 sc->sc_intrxfer = xfer;
2817 xfer->ux_status = USBD_IN_PROGRESS;
2818
2819 return USBD_IN_PROGRESS;
2820 }
2821
2822 /* Abort a root interrupt request. */
2823 Static void
ehci_root_intr_abort(struct usbd_xfer * xfer)2824 ehci_root_intr_abort(struct usbd_xfer *xfer)
2825 {
2826 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
2827
2828 KASSERT(mutex_owned(&sc->sc_lock));
2829 KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2830
2831 /* If xfer has already completed, nothing to do here. */
2832 if (sc->sc_intrxfer == NULL)
2833 return;
2834
2835 /*
2836 * Otherwise, sc->sc_intrxfer had better be this transfer.
2837 * Cancel it.
2838 */
2839 KASSERT(sc->sc_intrxfer == xfer);
2840 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
2841 xfer->ux_status = USBD_CANCELLED;
2842 usb_transfer_complete(xfer);
2843 }
2844
2845 /* Close the root pipe. */
2846 Static void
ehci_root_intr_close(struct usbd_pipe * pipe)2847 ehci_root_intr_close(struct usbd_pipe *pipe)
2848 {
2849 ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe);
2850
2851 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2852
2853 KASSERT(mutex_owned(&sc->sc_lock));
2854
2855 /*
2856 * Caller must guarantee the xfer has completed first, by
2857 * closing the pipe only after normal completion or an abort.
2858 */
2859 KASSERT(sc->sc_intrxfer == NULL);
2860 }
2861
2862 Static void
ehci_root_intr_done(struct usbd_xfer * xfer)2863 ehci_root_intr_done(struct usbd_xfer *xfer)
2864 {
2865 struct ehci_softc *sc = EHCI_XFER2SC(xfer);
2866
2867 KASSERT(mutex_owned(&sc->sc_lock));
2868
2869 /* Claim the xfer so it doesn't get completed again. */
2870 KASSERT(sc->sc_intrxfer == xfer);
2871 KASSERT(xfer->ux_status != USBD_IN_PROGRESS);
2872 sc->sc_intrxfer = NULL;
2873 }
2874
2875 /************************/
2876
2877 Static ehci_soft_qh_t *
ehci_alloc_sqh(ehci_softc_t * sc)2878 ehci_alloc_sqh(ehci_softc_t *sc)
2879 {
2880 ehci_soft_qh_t *sqh;
2881
2882 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2883
2884 mutex_enter(&sc->sc_lock);
2885 if (sc->sc_freeqhs == NULL) {
2886 DPRINTF("allocating chunk", 0, 0, 0, 0);
2887 mutex_exit(&sc->sc_lock);
2888
2889 usb_dma_t dma;
2890 int err = usb_allocmem(sc->sc_dmatag,
2891 EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2892 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
2893
2894 if (err) {
2895 DPRINTF("alloc returned %jd", err, 0, 0, 0);
2896 return NULL;
2897 }
2898
2899 mutex_enter(&sc->sc_lock);
2900 for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) {
2901 const int offs = i * EHCI_SQH_SIZE;
2902 const bus_addr_t baddr = DMAADDR(&dma, offs);
2903
2904 KASSERT(BUS_ADDR_HI32(baddr) == 0);
2905
2906 sqh = KERNADDR(&dma, offs);
2907 sqh->physaddr = BUS_ADDR_LO32(baddr);
2908 sqh->dma = dma;
2909 sqh->offs = offs;
2910
2911 sqh->next = sc->sc_freeqhs;
2912 sc->sc_freeqhs = sqh;
2913 }
2914 }
2915 sqh = sc->sc_freeqhs;
2916 sc->sc_freeqhs = sqh->next;
2917 mutex_exit(&sc->sc_lock);
2918
2919 memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2920 sqh->next = NULL;
2921 return sqh;
2922 }
2923
2924 Static void
ehci_free_sqh(ehci_softc_t * sc,ehci_soft_qh_t * sqh)2925 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2926 {
2927 KASSERT(mutex_owned(&sc->sc_lock));
2928
2929 sqh->next = sc->sc_freeqhs;
2930 sc->sc_freeqhs = sqh;
2931 }
2932
2933 Static ehci_soft_qtd_t *
ehci_alloc_sqtd(ehci_softc_t * sc)2934 ehci_alloc_sqtd(ehci_softc_t *sc)
2935 {
2936 ehci_soft_qtd_t *sqtd = NULL;
2937
2938 EHCIHIST_FUNC(); EHCIHIST_CALLED();
2939
2940 mutex_enter(&sc->sc_lock);
2941 if (sc->sc_freeqtds == NULL) {
2942 DPRINTF("allocating chunk", 0, 0, 0, 0);
2943 mutex_exit(&sc->sc_lock);
2944
2945 usb_dma_t dma;
2946 int err = usb_allocmem(sc->sc_dmatag,
2947 EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK,
2948 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
2949
2950 if (err) {
2951 DPRINTF("alloc returned %jd", err, 0, 0, 0);
2952 return NULL;
2953 }
2954
2955 mutex_enter(&sc->sc_lock);
2956 for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) {
2957 const int offs = i * EHCI_SQTD_SIZE;
2958 const bus_addr_t baddr = DMAADDR(&dma, offs);
2959
2960 KASSERT(BUS_ADDR_HI32(baddr) == 0);
2961
2962 sqtd = KERNADDR(&dma, offs);
2963 sqtd->physaddr = BUS_ADDR_LO32(baddr);
2964 sqtd->dma = dma;
2965 sqtd->offs = offs;
2966
2967 sqtd->nextqtd = sc->sc_freeqtds;
2968 sc->sc_freeqtds = sqtd;
2969 }
2970 }
2971
2972 sqtd = sc->sc_freeqtds;
2973 sc->sc_freeqtds = sqtd->nextqtd;
2974 mutex_exit(&sc->sc_lock);
2975
2976 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2977 sqtd->nextqtd = NULL;
2978 sqtd->xfer = NULL;
2979
2980 return sqtd;
2981 }
2982
2983 Static void
ehci_free_sqtd(ehci_softc_t * sc,ehci_soft_qtd_t * sqtd)2984 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2985 {
2986
2987 mutex_enter(&sc->sc_lock);
2988 sqtd->nextqtd = sc->sc_freeqtds;
2989 sc->sc_freeqtds = sqtd;
2990 mutex_exit(&sc->sc_lock);
2991 }
2992
2993 Static int
ehci_alloc_sqtd_chain(ehci_softc_t * sc,struct usbd_xfer * xfer,int alen,int rd,ehci_soft_qtd_t ** sp)2994 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer,
2995 int alen, int rd, ehci_soft_qtd_t **sp)
2996 {
2997 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
2998 uint16_t flags = xfer->ux_flags;
2999
3000 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3001
3002 ASSERT_SLEEPABLE();
3003 KASSERT(sp);
3004 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
3005
3006 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
3007 nsqtd += howmany(alen, EHCI_PAGE_SIZE);
3008 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd,
3009 KM_SLEEP);
3010 exfer->ex_nsqtd = nsqtd;
3011
3012 DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer,
3013 alen, nsqtd, flags);
3014
3015 for (size_t j = 0; j < exfer->ex_nsqtd;) {
3016 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc);
3017 if (cur == NULL)
3018 goto nomem;
3019 exfer->ex_sqtds[j++] = cur;
3020
3021 cur->xfer = xfer;
3022 cur->len = 0;
3023
3024 }
3025
3026 *sp = exfer->ex_sqtds[0];
3027 DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0);
3028
3029 return 0;
3030
3031 nomem:
3032 ehci_free_sqtds(sc, exfer);
3033 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd);
3034 DPRINTF("no memory", 0, 0, 0, 0);
3035 return ENOMEM;
3036 }
3037
3038 Static void
ehci_free_sqtds(ehci_softc_t * sc,struct ehci_xfer * exfer)3039 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer)
3040 {
3041 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3042 DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0);
3043
3044 mutex_enter(&sc->sc_lock);
3045 for (size_t i = 0; i < exfer->ex_nsqtd; i++) {
3046 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i];
3047
3048 if (sqtd == NULL)
3049 break;
3050
3051 sqtd->nextqtd = sc->sc_freeqtds;
3052 sc->sc_freeqtds = sqtd;
3053 }
3054 mutex_exit(&sc->sc_lock);
3055 }
3056
3057 Static void
ehci_append_sqtd(ehci_soft_qtd_t * sqtd,ehci_soft_qtd_t * prev)3058 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev)
3059 {
3060 if (prev) {
3061 prev->nextqtd = sqtd;
3062 prev->qtd.qtd_next = htole32(sqtd->physaddr);
3063 prev->qtd.qtd_altnext = prev->qtd.qtd_next;
3064 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd),
3065 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3066 }
3067 }
3068
3069 Static void
ehci_reset_sqtd_chain(ehci_softc_t * sc,struct usbd_xfer * xfer,int length,int isread,int * toggle,ehci_soft_qtd_t ** lsqtd)3070 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer,
3071 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd)
3072 {
3073 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3074 usb_dma_t *dma = &xfer->ux_dmabuf;
3075 uint16_t flags = xfer->ux_flags;
3076 ehci_soft_qtd_t *sqtd, *prev;
3077 int tog = *toggle;
3078 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
3079 int len = length;
3080
3081 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3082 DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer,
3083 len, isread, tog);
3084 DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0),
3085 0, 0, 0);
3086
3087 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER)));
3088
3089 const uint32_t qtdstatus = EHCI_QTD_ACTIVE |
3090 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
3091 EHCI_QTD_SET_CERR(3)
3092 ;
3093
3094 sqtd = prev = NULL;
3095 size_t curoffs = 0;
3096 size_t j = 0;
3097 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) {
3098 sqtd = exfer->ex_sqtds[j++];
3099 DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd,
3100 (uintptr_t)prev, 0);
3101
3102 /*
3103 * The EHCI hardware can handle at most 5 pages and they do
3104 * not have to be contiguous
3105 */
3106 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs);
3107 vaddr_t va_offs = EHCI_PAGE_OFFSET(va);
3108 size_t curlen = len;
3109 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) {
3110 /* must use multiple TDs, fill as much as possible. */
3111 curlen = EHCI_QTD_MAXTRANSFER - va_offs;
3112
3113 /* the length must be a multiple of the max size */
3114 curlen -= curlen % mps;
3115 }
3116 KASSERT(curlen != 0);
3117 DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen,
3118 curoffs, 0);
3119
3120 /* Fill the qTD */
3121 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL;
3122 sqtd->qtd.qtd_status = htole32(
3123 qtdstatus |
3124 EHCI_QTD_SET_BYTES(curlen) |
3125 EHCI_QTD_SET_TOGGLE(tog));
3126
3127 /* Find number of pages we'll be using, insert dma addresses */
3128 size_t pages = EHCI_NPAGES(curlen);
3129 KASSERT(pages <= EHCI_QTD_NBUFFERS);
3130 size_t pageoffs = EHCI_PAGE(curoffs);
3131 for (size_t i = 0; i < pages; i++) {
3132 paddr_t a = EHCI_PAGE(DMAADDR(dma,
3133 pageoffs + i * EHCI_PAGE_SIZE));
3134 sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a));
3135 sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a));
3136 DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx",
3137 i, pages,
3138 le32toh(sqtd->qtd.qtd_buffer_hi[i]),
3139 le32toh(sqtd->qtd.qtd_buffer[i]));
3140 }
3141 /* First buffer pointer requires a page offset to start at */
3142 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs);
3143
3144 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
3145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3146
3147 sqtd->len = curlen;
3148
3149 DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va,
3150 (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0);
3151
3152 ehci_append_sqtd(sqtd, prev);
3153
3154 if (howmany(curlen, mps) & 1) {
3155 tog ^= 1;
3156 }
3157
3158 curoffs += curlen;
3159 len -= curlen;
3160 }
3161 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu",
3162 xfer, length, len, mps, exfer->ex_nsqtd, j);
3163
3164 if (!isread &&
3165 (flags & USBD_FORCE_SHORT_XFER) &&
3166 length % mps == 0) {
3167 /* Force a 0 length transfer at the end. */
3168
3169 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j,
3170 exfer->ex_nsqtd);
3171 prev = sqtd;
3172 sqtd = exfer->ex_sqtds[j++];
3173 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd));
3174 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL;
3175 sqtd->qtd.qtd_status = htole32(
3176 qtdstatus |
3177 EHCI_QTD_SET_BYTES(0) |
3178 EHCI_QTD_SET_TOGGLE(tog));
3179
3180 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3182
3183 ehci_append_sqtd(sqtd, prev);
3184 tog ^= 1;
3185 }
3186
3187 *lsqtd = sqtd;
3188 *toggle = tog;
3189 }
3190
3191 Static ehci_soft_itd_t *
ehci_alloc_itd(ehci_softc_t * sc)3192 ehci_alloc_itd(ehci_softc_t *sc)
3193 {
3194 struct ehci_soft_itd *itd, *freeitd;
3195
3196 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3197
3198 mutex_enter(&sc->sc_lock);
3199
3200 freeitd = LIST_FIRST(&sc->sc_freeitds);
3201 if (freeitd == NULL) {
3202 DPRINTF("allocating chunk", 0, 0, 0, 0);
3203 mutex_exit(&sc->sc_lock);
3204
3205 usb_dma_t dma;
3206 int err = usb_allocmem(sc->sc_dmatag,
3207 EHCI_ITD_SIZE * EHCI_ITD_CHUNK,
3208 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
3209
3210 if (err) {
3211 DPRINTF("alloc returned %jd", err, 0, 0, 0);
3212 return NULL;
3213 }
3214
3215 mutex_enter(&sc->sc_lock);
3216 for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) {
3217 const int offs = i * EHCI_ITD_SIZE;
3218 const bus_addr_t baddr = DMAADDR(&dma, offs);
3219
3220 KASSERT(BUS_ADDR_HI32(baddr) == 0);
3221
3222 itd = KERNADDR(&dma, offs);
3223 itd->physaddr = BUS_ADDR_LO32(baddr);
3224 itd->dma = dma;
3225 itd->offs = offs;
3226
3227 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list);
3228 }
3229 freeitd = LIST_FIRST(&sc->sc_freeitds);
3230 }
3231
3232 itd = freeitd;
3233 LIST_REMOVE(itd, free_list);
3234 mutex_exit(&sc->sc_lock);
3235 memset(&itd->itd, 0, sizeof(ehci_itd_t));
3236
3237 itd->frame_list.next = NULL;
3238 itd->frame_list.prev = NULL;
3239 itd->xfer_next = NULL;
3240 itd->slot = 0;
3241
3242 return itd;
3243 }
3244
3245 Static ehci_soft_sitd_t *
ehci_alloc_sitd(ehci_softc_t * sc)3246 ehci_alloc_sitd(ehci_softc_t *sc)
3247 {
3248 struct ehci_soft_sitd *sitd, *freesitd;
3249
3250 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3251
3252 mutex_enter(&sc->sc_lock);
3253 freesitd = LIST_FIRST(&sc->sc_freesitds);
3254 if (freesitd == NULL) {
3255 DPRINTF("allocating chunk", 0, 0, 0, 0);
3256 mutex_exit(&sc->sc_lock);
3257
3258 usb_dma_t dma;
3259 int err = usb_allocmem(sc->sc_dmatag,
3260 EHCI_SITD_SIZE * EHCI_SITD_CHUNK,
3261 EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
3262
3263 if (err) {
3264 DPRINTF("alloc returned %jd", err, 0, 0, 0);
3265 return NULL;
3266 }
3267
3268 mutex_enter(&sc->sc_lock);
3269 for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) {
3270 const int offs = i * EHCI_SITD_SIZE;
3271 const bus_addr_t baddr = DMAADDR(&dma, offs);
3272
3273 KASSERT(BUS_ADDR_HI32(baddr) == 0);
3274
3275 sitd = KERNADDR(&dma, offs);
3276 sitd->physaddr = BUS_ADDR_LO32(baddr);
3277 sitd->dma = dma;
3278 sitd->offs = offs;
3279
3280 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list);
3281 }
3282 freesitd = LIST_FIRST(&sc->sc_freesitds);
3283 }
3284
3285 sitd = freesitd;
3286 LIST_REMOVE(sitd, free_list);
3287 mutex_exit(&sc->sc_lock);
3288
3289 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t));
3290
3291 sitd->frame_list.next = NULL;
3292 sitd->frame_list.prev = NULL;
3293 sitd->xfer_next = NULL;
3294 sitd->slot = 0;
3295
3296 return sitd;
3297 }
3298
3299 /****************/
3300
3301 /*
3302 * Close a reqular pipe.
3303 * Assumes that there are no pending transactions.
3304 */
3305 Static void
ehci_close_pipe(struct usbd_pipe * pipe,ehci_soft_qh_t * head)3306 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head)
3307 {
3308 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
3309 ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
3310 ehci_soft_qh_t *sqh = epipe->sqh;
3311
3312 KASSERT(mutex_owned(&sc->sc_lock));
3313
3314 ehci_rem_qh(sc, sqh, head);
3315 ehci_free_sqh(sc, epipe->sqh);
3316 }
3317
3318 /*
3319 * Arrange for the hardware to tells us that it is not still
3320 * processing the TDs by setting the QH halted bit and wait for the ehci
3321 * door bell
3322 */
3323 Static void
ehci_abortx(struct usbd_xfer * xfer)3324 ehci_abortx(struct usbd_xfer *xfer)
3325 {
3326 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3327 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3328 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3329 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3330 ehci_soft_qh_t *sqh = epipe->sqh;
3331 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd;
3332 ehci_physaddr_t cur;
3333 uint32_t qhstatus;
3334 int hit;
3335
3336 DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0);
3337
3338 KASSERT(mutex_owned(&sc->sc_lock));
3339 ASSERT_SLEEPABLE();
3340
3341 KASSERTMSG((xfer->ux_status == USBD_CANCELLED ||
3342 xfer->ux_status == USBD_TIMEOUT),
3343 "bad abort status: %d", xfer->ux_status);
3344
3345 /*
3346 * If we're dying, skip the hardware action and just notify the
3347 * software that we're done.
3348 */
3349 if (sc->sc_dying) {
3350 goto dying;
3351 }
3352
3353 /*
3354 * HC Step 1: Make interrupt routine and hardware ignore xfer.
3355 */
3356 ehci_del_intr_list(sc, exfer);
3357
3358 usb_syncmem(&sqh->dma,
3359 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3360 sizeof(sqh->qh.qh_qtd.qtd_status),
3361 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3362 qhstatus = sqh->qh.qh_qtd.qtd_status;
3363 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
3364 usb_syncmem(&sqh->dma,
3365 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3366 sizeof(sqh->qh.qh_qtd.qtd_status),
3367 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3368
3369 if (exfer->ex_type == EX_CTRL) {
3370 fsqtd = exfer->ex_setup;
3371 lsqtd = exfer->ex_status;
3372 } else {
3373 fsqtd = exfer->ex_sqtdstart;
3374 lsqtd = exfer->ex_sqtdend;
3375 }
3376 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) {
3377 usb_syncmem(&sqtd->dma,
3378 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
3379 sizeof(sqtd->qtd.qtd_status),
3380 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3381 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
3382 usb_syncmem(&sqtd->dma,
3383 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
3384 sizeof(sqtd->qtd.qtd_status),
3385 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3386 if (sqtd == lsqtd)
3387 break;
3388 }
3389
3390 /*
3391 * HC Step 2: Wait until we know hardware has finished any possible
3392 * use of the xfer.
3393 */
3394 ehci_sync_hc(sc);
3395
3396 /*
3397 * HC Step 3: Remove any vestiges of the xfer from the hardware.
3398 * The complication here is that the hardware may have executed
3399 * beyond the xfer we're trying to abort. So as we're scanning
3400 * the TDs of this xfer we check if the hardware points to
3401 * any of them.
3402 */
3403
3404 usb_syncmem(&sqh->dma,
3405 sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3406 sizeof(sqh->qh.qh_curqtd),
3407 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3408 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
3409 hit = 0;
3410 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) {
3411 hit |= cur == sqtd->physaddr;
3412 if (sqtd == lsqtd)
3413 break;
3414 }
3415 sqtd = sqtd->nextqtd;
3416 /* Zap curqtd register if hardware pointed inside the xfer. */
3417 if (hit && sqtd != NULL) {
3418 DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0);
3419 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
3420 usb_syncmem(&sqh->dma,
3421 sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3422 sizeof(sqh->qh.qh_curqtd),
3423 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3424 sqh->qh.qh_qtd.qtd_status = qhstatus;
3425 usb_syncmem(&sqh->dma,
3426 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3427 sizeof(sqh->qh.qh_qtd.qtd_status),
3428 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3429 } else {
3430 DPRINTF("no hit", 0, 0, 0, 0);
3431 usb_syncmem(&sqh->dma,
3432 sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3433 sizeof(sqh->qh.qh_curqtd),
3434 BUS_DMASYNC_PREREAD);
3435 }
3436
3437 dying:
3438 #ifdef DIAGNOSTIC
3439 exfer->ex_isdone = true;
3440 #endif
3441 DPRINTFN(14, "end", 0, 0, 0, 0);
3442
3443 KASSERT(mutex_owned(&sc->sc_lock));
3444 }
3445
3446 Static void
ehci_abort_isoc_xfer(struct usbd_xfer * xfer,usbd_status status)3447 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status)
3448 {
3449 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3450 ehci_isoc_trans_t trans_status;
3451 struct ehci_xfer *exfer;
3452 ehci_softc_t *sc;
3453 struct ehci_soft_itd *itd;
3454 struct ehci_soft_sitd *sitd;
3455 int i;
3456
3457 KASSERTMSG(status == USBD_CANCELLED,
3458 "invalid status for abort: %d", (int)status);
3459
3460 exfer = EHCI_XFER2EXFER(xfer);
3461 sc = EHCI_XFER2SC(xfer);
3462
3463 DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer,
3464 (uintptr_t)xfer->ux_pipe, 0, 0);
3465
3466 KASSERT(mutex_owned(&sc->sc_lock));
3467 ASSERT_SLEEPABLE();
3468
3469 /* No timeout or task here. */
3470
3471 /*
3472 * The xfer cannot have been cancelled already. It is the
3473 * responsibility of the caller of usbd_abort_pipe not to try
3474 * to abort a pipe multiple times, whether concurrently or
3475 * sequentially.
3476 */
3477 KASSERT(xfer->ux_status != USBD_CANCELLED);
3478
3479 /* If anyone else beat us, we're done. */
3480 if (xfer->ux_status != USBD_IN_PROGRESS)
3481 return;
3482
3483 /* We beat everyone else. Claim the status. */
3484 xfer->ux_status = status;
3485
3486 /*
3487 * If we're dying, skip the hardware action and just notify the
3488 * software that we're done.
3489 */
3490 if (sc->sc_dying) {
3491 goto dying;
3492 }
3493
3494 /*
3495 * HC Step 1: Make interrupt routine and hardware ignore xfer.
3496 */
3497 ehci_del_intr_list(sc, exfer);
3498
3499 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) {
3500 for (itd = exfer->ex_itdstart; itd != NULL;
3501 itd = itd->xfer_next) {
3502 usb_syncmem(&itd->dma,
3503 itd->offs + offsetof(ehci_itd_t, itd_ctl),
3504 sizeof(itd->itd.itd_ctl),
3505 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3506
3507 for (i = 0; i < 8; i++) {
3508 trans_status = le32toh(itd->itd.itd_ctl[i]);
3509 trans_status &= ~EHCI_ITD_ACTIVE;
3510 itd->itd.itd_ctl[i] = htole32(trans_status);
3511 }
3512
3513 usb_syncmem(&itd->dma,
3514 itd->offs + offsetof(ehci_itd_t, itd_ctl),
3515 sizeof(itd->itd.itd_ctl),
3516 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3517 }
3518 } else {
3519 for (sitd = exfer->ex_sitdstart; sitd != NULL;
3520 sitd = sitd->xfer_next) {
3521 usb_syncmem(&sitd->dma,
3522 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
3523 sizeof(sitd->sitd.sitd_buffer),
3524 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3525
3526 trans_status = le32toh(sitd->sitd.sitd_trans);
3527 trans_status &= ~EHCI_SITD_ACTIVE;
3528 sitd->sitd.sitd_trans = htole32(trans_status);
3529
3530 usb_syncmem(&sitd->dma,
3531 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
3532 sizeof(sitd->sitd.sitd_buffer),
3533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3534 }
3535 }
3536
3537 dying:
3538 #ifdef DIAGNOSTIC
3539 exfer->ex_isdone = true;
3540 #endif
3541 usb_transfer_complete(xfer);
3542 DPRINTFN(14, "end", 0, 0, 0, 0);
3543
3544 KASSERT(mutex_owned(&sc->sc_lock));
3545 }
3546
3547 /************************/
3548
3549 Static int
ehci_device_ctrl_init(struct usbd_xfer * xfer)3550 ehci_device_ctrl_init(struct usbd_xfer *xfer)
3551 {
3552 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3553 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3554 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3555 usb_device_request_t *req = &xfer->ux_request;
3556 ehci_soft_qtd_t *setup, *status, *next;
3557 int isread = req->bmRequestType & UT_READ;
3558 int len = xfer->ux_bufsize;
3559 int err;
3560
3561 exfer->ex_type = EX_CTRL;
3562 exfer->ex_status = NULL;
3563 exfer->ex_data = NULL;
3564 exfer->ex_setup = ehci_alloc_sqtd(sc);
3565 if (exfer->ex_setup == NULL) {
3566 err = ENOMEM;
3567 goto bad1;
3568 }
3569 exfer->ex_status = ehci_alloc_sqtd(sc);
3570 if (exfer->ex_status == NULL) {
3571 err = ENOMEM;
3572 goto bad2;
3573 }
3574 setup = exfer->ex_setup;
3575 status = exfer->ex_status;
3576 exfer->ex_nsqtd = 0;
3577 next = status;
3578 /* Set up data transaction */
3579 if (len != 0) {
3580 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread,
3581 &exfer->ex_data);
3582 if (err)
3583 goto bad3;
3584 next = exfer->ex_data;
3585 }
3586
3587 /* Clear toggle */
3588 setup->qtd.qtd_status = htole32(
3589 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
3590 EHCI_QTD_SET_TOGGLE(0) |
3591 EHCI_QTD_SET_BYTES(sizeof(*req))
3592 );
3593
3594 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
3595 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba));
3596 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba));
3597 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3598 setup->nextqtd = next;
3599 setup->xfer = xfer;
3600 setup->len = sizeof(*req);
3601
3602 status->qtd.qtd_status = htole32(
3603 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3604 EHCI_QTD_SET_TOGGLE(1) |
3605 EHCI_QTD_IOC
3606 );
3607 status->qtd.qtd_buffer[0] = 0;
3608 status->qtd.qtd_buffer_hi[0] = 0;
3609 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL;
3610 status->nextqtd = NULL;
3611 status->xfer = xfer;
3612 status->len = 0;
3613
3614 return 0;
3615 bad3:
3616 ehci_free_sqtd(sc, exfer->ex_status);
3617 bad2:
3618 ehci_free_sqtd(sc, exfer->ex_setup);
3619 bad1:
3620 return err;
3621 }
3622
3623 Static void
ehci_device_ctrl_fini(struct usbd_xfer * xfer)3624 ehci_device_ctrl_fini(struct usbd_xfer *xfer)
3625 {
3626 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3627 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
3628
3629 KASSERT(ex->ex_type == EX_CTRL);
3630
3631 ehci_free_sqtd(sc, ex->ex_setup);
3632 ehci_free_sqtd(sc, ex->ex_status);
3633 ehci_free_sqtds(sc, ex);
3634 if (ex->ex_nsqtd)
3635 kmem_free(ex->ex_sqtds,
3636 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd);
3637 }
3638
3639 Static usbd_status
ehci_device_ctrl_transfer(struct usbd_xfer * xfer)3640 ehci_device_ctrl_transfer(struct usbd_xfer *xfer)
3641 {
3642
3643 /* Pipe isn't running, start first */
3644 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3645 }
3646
3647 Static usbd_status
ehci_device_ctrl_start(struct usbd_xfer * xfer)3648 ehci_device_ctrl_start(struct usbd_xfer *xfer)
3649 {
3650 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3651 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3652 usb_device_request_t *req = &xfer->ux_request;
3653 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3654 ehci_soft_qtd_t *setup, *status, *next;
3655 ehci_soft_qh_t *sqh;
3656
3657 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3658
3659 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3660 KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3661
3662 if (sc->sc_dying)
3663 return USBD_IOERROR;
3664
3665 const int isread = req->bmRequestType & UT_READ;
3666 const int len = UGETW(req->wLength);
3667
3668 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx",
3669 req->bmRequestType, req->bRequest, UGETW(req->wValue),
3670 UGETW(req->wIndex));
3671 DPRINTF("len=%jd, addr=%jd, endpt=%jd",
3672 len, epipe->pipe.up_dev->ud_addr,
3673 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0);
3674
3675 sqh = epipe->sqh;
3676
3677 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr,
3678 "address QH %" __PRIuBIT " pipe %d\n",
3679 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)),
3680 epipe->pipe.up_dev->ud_addr);
3681 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) ==
3682 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
3683 "MPS QH %" __PRIuBIT " pipe %d\n",
3684 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)),
3685 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
3686
3687 setup = exfer->ex_setup;
3688 status = exfer->ex_status;
3689
3690 DPRINTF("setup %#jx status %#jx data %#jx",
3691 (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0);
3692 KASSERTMSG(setup != NULL && status != NULL,
3693 "Failed memory allocation, setup %p status %p",
3694 setup, status);
3695
3696 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req));
3697 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
3698
3699 /* Clear toggle */
3700 setup->qtd.qtd_status &= ~htole32(
3701 EHCI_QTD_STATUS_MASK |
3702 EHCI_QTD_BYTES_MASK |
3703 EHCI_QTD_TOGGLE_MASK |
3704 EHCI_QTD_CERR_MASK
3705 );
3706 setup->qtd.qtd_status |= htole32(
3707 EHCI_QTD_ACTIVE |
3708 EHCI_QTD_SET_CERR(3) |
3709 EHCI_QTD_SET_TOGGLE(0) |
3710 EHCI_QTD_SET_BYTES(sizeof(*req))
3711 );
3712
3713 const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
3714 setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba));
3715 setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba));
3716
3717 next = status;
3718 status->qtd.qtd_status &= ~htole32(
3719 EHCI_QTD_STATUS_MASK |
3720 EHCI_QTD_PID_MASK |
3721 EHCI_QTD_BYTES_MASK |
3722 EHCI_QTD_TOGGLE_MASK |
3723 EHCI_QTD_CERR_MASK
3724 );
3725 status->qtd.qtd_status |= htole32(
3726 EHCI_QTD_ACTIVE |
3727 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3728 EHCI_QTD_SET_CERR(3) |
3729 EHCI_QTD_SET_TOGGLE(1) |
3730 EHCI_QTD_SET_BYTES(0) |
3731 EHCI_QTD_IOC
3732 );
3733 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK));
3734
3735 KASSERT(exfer->ex_isdone);
3736 #ifdef DIAGNOSTIC
3737 exfer->ex_isdone = false;
3738 #endif
3739
3740 /* Set up data transaction */
3741 if (len != 0) {
3742 ehci_soft_qtd_t *end;
3743
3744 /* Start toggle at 1. */
3745 int toggle = 1;
3746 next = exfer->ex_data;
3747 KASSERTMSG(next != NULL, "Failed memory allocation");
3748 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end);
3749 end->nextqtd = status;
3750 end->qtd.qtd_next = end->qtd.qtd_altnext =
3751 htole32(status->physaddr);
3752
3753 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3754 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3755
3756 usb_syncmem(&xfer->ux_dmabuf, 0, len,
3757 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
3758 }
3759
3760 setup->nextqtd = next;
3761 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3762
3763 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd),
3764 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3765
3766 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd),
3767 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3768
3769 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK));
3770
3771 #ifdef EHCI_DEBUG
3772 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3773 ehci_dump_sqh(sqh);
3774 ehci_dump_sqtds(setup);
3775 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3776 #endif
3777
3778 /* Insert qTD in QH list - also does usb_syncmem(sqh) */
3779 ehci_set_qh_qtd(sqh, setup);
3780 usbd_xfer_schedule_timeout(xfer);
3781 ehci_add_intr_list(sc, exfer);
3782 xfer->ux_status = USBD_IN_PROGRESS;
3783
3784 #if 0
3785 #ifdef EHCI_DEBUG
3786 DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0);
3787 // delay(10000);
3788 ehci_dump_regs(sc);
3789 ehci_dump_sqh(sc->sc_async_head);
3790 ehci_dump_sqh(sqh);
3791 ehci_dump_sqtds(setup);
3792 #endif
3793 #endif
3794
3795 return USBD_IN_PROGRESS;
3796 }
3797
3798 Static void
ehci_device_ctrl_done(struct usbd_xfer * xfer)3799 ehci_device_ctrl_done(struct usbd_xfer *xfer)
3800 {
3801 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer);
3802 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3803 usb_device_request_t *req = &xfer->ux_request;
3804 int len = UGETW(req->wLength);
3805 int rd = req->bmRequestType & UT_READ;
3806
3807 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3808 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3809
3810 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3811 KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3812
3813 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req),
3814 BUS_DMASYNC_POSTWRITE);
3815 if (len)
3816 usb_syncmem(&xfer->ux_dmabuf, 0, len,
3817 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3818
3819 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0);
3820 }
3821
3822 /* Abort a device control request. */
3823 Static void
ehci_device_ctrl_abort(struct usbd_xfer * xfer)3824 ehci_device_ctrl_abort(struct usbd_xfer *xfer)
3825 {
3826 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3827
3828 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3829 usbd_xfer_abort(xfer);
3830 }
3831
3832 /* Close a device control pipe. */
3833 Static void
ehci_device_ctrl_close(struct usbd_pipe * pipe)3834 ehci_device_ctrl_close(struct usbd_pipe *pipe)
3835 {
3836 ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
3837 struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe);
3838
3839 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3840
3841 KASSERT(mutex_owned(&sc->sc_lock));
3842
3843 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
3844
3845 ehci_close_pipe(pipe, sc->sc_async_head);
3846
3847 usb_freemem(&epipe->ctrl.reqdma);
3848 }
3849
3850 /*
3851 * Some EHCI chips from VIA seem to trigger interrupts before writing back the
3852 * qTD status, or miss signalling occasionally under heavy load. If the host
3853 * machine is too fast, we can miss transaction completion - when we scan
3854 * the active list the transaction still seems to be active. This generally
3855 * exhibits itself as a umass stall that never recovers.
3856 *
3857 * We work around this behaviour by setting up this callback after any softintr
3858 * that completes with transactions still pending, giving us another chance to
3859 * check for completion after the writeback has taken place.
3860 */
3861 Static void
ehci_intrlist_timeout(void * arg)3862 ehci_intrlist_timeout(void *arg)
3863 {
3864 ehci_softc_t *sc = arg;
3865
3866 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3867
3868 usb_schedsoftintr(&sc->sc_bus);
3869 }
3870
3871 /************************/
3872
3873 Static int
ehci_device_bulk_init(struct usbd_xfer * xfer)3874 ehci_device_bulk_init(struct usbd_xfer *xfer)
3875 {
3876 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3877 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3878 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
3879 int endpt = ed->bEndpointAddress;
3880 int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3881 int len = xfer->ux_bufsize;
3882 int err = 0;
3883
3884 exfer->ex_type = EX_BULK;
3885 exfer->ex_nsqtd = 0;
3886 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread,
3887 &exfer->ex_sqtdstart);
3888
3889 return err;
3890 }
3891
3892 Static void
ehci_device_bulk_fini(struct usbd_xfer * xfer)3893 ehci_device_bulk_fini(struct usbd_xfer *xfer)
3894 {
3895 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3896 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
3897
3898 KASSERT(ex->ex_type == EX_BULK);
3899
3900 ehci_free_sqtds(sc, ex);
3901 if (ex->ex_nsqtd)
3902 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd);
3903 }
3904
3905 Static usbd_status
ehci_device_bulk_transfer(struct usbd_xfer * xfer)3906 ehci_device_bulk_transfer(struct usbd_xfer *xfer)
3907 {
3908
3909 /* Pipe isn't running, start first */
3910 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3911 }
3912
3913 Static usbd_status
ehci_device_bulk_start(struct usbd_xfer * xfer)3914 ehci_device_bulk_start(struct usbd_xfer *xfer)
3915 {
3916 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3917 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3918 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3919 ehci_soft_qh_t *sqh;
3920 ehci_soft_qtd_t *end;
3921 int len, isread, endpt;
3922
3923 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3924
3925 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
3926 xfer->ux_flags, 0);
3927
3928 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3929
3930 if (sc->sc_dying)
3931 return USBD_IOERROR;
3932
3933 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3934 KASSERT(xfer->ux_length <= xfer->ux_bufsize);
3935
3936 len = xfer->ux_length;
3937 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3938 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3939 sqh = epipe->sqh;
3940
3941 KASSERT(exfer->ex_isdone);
3942 #ifdef DIAGNOSTIC
3943 exfer->ex_isdone = false;
3944 #endif
3945
3946 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end);
3947
3948 exfer->ex_sqtdend = end;
3949 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
3950 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3951 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3952
3953 #ifdef EHCI_DEBUG
3954 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3955 ehci_dump_sqh(sqh);
3956 ehci_dump_sqtds(exfer->ex_sqtdstart);
3957 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3958 #endif
3959
3960 if (xfer->ux_length)
3961 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3962 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
3963
3964 /* also does usb_syncmem(sqh) */
3965 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart);
3966 usbd_xfer_schedule_timeout(xfer);
3967 ehci_add_intr_list(sc, exfer);
3968 xfer->ux_status = USBD_IN_PROGRESS;
3969
3970 #if 0
3971 #ifdef EHCI_DEBUG
3972 DPRINTFN(5, "data(2)", 0, 0, 0, 0);
3973 // delay(10000);
3974 DPRINTFN(5, "data(3)", 0, 0, 0, 0);
3975 ehci_dump_regs(sc);
3976 #if 0
3977 printf("async_head:\n");
3978 ehci_dump_sqh(sc->sc_async_head);
3979 #endif
3980 DPRINTF("sqh:", 0, 0, 0, 0);
3981 ehci_dump_sqh(sqh);
3982 ehci_dump_sqtds(exfer->ex_sqtdstart);
3983 #endif
3984 #endif
3985
3986 return USBD_IN_PROGRESS;
3987 }
3988
3989 Static void
ehci_device_bulk_abort(struct usbd_xfer * xfer)3990 ehci_device_bulk_abort(struct usbd_xfer *xfer)
3991 {
3992 EHCIHIST_FUNC(); EHCIHIST_CALLED();
3993
3994 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
3995 usbd_xfer_abort(xfer);
3996 }
3997
3998 /*
3999 * Close a device bulk pipe.
4000 */
4001 Static void
ehci_device_bulk_close(struct usbd_pipe * pipe)4002 ehci_device_bulk_close(struct usbd_pipe *pipe)
4003 {
4004 ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
4005 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
4006
4007 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4008
4009 KASSERT(mutex_owned(&sc->sc_lock));
4010
4011 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
4012 pipe->up_endpoint->ue_toggle = epipe->nexttoggle;
4013 ehci_close_pipe(pipe, sc->sc_async_head);
4014 }
4015
4016 Static void
ehci_device_bulk_done(struct usbd_xfer * xfer)4017 ehci_device_bulk_done(struct usbd_xfer *xfer)
4018 {
4019 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer);
4020 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4021 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4022 int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
4023
4024 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4025
4026 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0);
4027
4028 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4029
4030 if (xfer->ux_length)
4031 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4032 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
4033
4034 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0);
4035 }
4036
4037 /************************/
4038
4039 Static usbd_status
ehci_device_setintr(ehci_softc_t * sc,ehci_soft_qh_t * sqh,int ival)4040 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
4041 {
4042 struct ehci_soft_islot *isp;
4043 int islot, lev;
4044
4045 /* Find a poll rate that is large enough. */
4046 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
4047 if (EHCI_ILEV_IVAL(lev) <= ival)
4048 break;
4049
4050 /* Pick an interrupt slot at the right level. */
4051 /* XXX could do better than picking at random */
4052 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize;
4053 islot = EHCI_IQHIDX(lev, sc->sc_rand);
4054
4055 sqh->islot = islot;
4056 isp = &sc->sc_islots[islot];
4057 mutex_enter(&sc->sc_lock);
4058 ehci_add_qh(sc, sqh, isp->sqh);
4059 mutex_exit(&sc->sc_lock);
4060
4061 return USBD_NORMAL_COMPLETION;
4062 }
4063
4064 Static int
ehci_device_intr_init(struct usbd_xfer * xfer)4065 ehci_device_intr_init(struct usbd_xfer *xfer)
4066 {
4067 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4068 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4069 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
4070 int endpt = ed->bEndpointAddress;
4071 int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
4072 int len = xfer->ux_bufsize;
4073 int err;
4074
4075 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4076
4077 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
4078 xfer->ux_flags, 0);
4079
4080 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4081 KASSERT(len != 0);
4082
4083 exfer->ex_type = EX_INTR;
4084 exfer->ex_nsqtd = 0;
4085 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread,
4086 &exfer->ex_sqtdstart);
4087
4088 return err;
4089 }
4090
4091 Static void
ehci_device_intr_fini(struct usbd_xfer * xfer)4092 ehci_device_intr_fini(struct usbd_xfer *xfer)
4093 {
4094 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4095 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
4096
4097 KASSERT(ex->ex_type == EX_INTR);
4098
4099 ehci_free_sqtds(sc, ex);
4100 if (ex->ex_nsqtd)
4101 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd);
4102 }
4103
4104 Static usbd_status
ehci_device_intr_transfer(struct usbd_xfer * xfer)4105 ehci_device_intr_transfer(struct usbd_xfer *xfer)
4106 {
4107
4108 /* Pipe isn't running, so start it first. */
4109 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
4110 }
4111
4112 Static usbd_status
ehci_device_intr_start(struct usbd_xfer * xfer)4113 ehci_device_intr_start(struct usbd_xfer *xfer)
4114 {
4115 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4116 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4117 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4118 ehci_soft_qtd_t *end;
4119 ehci_soft_qh_t *sqh;
4120 int len, isread, endpt;
4121
4122 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4123
4124 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
4125 xfer->ux_flags, 0);
4126
4127 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4128
4129 if (sc->sc_dying)
4130 return USBD_IOERROR;
4131
4132 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4133 KASSERT(xfer->ux_length <= xfer->ux_bufsize);
4134
4135 len = xfer->ux_length;
4136 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4137 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
4138 sqh = epipe->sqh;
4139
4140 KASSERT(exfer->ex_isdone);
4141 #ifdef DIAGNOSTIC
4142 exfer->ex_isdone = false;
4143 #endif
4144
4145 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end);
4146
4147 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
4148 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
4149 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4150 exfer->ex_sqtdend = end;
4151
4152 #ifdef EHCI_DEBUG
4153 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
4154 ehci_dump_sqh(sqh);
4155 ehci_dump_sqtds(exfer->ex_sqtdstart);
4156 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
4157 #endif
4158
4159 if (xfer->ux_length)
4160 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4161 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
4162
4163 /* also does usb_syncmem(sqh) */
4164 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart);
4165 usbd_xfer_schedule_timeout(xfer);
4166 ehci_add_intr_list(sc, exfer);
4167 xfer->ux_status = USBD_IN_PROGRESS;
4168
4169 #if 0
4170 #ifdef EHCI_DEBUG
4171 DPRINTFN(5, "data(2)", 0, 0, 0, 0);
4172 // delay(10000);
4173 DPRINTFN(5, "data(3)", 0, 0, 0, 0);
4174 ehci_dump_regs(sc);
4175 DPRINTFN(5, "sqh:", 0, 0, 0, 0);
4176 ehci_dump_sqh(sqh);
4177 ehci_dump_sqtds(exfer->ex_sqtdstart);
4178 #endif
4179 #endif
4180
4181 return USBD_IN_PROGRESS;
4182 }
4183
4184 Static void
ehci_device_intr_abort(struct usbd_xfer * xfer)4185 ehci_device_intr_abort(struct usbd_xfer *xfer)
4186 {
4187 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4188
4189 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
4190
4191 /*
4192 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance
4193 * async doorbell. That's dependent on the async list, wheras
4194 * intr xfers are periodic, should not use this?
4195 */
4196 usbd_xfer_abort(xfer);
4197 }
4198
4199 Static void
ehci_device_intr_close(struct usbd_pipe * pipe)4200 ehci_device_intr_close(struct usbd_pipe *pipe)
4201 {
4202 ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
4203 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
4204 struct ehci_soft_islot *isp;
4205
4206 KASSERT(mutex_owned(&sc->sc_lock));
4207
4208 isp = &sc->sc_islots[epipe->sqh->islot];
4209 ehci_close_pipe(pipe, isp->sqh);
4210 }
4211
4212 Static void
ehci_device_intr_done(struct usbd_xfer * xfer)4213 ehci_device_intr_done(struct usbd_xfer *xfer)
4214 {
4215 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer);
4216 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4217
4218 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4219
4220 DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0);
4221
4222 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4223
4224 if (xfer->ux_length) {
4225 int isread, endpt;
4226
4227 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4228 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
4229 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4230 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
4231 }
4232 }
4233
4234 /************************/
4235 Static int
ehci_device_fs_isoc_init(struct usbd_xfer * xfer)4236 ehci_device_fs_isoc_init(struct usbd_xfer *xfer)
4237 {
4238 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe);
4239 struct usbd_device *dev = xfer->ux_pipe->up_dev;
4240 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4241 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4242 ehci_soft_sitd_t *sitd, *prev, *start, *stop;
4243 int i, k, frames;
4244 u_int huba, dir;
4245 int err;
4246
4247 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4248
4249 start = NULL;
4250 sitd = NULL;
4251
4252 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length,
4253 xfer->ux_flags, 0);
4254
4255 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4256 KASSERT(xfer->ux_nframes != 0);
4257 KASSERT(exfer->ex_isdone);
4258
4259 exfer->ex_type = EX_FS_ISOC;
4260 /*
4261 * Step 1: Allocate and initialize sitds.
4262 */
4263 i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4264 if (i > 16 || i == 0) {
4265 /* Spec page 271 says intervals > 16 are invalid */
4266 DPRINTF("bInterval %jd invalid", i, 0, 0, 0);
4267 return EINVAL;
4268 }
4269
4270 frames = xfer->ux_nframes;
4271 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) {
4272 sitd = ehci_alloc_sitd(sc);
4273 if (sitd == NULL) {
4274 err = ENOMEM;
4275 goto fail;
4276 }
4277
4278 if (prev)
4279 prev->xfer_next = sitd;
4280 else
4281 start = sitd;
4282
4283 huba = dev->ud_myhsport->up_parent->ud_addr;
4284
4285 #if 0
4286 if (sc->sc_flags & EHCIF_FREESCALE) {
4287 // Set hub address to 0 if embedded TT is used.
4288 if (huba == sc->sc_addr)
4289 huba = 0;
4290 }
4291 #endif
4292
4293 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4294 dir = UE_GET_DIR(k) ? 1 : 0;
4295 sitd->sitd.sitd_endp =
4296 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) |
4297 EHCI_SITD_SET_DADDR(dev->ud_addr) |
4298 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) |
4299 EHCI_SITD_SET_HUBA(huba) |
4300 EHCI_SITD_SET_DIR(dir));
4301
4302 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE);
4303 } /* End of frame */
4304
4305 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC);
4306
4307 stop = sitd;
4308 stop->xfer_next = NULL;
4309 exfer->ex_sitdstart = start;
4310 exfer->ex_sitdend = stop;
4311
4312 return 0;
4313
4314 fail:
4315 mutex_enter(&sc->sc_lock);
4316 ehci_soft_sitd_t *next;
4317 for (sitd = start; sitd; sitd = next) {
4318 next = sitd->xfer_next;
4319 ehci_free_sitd_locked(sc, sitd);
4320 }
4321 mutex_exit(&sc->sc_lock);
4322
4323 return err;
4324 }
4325
4326 Static void
ehci_device_fs_isoc_fini(struct usbd_xfer * xfer)4327 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer)
4328 {
4329 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4330 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
4331
4332 KASSERT(ex->ex_type == EX_FS_ISOC);
4333
4334 ehci_free_sitd_chain(sc, ex->ex_sitdstart);
4335 }
4336
4337 Static usbd_status
ehci_device_fs_isoc_transfer(struct usbd_xfer * xfer)4338 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer)
4339 {
4340 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4341 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4342 struct usbd_device *dev = xfer->ux_pipe->up_dev;
4343 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4344 ehci_soft_sitd_t *sitd;
4345 usb_dma_t *dma_buf;
4346 int i, j, k, frames;
4347 int offs;
4348 int frindex;
4349 u_int dir;
4350
4351 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4352
4353 sitd = NULL;
4354
4355 DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length,
4356 xfer->ux_flags, 0);
4357
4358 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4359
4360 if (sc->sc_dying)
4361 return USBD_IOERROR;
4362
4363 /*
4364 * To avoid complication, don't allow a request right now that'll span
4365 * the entire frame table. To within 4 frames, to allow some leeway
4366 * on either side of where the hc currently is.
4367 */
4368 if (epipe->pipe.up_endpoint->ue_edesc->bInterval *
4369 xfer->ux_nframes >= sc->sc_flsize - 4) {
4370 printf("ehci: isoc descriptor requested that spans the entire"
4371 " frametable, too many frames\n");
4372 return USBD_INVAL;
4373 }
4374
4375 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths);
4376 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4377 KASSERT(exfer->ex_isdone);
4378 #ifdef DIAGNOSTIC
4379 exfer->ex_isdone = false;
4380 #endif
4381
4382 /*
4383 * Step 1: Initialize sitds.
4384 */
4385
4386 frames = xfer->ux_nframes;
4387 dma_buf = &xfer->ux_dmabuf;
4388 offs = 0;
4389
4390 for (sitd = exfer->ex_sitdstart, i = 0; i < frames;
4391 i++, sitd = sitd->xfer_next) {
4392 KASSERT(sitd != NULL);
4393 KASSERT(xfer->ux_frlengths[i] <= 0x3ff);
4394
4395 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE |
4396 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i]));
4397
4398 /* Set page0 index and offset - TP and T-offset are set below */
4399 const bus_addr_t sba = DMAADDR(dma_buf, offs);
4400 sitd->sitd.sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba));
4401 sitd->sitd.sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba));
4402
4403 offs += xfer->ux_frlengths[i];
4404
4405 const bus_addr_t eba = DMAADDR(dma_buf, offs - 1);
4406 sitd->sitd.sitd_buffer[1] =
4407 htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba)));
4408 sitd->sitd.sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba));
4409
4410 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr;
4411
4412 #if 0
4413 if (sc->sc_flags & EHCIF_FREESCALE) {
4414 // Set hub address to 0 if embedded TT is used.
4415 if (huba == sc->sc_addr)
4416 huba = 0;
4417 }
4418 #endif
4419
4420 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4421 dir = UE_GET_DIR(k) ? 1 : 0;
4422 KASSERT(sitd->sitd.sitd_endp == htole32(
4423 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) |
4424 EHCI_SITD_SET_DADDR(dev->ud_addr) |
4425 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) |
4426 EHCI_SITD_SET_HUBA(huba) |
4427 EHCI_SITD_SET_DIR(dir)));
4428 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE));
4429
4430 uint8_t sa = 0;
4431 uint8_t sb = 0;
4432 u_int temp, tlen;
4433
4434 if (dir == 0) { /* OUT */
4435 temp = 0;
4436 tlen = xfer->ux_frlengths[i];
4437 if (tlen <= 188) {
4438 temp |= 1; /* T-count = 1, TP = ALL */
4439 tlen = 1;
4440 } else {
4441 tlen += 187;
4442 tlen /= 188;
4443 temp |= tlen; /* T-count = [1..6] */
4444 temp |= 8; /* TP = Begin */
4445 }
4446 sitd->sitd.sitd_buffer[1] |= htole32(temp);
4447
4448 tlen += sa;
4449
4450 if (tlen >= 8) {
4451 sb = 0;
4452 } else {
4453 sb = (1 << tlen);
4454 }
4455
4456 sa = (1 << sa);
4457 sa = (sb - sa) & 0x3F;
4458 sb = 0;
4459 } else {
4460 sb = (-(4 << sa)) & 0xFE;
4461 sa = (1 << sa) & 0x3F;
4462 sa = 0x01;
4463 sb = 0xfc;
4464 }
4465
4466 sitd->sitd.sitd_sched = htole32(
4467 EHCI_SITD_SET_SMASK(sa) |
4468 EHCI_SITD_SET_CMASK(sb)
4469 );
4470
4471 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t),
4472 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4473 } /* End of frame */
4474
4475 sitd = exfer->ex_sitdend;
4476 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC);
4477
4478 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
4479 sizeof(sitd->sitd.sitd_trans),
4480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4481
4482 if (xfer->ux_length)
4483 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length,
4484 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4485
4486 /*
4487 * Part 2: Transfer descriptors have now been set up, now they must
4488 * be scheduled into the periodic frame list. Erk. Not wanting to
4489 * complicate matters, transfer is denied if the transfer spans
4490 * more than the periodic frame list.
4491 */
4492
4493 /* Start inserting frames */
4494 if (epipe->isoc.cur_xfers > 0) {
4495 frindex = epipe->isoc.next_frame;
4496 } else {
4497 frindex = EOREAD4(sc, EHCI_FRINDEX);
4498 frindex = frindex >> 3; /* Erase microframe index */
4499 frindex += 2;
4500 }
4501
4502 if (frindex >= sc->sc_flsize)
4503 frindex &= (sc->sc_flsize - 1);
4504
4505 /* What's the frame interval? */
4506 i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4507
4508 for (sitd = exfer->ex_sitdstart, j = 0; j < frames;
4509 j++, sitd = sitd->xfer_next) {
4510 KASSERT(sitd);
4511
4512 usb_syncmem(&sc->sc_fldma,
4513 sizeof(ehci_link_t) * frindex,
4514 sizeof(ehci_link_t),
4515 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4516
4517 sitd->sitd.sitd_next = sc->sc_flist[frindex];
4518 if (sitd->sitd.sitd_next == 0)
4519 /*
4520 * FIXME: frindex table gets initialized to NULL
4521 * or EHCI_NULL?
4522 */
4523 sitd->sitd.sitd_next = EHCI_NULL;
4524
4525 usb_syncmem(&sitd->dma,
4526 sitd->offs + offsetof(ehci_sitd_t, sitd_next),
4527 sizeof(ehci_sitd_t),
4528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4529
4530 sc->sc_flist[frindex] =
4531 htole32(EHCI_LINK_SITD | sitd->physaddr);
4532
4533 usb_syncmem(&sc->sc_fldma,
4534 sizeof(ehci_link_t) * frindex,
4535 sizeof(ehci_link_t),
4536 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4537
4538 sitd->frame_list.next = sc->sc_softsitds[frindex];
4539 sc->sc_softsitds[frindex] = sitd;
4540 if (sitd->frame_list.next != NULL)
4541 sitd->frame_list.next->frame_list.prev = sitd;
4542 sitd->slot = frindex;
4543 sitd->frame_list.prev = NULL;
4544
4545 frindex += i;
4546 if (frindex >= sc->sc_flsize)
4547 frindex -= sc->sc_flsize;
4548 }
4549
4550 epipe->isoc.cur_xfers++;
4551 epipe->isoc.next_frame = frindex;
4552
4553 ehci_add_intr_list(sc, exfer);
4554 xfer->ux_status = USBD_IN_PROGRESS;
4555
4556 return USBD_IN_PROGRESS;
4557 }
4558
4559 Static void
ehci_device_fs_isoc_abort(struct usbd_xfer * xfer)4560 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer)
4561 {
4562 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4563
4564 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0);
4565 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
4566 }
4567
4568 Static void
ehci_device_fs_isoc_close(struct usbd_pipe * pipe)4569 ehci_device_fs_isoc_close(struct usbd_pipe *pipe)
4570 {
4571 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4572
4573 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0);
4574 }
4575
4576 Static void
ehci_device_fs_isoc_done(struct usbd_xfer * xfer)4577 ehci_device_fs_isoc_done(struct usbd_xfer *xfer)
4578 {
4579 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4580 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4581 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4582
4583 KASSERT(mutex_owned(&sc->sc_lock));
4584
4585 epipe->isoc.cur_xfers--;
4586 ehci_remove_sitd_chain(sc, exfer->ex_itdstart);
4587
4588 if (xfer->ux_length)
4589 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4590 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4591 }
4592
4593 /* -------------------------------------------------------------------------- */
4594
4595 Static int
ehci_device_isoc_init(struct usbd_xfer * xfer)4596 ehci_device_isoc_init(struct usbd_xfer *xfer)
4597 {
4598 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4599 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4600 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4601 ehci_soft_itd_t *itd, *prev, *start, *stop;
4602 int i, j, k;
4603 int frames, ufrperframe;
4604 int err;
4605
4606 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4607
4608 start = NULL;
4609 prev = NULL;
4610 itd = NULL;
4611
4612 KASSERT(xfer->ux_nframes != 0);
4613 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4614 KASSERT(exfer->ex_isdone);
4615
4616 exfer->ex_type = EX_ISOC;
4617
4618 /*
4619 * Step 1: Allocate and initialize itds, how many do we need?
4620 * One per transfer if interval >= 8 microframes, less if we use
4621 * multiple microframes per frame.
4622 */
4623 i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4624 if (i > 16 || i == 0) {
4625 /* Spec page 271 says intervals > 16 are invalid */
4626 DPRINTF("bInterval %jd invalid", i, 0, 0, 0);
4627 return EINVAL;
4628 }
4629
4630 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
4631 frames = howmany(xfer->ux_nframes, ufrperframe);
4632
4633 for (i = 0, prev = NULL; i < frames; i++, prev = itd) {
4634 itd = ehci_alloc_itd(sc);
4635 if (itd == NULL) {
4636 err = ENOMEM;
4637 goto fail;
4638 }
4639
4640 if (prev != NULL) {
4641 /* Maybe not as it's updated by the scheduling? */
4642 prev->itd.itd_next =
4643 htole32(itd->physaddr | EHCI_LINK_ITD);
4644
4645 prev->xfer_next = itd;
4646 } else {
4647 start = itd;
4648 }
4649
4650 /*
4651 * Other special values
4652 */
4653 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4654 itd->itd.itd_bufr[0] = htole32(
4655 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
4656 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr));
4657
4658 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress))
4659 ? 1 : 0;
4660 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
4661 itd->itd.itd_bufr[1] |= htole32(
4662 EHCI_ITD_SET_DIR(k) |
4663 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
4664
4665 /* FIXME: handle invalid trans - should be done in openpipe */
4666 itd->itd.itd_bufr[2] |=
4667 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
4668 } /* End of frame */
4669
4670 stop = itd;
4671 stop->xfer_next = NULL;
4672
4673 exfer->ex_itdstart = start;
4674 exfer->ex_itdend = stop;
4675
4676 return 0;
4677 fail:
4678 mutex_enter(&sc->sc_lock);
4679 ehci_soft_itd_t *next;
4680 for (itd = start; itd; itd = next) {
4681 next = itd->xfer_next;
4682 ehci_free_itd_locked(sc, itd);
4683 }
4684 mutex_exit(&sc->sc_lock);
4685
4686 return err;
4687
4688 }
4689
4690 Static void
ehci_device_isoc_fini(struct usbd_xfer * xfer)4691 ehci_device_isoc_fini(struct usbd_xfer *xfer)
4692 {
4693 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4694 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
4695
4696 KASSERT(ex->ex_type == EX_ISOC);
4697
4698 ehci_free_itd_chain(sc, ex->ex_itdstart);
4699 }
4700
4701 Static usbd_status
ehci_device_isoc_transfer(struct usbd_xfer * xfer)4702 ehci_device_isoc_transfer(struct usbd_xfer *xfer)
4703 {
4704 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4705 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4706 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4707 ehci_soft_itd_t *itd, *prev;
4708 usb_dma_t *dma_buf;
4709 int i, j;
4710 int frames, uframes, ufrperframe;
4711 int trans_count, offs;
4712 int frindex;
4713
4714 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4715
4716 prev = NULL;
4717 itd = NULL;
4718 trans_count = 0;
4719
4720 DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0);
4721
4722 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4723
4724 if (sc->sc_dying)
4725 return USBD_IOERROR;
4726
4727 /*
4728 * To avoid complication, don't allow a request right now that'll span
4729 * the entire frame table. To within 4 frames, to allow some leeway
4730 * on either side of where the hc currently is.
4731 */
4732 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) *
4733 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) {
4734 DPRINTF(
4735 "isoc descriptor spans entire frametable", 0, 0, 0, 0);
4736 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n");
4737 return USBD_INVAL;
4738 }
4739
4740 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths);
4741 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4742 KASSERT(exfer->ex_isdone);
4743 #ifdef DIAGNOSTIC
4744 exfer->ex_isdone = false;
4745 #endif
4746
4747 /*
4748 * Step 1: Re-Initialize itds
4749 */
4750
4751 i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4752 if (i > 16 || i == 0) {
4753 /* Spec page 271 says intervals > 16 are invalid */
4754 DPRINTF("bInterval %jd invalid", i, 0, 0, 0);
4755 return USBD_INVAL;
4756 }
4757
4758 ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
4759 frames = howmany(xfer->ux_nframes, ufrperframe);
4760 uframes = USB_UFRAMES_PER_FRAME / ufrperframe;
4761
4762 if (frames == 0) {
4763 DPRINTF("frames == 0", 0, 0, 0, 0);
4764 return USBD_INVAL;
4765 }
4766
4767 dma_buf = &xfer->ux_dmabuf;
4768 offs = 0;
4769
4770 itd = exfer->ex_itdstart;
4771 for (i = 0; i < frames; i++, itd = itd->xfer_next) {
4772 int froffs = offs;
4773
4774 if (prev != NULL) {
4775 prev->itd.itd_next =
4776 htole32(itd->physaddr | EHCI_LINK_ITD);
4777 usb_syncmem(&prev->dma,
4778 prev->offs + offsetof(ehci_itd_t, itd_next),
4779 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE);
4780 prev->xfer_next = itd;
4781 }
4782
4783 /*
4784 * Step 1.5, initialize uframes
4785 */
4786 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) {
4787 /* Calculate which page in the list this starts in */
4788 int addr = DMAADDR(dma_buf, froffs);
4789 addr = EHCI_PAGE_OFFSET(addr);
4790 addr += (offs - froffs);
4791 addr = EHCI_PAGE(addr);
4792 addr /= EHCI_PAGE_SIZE;
4793
4794 /*
4795 * This gets the initial offset into the first page,
4796 * looks how far further along the current uframe
4797 * offset is. Works out how many pages that is.
4798 */
4799
4800 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE |
4801 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) |
4802 EHCI_ITD_SET_PG(addr) |
4803 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
4804
4805 offs += xfer->ux_frlengths[trans_count];
4806 trans_count++;
4807
4808 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/
4809 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC);
4810 break;
4811 }
4812 }
4813
4814 /*
4815 * Step 1.75, set buffer pointers. To simplify matters, all
4816 * pointers are filled out for the next 7 hardware pages in
4817 * the dma block, so no need to worry what pages to cover
4818 * and what to not.
4819 */
4820
4821 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) {
4822 /*
4823 * Don't try to lookup a page that's past the end
4824 * of buffer
4825 */
4826 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j));
4827 if (page_offs >= dma_buf->udma_block->size)
4828 break;
4829
4830 uint64_t page = DMAADDR(dma_buf, page_offs);
4831 page = EHCI_PAGE(page);
4832 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page));
4833 itd->itd.itd_bufr_hi[j] = htole32(page >> 32);
4834 }
4835 /*
4836 * Other special values
4837 */
4838
4839 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4840 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
4841 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr));
4842
4843 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress))
4844 ? 1 : 0;
4845 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
4846 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) |
4847 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
4848
4849 /* FIXME: handle invalid trans */
4850 itd->itd.itd_bufr[2] |=
4851 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
4852
4853 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t),
4854 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4855
4856 prev = itd;
4857 } /* End of frame */
4858
4859 if (xfer->ux_length)
4860 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length,
4861 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4862
4863 /*
4864 * Part 2: Transfer descriptors have now been set up, now they must
4865 * be scheduled into the periodic frame list. Erk. Not wanting to
4866 * complicate matters, transfer is denied if the transfer spans
4867 * more than the periodic frame list.
4868 */
4869
4870 /* Start inserting frames */
4871 if (epipe->isoc.cur_xfers > 0) {
4872 frindex = epipe->isoc.next_frame;
4873 } else {
4874 frindex = EOREAD4(sc, EHCI_FRINDEX);
4875 frindex = frindex >> 3; /* Erase microframe index */
4876 frindex += 2;
4877 }
4878
4879 if (frindex >= sc->sc_flsize)
4880 frindex &= (sc->sc_flsize - 1);
4881
4882 /* What's the frame interval? */
4883 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1));
4884 if (i / USB_UFRAMES_PER_FRAME == 0)
4885 i = 1;
4886 else
4887 i /= USB_UFRAMES_PER_FRAME;
4888
4889 itd = exfer->ex_itdstart;
4890 for (j = 0; j < frames; j++) {
4891 KASSERTMSG(itd != NULL, "frame %d\n", j);
4892
4893 usb_syncmem(&sc->sc_fldma,
4894 sizeof(ehci_link_t) * frindex,
4895 sizeof(ehci_link_t),
4896 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4897
4898 itd->itd.itd_next = sc->sc_flist[frindex];
4899 if (itd->itd.itd_next == 0)
4900 /*
4901 * FIXME: frindex table gets initialized to NULL
4902 * or EHCI_NULL?
4903 */
4904 itd->itd.itd_next = EHCI_NULL;
4905
4906 usb_syncmem(&itd->dma,
4907 itd->offs + offsetof(ehci_itd_t, itd_next),
4908 sizeof(itd->itd.itd_next),
4909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4910
4911 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr);
4912
4913 usb_syncmem(&sc->sc_fldma,
4914 sizeof(ehci_link_t) * frindex,
4915 sizeof(ehci_link_t),
4916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4917
4918 itd->frame_list.next = sc->sc_softitds[frindex];
4919 sc->sc_softitds[frindex] = itd;
4920 if (itd->frame_list.next != NULL)
4921 itd->frame_list.next->frame_list.prev = itd;
4922 itd->slot = frindex;
4923 itd->frame_list.prev = NULL;
4924
4925 frindex += i;
4926 if (frindex >= sc->sc_flsize)
4927 frindex -= sc->sc_flsize;
4928
4929 itd = itd->xfer_next;
4930 }
4931
4932 epipe->isoc.cur_xfers++;
4933 epipe->isoc.next_frame = frindex;
4934
4935 ehci_add_intr_list(sc, exfer);
4936 xfer->ux_status = USBD_IN_PROGRESS;
4937
4938 return USBD_IN_PROGRESS;
4939 }
4940
4941 Static void
ehci_device_isoc_abort(struct usbd_xfer * xfer)4942 ehci_device_isoc_abort(struct usbd_xfer *xfer)
4943 {
4944 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4945
4946 DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0);
4947 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
4948 }
4949
4950 Static void
ehci_device_isoc_close(struct usbd_pipe * pipe)4951 ehci_device_isoc_close(struct usbd_pipe *pipe)
4952 {
4953 EHCIHIST_FUNC(); EHCIHIST_CALLED();
4954
4955 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0);
4956 }
4957
4958 Static void
ehci_device_isoc_done(struct usbd_xfer * xfer)4959 ehci_device_isoc_done(struct usbd_xfer *xfer)
4960 {
4961 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4962 ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4963 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4964
4965 KASSERT(mutex_owned(&sc->sc_lock));
4966
4967 epipe->isoc.cur_xfers--;
4968 ehci_remove_itd_chain(sc, exfer->ex_sitdstart);
4969 if (xfer->ux_length)
4970 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4971 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4972 }
4973