1 /* $NetBSD: ehci.c,v 1.40 2002/11/19 19:18:09 martin Exp $ */ 2 3 /* 4 * TODO 5 * hold off explorations by companion controllers until ehci has started. 6 */ 7 8 /* 9 * Copyright (c) 2001 The NetBSD Foundation, Inc. 10 * All rights reserved. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Lennart Augustsson (lennart@augustsson.net). 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the NetBSD 26 * Foundation, Inc. and its contributors. 27 * 4. Neither the name of The NetBSD Foundation nor the names of its 28 * contributors may be used to endorse or promote products derived 29 * from this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 32 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 33 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 34 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 35 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 /* 45 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 46 * 47 * The EHCI 1.0 spec can be found at 48 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 49 * and the USB 2.0 spec at 50 * http://www.usb.org/developers/data/usb_20.zip 51 * 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.40 2002/11/19 19:18:09 martin Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/kernel.h> 60 #include <sys/malloc.h> 61 #include <sys/device.h> 62 #include <sys/select.h> 63 #include <sys/proc.h> 64 #include <sys/queue.h> 65 66 #include <machine/bus.h> 67 #include <machine/endian.h> 68 69 #include <dev/usb/usb.h> 70 #include <dev/usb/usbdi.h> 71 #include <dev/usb/usbdivar.h> 72 #include <dev/usb/usb_mem.h> 73 #include <dev/usb/usb_quirks.h> 74 75 #include <dev/usb/ehcireg.h> 76 #include <dev/usb/ehcivar.h> 77 78 #ifdef EHCI_DEBUG 79 #define DPRINTF(x) if (ehcidebug) printf x 80 #define DPRINTFN(n,x) if (ehcidebug>(n)) printf x 81 int ehcidebug = 0; 82 #ifndef __NetBSD__ 83 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 84 #endif 85 #else 86 #define DPRINTF(x) 87 #define DPRINTFN(n,x) 88 #endif 89 90 struct ehci_pipe { 91 struct usbd_pipe pipe; 92 ehci_soft_qh_t *sqh; 93 union { 94 ehci_soft_qtd_t *qtd; 95 /* ehci_soft_itd_t *itd; */ 96 } tail; 97 union { 98 /* Control pipe */ 99 struct { 100 usb_dma_t reqdma; 101 u_int length; 102 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 103 } ctl; 104 /* Interrupt pipe */ 105 /* XXX */ 106 /* Bulk pipe */ 107 struct { 108 u_int length; 109 } bulk; 110 /* Iso pipe */ 111 /* XXX */ 112 } u; 113 }; 114 115 Static void ehci_shutdown(void *); 116 Static void ehci_power(int, void *); 117 118 Static usbd_status ehci_open(usbd_pipe_handle); 119 Static void ehci_poll(struct usbd_bus *); 120 Static void ehci_softintr(void *); 121 Static int ehci_intr1(ehci_softc_t *); 122 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 123 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 124 Static void ehci_idone(struct ehci_xfer *); 125 Static void ehci_timeout(void *); 126 Static void ehci_timeout_task(void *); 127 128 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 129 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 130 131 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 132 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 133 134 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 135 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 136 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 137 Static void ehci_root_ctrl_close(usbd_pipe_handle); 138 Static void ehci_root_ctrl_done(usbd_xfer_handle); 139 140 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 141 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 142 Static void ehci_root_intr_abort(usbd_xfer_handle); 143 Static void ehci_root_intr_close(usbd_pipe_handle); 144 Static void ehci_root_intr_done(usbd_xfer_handle); 145 146 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 147 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 148 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 149 Static void ehci_device_ctrl_close(usbd_pipe_handle); 150 Static void ehci_device_ctrl_done(usbd_xfer_handle); 151 152 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 153 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 154 Static void ehci_device_bulk_abort(usbd_xfer_handle); 155 Static void ehci_device_bulk_close(usbd_pipe_handle); 156 Static void ehci_device_bulk_done(usbd_xfer_handle); 157 158 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 159 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 160 Static void ehci_device_intr_abort(usbd_xfer_handle); 161 Static void ehci_device_intr_close(usbd_pipe_handle); 162 Static void ehci_device_intr_done(usbd_xfer_handle); 163 164 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 165 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 166 Static void ehci_device_isoc_abort(usbd_xfer_handle); 167 Static void ehci_device_isoc_close(usbd_pipe_handle); 168 Static void ehci_device_isoc_done(usbd_xfer_handle); 169 170 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 171 Static void ehci_noop(usbd_pipe_handle pipe); 172 173 Static int ehci_str(usb_string_descriptor_t *, int, char *); 174 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 175 Static void ehci_pcd_able(ehci_softc_t *, int); 176 Static void ehci_pcd_enable(void *); 177 Static void ehci_disown(ehci_softc_t *, int, int); 178 179 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 180 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 181 182 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 183 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 184 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 185 ehci_softc_t *, int, int, usbd_xfer_handle, 186 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 187 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 188 ehci_soft_qtd_t *); 189 190 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 191 192 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 193 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 194 ehci_soft_qh_t *); 195 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 196 Static void ehci_sync_hc(ehci_softc_t *); 197 198 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 199 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 200 201 #ifdef EHCI_DEBUG 202 Static void ehci_dump_regs(ehci_softc_t *); 203 Static void ehci_dump(void); 204 Static ehci_softc_t *theehci; 205 Static void ehci_dump_link(ehci_link_t, int); 206 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 207 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 208 Static void ehci_dump_qtd(ehci_qtd_t *); 209 Static void ehci_dump_sqh(ehci_soft_qh_t *); 210 #ifdef DIAGNOSTIC 211 Static void ehci_dump_exfer(struct ehci_xfer *); 212 #endif 213 #endif 214 215 #define MS_TO_TICKS(ms) ((ms) * hz / 1000) 216 217 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 218 219 #define EHCI_INTR_ENDPT 1 220 221 #define ehci_add_intr_list(sc, ex) \ 222 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 223 #define ehci_del_intr_list(ex) \ 224 LIST_REMOVE((ex), inext) 225 226 Static struct usbd_bus_methods ehci_bus_methods = { 227 ehci_open, 228 ehci_softintr, 229 ehci_poll, 230 ehci_allocm, 231 ehci_freem, 232 ehci_allocx, 233 ehci_freex, 234 }; 235 236 Static struct usbd_pipe_methods ehci_root_ctrl_methods = { 237 ehci_root_ctrl_transfer, 238 ehci_root_ctrl_start, 239 ehci_root_ctrl_abort, 240 ehci_root_ctrl_close, 241 ehci_noop, 242 ehci_root_ctrl_done, 243 }; 244 245 Static struct usbd_pipe_methods ehci_root_intr_methods = { 246 ehci_root_intr_transfer, 247 ehci_root_intr_start, 248 ehci_root_intr_abort, 249 ehci_root_intr_close, 250 ehci_noop, 251 ehci_root_intr_done, 252 }; 253 254 Static struct usbd_pipe_methods ehci_device_ctrl_methods = { 255 ehci_device_ctrl_transfer, 256 ehci_device_ctrl_start, 257 ehci_device_ctrl_abort, 258 ehci_device_ctrl_close, 259 ehci_noop, 260 ehci_device_ctrl_done, 261 }; 262 263 Static struct usbd_pipe_methods ehci_device_intr_methods = { 264 ehci_device_intr_transfer, 265 ehci_device_intr_start, 266 ehci_device_intr_abort, 267 ehci_device_intr_close, 268 ehci_device_clear_toggle, 269 ehci_device_intr_done, 270 }; 271 272 Static struct usbd_pipe_methods ehci_device_bulk_methods = { 273 ehci_device_bulk_transfer, 274 ehci_device_bulk_start, 275 ehci_device_bulk_abort, 276 ehci_device_bulk_close, 277 ehci_device_clear_toggle, 278 ehci_device_bulk_done, 279 }; 280 281 Static struct usbd_pipe_methods ehci_device_isoc_methods = { 282 ehci_device_isoc_transfer, 283 ehci_device_isoc_start, 284 ehci_device_isoc_abort, 285 ehci_device_isoc_close, 286 ehci_noop, 287 ehci_device_isoc_done, 288 }; 289 290 usbd_status 291 ehci_init(ehci_softc_t *sc) 292 { 293 u_int32_t version, sparams, cparams, hcr; 294 u_int i; 295 usbd_status err; 296 ehci_soft_qh_t *sqh; 297 298 DPRINTF(("ehci_init: start\n")); 299 #ifdef EHCI_DEBUG 300 theehci = sc; 301 #endif 302 303 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 304 305 version = EREAD2(sc, EHCI_HCIVERSION); 306 printf("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 307 version >> 8, version & 0xff); 308 309 sparams = EREAD4(sc, EHCI_HCSPARAMS); 310 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 311 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 312 if (EHCI_HCS_N_CC(sparams) != sc->sc_ncomp) { 313 printf("%s: wrong number of companions (%d != %d)\n", 314 USBDEVNAME(sc->sc_bus.bdev), 315 EHCI_HCS_N_CC(sparams), sc->sc_ncomp); 316 return (USBD_IOERROR); 317 } 318 if (sc->sc_ncomp > 0) { 319 printf("%s: companion controller%s, %d port%s each:", 320 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 321 EHCI_HCS_N_PCC(sparams), 322 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 323 for (i = 0; i < sc->sc_ncomp; i++) 324 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 325 printf("\n"); 326 } 327 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 328 cparams = EREAD4(sc, EHCI_HCCPARAMS); 329 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 330 331 if (EHCI_HCC_64BIT(cparams)) { 332 /* MUST clear segment register if 64 bit capable. */ 333 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 334 } 335 336 sc->sc_bus.usbrev = USBREV_2_0; 337 338 /* Reset the controller */ 339 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 340 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 341 usb_delay_ms(&sc->sc_bus, 1); 342 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 343 for (i = 0; i < 100; i++) { 344 usb_delay_ms(&sc->sc_bus, 1); 345 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 346 if (!hcr) 347 break; 348 } 349 if (hcr) { 350 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 351 return (USBD_IOERROR); 352 } 353 354 /* frame list size at default, read back what we got and use that */ 355 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 356 case 0: sc->sc_flsize = 1024*4; break; 357 case 1: sc->sc_flsize = 512*4; break; 358 case 2: sc->sc_flsize = 256*4; break; 359 case 3: return (USBD_IOERROR); 360 } 361 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize, 362 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 363 if (err) 364 return (err); 365 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 366 367 /* Set up the bus struct. */ 368 sc->sc_bus.methods = &ehci_bus_methods; 369 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 370 371 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 372 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 373 374 sc->sc_eintrs = EHCI_NORMAL_INTRS; 375 376 /* Allocate dummy QH that starts the async list. */ 377 sqh = ehci_alloc_sqh(sc); 378 if (sqh == NULL) { 379 err = USBD_NOMEM; 380 goto bad1; 381 } 382 /* Fill the QH */ 383 sqh->qh.qh_endp = 384 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 385 sqh->qh.qh_link = 386 htole32(sqh->physaddr | EHCI_LINK_QH); 387 sqh->qh.qh_curqtd = EHCI_NULL; 388 sqh->next = NULL; 389 /* Fill the overlay qTD */ 390 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 391 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 392 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 393 sqh->sqtd = NULL; 394 #ifdef EHCI_DEBUG 395 if (ehcidebug) { 396 ehci_dump_sqh(sqh); 397 } 398 #endif 399 400 /* Point to async list */ 401 sc->sc_async_head = sqh; 402 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 403 404 usb_callout_init(sc->sc_tmo_pcd); 405 406 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 407 408 /* Enable interrupts */ 409 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 410 411 /* Turn on controller */ 412 EOWRITE4(sc, EHCI_USBCMD, 413 EHCI_CMD_ITC_8 | /* 8 microframes */ 414 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 415 EHCI_CMD_ASE | 416 /* EHCI_CMD_PSE | */ 417 EHCI_CMD_RS); 418 419 /* Take over port ownership */ 420 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 421 422 for (i = 0; i < 100; i++) { 423 usb_delay_ms(&sc->sc_bus, 1); 424 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 425 if (!hcr) 426 break; 427 } 428 if (hcr) { 429 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 430 return (USBD_IOERROR); 431 } 432 433 return (USBD_NORMAL_COMPLETION); 434 435 #if 0 436 bad2: 437 ehci_free_sqh(sc, sc->sc_async_head); 438 #endif 439 bad1: 440 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 441 return (err); 442 } 443 444 int 445 ehci_intr(void *v) 446 { 447 ehci_softc_t *sc = v; 448 449 if (sc == NULL || sc->sc_dying) 450 return (0); 451 452 /* If we get an interrupt while polling, then just ignore it. */ 453 if (sc->sc_bus.use_polling) { 454 #ifdef DIAGNOSTIC 455 printf("ehci_intr: ignored interrupt while polling\n"); 456 #endif 457 return (0); 458 } 459 460 return (ehci_intr1(sc)); 461 } 462 463 Static int 464 ehci_intr1(ehci_softc_t *sc) 465 { 466 u_int32_t intrs, eintrs; 467 468 DPRINTFN(20,("ehci_intr1: enter\n")); 469 470 /* In case the interrupt occurs before initialization has completed. */ 471 if (sc == NULL) { 472 #ifdef DIAGNOSTIC 473 printf("ehci_intr: sc == NULL\n"); 474 #endif 475 return (0); 476 } 477 478 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 479 480 if (!intrs) 481 return (0); 482 483 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 484 eintrs = intrs & sc->sc_eintrs; 485 DPRINTFN(7, ("ehci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 486 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 487 (u_int)eintrs)); 488 if (!eintrs) 489 return (0); 490 491 sc->sc_bus.intr_context++; 492 sc->sc_bus.no_intrs++; 493 if (eintrs & EHCI_STS_IAA) { 494 DPRINTF(("ehci_intr1: door bell\n")); 495 wakeup(&sc->sc_async_head); 496 eintrs &= ~EHCI_STS_IAA; 497 } 498 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 499 DPRINTF(("ehci_intr1: %s %s\n", 500 eintrs & EHCI_STS_INT ? "INT" : "", 501 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 502 usb_schedsoftintr(&sc->sc_bus); 503 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 504 } 505 if (eintrs & EHCI_STS_HSE) { 506 printf("%s: unrecoverable error, controller halted\n", 507 USBDEVNAME(sc->sc_bus.bdev)); 508 /* XXX what else */ 509 } 510 if (eintrs & EHCI_STS_PCD) { 511 ehci_pcd(sc, sc->sc_intrxfer); 512 /* 513 * Disable PCD interrupt for now, because it will be 514 * on until the port has been reset. 515 */ 516 ehci_pcd_able(sc, 0); 517 /* Do not allow RHSC interrupts > 1 per second */ 518 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc); 519 eintrs &= ~EHCI_STS_PCD; 520 } 521 522 sc->sc_bus.intr_context--; 523 524 if (eintrs != 0) { 525 /* Block unprocessed interrupts. */ 526 sc->sc_eintrs &= ~eintrs; 527 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 528 printf("%s: blocking intrs 0x%x\n", 529 USBDEVNAME(sc->sc_bus.bdev), eintrs); 530 } 531 532 return (1); 533 } 534 535 void 536 ehci_pcd_able(ehci_softc_t *sc, int on) 537 { 538 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on)); 539 if (on) 540 sc->sc_eintrs |= EHCI_STS_PCD; 541 else 542 sc->sc_eintrs &= ~EHCI_STS_PCD; 543 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 544 } 545 546 void 547 ehci_pcd_enable(void *v_sc) 548 { 549 ehci_softc_t *sc = v_sc; 550 551 ehci_pcd_able(sc, 1); 552 } 553 554 void 555 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 556 { 557 usbd_pipe_handle pipe; 558 struct ehci_pipe *epipe; 559 u_char *p; 560 int i, m; 561 562 if (xfer == NULL) { 563 /* Just ignore the change. */ 564 return; 565 } 566 567 pipe = xfer->pipe; 568 epipe = (struct ehci_pipe *)pipe; 569 570 p = KERNADDR(&xfer->dmabuf, 0); 571 m = min(sc->sc_noport, xfer->length * 8 - 1); 572 memset(p, 0, xfer->length); 573 for (i = 1; i <= m; i++) { 574 /* Pick out CHANGE bits from the status reg. */ 575 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 576 p[i/8] |= 1 << (i%8); 577 } 578 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 579 xfer->actlen = xfer->length; 580 xfer->status = USBD_NORMAL_COMPLETION; 581 582 usb_transfer_complete(xfer); 583 } 584 585 void 586 ehci_softintr(void *v) 587 { 588 ehci_softc_t *sc = v; 589 struct ehci_xfer *ex; 590 591 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 592 sc->sc_bus.intr_context)); 593 594 sc->sc_bus.intr_context++; 595 596 /* 597 * The only explanation I can think of for why EHCI is as brain dead 598 * as UHCI interrupt-wise is that Intel was involved in both. 599 * An interrupt just tells us that something is done, we have no 600 * clue what, so we need to scan through all active transfers. :-( 601 */ 602 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = LIST_NEXT(ex, inext)) 603 ehci_check_intr(sc, ex); 604 605 if (sc->sc_softwake) { 606 sc->sc_softwake = 0; 607 wakeup(&sc->sc_softwake); 608 } 609 610 sc->sc_bus.intr_context--; 611 } 612 613 /* Check for an interrupt. */ 614 void 615 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 616 { 617 ehci_soft_qtd_t *sqtd, *lsqtd; 618 u_int32_t status; 619 620 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 621 622 if (ex->sqtdstart == NULL) { 623 printf("ehci_check_intr: sqtdstart=NULL\n"); 624 return; 625 } 626 lsqtd = ex->sqtdend; 627 #ifdef DIAGNOSTIC 628 if (lsqtd == NULL) { 629 printf("ehci_check_intr: sqtd==0\n"); 630 return; 631 } 632 #endif 633 /* 634 * If the last TD is still active we need to check whether there 635 * is a an error somewhere in the middle, or whether there was a 636 * short packet (SPD and not ACTIVE). 637 */ 638 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 639 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 640 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 641 status = le32toh(sqtd->qtd.qtd_status); 642 /* If there's an active QTD the xfer isn't done. */ 643 if (status & EHCI_QTD_ACTIVE) 644 break; 645 /* Any kind of error makes the xfer done. */ 646 if (status & EHCI_QTD_HALTED) 647 goto done; 648 /* We want short packets, and it is short: it's done */ 649 if (EHCI_QTD_SET_BYTES(status) != 0) 650 goto done; 651 } 652 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 653 ex, ex->sqtdstart)); 654 return; 655 } 656 done: 657 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 658 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 659 ehci_idone(ex); 660 } 661 662 void 663 ehci_idone(struct ehci_xfer *ex) 664 { 665 usbd_xfer_handle xfer = &ex->xfer; 666 #ifdef EHCI_DEBUG 667 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 668 #endif 669 ehci_soft_qtd_t *sqtd; 670 u_int32_t status = 0, nstatus; 671 int actlen; 672 673 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 674 #ifdef DIAGNOSTIC 675 { 676 int s = splhigh(); 677 if (ex->isdone) { 678 splx(s); 679 #ifdef EHCI_DEBUG 680 printf("ehci_idone: ex is done!\n "); 681 ehci_dump_exfer(ex); 682 #else 683 printf("ehci_idone: ex=%p is done!\n", ex); 684 #endif 685 return; 686 } 687 ex->isdone = 1; 688 splx(s); 689 } 690 #endif 691 692 if (xfer->status == USBD_CANCELLED || 693 xfer->status == USBD_TIMEOUT) { 694 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 695 return; 696 } 697 698 #ifdef EHCI_DEBUG 699 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 700 if (ehcidebug > 10) 701 ehci_dump_sqtds(ex->sqtdstart); 702 #endif 703 704 /* The transfer is done, compute actual length and status. */ 705 actlen = 0; 706 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 707 nstatus = le32toh(sqtd->qtd.qtd_status); 708 if (nstatus & EHCI_QTD_ACTIVE) 709 break; 710 711 status = nstatus; 712 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 713 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 714 } 715 716 /* If there are left over TDs we need to update the toggle. */ 717 if (sqtd != NULL) { 718 if (!(xfer->rqflags & URQ_REQUEST)) 719 printf("ehci_idone: need toggle update\n"); 720 #if 0 721 epipe->nexttoggle = EHCI_TD_GET_DT(le32toh(std->td.td_token)); 722 #endif 723 } 724 725 status &= EHCI_QTD_STATERRS; 726 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 727 xfer->length, actlen, status)); 728 xfer->actlen = actlen; 729 if (status != 0) { 730 #ifdef EHCI_DEBUG 731 char sbuf[128]; 732 733 bitmask_snprintf((u_int32_t)status, 734 "\20\3MISSEDMICRO\4XACT\5BABBLE\6BABBLE" 735 "\7HALTED", 736 sbuf, sizeof(sbuf)); 737 738 DPRINTFN((status == EHCI_QTD_HALTED)*/*10*/2, 739 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 740 "status 0x%s\n", 741 xfer->pipe->device->address, 742 xfer->pipe->endpoint->edesc->bEndpointAddress, 743 sbuf)); 744 if (ehcidebug > 2) { 745 ehci_dump_sqh(epipe->sqh); 746 ehci_dump_sqtds(ex->sqtdstart); 747 } 748 #endif 749 if (status == EHCI_QTD_HALTED) 750 xfer->status = USBD_STALLED; 751 else 752 xfer->status = USBD_IOERROR; /* more info XXX */ 753 } else { 754 xfer->status = USBD_NORMAL_COMPLETION; 755 } 756 757 usb_transfer_complete(xfer); 758 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 759 } 760 761 /* 762 * Wait here until controller claims to have an interrupt. 763 * Then call ehci_intr and return. Use timeout to avoid waiting 764 * too long. 765 */ 766 void 767 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 768 { 769 int timo = xfer->timeout; 770 int usecs; 771 u_int32_t intrs; 772 773 xfer->status = USBD_IN_PROGRESS; 774 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 775 usb_delay_ms(&sc->sc_bus, 1); 776 if (sc->sc_dying) 777 break; 778 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 779 sc->sc_eintrs; 780 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 781 #ifdef OHCI_DEBUG 782 if (ehcidebug > 15) 783 ehci_dump_regs(sc); 784 #endif 785 if (intrs) { 786 ehci_intr1(sc); 787 if (xfer->status != USBD_IN_PROGRESS) 788 return; 789 } 790 } 791 792 /* Timeout */ 793 DPRINTF(("ehci_waitintr: timeout\n")); 794 xfer->status = USBD_TIMEOUT; 795 usb_transfer_complete(xfer); 796 /* XXX should free TD */ 797 } 798 799 void 800 ehci_poll(struct usbd_bus *bus) 801 { 802 ehci_softc_t *sc = (ehci_softc_t *)bus; 803 #ifdef EHCI_DEBUG 804 static int last; 805 int new; 806 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 807 if (new != last) { 808 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 809 last = new; 810 } 811 #endif 812 813 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 814 ehci_intr1(sc); 815 } 816 817 int 818 ehci_detach(struct ehci_softc *sc, int flags) 819 { 820 int rv = 0; 821 822 if (sc->sc_child != NULL) 823 rv = config_detach(sc->sc_child, flags); 824 825 if (rv != 0) 826 return (rv); 827 828 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc); 829 830 if (sc->sc_powerhook != NULL) 831 powerhook_disestablish(sc->sc_powerhook); 832 if (sc->sc_shutdownhook != NULL) 833 shutdownhook_disestablish(sc->sc_shutdownhook); 834 835 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 836 837 /* XXX free other data structures XXX */ 838 839 return (rv); 840 } 841 842 843 int 844 ehci_activate(device_ptr_t self, enum devact act) 845 { 846 struct ehci_softc *sc = (struct ehci_softc *)self; 847 int rv = 0; 848 849 switch (act) { 850 case DVACT_ACTIVATE: 851 return (EOPNOTSUPP); 852 break; 853 854 case DVACT_DEACTIVATE: 855 if (sc->sc_child != NULL) 856 rv = config_deactivate(sc->sc_child); 857 sc->sc_dying = 1; 858 break; 859 } 860 return (rv); 861 } 862 863 /* 864 * Handle suspend/resume. 865 * 866 * We need to switch to polling mode here, because this routine is 867 * called from an intterupt context. This is all right since we 868 * are almost suspended anyway. 869 */ 870 void 871 ehci_power(int why, void *v) 872 { 873 ehci_softc_t *sc = v; 874 //u_int32_t ctl; 875 int s; 876 877 #ifdef EHCI_DEBUG 878 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 879 ehci_dump_regs(sc); 880 #endif 881 882 s = splhardusb(); 883 switch (why) { 884 case PWR_SUSPEND: 885 case PWR_STANDBY: 886 sc->sc_bus.use_polling++; 887 #if 0 888 OOO 889 ctl = OREAD4(sc, EHCI_CONTROL) & ~EHCI_HCFS_MASK; 890 if (sc->sc_control == 0) { 891 /* 892 * Preserve register values, in case that APM BIOS 893 * does not recover them. 894 */ 895 sc->sc_control = ctl; 896 sc->sc_intre = OREAD4(sc, EHCI_INTERRUPT_ENABLE); 897 } 898 ctl |= EHCI_HCFS_SUSPEND; 899 OWRITE4(sc, EHCI_CONTROL, ctl); 900 #endif 901 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 902 sc->sc_bus.use_polling--; 903 break; 904 case PWR_RESUME: 905 sc->sc_bus.use_polling++; 906 #if 0 907 OOO 908 /* Some broken BIOSes do not recover these values */ 909 OWRITE4(sc, EHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 910 OWRITE4(sc, EHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 911 OWRITE4(sc, EHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 912 if (sc->sc_intre) 913 OWRITE4(sc, EHCI_INTERRUPT_ENABLE, 914 sc->sc_intre & (EHCI_ALL_INTRS | EHCI_MIE)); 915 if (sc->sc_control) 916 ctl = sc->sc_control; 917 else 918 ctl = OREAD4(sc, EHCI_CONTROL); 919 ctl |= EHCI_HCFS_RESUME; 920 OWRITE4(sc, EHCI_CONTROL, ctl); 921 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 922 ctl = (ctl & ~EHCI_HCFS_MASK) | EHCI_HCFS_OPERATIONAL; 923 OWRITE4(sc, EHCI_CONTROL, ctl); 924 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 925 sc->sc_control = sc->sc_intre = 0; 926 #endif 927 sc->sc_bus.use_polling--; 928 break; 929 case PWR_SOFTSUSPEND: 930 case PWR_SOFTSTANDBY: 931 case PWR_SOFTRESUME: 932 break; 933 } 934 splx(s); 935 } 936 937 /* 938 * Shut down the controller when the system is going down. 939 */ 940 void 941 ehci_shutdown(void *v) 942 { 943 ehci_softc_t *sc = v; 944 945 DPRINTF(("ehci_shutdown: stopping the HC\n")); 946 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 947 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 948 } 949 950 usbd_status 951 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 952 { 953 struct ehci_softc *sc = (struct ehci_softc *)bus; 954 usbd_status err; 955 956 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 957 #ifdef EHCI_DEBUG 958 if (err) 959 printf("ehci_allocm: usb_allocmem()=%d\n", err); 960 #endif 961 return (err); 962 } 963 964 void 965 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 966 { 967 struct ehci_softc *sc = (struct ehci_softc *)bus; 968 969 usb_freemem(&sc->sc_bus, dma); 970 } 971 972 usbd_xfer_handle 973 ehci_allocx(struct usbd_bus *bus) 974 { 975 struct ehci_softc *sc = (struct ehci_softc *)bus; 976 usbd_xfer_handle xfer; 977 978 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 979 if (xfer != NULL) { 980 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 981 #ifdef DIAGNOSTIC 982 if (xfer->busy_free != XFER_FREE) { 983 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 984 xfer->busy_free); 985 } 986 #endif 987 } else { 988 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 989 } 990 if (xfer != NULL) { 991 memset(xfer, 0, sizeof (struct ehci_xfer)); 992 #ifdef DIAGNOSTIC 993 EXFER(xfer)->isdone = 1; 994 xfer->busy_free = XFER_BUSY; 995 #endif 996 } 997 return (xfer); 998 } 999 1000 void 1001 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1002 { 1003 struct ehci_softc *sc = (struct ehci_softc *)bus; 1004 1005 #ifdef DIAGNOSTIC 1006 if (xfer->busy_free != XFER_BUSY) { 1007 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1008 xfer->busy_free); 1009 return; 1010 } 1011 xfer->busy_free = XFER_FREE; 1012 if (!EXFER(xfer)->isdone) { 1013 printf("ehci_freex: !isdone\n"); 1014 return; 1015 } 1016 #endif 1017 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1018 } 1019 1020 Static void 1021 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1022 { 1023 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1024 1025 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1026 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1027 #ifdef USB_DEBUG 1028 if (ehcidebug) 1029 usbd_dump_pipe(pipe); 1030 #endif 1031 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE); 1032 } 1033 1034 Static void 1035 ehci_noop(usbd_pipe_handle pipe) 1036 { 1037 } 1038 1039 #ifdef EHCI_DEBUG 1040 void 1041 ehci_dump_regs(ehci_softc_t *sc) 1042 { 1043 int i; 1044 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1045 EOREAD4(sc, EHCI_USBCMD), 1046 EOREAD4(sc, EHCI_USBSTS), 1047 EOREAD4(sc, EHCI_USBINTR)); 1048 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1049 EOREAD4(sc, EHCI_FRINDEX), 1050 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1051 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1052 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1053 for (i = 1; i <= sc->sc_noport; i++) 1054 printf("port %d status=0x%08x\n", i, 1055 EOREAD4(sc, EHCI_PORTSC(i))); 1056 } 1057 1058 /* 1059 * Unused function - this is meant to be called from a kernel 1060 * debugger. 1061 */ 1062 void 1063 ehci_dump() 1064 { 1065 ehci_dump_regs(theehci); 1066 } 1067 1068 void 1069 ehci_dump_link(ehci_link_t link, int type) 1070 { 1071 link = le32toh(link); 1072 printf("0x%08x", link); 1073 if (link & EHCI_LINK_TERMINATE) 1074 printf("<T>"); 1075 else { 1076 printf("<"); 1077 if (type) { 1078 switch (EHCI_LINK_TYPE(link)) { 1079 case EHCI_LINK_ITD: printf("ITD"); break; 1080 case EHCI_LINK_QH: printf("QH"); break; 1081 case EHCI_LINK_SITD: printf("SITD"); break; 1082 case EHCI_LINK_FSTN: printf("FSTN"); break; 1083 } 1084 } 1085 printf(">"); 1086 } 1087 } 1088 1089 void 1090 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1091 { 1092 int i; 1093 u_int32_t stop; 1094 1095 stop = 0; 1096 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1097 ehci_dump_sqtd(sqtd); 1098 stop = sqtd->qtd.qtd_next & EHCI_LINK_TERMINATE; 1099 } 1100 if (sqtd) 1101 printf("dump aborted, too many TDs\n"); 1102 } 1103 1104 void 1105 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1106 { 1107 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1108 ehci_dump_qtd(&sqtd->qtd); 1109 } 1110 1111 void 1112 ehci_dump_qtd(ehci_qtd_t *qtd) 1113 { 1114 u_int32_t s; 1115 char sbuf[128]; 1116 1117 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1118 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1119 printf("\n"); 1120 s = le32toh(qtd->qtd_status); 1121 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1122 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1123 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1124 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1125 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1126 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1127 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1128 EHCI_QTD_GET_PID(s), sbuf); 1129 for (s = 0; s < 5; s++) 1130 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1131 } 1132 1133 void 1134 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1135 { 1136 ehci_qh_t *qh = &sqh->qh; 1137 u_int32_t endp, endphub; 1138 1139 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1140 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1141 endp = le32toh(qh->qh_endp); 1142 printf(" endp=0x%08x\n", endp); 1143 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1144 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1145 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1146 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1147 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1148 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1149 EHCI_QH_GET_NRL(endp)); 1150 endphub = le32toh(qh->qh_endphub); 1151 printf(" endphub=0x%08x\n", endphub); 1152 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1153 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1154 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1155 EHCI_QH_GET_MULT(endphub)); 1156 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1157 printf("Overlay qTD:\n"); 1158 ehci_dump_qtd(&qh->qh_qtd); 1159 } 1160 1161 #ifdef DIAGNOSTIC 1162 Static void 1163 ehci_dump_exfer(struct ehci_xfer *ex) 1164 { 1165 printf("ehci_dump_exfer: ex=%p\n", ex); 1166 } 1167 #endif 1168 #endif 1169 1170 usbd_status 1171 ehci_open(usbd_pipe_handle pipe) 1172 { 1173 usbd_device_handle dev = pipe->device; 1174 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1175 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1176 u_int8_t addr = dev->address; 1177 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1178 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1179 ehci_soft_qh_t *sqh; 1180 usbd_status err; 1181 int s; 1182 int speed, naks; 1183 1184 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1185 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1186 1187 if (sc->sc_dying) 1188 return (USBD_IOERROR); 1189 1190 if (addr == sc->sc_addr) { 1191 switch (ed->bEndpointAddress) { 1192 case USB_CONTROL_ENDPOINT: 1193 pipe->methods = &ehci_root_ctrl_methods; 1194 break; 1195 case UE_DIR_IN | EHCI_INTR_ENDPT: 1196 pipe->methods = &ehci_root_intr_methods; 1197 break; 1198 default: 1199 return (USBD_INVAL); 1200 } 1201 return (USBD_NORMAL_COMPLETION); 1202 } 1203 1204 /* XXX All this stuff is only valid for async. */ 1205 switch (dev->speed) { 1206 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1207 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1208 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1209 default: panic("ehci_open: bad device speed %d", dev->speed); 1210 } 1211 naks = 8; /* XXX */ 1212 sqh = ehci_alloc_sqh(sc); 1213 if (sqh == NULL) 1214 goto bad0; 1215 /* qh_link filled when the QH is added */ 1216 sqh->qh.qh_endp = htole32( 1217 EHCI_QH_SET_ADDR(addr) | 1218 EHCI_QH_SET_ENDPT(ed->bEndpointAddress) | 1219 EHCI_QH_SET_EPS(speed) | /* XXX */ 1220 /* XXX EHCI_QH_DTC ? */ 1221 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1222 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1223 EHCI_QH_CTL : 0) | 1224 EHCI_QH_SET_NRL(naks) 1225 ); 1226 sqh->qh.qh_endphub = htole32( 1227 EHCI_QH_SET_MULT(1) 1228 /* XXX TT stuff */ 1229 /* XXX interrupt mask */ 1230 ); 1231 sqh->qh.qh_curqtd = EHCI_NULL; 1232 /* Fill the overlay qTD */ 1233 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1234 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1235 sqh->qh.qh_qtd.qtd_status = htole32(0); 1236 1237 epipe->sqh = sqh; 1238 1239 switch (xfertype) { 1240 case UE_CONTROL: 1241 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1242 0, &epipe->u.ctl.reqdma); 1243 #ifdef EHCI_DEBUG 1244 if (err) 1245 printf("ehci_open: usb_allocmem()=%d\n", err); 1246 #endif 1247 if (err) 1248 goto bad1; 1249 pipe->methods = &ehci_device_ctrl_methods; 1250 s = splusb(); 1251 ehci_add_qh(sqh, sc->sc_async_head); 1252 splx(s); 1253 break; 1254 case UE_BULK: 1255 pipe->methods = &ehci_device_bulk_methods; 1256 s = splusb(); 1257 ehci_add_qh(sqh, sc->sc_async_head); 1258 splx(s); 1259 break; 1260 case UE_INTERRUPT: 1261 pipe->methods = &ehci_device_intr_methods; 1262 return (USBD_INVAL); 1263 case UE_ISOCHRONOUS: 1264 pipe->methods = &ehci_device_isoc_methods; 1265 return (USBD_INVAL); 1266 default: 1267 return (USBD_INVAL); 1268 } 1269 return (USBD_NORMAL_COMPLETION); 1270 1271 bad1: 1272 ehci_free_sqh(sc, sqh); 1273 bad0: 1274 return (USBD_NOMEM); 1275 } 1276 1277 /* 1278 * Add an ED to the schedule. Called at splusb(). 1279 */ 1280 void 1281 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1282 { 1283 SPLUSBCHECK; 1284 1285 sqh->next = head->next; 1286 sqh->qh.qh_link = head->qh.qh_link; 1287 head->next = sqh; 1288 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1289 1290 #ifdef EHCI_DEBUG 1291 if (ehcidebug > 5) { 1292 printf("ehci_add_qh:\n"); 1293 ehci_dump_sqh(sqh); 1294 } 1295 #endif 1296 } 1297 1298 /* 1299 * Remove an ED from the schedule. Called at splusb(). 1300 */ 1301 void 1302 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1303 { 1304 ehci_soft_qh_t *p; 1305 1306 SPLUSBCHECK; 1307 /* XXX */ 1308 for (p = head; p == NULL && p->next != sqh; p = p->next) 1309 ; 1310 if (p == NULL) 1311 panic("ehci_rem_qh: ED not found"); 1312 p->next = sqh->next; 1313 p->qh.qh_link = sqh->qh.qh_link; 1314 1315 ehci_sync_hc(sc); 1316 } 1317 1318 void 1319 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1320 { 1321 /* Halt while we are messing. */ 1322 sqh->qh.qh_qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 1323 sqh->qh.qh_curqtd = 0; 1324 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1325 sqh->sqtd = sqtd; 1326 /* Keep toggle, clear the rest, including length. */ 1327 sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_TOGGLE); 1328 } 1329 1330 /* 1331 * Ensure that the HC has released all references to the QH. We do this 1332 * by asking for a Async Advance Doorbell interrupt and then we wait for 1333 * the interrupt. 1334 * To make this easier we first obtain exclusive use of the doorbell. 1335 */ 1336 void 1337 ehci_sync_hc(ehci_softc_t *sc) 1338 { 1339 int s, error; 1340 1341 if (sc->sc_dying) { 1342 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1343 return; 1344 } 1345 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1346 lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */ 1347 s = splhardusb(); 1348 /* ask for doorbell */ 1349 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1350 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1351 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1352 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1353 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1354 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1355 splx(s); 1356 lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */ 1357 #ifdef DIAGNOSTIC 1358 if (error) 1359 printf("ehci_sync_hc: tsleep() = %d\n", error); 1360 #endif 1361 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1362 } 1363 1364 /***********/ 1365 1366 /* 1367 * Data structures and routines to emulate the root hub. 1368 */ 1369 Static usb_device_descriptor_t ehci_devd = { 1370 USB_DEVICE_DESCRIPTOR_SIZE, 1371 UDESC_DEVICE, /* type */ 1372 {0x00, 0x02}, /* USB version */ 1373 UDCLASS_HUB, /* class */ 1374 UDSUBCLASS_HUB, /* subclass */ 1375 UDPROTO_HSHUBSTT, /* protocol */ 1376 64, /* max packet */ 1377 {0},{0},{0x00,0x01}, /* device id */ 1378 1,2,0, /* string indicies */ 1379 1 /* # of configurations */ 1380 }; 1381 1382 Static usb_device_qualifier_t ehci_odevd = { 1383 USB_DEVICE_DESCRIPTOR_SIZE, 1384 UDESC_DEVICE_QUALIFIER, /* type */ 1385 {0x00, 0x02}, /* USB version */ 1386 UDCLASS_HUB, /* class */ 1387 UDSUBCLASS_HUB, /* subclass */ 1388 UDPROTO_FSHUB, /* protocol */ 1389 64, /* max packet */ 1390 1, /* # of configurations */ 1391 0 1392 }; 1393 1394 Static usb_config_descriptor_t ehci_confd = { 1395 USB_CONFIG_DESCRIPTOR_SIZE, 1396 UDESC_CONFIG, 1397 {USB_CONFIG_DESCRIPTOR_SIZE + 1398 USB_INTERFACE_DESCRIPTOR_SIZE + 1399 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1400 1, 1401 1, 1402 0, 1403 UC_SELF_POWERED, 1404 0 /* max power */ 1405 }; 1406 1407 Static usb_interface_descriptor_t ehci_ifcd = { 1408 USB_INTERFACE_DESCRIPTOR_SIZE, 1409 UDESC_INTERFACE, 1410 0, 1411 0, 1412 1, 1413 UICLASS_HUB, 1414 UISUBCLASS_HUB, 1415 UIPROTO_HSHUBSTT, 1416 0 1417 }; 1418 1419 Static usb_endpoint_descriptor_t ehci_endpd = { 1420 USB_ENDPOINT_DESCRIPTOR_SIZE, 1421 UDESC_ENDPOINT, 1422 UE_DIR_IN | EHCI_INTR_ENDPT, 1423 UE_INTERRUPT, 1424 {8, 0}, /* max packet */ 1425 255 1426 }; 1427 1428 Static usb_hub_descriptor_t ehci_hubd = { 1429 USB_HUB_DESCRIPTOR_SIZE, 1430 UDESC_HUB, 1431 0, 1432 {0,0}, 1433 0, 1434 0, 1435 {0}, 1436 }; 1437 1438 Static int 1439 ehci_str(p, l, s) 1440 usb_string_descriptor_t *p; 1441 int l; 1442 char *s; 1443 { 1444 int i; 1445 1446 if (l == 0) 1447 return (0); 1448 p->bLength = 2 * strlen(s) + 2; 1449 if (l == 1) 1450 return (1); 1451 p->bDescriptorType = UDESC_STRING; 1452 l -= 2; 1453 for (i = 0; s[i] && l > 1; i++, l -= 2) 1454 USETW2(p->bString[i], 0, s[i]); 1455 return (2*i+2); 1456 } 1457 1458 /* 1459 * Simulate a hardware hub by handling all the necessary requests. 1460 */ 1461 Static usbd_status 1462 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1463 { 1464 usbd_status err; 1465 1466 /* Insert last in queue. */ 1467 err = usb_insert_transfer(xfer); 1468 if (err) 1469 return (err); 1470 1471 /* Pipe isn't running, start first */ 1472 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1473 } 1474 1475 Static usbd_status 1476 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1477 { 1478 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1479 usb_device_request_t *req; 1480 void *buf = NULL; 1481 int port, i; 1482 int s, len, value, index, l, totlen = 0; 1483 usb_port_status_t ps; 1484 usb_hub_descriptor_t hubd; 1485 usbd_status err; 1486 u_int32_t v; 1487 1488 if (sc->sc_dying) 1489 return (USBD_IOERROR); 1490 1491 #ifdef DIAGNOSTIC 1492 if (!(xfer->rqflags & URQ_REQUEST)) 1493 /* XXX panic */ 1494 return (USBD_INVAL); 1495 #endif 1496 req = &xfer->request; 1497 1498 DPRINTFN(4,("ehci_root_ctrl_control type=0x%02x request=%02x\n", 1499 req->bmRequestType, req->bRequest)); 1500 1501 len = UGETW(req->wLength); 1502 value = UGETW(req->wValue); 1503 index = UGETW(req->wIndex); 1504 1505 if (len != 0) 1506 buf = KERNADDR(&xfer->dmabuf, 0); 1507 1508 #define C(x,y) ((x) | ((y) << 8)) 1509 switch(C(req->bRequest, req->bmRequestType)) { 1510 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1511 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1512 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1513 /* 1514 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1515 * for the integrated root hub. 1516 */ 1517 break; 1518 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1519 if (len > 0) { 1520 *(u_int8_t *)buf = sc->sc_conf; 1521 totlen = 1; 1522 } 1523 break; 1524 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1525 DPRINTFN(8,("ehci_root_ctrl_control wValue=0x%04x\n", value)); 1526 switch(value >> 8) { 1527 case UDESC_DEVICE: 1528 if ((value & 0xff) != 0) { 1529 err = USBD_IOERROR; 1530 goto ret; 1531 } 1532 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1533 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1534 memcpy(buf, &ehci_devd, l); 1535 break; 1536 /* 1537 * We can't really operate at another speed, but the spec says 1538 * we need this descriptor. 1539 */ 1540 case UDESC_DEVICE_QUALIFIER: 1541 if ((value & 0xff) != 0) { 1542 err = USBD_IOERROR; 1543 goto ret; 1544 } 1545 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1546 memcpy(buf, &ehci_odevd, l); 1547 break; 1548 /* 1549 * We can't really operate at another speed, but the spec says 1550 * we need this descriptor. 1551 */ 1552 case UDESC_OTHER_SPEED_CONFIGURATION: 1553 case UDESC_CONFIG: 1554 if ((value & 0xff) != 0) { 1555 err = USBD_IOERROR; 1556 goto ret; 1557 } 1558 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1559 memcpy(buf, &ehci_confd, l); 1560 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1561 value >> 8; 1562 buf = (char *)buf + l; 1563 len -= l; 1564 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1565 totlen += l; 1566 memcpy(buf, &ehci_ifcd, l); 1567 buf = (char *)buf + l; 1568 len -= l; 1569 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1570 totlen += l; 1571 memcpy(buf, &ehci_endpd, l); 1572 break; 1573 case UDESC_STRING: 1574 if (len == 0) 1575 break; 1576 *(u_int8_t *)buf = 0; 1577 totlen = 1; 1578 switch (value & 0xff) { 1579 case 1: /* Vendor */ 1580 totlen = ehci_str(buf, len, sc->sc_vendor); 1581 break; 1582 case 2: /* Product */ 1583 totlen = ehci_str(buf, len, "EHCI root hub"); 1584 break; 1585 } 1586 break; 1587 default: 1588 err = USBD_IOERROR; 1589 goto ret; 1590 } 1591 break; 1592 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1593 if (len > 0) { 1594 *(u_int8_t *)buf = 0; 1595 totlen = 1; 1596 } 1597 break; 1598 case C(UR_GET_STATUS, UT_READ_DEVICE): 1599 if (len > 1) { 1600 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1601 totlen = 2; 1602 } 1603 break; 1604 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1605 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1606 if (len > 1) { 1607 USETW(((usb_status_t *)buf)->wStatus, 0); 1608 totlen = 2; 1609 } 1610 break; 1611 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1612 if (value >= USB_MAX_DEVICES) { 1613 err = USBD_IOERROR; 1614 goto ret; 1615 } 1616 sc->sc_addr = value; 1617 break; 1618 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1619 if (value != 0 && value != 1) { 1620 err = USBD_IOERROR; 1621 goto ret; 1622 } 1623 sc->sc_conf = value; 1624 break; 1625 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1626 break; 1627 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1628 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1629 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1630 err = USBD_IOERROR; 1631 goto ret; 1632 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1633 break; 1634 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1635 break; 1636 /* Hub requests */ 1637 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1638 break; 1639 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1640 DPRINTFN(8, ("ehci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1641 "port=%d feature=%d\n", 1642 index, value)); 1643 if (index < 1 || index > sc->sc_noport) { 1644 err = USBD_IOERROR; 1645 goto ret; 1646 } 1647 port = EHCI_PORTSC(index); 1648 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1649 switch(value) { 1650 case UHF_PORT_ENABLE: 1651 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1652 break; 1653 case UHF_PORT_SUSPEND: 1654 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1655 break; 1656 case UHF_PORT_POWER: 1657 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1658 break; 1659 case UHF_PORT_TEST: 1660 DPRINTFN(2,("ehci_root_ctrl_transfer: clear port test " 1661 "%d\n", index)); 1662 break; 1663 case UHF_PORT_INDICATOR: 1664 DPRINTFN(2,("ehci_root_ctrl_transfer: clear port ind " 1665 "%d\n", index)); 1666 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1667 break; 1668 case UHF_C_PORT_CONNECTION: 1669 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1670 break; 1671 case UHF_C_PORT_ENABLE: 1672 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1673 break; 1674 case UHF_C_PORT_SUSPEND: 1675 /* how? */ 1676 break; 1677 case UHF_C_PORT_OVER_CURRENT: 1678 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1679 break; 1680 case UHF_C_PORT_RESET: 1681 sc->sc_isreset = 0; 1682 break; 1683 default: 1684 err = USBD_IOERROR; 1685 goto ret; 1686 } 1687 #if 0 1688 switch(value) { 1689 case UHF_C_PORT_CONNECTION: 1690 case UHF_C_PORT_ENABLE: 1691 case UHF_C_PORT_SUSPEND: 1692 case UHF_C_PORT_OVER_CURRENT: 1693 case UHF_C_PORT_RESET: 1694 /* Enable RHSC interrupt if condition is cleared. */ 1695 if ((OREAD4(sc, port) >> 16) == 0) 1696 ehci_pcd_able(sc, 1); 1697 break; 1698 default: 1699 break; 1700 } 1701 #endif 1702 break; 1703 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1704 if (value != 0) { 1705 err = USBD_IOERROR; 1706 goto ret; 1707 } 1708 hubd = ehci_hubd; 1709 hubd.bNbrPorts = sc->sc_noport; 1710 v = EOREAD4(sc, EHCI_HCSPARAMS); 1711 USETW(hubd.wHubCharacteristics, 1712 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 1713 EHCI_HCS_P_INCICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 1714 ? UHD_PORT_IND : 0); 1715 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1716 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1717 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 1718 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1719 l = min(len, hubd.bDescLength); 1720 totlen = l; 1721 memcpy(buf, &hubd, l); 1722 break; 1723 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1724 if (len != 4) { 1725 err = USBD_IOERROR; 1726 goto ret; 1727 } 1728 memset(buf, 0, len); /* ? XXX */ 1729 totlen = len; 1730 break; 1731 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1732 DPRINTFN(8,("ehci_root_ctrl_transfer: get port status i=%d\n", 1733 index)); 1734 if (index < 1 || index > sc->sc_noport) { 1735 err = USBD_IOERROR; 1736 goto ret; 1737 } 1738 if (len != 4) { 1739 err = USBD_IOERROR; 1740 goto ret; 1741 } 1742 v = EOREAD4(sc, EHCI_PORTSC(index)); 1743 DPRINTFN(8,("ehci_root_ctrl_transfer: port status=0x%04x\n", 1744 v)); 1745 i = UPS_HIGH_SPEED; 1746 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 1747 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 1748 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 1749 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 1750 if (v & EHCI_PS_PR) i |= UPS_RESET; 1751 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 1752 USETW(ps.wPortStatus, i); 1753 i = 0; 1754 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 1755 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 1756 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 1757 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 1758 USETW(ps.wPortChange, i); 1759 l = min(len, sizeof ps); 1760 memcpy(buf, &ps, l); 1761 totlen = l; 1762 break; 1763 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1764 err = USBD_IOERROR; 1765 goto ret; 1766 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1767 break; 1768 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1769 if (index < 1 || index > sc->sc_noport) { 1770 err = USBD_IOERROR; 1771 goto ret; 1772 } 1773 port = EHCI_PORTSC(index); 1774 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1775 switch(value) { 1776 case UHF_PORT_ENABLE: 1777 EOWRITE4(sc, port, v | EHCI_PS_PE); 1778 break; 1779 case UHF_PORT_SUSPEND: 1780 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 1781 break; 1782 case UHF_PORT_RESET: 1783 DPRINTFN(5,("ehci_root_ctrl_transfer: reset port %d\n", 1784 index)); 1785 if (EHCI_PS_IS_LOWSPEED(v)) { 1786 /* Low speed device, give up ownership. */ 1787 ehci_disown(sc, index, 1); 1788 break; 1789 } 1790 /* Start reset sequence. */ 1791 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 1792 EOWRITE4(sc, port, v | EHCI_PS_PR); 1793 /* Wait for reset to complete. */ 1794 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 1795 if (sc->sc_dying) { 1796 err = USBD_IOERROR; 1797 goto ret; 1798 } 1799 /* Terminate reset sequence. */ 1800 EOWRITE4(sc, port, v); 1801 /* Wait for HC to complete reset. */ 1802 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 1803 if (sc->sc_dying) { 1804 err = USBD_IOERROR; 1805 goto ret; 1806 } 1807 v = EOREAD4(sc, port); 1808 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 1809 if (v & EHCI_PS_PR) { 1810 printf("%s: port reset timeout\n", 1811 USBDEVNAME(sc->sc_bus.bdev)); 1812 return (USBD_TIMEOUT); 1813 } 1814 if (!(v & EHCI_PS_PE)) { 1815 /* Not a high speed device, give up ownership.*/ 1816 ehci_disown(sc, index, 0); 1817 break; 1818 } 1819 sc->sc_isreset = 1; 1820 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 1821 index, v)); 1822 break; 1823 case UHF_PORT_POWER: 1824 DPRINTFN(2,("ehci_root_ctrl_transfer: set port power " 1825 "%d\n", index)); 1826 EOWRITE4(sc, port, v | EHCI_PS_PP); 1827 break; 1828 case UHF_PORT_TEST: 1829 DPRINTFN(2,("ehci_root_ctrl_transfer: set port test " 1830 "%d\n", index)); 1831 break; 1832 case UHF_PORT_INDICATOR: 1833 DPRINTFN(2,("ehci_root_ctrl_transfer: set port ind " 1834 "%d\n", index)); 1835 EOWRITE4(sc, port, v | EHCI_PS_PIC); 1836 break; 1837 default: 1838 err = USBD_IOERROR; 1839 goto ret; 1840 } 1841 break; 1842 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 1843 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 1844 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 1845 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 1846 break; 1847 default: 1848 err = USBD_IOERROR; 1849 goto ret; 1850 } 1851 xfer->actlen = totlen; 1852 err = USBD_NORMAL_COMPLETION; 1853 ret: 1854 xfer->status = err; 1855 s = splusb(); 1856 usb_transfer_complete(xfer); 1857 splx(s); 1858 return (USBD_IN_PROGRESS); 1859 } 1860 1861 void 1862 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 1863 { 1864 int port; 1865 u_int32_t v; 1866 1867 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 1868 #ifdef DIAGNOSTIC 1869 if (sc->sc_npcomp != 0) { 1870 int i = (index-1) / sc->sc_npcomp; 1871 if (i >= sc->sc_ncomp) 1872 printf("%s: strange port\n", 1873 USBDEVNAME(sc->sc_bus.bdev)); 1874 else 1875 printf("%s: handing over %s speed device on " 1876 "port %d to %s\n", 1877 USBDEVNAME(sc->sc_bus.bdev), 1878 lowspeed ? "low" : "full", 1879 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 1880 } else { 1881 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 1882 } 1883 #endif 1884 port = EHCI_PORTSC(index); 1885 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1886 EOWRITE4(sc, port, v | EHCI_PS_PO); 1887 } 1888 1889 /* Abort a root control request. */ 1890 Static void 1891 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 1892 { 1893 /* Nothing to do, all transfers are synchronous. */ 1894 } 1895 1896 /* Close the root pipe. */ 1897 Static void 1898 ehci_root_ctrl_close(usbd_pipe_handle pipe) 1899 { 1900 DPRINTF(("ehci_root_ctrl_close\n")); 1901 /* Nothing to do. */ 1902 } 1903 1904 void 1905 ehci_root_intr_done(usbd_xfer_handle xfer) 1906 { 1907 xfer->hcpriv = NULL; 1908 } 1909 1910 Static usbd_status 1911 ehci_root_intr_transfer(usbd_xfer_handle xfer) 1912 { 1913 usbd_status err; 1914 1915 /* Insert last in queue. */ 1916 err = usb_insert_transfer(xfer); 1917 if (err) 1918 return (err); 1919 1920 /* Pipe isn't running, start first */ 1921 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1922 } 1923 1924 Static usbd_status 1925 ehci_root_intr_start(usbd_xfer_handle xfer) 1926 { 1927 usbd_pipe_handle pipe = xfer->pipe; 1928 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1929 1930 if (sc->sc_dying) 1931 return (USBD_IOERROR); 1932 1933 sc->sc_intrxfer = xfer; 1934 1935 return (USBD_IN_PROGRESS); 1936 } 1937 1938 /* Abort a root interrupt request. */ 1939 Static void 1940 ehci_root_intr_abort(usbd_xfer_handle xfer) 1941 { 1942 int s; 1943 1944 if (xfer->pipe->intrxfer == xfer) { 1945 DPRINTF(("ehci_root_intr_abort: remove\n")); 1946 xfer->pipe->intrxfer = NULL; 1947 } 1948 xfer->status = USBD_CANCELLED; 1949 s = splusb(); 1950 usb_transfer_complete(xfer); 1951 splx(s); 1952 } 1953 1954 /* Close the root pipe. */ 1955 Static void 1956 ehci_root_intr_close(usbd_pipe_handle pipe) 1957 { 1958 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1959 1960 DPRINTF(("ehci_root_intr_close\n")); 1961 1962 sc->sc_intrxfer = NULL; 1963 } 1964 1965 void 1966 ehci_root_ctrl_done(usbd_xfer_handle xfer) 1967 { 1968 xfer->hcpriv = NULL; 1969 } 1970 1971 /************************/ 1972 1973 ehci_soft_qh_t * 1974 ehci_alloc_sqh(ehci_softc_t *sc) 1975 { 1976 ehci_soft_qh_t *sqh; 1977 usbd_status err; 1978 int i, offs; 1979 usb_dma_t dma; 1980 1981 if (sc->sc_freeqhs == NULL) { 1982 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 1983 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 1984 EHCI_PAGE_SIZE, &dma); 1985 #ifdef EHCI_DEBUG 1986 if (err) 1987 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 1988 #endif 1989 if (err) 1990 return (NULL); 1991 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 1992 offs = i * EHCI_SQH_SIZE; 1993 sqh = KERNADDR(&dma, offs); 1994 sqh->physaddr = DMAADDR(&dma, offs); 1995 sqh->next = sc->sc_freeqhs; 1996 sc->sc_freeqhs = sqh; 1997 } 1998 } 1999 sqh = sc->sc_freeqhs; 2000 sc->sc_freeqhs = sqh->next; 2001 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2002 sqh->next = NULL; 2003 return (sqh); 2004 } 2005 2006 void 2007 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2008 { 2009 sqh->next = sc->sc_freeqhs; 2010 sc->sc_freeqhs = sqh; 2011 } 2012 2013 ehci_soft_qtd_t * 2014 ehci_alloc_sqtd(ehci_softc_t *sc) 2015 { 2016 ehci_soft_qtd_t *sqtd; 2017 usbd_status err; 2018 int i, offs; 2019 usb_dma_t dma; 2020 int s; 2021 2022 if (sc->sc_freeqtds == NULL) { 2023 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2024 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2025 EHCI_PAGE_SIZE, &dma); 2026 #ifdef EHCI_DEBUG 2027 if (err) 2028 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2029 #endif 2030 if (err) 2031 return (NULL); 2032 s = splusb(); 2033 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2034 offs = i * EHCI_SQTD_SIZE; 2035 sqtd = KERNADDR(&dma, offs); 2036 sqtd->physaddr = DMAADDR(&dma, offs); 2037 sqtd->nextqtd = sc->sc_freeqtds; 2038 sc->sc_freeqtds = sqtd; 2039 } 2040 splx(s); 2041 } 2042 2043 s = splusb(); 2044 sqtd = sc->sc_freeqtds; 2045 sc->sc_freeqtds = sqtd->nextqtd; 2046 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2047 sqtd->nextqtd = NULL; 2048 sqtd->xfer = NULL; 2049 splx(s); 2050 2051 return (sqtd); 2052 } 2053 2054 void 2055 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2056 { 2057 int s; 2058 2059 s = splusb(); 2060 sqtd->nextqtd = sc->sc_freeqtds; 2061 sc->sc_freeqtds = sqtd; 2062 splx(s); 2063 } 2064 2065 usbd_status 2066 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2067 int alen, int rd, usbd_xfer_handle xfer, 2068 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2069 { 2070 ehci_soft_qtd_t *next, *cur; 2071 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2072 u_int32_t qtdstatus; 2073 int len, curlen; 2074 int i; 2075 usb_dma_t *dma = &xfer->dmabuf; 2076 2077 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2078 2079 len = alen; 2080 dataphys = DMAADDR(dma, 0); 2081 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2082 qtdstatus = htole32( 2083 EHCI_QTD_ACTIVE | 2084 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2085 EHCI_QTD_SET_CERR(3) 2086 /* IOC set below */ 2087 /* BYTES set below */ 2088 /* XXX Data toggle */ 2089 ); 2090 2091 cur = ehci_alloc_sqtd(sc); 2092 *sp = cur; 2093 if (cur == NULL) 2094 goto nomem; 2095 for (;;) { 2096 dataphyspage = EHCI_PAGE(dataphys); 2097 /* The EHCI hardware can handle at most 5 pages. */ 2098 if (dataphyslastpage - dataphyspage < 2099 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2100 /* we can handle it in this QTD */ 2101 curlen = len; 2102 } else { 2103 /* must use multiple TDs, fill as much as possible. */ 2104 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2105 EHCI_PAGE_OFFSET(dataphys); 2106 #ifdef DIAGNOSTIC 2107 if (curlen > len) { 2108 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2109 "len=0x%x offs=0x%x\n", curlen, len, 2110 EHCI_PAGE_OFFSET(dataphys)); 2111 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2112 dataphyslastpage, dataphyspage, 2113 dataphys); 2114 curlen = len; 2115 } 2116 #endif 2117 2118 /* XXX true for EHCI? */ 2119 /* the length must be a multiple of the max size */ 2120 curlen -= curlen % UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2121 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2122 "curlen=%d\n", curlen)); 2123 #ifdef DIAGNOSTIC 2124 if (curlen == 0) 2125 panic("ehci_alloc_std: curlen == 0"); 2126 #endif 2127 } 2128 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2129 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2130 dataphys, dataphyslastpage, 2131 len, curlen)); 2132 len -= curlen; 2133 2134 if (len != 0) { 2135 next = ehci_alloc_sqtd(sc); 2136 if (next == NULL) 2137 goto nomem; 2138 nextphys = next->physaddr; 2139 } else { 2140 next = NULL; 2141 nextphys = EHCI_NULL; 2142 } 2143 2144 for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) { 2145 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2146 if (i != 0) /* use offset only in first buffer */ 2147 a = EHCI_PAGE(a); 2148 cur->qtd.qtd_buffer[i] = htole32(a); 2149 #ifdef DIAGNOSTIC 2150 if (i >= EHCI_QTD_NBUFFERS) { 2151 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2152 goto nomem; 2153 } 2154 #endif 2155 } 2156 cur->nextqtd = next; 2157 cur->qtd.qtd_next = cur->qtd.qtd_altnext = htole32(nextphys); 2158 cur->qtd.qtd_status = 2159 qtdstatus | htole32(EHCI_QTD_SET_BYTES(curlen)); 2160 cur->xfer = xfer; 2161 cur->len = curlen; 2162 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2163 dataphys, dataphys + curlen)); 2164 if (len == 0) 2165 break; 2166 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2167 dataphys += curlen; 2168 cur = next; 2169 } 2170 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2171 *ep = cur; 2172 2173 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2174 *sp, *ep)); 2175 2176 return (USBD_NORMAL_COMPLETION); 2177 2178 nomem: 2179 /* XXX free chain */ 2180 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2181 return (USBD_NOMEM); 2182 } 2183 2184 Static void 2185 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2186 ehci_soft_qtd_t *sqtdend) 2187 { 2188 ehci_soft_qtd_t *p; 2189 int i; 2190 2191 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2192 sqtd, sqtdend)); 2193 2194 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2195 p = sqtd->nextqtd; 2196 ehci_free_sqtd(sc, sqtd); 2197 } 2198 } 2199 2200 /****************/ 2201 2202 /* 2203 * Close a reqular pipe. 2204 * Assumes that there are no pending transactions. 2205 */ 2206 void 2207 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2208 { 2209 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2210 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2211 ehci_soft_qh_t *sqh = epipe->sqh; 2212 int s; 2213 2214 s = splusb(); 2215 ehci_rem_qh(sc, sqh, head); 2216 splx(s); 2217 ehci_free_sqh(sc, epipe->sqh); 2218 } 2219 2220 /* 2221 * Abort a device request. 2222 * If this routine is called at splusb() it guarantees that the request 2223 * will be removed from the hardware scheduling and that the callback 2224 * for it will be called with USBD_CANCELLED status. 2225 * It's impossible to guarantee that the requested transfer will not 2226 * have happened since the hardware runs concurrently. 2227 * If the transaction has already happened we rely on the ordinary 2228 * interrupt processing to process it. 2229 * XXX This is most probably wrong. 2230 */ 2231 void 2232 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2233 { 2234 #define exfer EXFER(xfer) 2235 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2236 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2237 ehci_soft_qh_t *sqh = epipe->sqh; 2238 ehci_soft_qtd_t *sqtd; 2239 ehci_physaddr_t cur; 2240 u_int32_t qhstatus; 2241 int s; 2242 int hit; 2243 2244 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2245 2246 if (sc->sc_dying) { 2247 /* If we're dying, just do the software part. */ 2248 s = splusb(); 2249 xfer->status = status; /* make software ignore it */ 2250 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2251 usb_transfer_complete(xfer); 2252 splx(s); 2253 return; 2254 } 2255 2256 if (xfer->device->bus->intr_context || !curproc) 2257 panic("ehci_abort_xfer: not in process context"); 2258 2259 /* 2260 * Step 1: Make interrupt routine and hardware ignore xfer. 2261 */ 2262 s = splusb(); 2263 xfer->status = status; /* make software ignore it */ 2264 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2265 qhstatus = sqh->qh.qh_qtd.qtd_status; 2266 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2267 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2268 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2269 if (sqtd == exfer->sqtdend) 2270 break; 2271 } 2272 splx(s); 2273 2274 /* 2275 * Step 2: Wait until we know hardware has finished any possible 2276 * use of the xfer. Also make sure the soft interrupt routine 2277 * has run. 2278 */ 2279 ehci_sync_hc(sc); 2280 s = splusb(); 2281 sc->sc_softwake = 1; 2282 usb_schedsoftintr(&sc->sc_bus); 2283 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2284 splx(s); 2285 2286 /* 2287 * Step 3: Remove any vestiges of the xfer from the hardware. 2288 * The complication here is that the hardware may have executed 2289 * beyond the xfer we're trying to abort. So as we're scanning 2290 * the TDs of this xfer we check if the hardware points to 2291 * any of them. 2292 */ 2293 s = splusb(); /* XXX why? */ 2294 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2295 hit = 0; 2296 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2297 hit |= cur == sqtd->physaddr; 2298 if (sqtd == exfer->sqtdend) 2299 break; 2300 } 2301 sqtd = sqtd->nextqtd; 2302 /* Zap curqtd register if hardware pointed inside the xfer. */ 2303 if (hit && sqtd != NULL) { 2304 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2305 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2306 sqh->qh.qh_qtd.qtd_status = qhstatus; 2307 } else { 2308 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2309 } 2310 2311 /* 2312 * Step 4: Execute callback. 2313 */ 2314 #ifdef DIAGNOSTIC 2315 exfer->isdone = 1; 2316 #endif 2317 usb_transfer_complete(xfer); 2318 2319 splx(s); 2320 #undef exfer 2321 } 2322 2323 void 2324 ehci_timeout(void *addr) 2325 { 2326 struct ehci_xfer *exfer = addr; 2327 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2328 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2329 2330 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2331 #ifdef USB_DEBUG 2332 if (ehcidebug > 1) 2333 usbd_dump_pipe(exfer->xfer.pipe); 2334 #endif 2335 2336 if (sc->sc_dying) { 2337 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2338 return; 2339 } 2340 2341 /* Execute the abort in a process context. */ 2342 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 2343 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2344 } 2345 2346 void 2347 ehci_timeout_task(void *addr) 2348 { 2349 usbd_xfer_handle xfer = addr; 2350 int s; 2351 2352 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2353 2354 s = splusb(); 2355 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2356 splx(s); 2357 } 2358 2359 /************************/ 2360 2361 Static usbd_status 2362 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 2363 { 2364 usbd_status err; 2365 2366 /* Insert last in queue. */ 2367 err = usb_insert_transfer(xfer); 2368 if (err) 2369 return (err); 2370 2371 /* Pipe isn't running, start first */ 2372 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2373 } 2374 2375 Static usbd_status 2376 ehci_device_ctrl_start(usbd_xfer_handle xfer) 2377 { 2378 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2379 usbd_status err; 2380 2381 if (sc->sc_dying) 2382 return (USBD_IOERROR); 2383 2384 #ifdef DIAGNOSTIC 2385 if (!(xfer->rqflags & URQ_REQUEST)) { 2386 /* XXX panic */ 2387 printf("ehci_device_ctrl_transfer: not a request\n"); 2388 return (USBD_INVAL); 2389 } 2390 #endif 2391 2392 err = ehci_device_request(xfer); 2393 if (err) 2394 return (err); 2395 2396 if (sc->sc_bus.use_polling) 2397 ehci_waitintr(sc, xfer); 2398 return (USBD_IN_PROGRESS); 2399 } 2400 2401 void 2402 ehci_device_ctrl_done(usbd_xfer_handle xfer) 2403 { 2404 struct ehci_xfer *ex = EXFER(xfer); 2405 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2406 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 2407 2408 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 2409 2410 #ifdef DIAGNOSTIC 2411 if (!(xfer->rqflags & URQ_REQUEST)) { 2412 panic("ehci_ctrl_done: not a request"); 2413 } 2414 #endif 2415 2416 if (xfer->status != USBD_NOMEM) { 2417 ehci_del_intr_list(ex); /* remove from active list */ 2418 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 2419 } 2420 2421 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 2422 } 2423 2424 /* Abort a device control request. */ 2425 Static void 2426 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 2427 { 2428 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 2429 ehci_abort_xfer(xfer, USBD_CANCELLED); 2430 } 2431 2432 /* Close a device control pipe. */ 2433 Static void 2434 ehci_device_ctrl_close(usbd_pipe_handle pipe) 2435 { 2436 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2437 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 2438 2439 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 2440 ehci_close_pipe(pipe, sc->sc_async_head); 2441 } 2442 2443 usbd_status 2444 ehci_device_request(usbd_xfer_handle xfer) 2445 { 2446 #define exfer EXFER(xfer) 2447 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2448 usb_device_request_t *req = &xfer->request; 2449 usbd_device_handle dev = epipe->pipe.device; 2450 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2451 int addr = dev->address; 2452 ehci_soft_qtd_t *setup, *stat, *next; 2453 ehci_soft_qh_t *sqh; 2454 int isread; 2455 int len; 2456 usbd_status err; 2457 int s; 2458 2459 isread = req->bmRequestType & UT_READ; 2460 len = UGETW(req->wLength); 2461 2462 DPRINTFN(3,("ehci_device_control type=0x%02x, request=0x%02x, " 2463 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2464 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2465 UGETW(req->wIndex), len, addr, 2466 epipe->pipe.endpoint->edesc->bEndpointAddress)); 2467 2468 setup = ehci_alloc_sqtd(sc); 2469 if (setup == NULL) { 2470 err = USBD_NOMEM; 2471 goto bad1; 2472 } 2473 stat = ehci_alloc_sqtd(sc); 2474 if (stat == NULL) { 2475 err = USBD_NOMEM; 2476 goto bad2; 2477 } 2478 2479 sqh = epipe->sqh; 2480 epipe->u.ctl.length = len; 2481 2482 /* XXX 2483 * Since we're messing with the QH we must know the HC is in sync. 2484 * This needs to go away since it slows down control transfers. 2485 * Removing it entails: 2486 * - fill the QH only once with addr & wMaxPacketSize 2487 * - put the correct data toggles in the qtds and set DTC 2488 */ 2489 /* ehci_sync_hc(sc); */ 2490 /* Update device address and length since they may have changed. */ 2491 /* XXX This only needs to be done once, but it's too early in open. */ 2492 /* XXXX Should not touch ED here! */ 2493 sqh->qh.qh_endp = 2494 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QG_MPLMASK))) | 2495 htole32( 2496 EHCI_QH_SET_ADDR(addr) | 2497 /* EHCI_QH_DTC | */ 2498 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 2499 ); 2500 /* Clear toggle */ 2501 sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE); 2502 2503 /* Set up data transaction */ 2504 if (len != 0) { 2505 ehci_soft_qtd_t *end; 2506 2507 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 2508 &next, &end); 2509 if (err) 2510 goto bad3; 2511 end->nextqtd = stat; 2512 end->qtd.qtd_next = 2513 end->qtd.qtd_altnext = htole32(stat->physaddr); 2514 /* Start toggle at 1. */ 2515 /*next->qtd.td_flags |= htole32(EHCI_QTD_TOGGLE);*/ 2516 } else { 2517 next = stat; 2518 } 2519 2520 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 2521 2522 setup->qtd.qtd_status = htole32( 2523 EHCI_QTD_ACTIVE | 2524 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2525 EHCI_QTD_SET_CERR(3) | 2526 EHCI_QTD_SET_BYTES(sizeof *req) 2527 ); 2528 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2529 setup->nextqtd = next; 2530 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2531 setup->xfer = xfer; 2532 setup->len = sizeof *req; 2533 2534 stat->qtd.qtd_status = htole32( 2535 EHCI_QTD_ACTIVE | 2536 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2537 EHCI_QTD_SET_CERR(3) | 2538 EHCI_QTD_IOC 2539 ); 2540 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2541 stat->nextqtd = NULL; 2542 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 2543 stat->xfer = xfer; 2544 stat->len = 0; 2545 2546 #ifdef EHCI_DEBUG 2547 if (ehcidebug > 5) { 2548 DPRINTF(("ehci_device_request:\n")); 2549 ehci_dump_sqh(sqh); 2550 ehci_dump_sqtds(setup); 2551 } 2552 #endif 2553 2554 exfer->sqtdstart = setup; 2555 exfer->sqtdend = stat; 2556 #ifdef DIAGNOSTIC 2557 if (!exfer->isdone) { 2558 printf("ehci_device_request: not done, exfer=%p\n", exfer); 2559 } 2560 exfer->isdone = 0; 2561 #endif 2562 2563 /* Insert qTD in QH list. */ 2564 s = splusb(); 2565 ehci_set_qh_qtd(sqh, setup); 2566 if (xfer->timeout && !sc->sc_bus.use_polling) { 2567 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 2568 ehci_timeout, xfer); 2569 } 2570 ehci_add_intr_list(sc, exfer); 2571 xfer->status = USBD_IN_PROGRESS; 2572 splx(s); 2573 2574 #ifdef EHCI_DEBUG 2575 if (ehcidebug > 10) { 2576 DPRINTF(("ehci_device_request: status=%x\n", 2577 EOREAD4(sc, EHCI_USBSTS))); 2578 delay(10000); 2579 ehci_dump_regs(sc); 2580 ehci_dump_sqh(sc->sc_async_head); 2581 ehci_dump_sqh(sqh); 2582 ehci_dump_sqtds(setup); 2583 } 2584 #endif 2585 2586 return (USBD_NORMAL_COMPLETION); 2587 2588 bad3: 2589 ehci_free_sqtd(sc, stat); 2590 bad2: 2591 ehci_free_sqtd(sc, setup); 2592 bad1: 2593 DPRINTFN(-1,("ehci_device_request: no memory\n")); 2594 xfer->status = err; 2595 usb_transfer_complete(xfer); 2596 return (err); 2597 #undef exfer 2598 } 2599 2600 /************************/ 2601 2602 Static usbd_status 2603 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 2604 { 2605 usbd_status err; 2606 2607 /* Insert last in queue. */ 2608 err = usb_insert_transfer(xfer); 2609 if (err) 2610 return (err); 2611 2612 /* Pipe isn't running, start first */ 2613 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2614 } 2615 2616 usbd_status 2617 ehci_device_bulk_start(usbd_xfer_handle xfer) 2618 { 2619 #define exfer EXFER(xfer) 2620 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2621 usbd_device_handle dev = epipe->pipe.device; 2622 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2623 ehci_soft_qtd_t *data, *dataend; 2624 ehci_soft_qh_t *sqh; 2625 usbd_status err; 2626 int len, isread, endpt; 2627 int s; 2628 2629 DPRINTFN(2, ("ehci_device_bulk_transfer: xfer=%p len=%d flags=%d\n", 2630 xfer, xfer->length, xfer->flags)); 2631 2632 if (sc->sc_dying) 2633 return (USBD_IOERROR); 2634 2635 #ifdef DIAGNOSTIC 2636 if (xfer->rqflags & URQ_REQUEST) 2637 panic("ehci_device_bulk_transfer: a request"); 2638 #endif 2639 2640 len = xfer->length; 2641 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 2642 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2643 sqh = epipe->sqh; 2644 2645 epipe->u.bulk.length = len; 2646 2647 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 2648 &dataend); 2649 if (err) { 2650 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 2651 xfer->status = err; 2652 usb_transfer_complete(xfer); 2653 return (err); 2654 } 2655 2656 #ifdef EHCI_DEBUG 2657 if (ehcidebug > 5) { 2658 DPRINTF(("ehci_device_bulk_transfer: data(1)\n")); 2659 ehci_dump_sqh(sqh); 2660 ehci_dump_sqtds(data); 2661 } 2662 #endif 2663 2664 /* Set up interrupt info. */ 2665 exfer->sqtdstart = data; 2666 exfer->sqtdend = dataend; 2667 #ifdef DIAGNOSTIC 2668 if (!exfer->isdone) { 2669 printf("ehci_device_bulk_transfer: not done, ex=%p\n", exfer); 2670 } 2671 exfer->isdone = 0; 2672 #endif 2673 2674 s = splusb(); 2675 ehci_set_qh_qtd(sqh, data); 2676 if (xfer->timeout && !sc->sc_bus.use_polling) { 2677 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 2678 ehci_timeout, xfer); 2679 } 2680 ehci_add_intr_list(sc, exfer); 2681 xfer->status = USBD_IN_PROGRESS; 2682 splx(s); 2683 2684 #ifdef EHCI_DEBUG 2685 if (ehcidebug > 10) { 2686 DPRINTF(("ehci_device_bulk_transfer: data(2)\n")); 2687 delay(10000); 2688 DPRINTF(("ehci_device_bulk_transfer: data(3)\n")); 2689 ehci_dump_regs(sc); 2690 #if 0 2691 printf("async_head:\n"); 2692 ehci_dump_sqh(sc->sc_async_head); 2693 #endif 2694 printf("sqh:\n"); 2695 ehci_dump_sqh(sqh); 2696 ehci_dump_sqtds(data); 2697 } 2698 #endif 2699 2700 if (sc->sc_bus.use_polling) 2701 ehci_waitintr(sc, xfer); 2702 2703 return (USBD_IN_PROGRESS); 2704 #undef exfer 2705 } 2706 2707 Static void 2708 ehci_device_bulk_abort(usbd_xfer_handle xfer) 2709 { 2710 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 2711 ehci_abort_xfer(xfer, USBD_CANCELLED); 2712 } 2713 2714 /* 2715 * Close a device bulk pipe. 2716 */ 2717 Static void 2718 ehci_device_bulk_close(usbd_pipe_handle pipe) 2719 { 2720 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2721 2722 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 2723 ehci_close_pipe(pipe, sc->sc_async_head); 2724 } 2725 2726 void 2727 ehci_device_bulk_done(usbd_xfer_handle xfer) 2728 { 2729 struct ehci_xfer *ex = EXFER(xfer); 2730 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2731 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 2732 2733 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 2734 xfer, xfer->actlen)); 2735 2736 if (xfer->status != USBD_NOMEM) { 2737 ehci_del_intr_list(ex); /* remove from active list */ 2738 ehci_free_sqtd_chain(sc, ex->sqtdstart, 0); 2739 } 2740 2741 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 2742 } 2743 2744 /************************/ 2745 2746 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2747 Static usbd_status ehci_device_intr_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2748 Static void ehci_device_intr_abort(usbd_xfer_handle xfer) { } 2749 Static void ehci_device_intr_close(usbd_pipe_handle pipe) { } 2750 Static void ehci_device_intr_done(usbd_xfer_handle xfer) { } 2751 2752 /************************/ 2753 2754 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2755 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2756 Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { } 2757 Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { } 2758 Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { } 2759