1 /* $NetBSD: amdgpu_athub_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_athub_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "athub_v1_0.h"
30
31 #include "athub/athub_1_0_offset.h"
32 #include "athub/athub_1_0_sh_mask.h"
33 #include "vega10_enum.h"
34
35 #include "soc15_common.h"
36
athub_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)37 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
38 bool enable)
39 {
40 uint32_t def, data;
41
42 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
43
44 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
45 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
46 else
47 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
48
49 if (def != data)
50 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
51 }
52
athub_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)53 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
54 bool enable)
55 {
56 uint32_t def, data;
57
58 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
59
60 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
61 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
62 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
63 else
64 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
65
66 if(def != data)
67 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
68 }
69
athub_v1_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)70 int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
71 enum amd_clockgating_state state)
72 {
73 if (amdgpu_sriov_vf(adev))
74 return 0;
75
76 switch (adev->asic_type) {
77 case CHIP_VEGA10:
78 case CHIP_VEGA12:
79 case CHIP_VEGA20:
80 case CHIP_RAVEN:
81 athub_update_medium_grain_clock_gating(adev,
82 state == AMD_CG_STATE_GATE);
83 athub_update_medium_grain_light_sleep(adev,
84 state == AMD_CG_STATE_GATE);
85 break;
86 default:
87 break;
88 }
89
90 return 0;
91 }
92
athub_v1_0_get_clockgating(struct amdgpu_device * adev,u32 * flags)93 void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
94 {
95 int data;
96
97 if (amdgpu_sriov_vf(adev))
98 *flags = 0;
99
100 /* AMD_CG_SUPPORT_ATHUB_MGCG */
101 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
102 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
103 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
104
105 /* AMD_CG_SUPPORT_ATHUB_LS */
106 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
107 *flags |= AMD_CG_SUPPORT_ATHUB_LS;
108 }
109