1 /* $NetBSD: amdgpu_psp_v10_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Author: Huang Rui
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_psp_v10_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
30
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34
35 #include "amdgpu.h"
36 #include "amdgpu_psp.h"
37 #include "amdgpu_ucode.h"
38 #include "soc15_common.h"
39 #include "psp_v10_0.h"
40
41 #include "mp/mp_10_0_offset.h"
42 #include "gc/gc_9_1_offset.h"
43 #include "sdma0/sdma0_4_1_offset.h"
44
45 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
46 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
47 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
48 MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
49 MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
50 MODULE_FIRMWARE("amdgpu/raven_ta.bin");
51
psp_v10_0_init_microcode(struct psp_context * psp)52 static int psp_v10_0_init_microcode(struct psp_context *psp)
53 {
54 struct amdgpu_device *adev = psp->adev;
55 const char *chip_name;
56 char fw_name[30];
57 int err = 0;
58 const struct psp_firmware_header_v1_0 *hdr;
59 const struct ta_firmware_header_v1_0 *ta_hdr;
60 DRM_DEBUG("\n");
61
62 switch (adev->asic_type) {
63 case CHIP_RAVEN:
64 if (adev->rev_id >= 0x8)
65 chip_name = "raven2";
66 else if (adev->pdev->device == 0x15d8)
67 chip_name = "picasso";
68 else
69 chip_name = "raven";
70 break;
71 default: BUG();
72 }
73
74 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
75 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
76 if (err)
77 goto out;
78
79 err = amdgpu_ucode_validate(adev->psp.asd_fw);
80 if (err)
81 goto out;
82
83 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
84 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
85 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
86 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
87 adev->psp.asd_start_addr = (const uint8_t *)hdr +
88 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
89
90 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
91 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
92 if (err) {
93 release_firmware(adev->psp.ta_fw);
94 adev->psp.ta_fw = NULL;
95 dev_info(adev->dev,
96 "psp v10.0: Failed to load firmware \"%s\"\n",
97 fw_name);
98 } else {
99 err = amdgpu_ucode_validate(adev->psp.ta_fw);
100 if (err)
101 goto out2;
102
103 ta_hdr = (const struct ta_firmware_header_v1_0 *)
104 adev->psp.ta_fw->data;
105 adev->psp.ta_hdcp_ucode_version =
106 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
107 adev->psp.ta_hdcp_ucode_size =
108 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
109 adev->psp.ta_hdcp_start_addr =
110 (const uint8_t *)ta_hdr +
111 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
112
113 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
114
115 adev->psp.ta_dtm_ucode_version =
116 le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
117 adev->psp.ta_dtm_ucode_size =
118 le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
119 adev->psp.ta_dtm_start_addr =
120 (const uint8_t *)adev->psp.ta_hdcp_start_addr +
121 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
122 }
123
124 return 0;
125
126 out2:
127 release_firmware(adev->psp.ta_fw);
128 adev->psp.ta_fw = NULL;
129 out:
130 if (err) {
131 dev_err(adev->dev,
132 "psp v10.0: Failed to load firmware \"%s\"\n",
133 fw_name);
134 release_firmware(adev->psp.asd_fw);
135 adev->psp.asd_fw = NULL;
136 }
137
138 return err;
139 }
140
psp_v10_0_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)141 static int psp_v10_0_ring_init(struct psp_context *psp,
142 enum psp_ring_type ring_type)
143 {
144 int ret = 0;
145 struct psp_ring *ring;
146 struct amdgpu_device *adev = psp->adev;
147
148 ring = &psp->km_ring;
149
150 ring->ring_type = ring_type;
151
152 /* allocate 4k Page of Local Frame Buffer memory for ring */
153 ring->ring_size = 0x1000;
154 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
155 AMDGPU_GEM_DOMAIN_VRAM,
156 &adev->firmware.rbuf,
157 &ring->ring_mem_mc_addr,
158 (void **)&ring->ring_mem);
159 if (ret) {
160 ring->ring_size = 0;
161 return ret;
162 }
163
164 return 0;
165 }
166
psp_v10_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)167 static int psp_v10_0_ring_create(struct psp_context *psp,
168 enum psp_ring_type ring_type)
169 {
170 int ret = 0;
171 unsigned int psp_ring_reg = 0;
172 struct psp_ring *ring = &psp->km_ring;
173 struct amdgpu_device *adev = psp->adev;
174
175 /* Write low address of the ring to C2PMSG_69 */
176 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
177 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
178 /* Write high address of the ring to C2PMSG_70 */
179 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
180 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
181 /* Write size of ring to C2PMSG_71 */
182 psp_ring_reg = ring->ring_size;
183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
184 /* Write the ring initialization command to C2PMSG_64 */
185 psp_ring_reg = ring_type;
186 psp_ring_reg = psp_ring_reg << 16;
187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
188
189 /* There might be handshake issue with hardware which needs delay */
190 mdelay(20);
191
192 /* Wait for response flag (bit 31) in C2PMSG_64 */
193 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
194 0x80000000, 0x8000FFFF, false);
195
196 return ret;
197 }
198
psp_v10_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)199 static int psp_v10_0_ring_stop(struct psp_context *psp,
200 enum psp_ring_type ring_type)
201 {
202 int ret = 0;
203 unsigned int psp_ring_reg = 0;
204 struct amdgpu_device *adev = psp->adev;
205
206 /* Write the ring destroy command to C2PMSG_64 */
207 psp_ring_reg = 3 << 16;
208 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
209
210 /* There might be handshake issue with hardware which needs delay */
211 mdelay(20);
212
213 /* Wait for response flag (bit 31) in C2PMSG_64 */
214 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
215 0x80000000, 0x80000000, false);
216
217 return ret;
218 }
219
psp_v10_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)220 static int psp_v10_0_ring_destroy(struct psp_context *psp,
221 enum psp_ring_type ring_type)
222 {
223 int ret = 0;
224 struct psp_ring *ring = &psp->km_ring;
225 struct amdgpu_device *adev = psp->adev;
226
227 ret = psp_v10_0_ring_stop(psp, ring_type);
228 if (ret)
229 DRM_ERROR("Fail to stop psp ring\n");
230
231 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
232 &ring->ring_mem_mc_addr,
233 (void **)&ring->ring_mem);
234
235 return ret;
236 }
237
238 static int
psp_v10_0_sram_map(struct amdgpu_device * adev,unsigned int * sram_offset,unsigned int * sram_addr_reg_offset,unsigned int * sram_data_reg_offset,enum AMDGPU_UCODE_ID ucode_id)239 psp_v10_0_sram_map(struct amdgpu_device *adev,
240 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
241 unsigned int *sram_data_reg_offset,
242 enum AMDGPU_UCODE_ID ucode_id)
243 {
244 int ret = 0;
245
246 switch(ucode_id) {
247 /* TODO: needs to confirm */
248 #if 0
249 case AMDGPU_UCODE_ID_SMC:
250 *sram_offset = 0;
251 *sram_addr_reg_offset = 0;
252 *sram_data_reg_offset = 0;
253 break;
254 #endif
255
256 case AMDGPU_UCODE_ID_CP_CE:
257 *sram_offset = 0x0;
258 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
259 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
260 break;
261
262 case AMDGPU_UCODE_ID_CP_PFP:
263 *sram_offset = 0x0;
264 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
265 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
266 break;
267
268 case AMDGPU_UCODE_ID_CP_ME:
269 *sram_offset = 0x0;
270 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
271 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
272 break;
273
274 case AMDGPU_UCODE_ID_CP_MEC1:
275 *sram_offset = 0x10000;
276 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
277 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
278 break;
279
280 case AMDGPU_UCODE_ID_CP_MEC2:
281 *sram_offset = 0x10000;
282 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
283 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
284 break;
285
286 case AMDGPU_UCODE_ID_RLC_G:
287 *sram_offset = 0x2000;
288 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
289 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
290 break;
291
292 case AMDGPU_UCODE_ID_SDMA0:
293 *sram_offset = 0x0;
294 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
295 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
296 break;
297
298 /* TODO: needs to confirm */
299 #if 0
300 case AMDGPU_UCODE_ID_SDMA1:
301 *sram_offset = ;
302 *sram_addr_reg_offset = ;
303 break;
304
305 case AMDGPU_UCODE_ID_UVD:
306 *sram_offset = ;
307 *sram_addr_reg_offset = ;
308 break;
309
310 case AMDGPU_UCODE_ID_VCE:
311 *sram_offset = ;
312 *sram_addr_reg_offset = ;
313 break;
314 #endif
315
316 case AMDGPU_UCODE_ID_MAXIMUM:
317 default:
318 ret = -EINVAL;
319 break;
320 }
321
322 return ret;
323 }
324
psp_v10_0_compare_sram_data(struct psp_context * psp,struct amdgpu_firmware_info * ucode,enum AMDGPU_UCODE_ID ucode_type)325 static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
326 struct amdgpu_firmware_info *ucode,
327 enum AMDGPU_UCODE_ID ucode_type)
328 {
329 int err = 0;
330 unsigned int fw_sram_reg_val = 0;
331 unsigned int fw_sram_addr_reg_offset = 0;
332 unsigned int fw_sram_data_reg_offset = 0;
333 unsigned int ucode_size;
334 uint32_t *ucode_mem = NULL;
335 struct amdgpu_device *adev = psp->adev;
336
337 err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
338 &fw_sram_data_reg_offset, ucode_type);
339 if (err)
340 return false;
341
342 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
343
344 ucode_size = ucode->ucode_size;
345 ucode_mem = (uint32_t *)ucode->kaddr;
346 while (!ucode_size) {
347 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
348
349 if (*ucode_mem != fw_sram_reg_val)
350 return false;
351
352 ucode_mem++;
353 /* 4 bytes */
354 ucode_size -= 4;
355 }
356
357 return true;
358 }
359
360
psp_v10_0_mode1_reset(struct psp_context * psp)361 static int psp_v10_0_mode1_reset(struct psp_context *psp)
362 {
363 DRM_INFO("psp mode 1 reset not supported now! \n");
364 return -EINVAL;
365 }
366
psp_v10_0_ring_get_wptr(struct psp_context * psp)367 static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
368 {
369 struct amdgpu_device *adev = psp->adev;
370
371 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
372 }
373
psp_v10_0_ring_set_wptr(struct psp_context * psp,uint32_t value)374 static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
375 {
376 struct amdgpu_device *adev = psp->adev;
377
378 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
379 }
380
381 static const struct psp_funcs psp_v10_0_funcs = {
382 .init_microcode = psp_v10_0_init_microcode,
383 .ring_init = psp_v10_0_ring_init,
384 .ring_create = psp_v10_0_ring_create,
385 .ring_stop = psp_v10_0_ring_stop,
386 .ring_destroy = psp_v10_0_ring_destroy,
387 .compare_sram_data = psp_v10_0_compare_sram_data,
388 .mode1_reset = psp_v10_0_mode1_reset,
389 .ring_get_wptr = psp_v10_0_ring_get_wptr,
390 .ring_set_wptr = psp_v10_0_ring_set_wptr,
391 };
392
psp_v10_0_set_psp_funcs(struct psp_context * psp)393 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
394 {
395 psp->funcs = &psp_v10_0_funcs;
396 }
397