1 /* $NetBSD: amdgpu_psp_v12_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_psp_v12_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
27
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include "amdgpu.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_ucode.h"
33 #include "soc15_common.h"
34 #include "psp_v12_0.h"
35
36 #include "mp/mp_12_0_0_offset.h"
37 #include "mp/mp_12_0_0_sh_mask.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "sdma0/sdma0_4_0_offset.h"
40 #include "nbio/nbio_7_4_offset.h"
41
42 #include "oss/osssys_4_0_offset.h"
43 #include "oss/osssys_4_0_sh_mask.h"
44
45 MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
46 /* address block */
47 #define smnMP1_FIRMWARE_FLAGS 0x3010024
48
psp_v12_0_init_microcode(struct psp_context * psp)49 static int psp_v12_0_init_microcode(struct psp_context *psp)
50 {
51 struct amdgpu_device *adev = psp->adev;
52 const char *chip_name;
53 char fw_name[30];
54 int err = 0;
55 const struct psp_firmware_header_v1_0 *asd_hdr;
56
57 DRM_DEBUG("\n");
58
59 switch (adev->asic_type) {
60 case CHIP_RENOIR:
61 chip_name = "renoir";
62 break;
63 default:
64 BUG();
65 }
66
67 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
68 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
69 if (err)
70 goto out1;
71
72 err = amdgpu_ucode_validate(adev->psp.asd_fw);
73 if (err)
74 goto out1;
75
76 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
77 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
78 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
79 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
80 adev->psp.asd_start_addr = (const uint8_t *)asd_hdr +
81 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
82
83 return 0;
84
85 out1:
86 release_firmware(adev->psp.asd_fw);
87 adev->psp.asd_fw = NULL;
88
89 return err;
90 }
91
psp_v12_0_bootloader_load_sysdrv(struct psp_context * psp)92 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
93 {
94 int ret;
95 uint32_t psp_gfxdrv_command_reg = 0;
96 struct amdgpu_device *adev = psp->adev;
97 uint32_t sol_reg;
98
99 /* Check sOS sign of life register to confirm sys driver and sOS
100 * are already been loaded.
101 */
102 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
103 if (sol_reg) {
104 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
105 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
106 return 0;
107 }
108
109 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
110 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
111 0x80000000, 0x80000000, false);
112 if (ret)
113 return ret;
114
115 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
116
117 /* Copy PSP System Driver binary to memory */
118 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
119
120 /* Provide the sys driver to bootloader */
121 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
122 (uint32_t)(psp->fw_pri_mc_addr >> 20));
123 psp_gfxdrv_command_reg = 1 << 16;
124 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
125 psp_gfxdrv_command_reg);
126
127 /* there might be handshake issue with hardware which needs delay */
128 mdelay(20);
129
130 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
131 0x80000000, 0x80000000, false);
132
133 return ret;
134 }
135
psp_v12_0_bootloader_load_sos(struct psp_context * psp)136 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
137 {
138 int ret;
139 unsigned int psp_gfxdrv_command_reg = 0;
140 struct amdgpu_device *adev = psp->adev;
141 uint32_t sol_reg;
142
143 /* Check sOS sign of life register to confirm sys driver and sOS
144 * are already been loaded.
145 */
146 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
147 if (sol_reg)
148 return 0;
149
150 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
151 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
152 0x80000000, 0x80000000, false);
153 if (ret)
154 return ret;
155
156 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
157
158 /* Copy Secure OS binary to PSP memory */
159 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
160
161 /* Provide the PSP secure OS to bootloader */
162 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
163 (uint32_t)(psp->fw_pri_mc_addr >> 20));
164 psp_gfxdrv_command_reg = 2 << 16;
165 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
166 psp_gfxdrv_command_reg);
167
168 /* there might be handshake issue with hardware which needs delay */
169 mdelay(20);
170 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
171 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
172 0, true);
173
174 return ret;
175 }
176
psp_v12_0_reroute_ih(struct psp_context * psp)177 static void psp_v12_0_reroute_ih(struct psp_context *psp)
178 {
179 struct amdgpu_device *adev = psp->adev;
180 uint32_t tmp;
181
182 /* Change IH ring for VMC */
183 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
184 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
185 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
186
187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
188 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
189 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
190
191 mdelay(20);
192 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
193 0x80000000, 0x8000FFFF, false);
194
195 /* Change IH ring for UMC */
196 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
197 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
198
199 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
201 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
202
203 mdelay(20);
204 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
205 0x80000000, 0x8000FFFF, false);
206 }
207
psp_v12_0_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)208 static int psp_v12_0_ring_init(struct psp_context *psp,
209 enum psp_ring_type ring_type)
210 {
211 int ret = 0;
212 struct psp_ring *ring;
213 struct amdgpu_device *adev = psp->adev;
214
215 psp_v12_0_reroute_ih(psp);
216
217 ring = &psp->km_ring;
218
219 ring->ring_type = ring_type;
220
221 /* allocate 4k Page of Local Frame Buffer memory for ring */
222 ring->ring_size = 0x1000;
223 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
224 AMDGPU_GEM_DOMAIN_VRAM,
225 &adev->firmware.rbuf,
226 &ring->ring_mem_mc_addr,
227 (void **)&ring->ring_mem);
228 if (ret) {
229 ring->ring_size = 0;
230 return ret;
231 }
232
233 return 0;
234 }
235
psp_v12_0_support_vmr_ring(struct psp_context * psp)236 static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
237 {
238 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
239 return true;
240 return false;
241 }
242
psp_v12_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)243 static int psp_v12_0_ring_create(struct psp_context *psp,
244 enum psp_ring_type ring_type)
245 {
246 int ret = 0;
247 unsigned int psp_ring_reg = 0;
248 struct psp_ring *ring = &psp->km_ring;
249 struct amdgpu_device *adev = psp->adev;
250
251 if (psp_v12_0_support_vmr_ring(psp)) {
252 /* Write low address of the ring to C2PMSG_102 */
253 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
254 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
255 /* Write high address of the ring to C2PMSG_103 */
256 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
257 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
258
259 /* Write the ring initialization command to C2PMSG_101 */
260 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
261 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
262
263 /* there might be handshake issue with hardware which needs delay */
264 mdelay(20);
265
266 /* Wait for response flag (bit 31) in C2PMSG_101 */
267 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
268 0x80000000, 0x8000FFFF, false);
269
270 } else {
271 /* Write low address of the ring to C2PMSG_69 */
272 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
274 /* Write high address of the ring to C2PMSG_70 */
275 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
277 /* Write size of ring to C2PMSG_71 */
278 psp_ring_reg = ring->ring_size;
279 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
280 /* Write the ring initialization command to C2PMSG_64 */
281 psp_ring_reg = ring_type;
282 psp_ring_reg = psp_ring_reg << 16;
283 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
284
285 /* there might be handshake issue with hardware which needs delay */
286 mdelay(20);
287
288 /* Wait for response flag (bit 31) in C2PMSG_64 */
289 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
290 0x80000000, 0x8000FFFF, false);
291 }
292
293 return ret;
294 }
295
psp_v12_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)296 static int psp_v12_0_ring_stop(struct psp_context *psp,
297 enum psp_ring_type ring_type)
298 {
299 int ret = 0;
300 struct amdgpu_device *adev = psp->adev;
301
302 /* Write the ring destroy command*/
303 if (psp_v12_0_support_vmr_ring(psp))
304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
305 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
306 else
307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
308 GFX_CTRL_CMD_ID_DESTROY_RINGS);
309
310 /* there might be handshake issue with hardware which needs delay */
311 mdelay(20);
312
313 /* Wait for response flag (bit 31) */
314 if (psp_v12_0_support_vmr_ring(psp))
315 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
316 0x80000000, 0x80000000, false);
317 else
318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
319 0x80000000, 0x80000000, false);
320
321 return ret;
322 }
323
psp_v12_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)324 static int psp_v12_0_ring_destroy(struct psp_context *psp,
325 enum psp_ring_type ring_type)
326 {
327 int ret = 0;
328 struct psp_ring *ring = &psp->km_ring;
329 struct amdgpu_device *adev = psp->adev;
330
331 ret = psp_v12_0_ring_stop(psp, ring_type);
332 if (ret)
333 DRM_ERROR("Fail to stop psp ring\n");
334
335 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
336 &ring->ring_mem_mc_addr,
337 (void **)&ring->ring_mem);
338
339 return ret;
340 }
341
342 static int
psp_v12_0_sram_map(struct amdgpu_device * adev,unsigned int * sram_offset,unsigned int * sram_addr_reg_offset,unsigned int * sram_data_reg_offset,enum AMDGPU_UCODE_ID ucode_id)343 psp_v12_0_sram_map(struct amdgpu_device *adev,
344 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
345 unsigned int *sram_data_reg_offset,
346 enum AMDGPU_UCODE_ID ucode_id)
347 {
348 int ret = 0;
349
350 switch (ucode_id) {
351 /* TODO: needs to confirm */
352 #if 0
353 case AMDGPU_UCODE_ID_SMC:
354 *sram_offset = 0;
355 *sram_addr_reg_offset = 0;
356 *sram_data_reg_offset = 0;
357 break;
358 #endif
359
360 case AMDGPU_UCODE_ID_CP_CE:
361 *sram_offset = 0x0;
362 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
363 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
364 break;
365
366 case AMDGPU_UCODE_ID_CP_PFP:
367 *sram_offset = 0x0;
368 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
369 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
370 break;
371
372 case AMDGPU_UCODE_ID_CP_ME:
373 *sram_offset = 0x0;
374 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
375 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
376 break;
377
378 case AMDGPU_UCODE_ID_CP_MEC1:
379 *sram_offset = 0x10000;
380 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
381 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
382 break;
383
384 case AMDGPU_UCODE_ID_CP_MEC2:
385 *sram_offset = 0x10000;
386 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
387 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
388 break;
389
390 case AMDGPU_UCODE_ID_RLC_G:
391 *sram_offset = 0x2000;
392 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
393 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
394 break;
395
396 case AMDGPU_UCODE_ID_SDMA0:
397 *sram_offset = 0x0;
398 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
399 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
400 break;
401
402 /* TODO: needs to confirm */
403 #if 0
404 case AMDGPU_UCODE_ID_SDMA1:
405 *sram_offset = ;
406 *sram_addr_reg_offset = ;
407 break;
408
409 case AMDGPU_UCODE_ID_UVD:
410 *sram_offset = ;
411 *sram_addr_reg_offset = ;
412 break;
413
414 case AMDGPU_UCODE_ID_VCE:
415 *sram_offset = ;
416 *sram_addr_reg_offset = ;
417 break;
418 #endif
419
420 case AMDGPU_UCODE_ID_MAXIMUM:
421 default:
422 ret = -EINVAL;
423 break;
424 }
425
426 return ret;
427 }
428
psp_v12_0_compare_sram_data(struct psp_context * psp,struct amdgpu_firmware_info * ucode,enum AMDGPU_UCODE_ID ucode_type)429 static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
430 struct amdgpu_firmware_info *ucode,
431 enum AMDGPU_UCODE_ID ucode_type)
432 {
433 int err = 0;
434 unsigned int fw_sram_reg_val = 0;
435 unsigned int fw_sram_addr_reg_offset = 0;
436 unsigned int fw_sram_data_reg_offset = 0;
437 unsigned int ucode_size;
438 uint32_t *ucode_mem = NULL;
439 struct amdgpu_device *adev = psp->adev;
440
441 err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
442 &fw_sram_data_reg_offset, ucode_type);
443 if (err)
444 return false;
445
446 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
447
448 ucode_size = ucode->ucode_size;
449 ucode_mem = (uint32_t *)ucode->kaddr;
450 while (ucode_size) {
451 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
452
453 if (*ucode_mem != fw_sram_reg_val)
454 return false;
455
456 ucode_mem++;
457 /* 4 bytes */
458 ucode_size -= 4;
459 }
460
461 return true;
462 }
463
psp_v12_0_mode1_reset(struct psp_context * psp)464 static int psp_v12_0_mode1_reset(struct psp_context *psp)
465 {
466 int ret;
467 uint32_t offset;
468 struct amdgpu_device *adev = psp->adev;
469
470 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
471
472 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
473
474 if (ret) {
475 DRM_INFO("psp is not working correctly before mode1 reset!\n");
476 return -EINVAL;
477 }
478
479 /*send the mode 1 reset command*/
480 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
481
482 msleep(500);
483
484 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
485
486 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
487
488 if (ret) {
489 DRM_INFO("psp mode 1 reset failed!\n");
490 return -EINVAL;
491 }
492
493 DRM_INFO("psp mode1 reset succeed \n");
494
495 return 0;
496 }
497
psp_v12_0_ring_get_wptr(struct psp_context * psp)498 static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
499 {
500 uint32_t data;
501 struct amdgpu_device *adev = psp->adev;
502
503 if (psp_v12_0_support_vmr_ring(psp))
504 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
505 else
506 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
507
508 return data;
509 }
510
psp_v12_0_ring_set_wptr(struct psp_context * psp,uint32_t value)511 static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
512 {
513 struct amdgpu_device *adev = psp->adev;
514
515 if (psp_v12_0_support_vmr_ring(psp)) {
516 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
517 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
518 } else
519 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
520 }
521
522 static const struct psp_funcs psp_v12_0_funcs = {
523 .init_microcode = psp_v12_0_init_microcode,
524 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
525 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
526 .ring_init = psp_v12_0_ring_init,
527 .ring_create = psp_v12_0_ring_create,
528 .ring_stop = psp_v12_0_ring_stop,
529 .ring_destroy = psp_v12_0_ring_destroy,
530 .compare_sram_data = psp_v12_0_compare_sram_data,
531 .mode1_reset = psp_v12_0_mode1_reset,
532 .ring_get_wptr = psp_v12_0_ring_get_wptr,
533 .ring_set_wptr = psp_v12_0_ring_set_wptr,
534 };
535
psp_v12_0_set_psp_funcs(struct psp_context * psp)536 void psp_v12_0_set_psp_funcs(struct psp_context *psp)
537 {
538 psp->funcs = &psp_v12_0_funcs;
539 }
540