1 /* $NetBSD: vid.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef VI_H 26 #define VI_H 27 28 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 29 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 30 #define SDMA_MAX_INSTANCE 2 31 32 #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */ 33 34 /* crtc instance offsets */ 35 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) 36 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) 37 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c) 38 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c) 39 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c) 40 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) 41 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c) 42 43 /* dig instance offsets */ 44 #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00) 45 #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00) 46 #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00) 47 #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00) 48 #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00) 49 #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00) 50 #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00) 51 #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00) 52 #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00) 53 54 /* audio endpt instance offsets */ 55 #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8) 56 #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8) 57 #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8) 58 #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) 59 #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) 60 #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) 61 #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8) 62 #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8) 63 64 /* hpd instance offsets */ 65 #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) 66 #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898) 67 #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898) 68 #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898) 69 #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) 70 #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) 71 72 #define AMDGPU_NUM_OF_VMIDS 8 73 74 #define PIPEID(x) ((x) << 0) 75 #define MEID(x) ((x) << 2) 76 #define VMID(x) ((x) << 4) 77 #define QUEUEID(x) ((x) << 8) 78 79 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 80 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 81 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 82 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 83 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 84 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 85 #define MC_SEQ_MISC0__MT__HBM 0x60000000 86 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 87 88 /* 89 * PM4 90 */ 91 #define PACKET_TYPE0 0 92 #define PACKET_TYPE1 1 93 #define PACKET_TYPE2 2 94 #define PACKET_TYPE3 3 95 96 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 97 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 98 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 99 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 100 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 101 ((reg) & 0xFFFF) | \ 102 ((n) & 0x3FFF) << 16) 103 #define CP_PACKET2 0x80000000 104 #define PACKET2_PAD_SHIFT 0 105 #define PACKET2_PAD_MASK (0x3fffffff << 0) 106 107 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 108 109 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 110 (((op) & 0xFF) << 8) | \ 111 ((n) & 0x3FFF) << 16) 112 113 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 114 115 /* Packet 3 types */ 116 #define PACKET3_NOP 0x10 117 #define PACKET3_SET_BASE 0x11 118 #define PACKET3_BASE_INDEX(x) ((x) << 0) 119 #define CE_PARTITION_BASE 3 120 #define PACKET3_CLEAR_STATE 0x12 121 #define PACKET3_INDEX_BUFFER_SIZE 0x13 122 #define PACKET3_DISPATCH_DIRECT 0x15 123 #define PACKET3_DISPATCH_INDIRECT 0x16 124 #define PACKET3_ATOMIC_GDS 0x1D 125 #define PACKET3_ATOMIC_MEM 0x1E 126 #define PACKET3_OCCLUSION_QUERY 0x1F 127 #define PACKET3_SET_PREDICATION 0x20 128 #define PACKET3_REG_RMW 0x21 129 #define PACKET3_COND_EXEC 0x22 130 #define PACKET3_PRED_EXEC 0x23 131 #define PACKET3_DRAW_INDIRECT 0x24 132 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 133 #define PACKET3_INDEX_BASE 0x26 134 #define PACKET3_DRAW_INDEX_2 0x27 135 #define PACKET3_CONTEXT_CONTROL 0x28 136 #define PACKET3_INDEX_TYPE 0x2A 137 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 138 #define PACKET3_DRAW_INDEX_AUTO 0x2D 139 #define PACKET3_NUM_INSTANCES 0x2F 140 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 141 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 142 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 143 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 144 #define PACKET3_DRAW_PREAMBLE 0x36 145 #define PACKET3_WRITE_DATA 0x37 146 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 147 /* 0 - register 148 * 1 - memory (sync - via GRBM) 149 * 2 - gl2 150 * 3 - gds 151 * 4 - reserved 152 * 5 - memory (async - direct) 153 */ 154 #define WR_ONE_ADDR (1 << 16) 155 #define WR_CONFIRM (1 << 20) 156 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 157 /* 0 - LRU 158 * 1 - Stream 159 */ 160 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 161 /* 0 - me 162 * 1 - pfp 163 * 2 - ce 164 */ 165 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 166 #define PACKET3_MEM_SEMAPHORE 0x39 167 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 168 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 169 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 170 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 171 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 172 #define PACKET3_WAIT_REG_MEM 0x3C 173 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 174 /* 0 - always 175 * 1 - < 176 * 2 - <= 177 * 3 - == 178 * 4 - != 179 * 5 - >= 180 * 6 - > 181 */ 182 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 183 /* 0 - reg 184 * 1 - mem 185 */ 186 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 187 /* 0 - wait_reg_mem 188 * 1 - wr_wait_wr_reg 189 */ 190 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 191 /* 0 - me 192 * 1 - pfp 193 */ 194 #define PACKET3_INDIRECT_BUFFER 0x3F 195 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 196 #define INDIRECT_BUFFER_VALID (1 << 23) 197 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 198 /* 0 - LRU 199 * 1 - Stream 200 * 2 - Bypass 201 */ 202 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 203 #define PACKET3_COPY_DATA 0x40 204 #define PACKET3_PFP_SYNC_ME 0x42 205 #define PACKET3_SURFACE_SYNC 0x43 206 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 207 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 208 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 209 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 210 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 211 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 212 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 213 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 214 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 215 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 216 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 217 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 218 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 219 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 220 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 221 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 222 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 223 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 224 # define PACKET3_CB_ACTION_ENA (1 << 25) 225 # define PACKET3_DB_ACTION_ENA (1 << 26) 226 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 227 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 228 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 229 #define PACKET3_COND_WRITE 0x45 230 #define PACKET3_EVENT_WRITE 0x46 231 #define EVENT_TYPE(x) ((x) << 0) 232 #define EVENT_INDEX(x) ((x) << 8) 233 /* 0 - any non-TS event 234 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 235 * 2 - SAMPLE_PIPELINESTAT 236 * 3 - SAMPLE_STREAMOUTSTAT* 237 * 4 - *S_PARTIAL_FLUSH 238 * 5 - EOP events 239 * 6 - EOS events 240 */ 241 #define PACKET3_EVENT_WRITE_EOP 0x47 242 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 243 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 244 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 245 #define EOP_TCL1_ACTION_EN (1 << 16) 246 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 247 #define EOP_TCL2_VOLATILE (1 << 24) 248 #define EOP_CACHE_POLICY(x) ((x) << 25) 249 /* 0 - LRU 250 * 1 - Stream 251 * 2 - Bypass 252 */ 253 #define DATA_SEL(x) ((x) << 29) 254 /* 0 - discard 255 * 1 - send low 32bit data 256 * 2 - send 64bit data 257 * 3 - send 64bit GPU counter value 258 * 4 - send 64bit sys counter value 259 */ 260 #define INT_SEL(x) ((x) << 24) 261 /* 0 - none 262 * 1 - interrupt only (DATA_SEL = 0) 263 * 2 - interrupt when data write is confirmed 264 */ 265 #define DST_SEL(x) ((x) << 16) 266 /* 0 - MC 267 * 1 - TC/L2 268 */ 269 #define PACKET3_EVENT_WRITE_EOS 0x48 270 #define PACKET3_RELEASE_MEM 0x49 271 #define PACKET3_PREAMBLE_CNTL 0x4A 272 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 273 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 274 #define PACKET3_DMA_DATA 0x50 275 /* 1. header 276 * 2. CONTROL 277 * 3. SRC_ADDR_LO or DATA [31:0] 278 * 4. SRC_ADDR_HI [31:0] 279 * 5. DST_ADDR_LO [31:0] 280 * 6. DST_ADDR_HI [7:0] 281 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 282 */ 283 /* CONTROL */ 284 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 285 /* 0 - ME 286 * 1 - PFP 287 */ 288 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 289 /* 0 - LRU 290 * 1 - Stream 291 * 2 - Bypass 292 */ 293 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 294 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 295 /* 0 - DST_ADDR using DAS 296 * 1 - GDS 297 * 3 - DST_ADDR using L2 298 */ 299 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 300 /* 0 - LRU 301 * 1 - Stream 302 * 2 - Bypass 303 */ 304 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 305 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 306 /* 0 - SRC_ADDR using SAS 307 * 1 - GDS 308 * 2 - DATA 309 * 3 - SRC_ADDR using L2 310 */ 311 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 312 /* COMMAND */ 313 # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 314 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 315 /* 0 - none 316 * 1 - 8 in 16 317 * 2 - 8 in 32 318 * 3 - 8 in 64 319 */ 320 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 321 /* 0 - none 322 * 1 - 8 in 16 323 * 2 - 8 in 32 324 * 3 - 8 in 64 325 */ 326 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 327 /* 0 - memory 328 * 1 - register 329 */ 330 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 331 /* 0 - memory 332 * 1 - register 333 */ 334 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 335 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 336 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 337 #define PACKET3_AQUIRE_MEM 0x58 338 #define PACKET3_REWIND 0x59 339 #define PACKET3_LOAD_UCONFIG_REG 0x5E 340 #define PACKET3_LOAD_SH_REG 0x5F 341 #define PACKET3_LOAD_CONFIG_REG 0x60 342 #define PACKET3_LOAD_CONTEXT_REG 0x61 343 #define PACKET3_SET_CONFIG_REG 0x68 344 #define PACKET3_SET_CONFIG_REG_START 0x00002000 345 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 346 #define PACKET3_SET_CONTEXT_REG 0x69 347 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 348 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 349 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 350 #define PACKET3_SET_SH_REG 0x76 351 #define PACKET3_SET_SH_REG_START 0x00002c00 352 #define PACKET3_SET_SH_REG_END 0x00003000 353 #define PACKET3_SET_SH_REG_OFFSET 0x77 354 #define PACKET3_SET_QUEUE_REG 0x78 355 #define PACKET3_SET_UCONFIG_REG 0x79 356 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 357 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 358 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 359 #define PACKET3_SCRATCH_RAM_READ 0x7E 360 #define PACKET3_LOAD_CONST_RAM 0x80 361 #define PACKET3_WRITE_CONST_RAM 0x81 362 #define PACKET3_DUMP_CONST_RAM 0x83 363 #define PACKET3_INCREMENT_CE_COUNTER 0x84 364 #define PACKET3_INCREMENT_DE_COUNTER 0x85 365 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 366 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 367 #define PACKET3_SWITCH_BUFFER 0x8B 368 #define PACKET3_FRAME_CONTROL 0x90 369 # define FRAME_CMD(x) ((x) << 28) 370 /* 371 * x=0: tmz_begin 372 * x=1: tmz_end 373 */ 374 #define PACKET3_SET_RESOURCES 0xA0 375 /* 1. header 376 * 2. CONTROL 377 * 3. QUEUE_MASK_LO [31:0] 378 * 4. QUEUE_MASK_HI [31:0] 379 * 5. GWS_MASK_LO [31:0] 380 * 6. GWS_MASK_HI [31:0] 381 * 7. OAC_MASK [15:0] 382 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 383 */ 384 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 385 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 386 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 387 #define PACKET3_MAP_QUEUES 0xA2 388 /* 1. header 389 * 2. CONTROL 390 * 3. CONTROL2 391 * 4. MQD_ADDR_LO [31:0] 392 * 5. MQD_ADDR_HI [31:0] 393 * 6. WPTR_ADDR_LO [31:0] 394 * 7. WPTR_ADDR_HI [31:0] 395 */ 396 /* CONTROL */ 397 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 398 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 399 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 400 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 401 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 402 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 403 /* CONTROL2 */ 404 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 405 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 406 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26) 407 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29) 408 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31) 409 #define PACKET3_UNMAP_QUEUES 0xA3 410 /* 1. header 411 * 2. CONTROL 412 * 3. CONTROL2 413 * 4. CONTROL3 414 * 5. CONTROL4 415 * 6. CONTROL5 416 */ 417 /* CONTROL */ 418 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 419 /* 0 - PREEMPT_QUEUES 420 * 1 - RESET_QUEUES 421 * 2 - DISABLE_PROCESS_QUEUES 422 * 3 - PREEMPT_QUEUES_NO_UNMAP 423 */ 424 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 425 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 426 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 427 /* CONTROL2a */ 428 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 429 /* CONTROL2b */ 430 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 431 /* CONTROL3a */ 432 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 433 /* CONTROL3b */ 434 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 435 /* CONTROL4 */ 436 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 437 /* CONTROL5 */ 438 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 439 #define PACKET3_QUERY_STATUS 0xA4 440 /* 1. header 441 * 2. CONTROL 442 * 3. CONTROL2 443 * 4. ADDR_LO [31:0] 444 * 5. ADDR_HI [31:0] 445 * 6. DATA_LO [31:0] 446 * 7. DATA_HI [31:0] 447 */ 448 /* CONTROL */ 449 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 450 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 451 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 452 /* CONTROL2a */ 453 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 454 /* CONTROL2b */ 455 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 456 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 457 458 459 #define VCE_CMD_NO_OP 0x00000000 460 #define VCE_CMD_END 0x00000001 461 #define VCE_CMD_IB 0x00000002 462 #define VCE_CMD_FENCE 0x00000003 463 #define VCE_CMD_TRAP 0x00000004 464 #define VCE_CMD_IB_AUTO 0x00000005 465 #define VCE_CMD_SEMAPHORE 0x00000006 466 467 #define VCE_CMD_IB_VM 0x00000102 468 #define VCE_CMD_WAIT_GE 0x00000106 469 #define VCE_CMD_UPDATE_PTB 0x00000107 470 #define VCE_CMD_FLUSH_TLB 0x00000108 471 472 /* HEVC ENC */ 473 #define HEVC_ENC_CMD_NO_OP 0x00000000 474 #define HEVC_ENC_CMD_END 0x00000001 475 #define HEVC_ENC_CMD_FENCE 0x00000003 476 #define HEVC_ENC_CMD_TRAP 0x00000004 477 #define HEVC_ENC_CMD_IB_VM 0x00000102 478 #define HEVC_ENC_CMD_WAIT_GE 0x00000106 479 #define HEVC_ENC_CMD_UPDATE_PTB 0x00000107 480 #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108 481 482 /* mmPA_SC_RASTER_CONFIG mask */ 483 #define RB_MAP_PKR0(x) ((x) << 0) 484 #define RB_MAP_PKR0_MASK (0x3 << 0) 485 #define RB_MAP_PKR1(x) ((x) << 2) 486 #define RB_MAP_PKR1_MASK (0x3 << 2) 487 #define RB_XSEL2(x) ((x) << 4) 488 #define RB_XSEL2_MASK (0x3 << 4) 489 #define RB_XSEL (1 << 6) 490 #define RB_YSEL (1 << 7) 491 #define PKR_MAP(x) ((x) << 8) 492 #define PKR_MAP_MASK (0x3 << 8) 493 #define PKR_XSEL(x) ((x) << 10) 494 #define PKR_XSEL_MASK (0x3 << 10) 495 #define PKR_YSEL(x) ((x) << 12) 496 #define PKR_YSEL_MASK (0x3 << 12) 497 #define SC_MAP(x) ((x) << 16) 498 #define SC_MAP_MASK (0x3 << 16) 499 #define SC_XSEL(x) ((x) << 18) 500 #define SC_XSEL_MASK (0x3 << 18) 501 #define SC_YSEL(x) ((x) << 20) 502 #define SC_YSEL_MASK (0x3 << 20) 503 #define SE_MAP(x) ((x) << 24) 504 #define SE_MAP_MASK (0x3 << 24) 505 #define SE_XSEL(x) ((x) << 26) 506 #define SE_XSEL_MASK (0x3 << 26) 507 #define SE_YSEL(x) ((x) << 28) 508 #define SE_YSEL_MASK (0x3 << 28) 509 510 /* mmPA_SC_RASTER_CONFIG_1 mask */ 511 #define SE_PAIR_MAP(x) ((x) << 0) 512 #define SE_PAIR_MAP_MASK (0x3 << 0) 513 #define SE_PAIR_XSEL(x) ((x) << 2) 514 #define SE_PAIR_XSEL_MASK (0x3 << 2) 515 #define SE_PAIR_YSEL(x) ((x) << 4) 516 #define SE_PAIR_YSEL_MASK (0x3 << 4) 517 518 #endif 519