1 /* $NetBSD: smu_7_1_1_enum.h,v 1.3 2021/12/18 23:45:23 riastradh Exp $ */ 2 3 /* 4 * SMU_7_1_1 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef SMU_7_1_1_ENUM_H 27 #define SMU_7_1_1_ENUM_H 28 29 #define CG_SRBM_START_ADDR 0x600 30 #define CG_SRBM_END_ADDR 0x8ff 31 #define RCU_CCF_DWORDS0 0x80 32 #define RCU_CCF_BITS0 0x1000 33 #define RCU_CCF_DWORDS1 0x0 34 #define RCU_CCF_BITS1 0x0 35 #define RCU_SAM_BYTES 0x0 36 #define RCU_SAM_RTL_BYTES 0x0 37 #define RCU_SMU_BYTES 0x0 38 #define RCU_SMU_RTL_BYTES 0x0 39 #define SFP_CHAIN_ADDR 0x0 40 #define SFP_BYTES 0x80 41 #define SFP_SADR 0x180 42 #define SFP_EADR 0x1ff 43 #define SAMU_KEY_CHAIN_ADR 0x0 44 #define SAMU_KEY_SADR 0x0 45 #define SAMU_KEY_EADR 0x0 46 #define SMU_KEY_CHAIN_ADR 0x0 47 #define SMU_KEY_SADR 0x0 48 #define SMU_KEY_EADR 0x0 49 #define SMC_MSG_TEST 0x1 50 #define SMC_MSG_PHY_LN_OFF 0x2 51 #define SMC_MSG_PHY_LN_ON 0x3 52 #define SMC_MSG_DDI_PHY_OFF 0x4 53 #define SMC_MSG_DDI_PHY_ON 0x5 54 #define SMC_MSG_CASCADE_PLL_OFF 0x6 55 #define SMC_MSG_CASCADE_PLL_ON 0x7 56 #define SMC_MSG_PWR_OFF_x16 0x8 57 #define SMC_MSG_CONFIG_LCLK_DPM 0x9 58 #define SMC_MSG_FLUSH_DATA_CACHE 0xa 59 #define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb 60 #define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc 61 #define SMC_MSG_CONFIG_BAPM 0xd 62 #define SMC_MSG_CONFIG_TDC_LIMIT 0xe 63 #define SMC_MSG_CONFIG_LPMx 0xf 64 #define SMC_MSG_CONFIG_HTC_LIMIT 0x10 65 #define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 66 #define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 67 #define SMC_MSG_CONFIG_TDP_CNTL 0x13 68 #define SMC_MSG_EN_PM_CNTL 0x14 69 #define SMC_MSG_DIS_PM_CNTL 0x15 70 #define SMC_MSG_CONFIG_NBDPM 0x16 71 #define SMC_MSG_CONFIG_LOADLINE 0x17 72 #define SMC_MSG_ADJUST_LOADLINE 0x18 73 #define SMC_MSG_RESET 0x20 74 #define SMC_MSG_VOLTAGE 0x25 75 #define SMC_VERSION_MAJOR 0x7 76 #define SMC_VERSION_MINOR 0x0 77 #define SMC_HEADER_SIZE 0x40 78 #define ROM_SIGNATURE 0xaa55 79 typedef enum SurfaceEndian { 80 ENDIAN_NONE = 0x0, 81 ENDIAN_8IN16 = 0x1, 82 ENDIAN_8IN32 = 0x2, 83 ENDIAN_8IN64 = 0x3, 84 } SurfaceEndian; 85 typedef enum ArrayMode { 86 ARRAY_LINEAR_GENERAL = 0x0, 87 ARRAY_LINEAR_ALIGNED = 0x1, 88 ARRAY_1D_TILED_THIN1 = 0x2, 89 ARRAY_1D_TILED_THICK = 0x3, 90 ARRAY_2D_TILED_THIN1 = 0x4, 91 ARRAY_PRT_TILED_THIN1 = 0x5, 92 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 93 ARRAY_2D_TILED_THICK = 0x7, 94 ARRAY_2D_TILED_XTHICK = 0x8, 95 ARRAY_PRT_TILED_THICK = 0x9, 96 ARRAY_PRT_2D_TILED_THICK = 0xa, 97 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 98 ARRAY_3D_TILED_THIN1 = 0xc, 99 ARRAY_3D_TILED_THICK = 0xd, 100 ARRAY_3D_TILED_XTHICK = 0xe, 101 ARRAY_PRT_3D_TILED_THICK = 0xf, 102 } ArrayMode; 103 typedef enum PipeTiling { 104 CONFIG_1_PIPE = 0x0, 105 CONFIG_2_PIPE = 0x1, 106 CONFIG_4_PIPE = 0x2, 107 CONFIG_8_PIPE = 0x3, 108 } PipeTiling; 109 typedef enum BankTiling { 110 CONFIG_4_BANK = 0x0, 111 CONFIG_8_BANK = 0x1, 112 } BankTiling; 113 typedef enum GroupInterleave { 114 CONFIG_256B_GROUP = 0x0, 115 CONFIG_512B_GROUP = 0x1, 116 } GroupInterleave; 117 typedef enum RowTiling { 118 CONFIG_1KB_ROW = 0x0, 119 CONFIG_2KB_ROW = 0x1, 120 CONFIG_4KB_ROW = 0x2, 121 CONFIG_8KB_ROW = 0x3, 122 CONFIG_1KB_ROW_OPT = 0x4, 123 CONFIG_2KB_ROW_OPT = 0x5, 124 CONFIG_4KB_ROW_OPT = 0x6, 125 CONFIG_8KB_ROW_OPT = 0x7, 126 } RowTiling; 127 typedef enum BankSwapBytes { 128 CONFIG_128B_SWAPS = 0x0, 129 CONFIG_256B_SWAPS = 0x1, 130 CONFIG_512B_SWAPS = 0x2, 131 CONFIG_1KB_SWAPS = 0x3, 132 } BankSwapBytes; 133 typedef enum SampleSplitBytes { 134 CONFIG_1KB_SPLIT = 0x0, 135 CONFIG_2KB_SPLIT = 0x1, 136 CONFIG_4KB_SPLIT = 0x2, 137 CONFIG_8KB_SPLIT = 0x3, 138 } SampleSplitBytes; 139 typedef enum NumPipes { 140 ADDR_CONFIG_1_PIPE = 0x0, 141 ADDR_CONFIG_2_PIPE = 0x1, 142 ADDR_CONFIG_4_PIPE = 0x2, 143 ADDR_CONFIG_8_PIPE = 0x3, 144 } NumPipes; 145 typedef enum PipeInterleaveSize { 146 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 147 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 148 } PipeInterleaveSize; 149 typedef enum BankInterleaveSize { 150 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 151 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 152 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 153 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 154 } BankInterleaveSize; 155 typedef enum NumShaderEngines { 156 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 157 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 158 } NumShaderEngines; 159 typedef enum ShaderEngineTileSize { 160 ADDR_CONFIG_SE_TILE_16 = 0x0, 161 ADDR_CONFIG_SE_TILE_32 = 0x1, 162 } ShaderEngineTileSize; 163 typedef enum NumGPUs { 164 ADDR_CONFIG_1_GPU = 0x0, 165 ADDR_CONFIG_2_GPU = 0x1, 166 ADDR_CONFIG_4_GPU = 0x2, 167 } NumGPUs; 168 typedef enum MultiGPUTileSize { 169 ADDR_CONFIG_GPU_TILE_16 = 0x0, 170 ADDR_CONFIG_GPU_TILE_32 = 0x1, 171 ADDR_CONFIG_GPU_TILE_64 = 0x2, 172 ADDR_CONFIG_GPU_TILE_128 = 0x3, 173 } MultiGPUTileSize; 174 typedef enum RowSize { 175 ADDR_CONFIG_1KB_ROW = 0x0, 176 ADDR_CONFIG_2KB_ROW = 0x1, 177 ADDR_CONFIG_4KB_ROW = 0x2, 178 } RowSize; 179 typedef enum NumLowerPipes { 180 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 181 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 182 } NumLowerPipes; 183 typedef enum DebugBlockId { 184 DBG_CLIENT_BLKID_RESERVED = 0x0, 185 DBG_CLIENT_BLKID_dbg = 0x1, 186 DBG_CLIENT_BLKID_uvdu_0 = 0x2, 187 DBG_CLIENT_BLKID_uvdu_1 = 0x3, 188 DBG_CLIENT_BLKID_uvdu_2 = 0x4, 189 DBG_CLIENT_BLKID_uvdu_3 = 0x5, 190 DBG_CLIENT_BLKID_uvdu_4 = 0x6, 191 DBG_CLIENT_BLKID_uvdu_5 = 0x7, 192 DBG_CLIENT_BLKID_uvdu_6 = 0x8, 193 DBG_CLIENT_BLKID_uvdb_0 = 0x9, 194 DBG_CLIENT_BLKID_uvdc_0 = 0xa, 195 DBG_CLIENT_BLKID_uvdc_1 = 0xb, 196 DBG_CLIENT_BLKID_uvdf_0 = 0xc, 197 DBG_CLIENT_BLKID_uvdf_1 = 0xd, 198 DBG_CLIENT_BLKID_uvdm_0 = 0xe, 199 DBG_CLIENT_BLKID_uvdm_1 = 0xf, 200 DBG_CLIENT_BLKID_uvdm_2 = 0x10, 201 DBG_CLIENT_BLKID_uvdm_3 = 0x11, 202 DBG_CLIENT_BLKID_vcea_0 = 0x12, 203 DBG_CLIENT_BLKID_vcea_1 = 0x13, 204 DBG_CLIENT_BLKID_vcea_2 = 0x14, 205 DBG_CLIENT_BLKID_vcea_3 = 0x15, 206 DBG_CLIENT_BLKID_vceb_0 = 0x16, 207 DBG_CLIENT_BLKID_vcec_0 = 0x17, 208 DBG_CLIENT_BLKID_dco = 0x18, 209 DBG_CLIENT_BLKID_xdma = 0x19, 210 DBG_CLIENT_BLKID_dci_pg = 0x1a, 211 DBG_CLIENT_BLKID_smu_0 = 0x1b, 212 DBG_CLIENT_BLKID_smu_1 = 0x1c, 213 DBG_CLIENT_BLKID_smu_2 = 0x1d, 214 DBG_CLIENT_BLKID_gck = 0x1e, 215 DBG_CLIENT_BLKID_tmonw0 = 0x1f, 216 DBG_CLIENT_BLKID_tmonw1 = 0x20, 217 DBG_CLIENT_BLKID_grbm = 0x21, 218 DBG_CLIENT_BLKID_rlc = 0x22, 219 DBG_CLIENT_BLKID_ds0 = 0x23, 220 DBG_CLIENT_BLKID_cpg_0 = 0x24, 221 DBG_CLIENT_BLKID_cpg_1 = 0x25, 222 DBG_CLIENT_BLKID_cpc_0 = 0x26, 223 DBG_CLIENT_BLKID_cpc_1 = 0x27, 224 DBG_CLIENT_BLKID_cpf_0 = 0x28, 225 DBG_CLIENT_BLKID_cpf_1 = 0x29, 226 DBG_CLIENT_BLKID_scf0 = 0x2a, 227 DBG_CLIENT_BLKID_scf1 = 0x2b, 228 DBG_CLIENT_BLKID_scf2 = 0x2c, 229 DBG_CLIENT_BLKID_scf3 = 0x2d, 230 DBG_CLIENT_BLKID_pc0 = 0x2e, 231 DBG_CLIENT_BLKID_pc1 = 0x2f, 232 DBG_CLIENT_BLKID_pc2 = 0x30, 233 DBG_CLIENT_BLKID_pc3 = 0x31, 234 DBG_CLIENT_BLKID_vgt0 = 0x32, 235 DBG_CLIENT_BLKID_vgt1 = 0x33, 236 DBG_CLIENT_BLKID_vgt2 = 0x34, 237 DBG_CLIENT_BLKID_vgt3 = 0x35, 238 DBG_CLIENT_BLKID_sx00 = 0x36, 239 DBG_CLIENT_BLKID_sx10 = 0x37, 240 DBG_CLIENT_BLKID_sx20 = 0x38, 241 DBG_CLIENT_BLKID_sx30 = 0x39, 242 DBG_CLIENT_BLKID_cb001 = 0x3a, 243 DBG_CLIENT_BLKID_cb200 = 0x3b, 244 DBG_CLIENT_BLKID_cb201 = 0x3c, 245 DBG_CLIENT_BLKID_cbr0 = 0x3d, 246 DBG_CLIENT_BLKID_cb000 = 0x3e, 247 DBG_CLIENT_BLKID_cb101 = 0x3f, 248 DBG_CLIENT_BLKID_cb300 = 0x40, 249 DBG_CLIENT_BLKID_cb301 = 0x41, 250 DBG_CLIENT_BLKID_cbr1 = 0x42, 251 DBG_CLIENT_BLKID_cb100 = 0x43, 252 DBG_CLIENT_BLKID_ia0 = 0x44, 253 DBG_CLIENT_BLKID_ia1 = 0x45, 254 DBG_CLIENT_BLKID_bci0 = 0x46, 255 DBG_CLIENT_BLKID_bci1 = 0x47, 256 DBG_CLIENT_BLKID_bci2 = 0x48, 257 DBG_CLIENT_BLKID_bci3 = 0x49, 258 DBG_CLIENT_BLKID_pa0 = 0x4a, 259 DBG_CLIENT_BLKID_pa1 = 0x4b, 260 DBG_CLIENT_BLKID_spim0 = 0x4c, 261 DBG_CLIENT_BLKID_spim1 = 0x4d, 262 DBG_CLIENT_BLKID_spim2 = 0x4e, 263 DBG_CLIENT_BLKID_spim3 = 0x4f, 264 DBG_CLIENT_BLKID_sdma = 0x50, 265 DBG_CLIENT_BLKID_ih = 0x51, 266 DBG_CLIENT_BLKID_sem = 0x52, 267 DBG_CLIENT_BLKID_srbm = 0x53, 268 DBG_CLIENT_BLKID_hdp = 0x54, 269 DBG_CLIENT_BLKID_acp_0 = 0x55, 270 DBG_CLIENT_BLKID_acp_1 = 0x56, 271 DBG_CLIENT_BLKID_sam = 0x57, 272 DBG_CLIENT_BLKID_mcc0 = 0x58, 273 DBG_CLIENT_BLKID_mcc1 = 0x59, 274 DBG_CLIENT_BLKID_mcc2 = 0x5a, 275 DBG_CLIENT_BLKID_mcc3 = 0x5b, 276 DBG_CLIENT_BLKID_mcd0 = 0x5c, 277 DBG_CLIENT_BLKID_mcd1 = 0x5d, 278 DBG_CLIENT_BLKID_mcd2 = 0x5e, 279 DBG_CLIENT_BLKID_mcd3 = 0x5f, 280 DBG_CLIENT_BLKID_mcb = 0x60, 281 DBG_CLIENT_BLKID_vmc = 0x61, 282 DBG_CLIENT_BLKID_gmcon = 0x62, 283 DBG_CLIENT_BLKID_gdc_0 = 0x63, 284 DBG_CLIENT_BLKID_gdc_1 = 0x64, 285 DBG_CLIENT_BLKID_gdc_2 = 0x65, 286 DBG_CLIENT_BLKID_gdc_3 = 0x66, 287 DBG_CLIENT_BLKID_gdc_4 = 0x67, 288 DBG_CLIENT_BLKID_gdc_5 = 0x68, 289 DBG_CLIENT_BLKID_gdc_6 = 0x69, 290 DBG_CLIENT_BLKID_gdc_7 = 0x6a, 291 DBG_CLIENT_BLKID_gdc_8 = 0x6b, 292 DBG_CLIENT_BLKID_gdc_9 = 0x6c, 293 DBG_CLIENT_BLKID_gdc_10 = 0x6d, 294 DBG_CLIENT_BLKID_gdc_11 = 0x6e, 295 DBG_CLIENT_BLKID_gdc_12 = 0x6f, 296 DBG_CLIENT_BLKID_gdc_13 = 0x70, 297 DBG_CLIENT_BLKID_gdc_14 = 0x71, 298 DBG_CLIENT_BLKID_gdc_15 = 0x72, 299 DBG_CLIENT_BLKID_gdc_16 = 0x73, 300 DBG_CLIENT_BLKID_gdc_17 = 0x74, 301 DBG_CLIENT_BLKID_gdc_18 = 0x75, 302 DBG_CLIENT_BLKID_gdc_19 = 0x76, 303 DBG_CLIENT_BLKID_gdc_20 = 0x77, 304 DBG_CLIENT_BLKID_gdc_21 = 0x78, 305 DBG_CLIENT_BLKID_gdc_22 = 0x79, 306 DBG_CLIENT_BLKID_gdc_23 = 0x7a, 307 DBG_CLIENT_BLKID_gdc_24 = 0x7b, 308 DBG_CLIENT_BLKID_gdc_25 = 0x7c, 309 DBG_CLIENT_BLKID_gdc_26 = 0x7d, 310 DBG_CLIENT_BLKID_gdc_27 = 0x7e, 311 DBG_CLIENT_BLKID_gdc_28 = 0x7f, 312 DBG_CLIENT_BLKID_wd = 0x80, 313 DBG_CLIENT_BLKID_sdma_0 = 0x81, 314 DBG_CLIENT_BLKID_sdma_1 = 0x82, 315 DBG_CLIENT_BLKID_sammsp = 0x83, 316 DBG_CLIENT_BLKID_dci_0 = 0x84, 317 DBG_CLIENT_BLKID_dccg0_0 = 0x85, 318 DBG_CLIENT_BLKID_dcfe01_0 = 0x86, 319 DBG_CLIENT_BLKID_dcfe02_0 = 0x87, 320 DBG_CLIENT_BLKID_dcfe03_0 = 0x88, 321 DBG_CLIENT_BLKID_dccg0_1 = 0x89, 322 } DebugBlockId; 323 typedef enum DebugBlockId_OLD { 324 DBG_BLOCK_ID_RESERVED = 0x0, 325 DBG_BLOCK_ID_DBG = 0x1, 326 DBG_BLOCK_ID_VMC = 0x2, 327 DBG_BLOCK_ID_PDMA = 0x3, 328 DBG_BLOCK_ID_CG = 0x4, 329 DBG_BLOCK_ID_SRBM = 0x5, 330 DBG_BLOCK_ID_GRBM = 0x6, 331 DBG_BLOCK_ID_RLC = 0x7, 332 DBG_BLOCK_ID_CSC = 0x8, 333 DBG_BLOCK_ID_SEM = 0x9, 334 DBG_BLOCK_ID_IH = 0xa, 335 DBG_BLOCK_ID_SC = 0xb, 336 DBG_BLOCK_ID_SQ = 0xc, 337 DBG_BLOCK_ID_AVP = 0xd, 338 DBG_BLOCK_ID_GMCON = 0xe, 339 DBG_BLOCK_ID_SMU = 0xf, 340 DBG_BLOCK_ID_DMA0 = 0x10, 341 DBG_BLOCK_ID_DMA1 = 0x11, 342 DBG_BLOCK_ID_SPIM = 0x12, 343 DBG_BLOCK_ID_GDS = 0x13, 344 DBG_BLOCK_ID_SPIS = 0x14, 345 DBG_BLOCK_ID_UNUSED0 = 0x15, 346 DBG_BLOCK_ID_PA0 = 0x16, 347 DBG_BLOCK_ID_PA1 = 0x17, 348 DBG_BLOCK_ID_CP0 = 0x18, 349 DBG_BLOCK_ID_CP1 = 0x19, 350 DBG_BLOCK_ID_CP2 = 0x1a, 351 DBG_BLOCK_ID_UNUSED1 = 0x1b, 352 DBG_BLOCK_ID_UVDU = 0x1c, 353 DBG_BLOCK_ID_UVDM = 0x1d, 354 DBG_BLOCK_ID_VCE = 0x1e, 355 DBG_BLOCK_ID_UNUSED2 = 0x1f, 356 DBG_BLOCK_ID_VGT0 = 0x20, 357 DBG_BLOCK_ID_VGT1 = 0x21, 358 DBG_BLOCK_ID_IA = 0x22, 359 DBG_BLOCK_ID_UNUSED3 = 0x23, 360 DBG_BLOCK_ID_SCT0 = 0x24, 361 DBG_BLOCK_ID_SCT1 = 0x25, 362 DBG_BLOCK_ID_SPM0 = 0x26, 363 DBG_BLOCK_ID_SPM1 = 0x27, 364 DBG_BLOCK_ID_TCAA = 0x28, 365 DBG_BLOCK_ID_TCAB = 0x29, 366 DBG_BLOCK_ID_TCCA = 0x2a, 367 DBG_BLOCK_ID_TCCB = 0x2b, 368 DBG_BLOCK_ID_MCC0 = 0x2c, 369 DBG_BLOCK_ID_MCC1 = 0x2d, 370 DBG_BLOCK_ID_MCC2 = 0x2e, 371 DBG_BLOCK_ID_MCC3 = 0x2f, 372 DBG_BLOCK_ID_SX0 = 0x30, 373 DBG_BLOCK_ID_SX1 = 0x31, 374 DBG_BLOCK_ID_SX2 = 0x32, 375 DBG_BLOCK_ID_SX3 = 0x33, 376 DBG_BLOCK_ID_UNUSED4 = 0x34, 377 DBG_BLOCK_ID_UNUSED5 = 0x35, 378 DBG_BLOCK_ID_UNUSED6 = 0x36, 379 DBG_BLOCK_ID_UNUSED7 = 0x37, 380 DBG_BLOCK_ID_PC0 = 0x38, 381 DBG_BLOCK_ID_PC1 = 0x39, 382 DBG_BLOCK_ID_UNUSED8 = 0x3a, 383 DBG_BLOCK_ID_UNUSED9 = 0x3b, 384 DBG_BLOCK_ID_UNUSED10 = 0x3c, 385 DBG_BLOCK_ID_UNUSED11 = 0x3d, 386 DBG_BLOCK_ID_MCB = 0x3e, 387 DBG_BLOCK_ID_UNUSED12 = 0x3f, 388 DBG_BLOCK_ID_SCB0 = 0x40, 389 DBG_BLOCK_ID_SCB1 = 0x41, 390 DBG_BLOCK_ID_UNUSED13 = 0x42, 391 DBG_BLOCK_ID_UNUSED14 = 0x43, 392 DBG_BLOCK_ID_SCF0 = 0x44, 393 DBG_BLOCK_ID_SCF1 = 0x45, 394 DBG_BLOCK_ID_UNUSED15 = 0x46, 395 DBG_BLOCK_ID_UNUSED16 = 0x47, 396 DBG_BLOCK_ID_BCI0 = 0x48, 397 DBG_BLOCK_ID_BCI1 = 0x49, 398 DBG_BLOCK_ID_BCI2 = 0x4a, 399 DBG_BLOCK_ID_BCI3 = 0x4b, 400 DBG_BLOCK_ID_UNUSED17 = 0x4c, 401 DBG_BLOCK_ID_UNUSED18 = 0x4d, 402 DBG_BLOCK_ID_UNUSED19 = 0x4e, 403 DBG_BLOCK_ID_UNUSED20 = 0x4f, 404 DBG_BLOCK_ID_CB00 = 0x50, 405 DBG_BLOCK_ID_CB01 = 0x51, 406 DBG_BLOCK_ID_CB02 = 0x52, 407 DBG_BLOCK_ID_CB03 = 0x53, 408 DBG_BLOCK_ID_CB04 = 0x54, 409 DBG_BLOCK_ID_UNUSED21 = 0x55, 410 DBG_BLOCK_ID_UNUSED22 = 0x56, 411 DBG_BLOCK_ID_UNUSED23 = 0x57, 412 DBG_BLOCK_ID_CB10 = 0x58, 413 DBG_BLOCK_ID_CB11 = 0x59, 414 DBG_BLOCK_ID_CB12 = 0x5a, 415 DBG_BLOCK_ID_CB13 = 0x5b, 416 DBG_BLOCK_ID_CB14 = 0x5c, 417 DBG_BLOCK_ID_UNUSED24 = 0x5d, 418 DBG_BLOCK_ID_UNUSED25 = 0x5e, 419 DBG_BLOCK_ID_UNUSED26 = 0x5f, 420 DBG_BLOCK_ID_TCP0 = 0x60, 421 DBG_BLOCK_ID_TCP1 = 0x61, 422 DBG_BLOCK_ID_TCP2 = 0x62, 423 DBG_BLOCK_ID_TCP3 = 0x63, 424 DBG_BLOCK_ID_TCP4 = 0x64, 425 DBG_BLOCK_ID_TCP5 = 0x65, 426 DBG_BLOCK_ID_TCP6 = 0x66, 427 DBG_BLOCK_ID_TCP7 = 0x67, 428 DBG_BLOCK_ID_TCP8 = 0x68, 429 DBG_BLOCK_ID_TCP9 = 0x69, 430 DBG_BLOCK_ID_TCP10 = 0x6a, 431 DBG_BLOCK_ID_TCP11 = 0x6b, 432 DBG_BLOCK_ID_TCP12 = 0x6c, 433 DBG_BLOCK_ID_TCP13 = 0x6d, 434 DBG_BLOCK_ID_TCP14 = 0x6e, 435 DBG_BLOCK_ID_TCP15 = 0x6f, 436 DBG_BLOCK_ID_TCP16 = 0x70, 437 DBG_BLOCK_ID_TCP17 = 0x71, 438 DBG_BLOCK_ID_TCP18 = 0x72, 439 DBG_BLOCK_ID_TCP19 = 0x73, 440 DBG_BLOCK_ID_TCP20 = 0x74, 441 DBG_BLOCK_ID_TCP21 = 0x75, 442 DBG_BLOCK_ID_TCP22 = 0x76, 443 DBG_BLOCK_ID_TCP23 = 0x77, 444 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 445 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 446 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 447 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 448 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 449 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 450 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 451 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 452 DBG_BLOCK_ID_DB00 = 0x80, 453 DBG_BLOCK_ID_DB01 = 0x81, 454 DBG_BLOCK_ID_DB02 = 0x82, 455 DBG_BLOCK_ID_DB03 = 0x83, 456 DBG_BLOCK_ID_DB04 = 0x84, 457 DBG_BLOCK_ID_UNUSED27 = 0x85, 458 DBG_BLOCK_ID_UNUSED28 = 0x86, 459 DBG_BLOCK_ID_UNUSED29 = 0x87, 460 DBG_BLOCK_ID_DB10 = 0x88, 461 DBG_BLOCK_ID_DB11 = 0x89, 462 DBG_BLOCK_ID_DB12 = 0x8a, 463 DBG_BLOCK_ID_DB13 = 0x8b, 464 DBG_BLOCK_ID_DB14 = 0x8c, 465 DBG_BLOCK_ID_UNUSED30 = 0x8d, 466 DBG_BLOCK_ID_UNUSED31 = 0x8e, 467 DBG_BLOCK_ID_UNUSED32 = 0x8f, 468 DBG_BLOCK_ID_TCC0 = 0x90, 469 DBG_BLOCK_ID_TCC1 = 0x91, 470 DBG_BLOCK_ID_TCC2 = 0x92, 471 DBG_BLOCK_ID_TCC3 = 0x93, 472 DBG_BLOCK_ID_TCC4 = 0x94, 473 DBG_BLOCK_ID_TCC5 = 0x95, 474 DBG_BLOCK_ID_TCC6 = 0x96, 475 DBG_BLOCK_ID_TCC7 = 0x97, 476 DBG_BLOCK_ID_SPS00 = 0x98, 477 DBG_BLOCK_ID_SPS01 = 0x99, 478 DBG_BLOCK_ID_SPS02 = 0x9a, 479 DBG_BLOCK_ID_SPS10 = 0x9b, 480 DBG_BLOCK_ID_SPS11 = 0x9c, 481 DBG_BLOCK_ID_SPS12 = 0x9d, 482 DBG_BLOCK_ID_UNUSED33 = 0x9e, 483 DBG_BLOCK_ID_UNUSED34 = 0x9f, 484 DBG_BLOCK_ID_TA00 = 0xa0, 485 DBG_BLOCK_ID_TA01 = 0xa1, 486 DBG_BLOCK_ID_TA02 = 0xa2, 487 DBG_BLOCK_ID_TA03 = 0xa3, 488 DBG_BLOCK_ID_TA04 = 0xa4, 489 DBG_BLOCK_ID_TA05 = 0xa5, 490 DBG_BLOCK_ID_TA06 = 0xa6, 491 DBG_BLOCK_ID_TA07 = 0xa7, 492 DBG_BLOCK_ID_TA08 = 0xa8, 493 DBG_BLOCK_ID_TA09 = 0xa9, 494 DBG_BLOCK_ID_TA0A = 0xaa, 495 DBG_BLOCK_ID_TA0B = 0xab, 496 DBG_BLOCK_ID_UNUSED35 = 0xac, 497 DBG_BLOCK_ID_UNUSED36 = 0xad, 498 DBG_BLOCK_ID_UNUSED37 = 0xae, 499 DBG_BLOCK_ID_UNUSED38 = 0xaf, 500 DBG_BLOCK_ID_TA10 = 0xb0, 501 DBG_BLOCK_ID_TA11 = 0xb1, 502 DBG_BLOCK_ID_TA12 = 0xb2, 503 DBG_BLOCK_ID_TA13 = 0xb3, 504 DBG_BLOCK_ID_TA14 = 0xb4, 505 DBG_BLOCK_ID_TA15 = 0xb5, 506 DBG_BLOCK_ID_TA16 = 0xb6, 507 DBG_BLOCK_ID_TA17 = 0xb7, 508 DBG_BLOCK_ID_TA18 = 0xb8, 509 DBG_BLOCK_ID_TA19 = 0xb9, 510 DBG_BLOCK_ID_TA1A = 0xba, 511 DBG_BLOCK_ID_TA1B = 0xbb, 512 DBG_BLOCK_ID_UNUSED39 = 0xbc, 513 DBG_BLOCK_ID_UNUSED40 = 0xbd, 514 DBG_BLOCK_ID_UNUSED41 = 0xbe, 515 DBG_BLOCK_ID_UNUSED42 = 0xbf, 516 DBG_BLOCK_ID_TD00 = 0xc0, 517 DBG_BLOCK_ID_TD01 = 0xc1, 518 DBG_BLOCK_ID_TD02 = 0xc2, 519 DBG_BLOCK_ID_TD03 = 0xc3, 520 DBG_BLOCK_ID_TD04 = 0xc4, 521 DBG_BLOCK_ID_TD05 = 0xc5, 522 DBG_BLOCK_ID_TD06 = 0xc6, 523 DBG_BLOCK_ID_TD07 = 0xc7, 524 DBG_BLOCK_ID_TD08 = 0xc8, 525 DBG_BLOCK_ID_TD09 = 0xc9, 526 DBG_BLOCK_ID_TD0A = 0xca, 527 DBG_BLOCK_ID_TD0B = 0xcb, 528 DBG_BLOCK_ID_UNUSED43 = 0xcc, 529 DBG_BLOCK_ID_UNUSED44 = 0xcd, 530 DBG_BLOCK_ID_UNUSED45 = 0xce, 531 DBG_BLOCK_ID_UNUSED46 = 0xcf, 532 DBG_BLOCK_ID_TD10 = 0xd0, 533 DBG_BLOCK_ID_TD11 = 0xd1, 534 DBG_BLOCK_ID_TD12 = 0xd2, 535 DBG_BLOCK_ID_TD13 = 0xd3, 536 DBG_BLOCK_ID_TD14 = 0xd4, 537 DBG_BLOCK_ID_TD15 = 0xd5, 538 DBG_BLOCK_ID_TD16 = 0xd6, 539 DBG_BLOCK_ID_TD17 = 0xd7, 540 DBG_BLOCK_ID_TD18 = 0xd8, 541 DBG_BLOCK_ID_TD19 = 0xd9, 542 DBG_BLOCK_ID_TD1A = 0xda, 543 DBG_BLOCK_ID_TD1B = 0xdb, 544 DBG_BLOCK_ID_UNUSED47 = 0xdc, 545 DBG_BLOCK_ID_UNUSED48 = 0xdd, 546 DBG_BLOCK_ID_UNUSED49 = 0xde, 547 DBG_BLOCK_ID_UNUSED50 = 0xdf, 548 DBG_BLOCK_ID_MCD0 = 0xe0, 549 DBG_BLOCK_ID_MCD1 = 0xe1, 550 DBG_BLOCK_ID_MCD2 = 0xe2, 551 DBG_BLOCK_ID_MCD3 = 0xe3, 552 DBG_BLOCK_ID_MCD4 = 0xe4, 553 DBG_BLOCK_ID_MCD5 = 0xe5, 554 DBG_BLOCK_ID_UNUSED51 = 0xe6, 555 DBG_BLOCK_ID_UNUSED52 = 0xe7, 556 } DebugBlockId_OLD; 557 typedef enum DebugBlockId_BY2 { 558 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 559 DBG_BLOCK_ID_VMC_BY2 = 0x1, 560 DBG_BLOCK_ID_CG_BY2 = 0x2, 561 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 562 DBG_BLOCK_ID_CSC_BY2 = 0x4, 563 DBG_BLOCK_ID_IH_BY2 = 0x5, 564 DBG_BLOCK_ID_SQ_BY2 = 0x6, 565 DBG_BLOCK_ID_GMCON_BY2 = 0x7, 566 DBG_BLOCK_ID_DMA0_BY2 = 0x8, 567 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 568 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 569 DBG_BLOCK_ID_PA0_BY2 = 0xb, 570 DBG_BLOCK_ID_CP0_BY2 = 0xc, 571 DBG_BLOCK_ID_CP2_BY2 = 0xd, 572 DBG_BLOCK_ID_UVDU_BY2 = 0xe, 573 DBG_BLOCK_ID_VCE_BY2 = 0xf, 574 DBG_BLOCK_ID_VGT0_BY2 = 0x10, 575 DBG_BLOCK_ID_IA_BY2 = 0x11, 576 DBG_BLOCK_ID_SCT0_BY2 = 0x12, 577 DBG_BLOCK_ID_SPM0_BY2 = 0x13, 578 DBG_BLOCK_ID_TCAA_BY2 = 0x14, 579 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 580 DBG_BLOCK_ID_MCC0_BY2 = 0x16, 581 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 582 DBG_BLOCK_ID_SX0_BY2 = 0x18, 583 DBG_BLOCK_ID_SX2_BY2 = 0x19, 584 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 585 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 586 DBG_BLOCK_ID_PC0_BY2 = 0x1c, 587 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 588 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 589 DBG_BLOCK_ID_MCB_BY2 = 0x1f, 590 DBG_BLOCK_ID_SCB0_BY2 = 0x20, 591 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 592 DBG_BLOCK_ID_SCF0_BY2 = 0x22, 593 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 594 DBG_BLOCK_ID_BCI0_BY2 = 0x24, 595 DBG_BLOCK_ID_BCI2_BY2 = 0x25, 596 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 597 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 598 DBG_BLOCK_ID_CB00_BY2 = 0x28, 599 DBG_BLOCK_ID_CB02_BY2 = 0x29, 600 DBG_BLOCK_ID_CB04_BY2 = 0x2a, 601 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 602 DBG_BLOCK_ID_CB10_BY2 = 0x2c, 603 DBG_BLOCK_ID_CB12_BY2 = 0x2d, 604 DBG_BLOCK_ID_CB14_BY2 = 0x2e, 605 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 606 DBG_BLOCK_ID_TCP0_BY2 = 0x30, 607 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 608 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 609 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 610 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 611 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 612 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 613 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 614 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 615 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 616 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 617 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 618 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 619 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 620 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 621 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 622 DBG_BLOCK_ID_DB00_BY2 = 0x40, 623 DBG_BLOCK_ID_DB02_BY2 = 0x41, 624 DBG_BLOCK_ID_DB04_BY2 = 0x42, 625 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 626 DBG_BLOCK_ID_DB10_BY2 = 0x44, 627 DBG_BLOCK_ID_DB12_BY2 = 0x45, 628 DBG_BLOCK_ID_DB14_BY2 = 0x46, 629 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 630 DBG_BLOCK_ID_TCC0_BY2 = 0x48, 631 DBG_BLOCK_ID_TCC2_BY2 = 0x49, 632 DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 633 DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 634 DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 635 DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 636 DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 637 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 638 DBG_BLOCK_ID_TA00_BY2 = 0x50, 639 DBG_BLOCK_ID_TA02_BY2 = 0x51, 640 DBG_BLOCK_ID_TA04_BY2 = 0x52, 641 DBG_BLOCK_ID_TA06_BY2 = 0x53, 642 DBG_BLOCK_ID_TA08_BY2 = 0x54, 643 DBG_BLOCK_ID_TA0A_BY2 = 0x55, 644 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 645 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 646 DBG_BLOCK_ID_TA10_BY2 = 0x58, 647 DBG_BLOCK_ID_TA12_BY2 = 0x59, 648 DBG_BLOCK_ID_TA14_BY2 = 0x5a, 649 DBG_BLOCK_ID_TA16_BY2 = 0x5b, 650 DBG_BLOCK_ID_TA18_BY2 = 0x5c, 651 DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 652 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 653 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 654 DBG_BLOCK_ID_TD00_BY2 = 0x60, 655 DBG_BLOCK_ID_TD02_BY2 = 0x61, 656 DBG_BLOCK_ID_TD04_BY2 = 0x62, 657 DBG_BLOCK_ID_TD06_BY2 = 0x63, 658 DBG_BLOCK_ID_TD08_BY2 = 0x64, 659 DBG_BLOCK_ID_TD0A_BY2 = 0x65, 660 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 661 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 662 DBG_BLOCK_ID_TD10_BY2 = 0x68, 663 DBG_BLOCK_ID_TD12_BY2 = 0x69, 664 DBG_BLOCK_ID_TD14_BY2 = 0x6a, 665 DBG_BLOCK_ID_TD16_BY2 = 0x6b, 666 DBG_BLOCK_ID_TD18_BY2 = 0x6c, 667 DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 668 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 669 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 670 DBG_BLOCK_ID_MCD0_BY2 = 0x70, 671 DBG_BLOCK_ID_MCD2_BY2 = 0x71, 672 DBG_BLOCK_ID_MCD4_BY2 = 0x72, 673 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 674 } DebugBlockId_BY2; 675 typedef enum DebugBlockId_BY4 { 676 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 677 DBG_BLOCK_ID_CG_BY4 = 0x1, 678 DBG_BLOCK_ID_CSC_BY4 = 0x2, 679 DBG_BLOCK_ID_SQ_BY4 = 0x3, 680 DBG_BLOCK_ID_DMA0_BY4 = 0x4, 681 DBG_BLOCK_ID_SPIS_BY4 = 0x5, 682 DBG_BLOCK_ID_CP0_BY4 = 0x6, 683 DBG_BLOCK_ID_UVDU_BY4 = 0x7, 684 DBG_BLOCK_ID_VGT0_BY4 = 0x8, 685 DBG_BLOCK_ID_SCT0_BY4 = 0x9, 686 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 687 DBG_BLOCK_ID_MCC0_BY4 = 0xb, 688 DBG_BLOCK_ID_SX0_BY4 = 0xc, 689 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 690 DBG_BLOCK_ID_PC0_BY4 = 0xe, 691 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 692 DBG_BLOCK_ID_SCB0_BY4 = 0x10, 693 DBG_BLOCK_ID_SCF0_BY4 = 0x11, 694 DBG_BLOCK_ID_BCI0_BY4 = 0x12, 695 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 696 DBG_BLOCK_ID_CB00_BY4 = 0x14, 697 DBG_BLOCK_ID_CB04_BY4 = 0x15, 698 DBG_BLOCK_ID_CB10_BY4 = 0x16, 699 DBG_BLOCK_ID_CB14_BY4 = 0x17, 700 DBG_BLOCK_ID_TCP0_BY4 = 0x18, 701 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 702 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 703 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 704 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 705 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 706 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 707 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 708 DBG_BLOCK_ID_DB_BY4 = 0x20, 709 DBG_BLOCK_ID_DB04_BY4 = 0x21, 710 DBG_BLOCK_ID_DB10_BY4 = 0x22, 711 DBG_BLOCK_ID_DB14_BY4 = 0x23, 712 DBG_BLOCK_ID_TCC0_BY4 = 0x24, 713 DBG_BLOCK_ID_TCC4_BY4 = 0x25, 714 DBG_BLOCK_ID_SPS00_BY4 = 0x26, 715 DBG_BLOCK_ID_SPS11_BY4 = 0x27, 716 DBG_BLOCK_ID_TA00_BY4 = 0x28, 717 DBG_BLOCK_ID_TA04_BY4 = 0x29, 718 DBG_BLOCK_ID_TA08_BY4 = 0x2a, 719 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 720 DBG_BLOCK_ID_TA10_BY4 = 0x2c, 721 DBG_BLOCK_ID_TA14_BY4 = 0x2d, 722 DBG_BLOCK_ID_TA18_BY4 = 0x2e, 723 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 724 DBG_BLOCK_ID_TD00_BY4 = 0x30, 725 DBG_BLOCK_ID_TD04_BY4 = 0x31, 726 DBG_BLOCK_ID_TD08_BY4 = 0x32, 727 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 728 DBG_BLOCK_ID_TD10_BY4 = 0x34, 729 DBG_BLOCK_ID_TD14_BY4 = 0x35, 730 DBG_BLOCK_ID_TD18_BY4 = 0x36, 731 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 732 DBG_BLOCK_ID_MCD0_BY4 = 0x38, 733 DBG_BLOCK_ID_MCD4_BY4 = 0x39, 734 } DebugBlockId_BY4; 735 typedef enum DebugBlockId_BY8 { 736 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 737 DBG_BLOCK_ID_CSC_BY8 = 0x1, 738 DBG_BLOCK_ID_DMA0_BY8 = 0x2, 739 DBG_BLOCK_ID_CP0_BY8 = 0x3, 740 DBG_BLOCK_ID_VGT0_BY8 = 0x4, 741 DBG_BLOCK_ID_TCAA_BY8 = 0x5, 742 DBG_BLOCK_ID_SX0_BY8 = 0x6, 743 DBG_BLOCK_ID_PC0_BY8 = 0x7, 744 DBG_BLOCK_ID_SCB0_BY8 = 0x8, 745 DBG_BLOCK_ID_BCI0_BY8 = 0x9, 746 DBG_BLOCK_ID_CB00_BY8 = 0xa, 747 DBG_BLOCK_ID_CB10_BY8 = 0xb, 748 DBG_BLOCK_ID_TCP0_BY8 = 0xc, 749 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 750 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 751 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 752 DBG_BLOCK_ID_DB00_BY8 = 0x10, 753 DBG_BLOCK_ID_DB10_BY8 = 0x11, 754 DBG_BLOCK_ID_TCC0_BY8 = 0x12, 755 DBG_BLOCK_ID_SPS00_BY8 = 0x13, 756 DBG_BLOCK_ID_TA00_BY8 = 0x14, 757 DBG_BLOCK_ID_TA08_BY8 = 0x15, 758 DBG_BLOCK_ID_TA10_BY8 = 0x16, 759 DBG_BLOCK_ID_TA18_BY8 = 0x17, 760 DBG_BLOCK_ID_TD00_BY8 = 0x18, 761 DBG_BLOCK_ID_TD08_BY8 = 0x19, 762 DBG_BLOCK_ID_TD10_BY8 = 0x1a, 763 DBG_BLOCK_ID_TD18_BY8 = 0x1b, 764 DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 765 } DebugBlockId_BY8; 766 typedef enum DebugBlockId_BY16 { 767 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 768 DBG_BLOCK_ID_DMA0_BY16 = 0x1, 769 DBG_BLOCK_ID_VGT0_BY16 = 0x2, 770 DBG_BLOCK_ID_SX0_BY16 = 0x3, 771 DBG_BLOCK_ID_SCB0_BY16 = 0x4, 772 DBG_BLOCK_ID_CB00_BY16 = 0x5, 773 DBG_BLOCK_ID_TCP0_BY16 = 0x6, 774 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 775 DBG_BLOCK_ID_DB00_BY16 = 0x8, 776 DBG_BLOCK_ID_TCC0_BY16 = 0x9, 777 DBG_BLOCK_ID_TA00_BY16 = 0xa, 778 DBG_BLOCK_ID_TA10_BY16 = 0xb, 779 DBG_BLOCK_ID_TD00_BY16 = 0xc, 780 DBG_BLOCK_ID_TD10_BY16 = 0xd, 781 DBG_BLOCK_ID_MCD0_BY16 = 0xe, 782 } DebugBlockId_BY16; 783 typedef enum ColorTransform { 784 DCC_CT_AUTO = 0x0, 785 DCC_CT_NONE = 0x1, 786 ABGR_TO_A_BG_G_RB = 0x2, 787 BGRA_TO_BG_G_RB_A = 0x3, 788 } ColorTransform; 789 typedef enum CompareRef { 790 REF_NEVER = 0x0, 791 REF_LESS = 0x1, 792 REF_EQUAL = 0x2, 793 REF_LEQUAL = 0x3, 794 REF_GREATER = 0x4, 795 REF_NOTEQUAL = 0x5, 796 REF_GEQUAL = 0x6, 797 REF_ALWAYS = 0x7, 798 } CompareRef; 799 typedef enum ReadSize { 800 READ_256_BITS = 0x0, 801 READ_512_BITS = 0x1, 802 } ReadSize; 803 typedef enum DepthFormat { 804 DEPTH_INVALID = 0x0, 805 DEPTH_16 = 0x1, 806 DEPTH_X8_24 = 0x2, 807 DEPTH_8_24 = 0x3, 808 DEPTH_X8_24_FLOAT = 0x4, 809 DEPTH_8_24_FLOAT = 0x5, 810 DEPTH_32_FLOAT = 0x6, 811 DEPTH_X24_8_32_FLOAT = 0x7, 812 } DepthFormat; 813 typedef enum ZFormat { 814 Z_INVALID = 0x0, 815 Z_16 = 0x1, 816 Z_24 = 0x2, 817 Z_32_FLOAT = 0x3, 818 } ZFormat; 819 typedef enum StencilFormat { 820 STENCIL_INVALID = 0x0, 821 STENCIL_8 = 0x1, 822 } StencilFormat; 823 typedef enum CmaskMode { 824 CMASK_CLEAR_NONE = 0x0, 825 CMASK_CLEAR_ONE = 0x1, 826 CMASK_CLEAR_ALL = 0x2, 827 CMASK_ANY_EXPANDED = 0x3, 828 CMASK_ALPHA0_FRAG1 = 0x4, 829 CMASK_ALPHA0_FRAG2 = 0x5, 830 CMASK_ALPHA0_FRAG4 = 0x6, 831 CMASK_ALPHA0_FRAGS = 0x7, 832 CMASK_ALPHA1_FRAG1 = 0x8, 833 CMASK_ALPHA1_FRAG2 = 0x9, 834 CMASK_ALPHA1_FRAG4 = 0xa, 835 CMASK_ALPHA1_FRAGS = 0xb, 836 CMASK_ALPHAX_FRAG1 = 0xc, 837 CMASK_ALPHAX_FRAG2 = 0xd, 838 CMASK_ALPHAX_FRAG4 = 0xe, 839 CMASK_ALPHAX_FRAGS = 0xf, 840 } CmaskMode; 841 typedef enum QuadExportFormat { 842 EXPORT_UNUSED = 0x0, 843 EXPORT_32_R = 0x1, 844 EXPORT_32_GR = 0x2, 845 EXPORT_32_AR = 0x3, 846 EXPORT_FP16_ABGR = 0x4, 847 EXPORT_UNSIGNED16_ABGR = 0x5, 848 EXPORT_SIGNED16_ABGR = 0x6, 849 EXPORT_32_ABGR = 0x7, 850 } QuadExportFormat; 851 typedef enum QuadExportFormatOld { 852 EXPORT_4P_32BPC_ABGR = 0x0, 853 EXPORT_4P_16BPC_ABGR = 0x1, 854 EXPORT_4P_32BPC_GR = 0x2, 855 EXPORT_4P_32BPC_AR = 0x3, 856 EXPORT_2P_32BPC_ABGR = 0x4, 857 EXPORT_8P_32BPC_R = 0x5, 858 } QuadExportFormatOld; 859 typedef enum ColorFormat { 860 COLOR_INVALID = 0x0, 861 COLOR_8 = 0x1, 862 COLOR_16 = 0x2, 863 COLOR_8_8 = 0x3, 864 COLOR_32 = 0x4, 865 COLOR_16_16 = 0x5, 866 COLOR_10_11_11 = 0x6, 867 COLOR_11_11_10 = 0x7, 868 COLOR_10_10_10_2 = 0x8, 869 COLOR_2_10_10_10 = 0x9, 870 COLOR_8_8_8_8 = 0xa, 871 COLOR_32_32 = 0xb, 872 COLOR_16_16_16_16 = 0xc, 873 COLOR_RESERVED_13 = 0xd, 874 COLOR_32_32_32_32 = 0xe, 875 COLOR_RESERVED_15 = 0xf, 876 COLOR_5_6_5 = 0x10, 877 COLOR_1_5_5_5 = 0x11, 878 COLOR_5_5_5_1 = 0x12, 879 COLOR_4_4_4_4 = 0x13, 880 COLOR_8_24 = 0x14, 881 COLOR_24_8 = 0x15, 882 COLOR_X24_8_32_FLOAT = 0x16, 883 COLOR_RESERVED_23 = 0x17, 884 } ColorFormat; 885 typedef enum SurfaceFormat { 886 FMT_INVALID = 0x0, 887 FMT_8 = 0x1, 888 FMT_16 = 0x2, 889 FMT_8_8 = 0x3, 890 FMT_32 = 0x4, 891 FMT_16_16 = 0x5, 892 FMT_10_11_11 = 0x6, 893 FMT_11_11_10 = 0x7, 894 FMT_10_10_10_2 = 0x8, 895 FMT_2_10_10_10 = 0x9, 896 FMT_8_8_8_8 = 0xa, 897 FMT_32_32 = 0xb, 898 FMT_16_16_16_16 = 0xc, 899 FMT_32_32_32 = 0xd, 900 FMT_32_32_32_32 = 0xe, 901 FMT_RESERVED_4 = 0xf, 902 FMT_5_6_5 = 0x10, 903 FMT_1_5_5_5 = 0x11, 904 FMT_5_5_5_1 = 0x12, 905 FMT_4_4_4_4 = 0x13, 906 FMT_8_24 = 0x14, 907 FMT_24_8 = 0x15, 908 FMT_X24_8_32_FLOAT = 0x16, 909 FMT_RESERVED_33 = 0x17, 910 FMT_11_11_10_FLOAT = 0x18, 911 FMT_16_FLOAT = 0x19, 912 FMT_32_FLOAT = 0x1a, 913 FMT_16_16_FLOAT = 0x1b, 914 FMT_8_24_FLOAT = 0x1c, 915 FMT_24_8_FLOAT = 0x1d, 916 FMT_32_32_FLOAT = 0x1e, 917 FMT_10_11_11_FLOAT = 0x1f, 918 FMT_16_16_16_16_FLOAT = 0x20, 919 FMT_3_3_2 = 0x21, 920 FMT_6_5_5 = 0x22, 921 FMT_32_32_32_32_FLOAT = 0x23, 922 FMT_RESERVED_36 = 0x24, 923 FMT_1 = 0x25, 924 FMT_1_REVERSED = 0x26, 925 FMT_GB_GR = 0x27, 926 FMT_BG_RG = 0x28, 927 FMT_32_AS_8 = 0x29, 928 FMT_32_AS_8_8 = 0x2a, 929 FMT_5_9_9_9_SHAREDEXP = 0x2b, 930 FMT_8_8_8 = 0x2c, 931 FMT_16_16_16 = 0x2d, 932 FMT_16_16_16_FLOAT = 0x2e, 933 FMT_4_4 = 0x2f, 934 FMT_32_32_32_FLOAT = 0x30, 935 FMT_BC1 = 0x31, 936 FMT_BC2 = 0x32, 937 FMT_BC3 = 0x33, 938 FMT_BC4 = 0x34, 939 FMT_BC5 = 0x35, 940 FMT_BC6 = 0x36, 941 FMT_BC7 = 0x37, 942 FMT_32_AS_32_32_32_32 = 0x38, 943 FMT_APC3 = 0x39, 944 FMT_APC4 = 0x3a, 945 FMT_APC5 = 0x3b, 946 FMT_APC6 = 0x3c, 947 FMT_APC7 = 0x3d, 948 FMT_CTX1 = 0x3e, 949 FMT_RESERVED_63 = 0x3f, 950 } SurfaceFormat; 951 typedef enum BUF_DATA_FORMAT { 952 BUF_DATA_FORMAT_INVALID = 0x0, 953 BUF_DATA_FORMAT_8 = 0x1, 954 BUF_DATA_FORMAT_16 = 0x2, 955 BUF_DATA_FORMAT_8_8 = 0x3, 956 BUF_DATA_FORMAT_32 = 0x4, 957 BUF_DATA_FORMAT_16_16 = 0x5, 958 BUF_DATA_FORMAT_10_11_11 = 0x6, 959 BUF_DATA_FORMAT_11_11_10 = 0x7, 960 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 961 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 962 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 963 BUF_DATA_FORMAT_32_32 = 0xb, 964 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 965 BUF_DATA_FORMAT_32_32_32 = 0xd, 966 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 967 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 968 } BUF_DATA_FORMAT; 969 typedef enum IMG_DATA_FORMAT { 970 IMG_DATA_FORMAT_INVALID = 0x0, 971 IMG_DATA_FORMAT_8 = 0x1, 972 IMG_DATA_FORMAT_16 = 0x2, 973 IMG_DATA_FORMAT_8_8 = 0x3, 974 IMG_DATA_FORMAT_32 = 0x4, 975 IMG_DATA_FORMAT_16_16 = 0x5, 976 IMG_DATA_FORMAT_10_11_11 = 0x6, 977 IMG_DATA_FORMAT_11_11_10 = 0x7, 978 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 979 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 980 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 981 IMG_DATA_FORMAT_32_32 = 0xb, 982 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 983 IMG_DATA_FORMAT_32_32_32 = 0xd, 984 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 985 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 986 IMG_DATA_FORMAT_5_6_5 = 0x10, 987 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 988 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 989 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 990 IMG_DATA_FORMAT_8_24 = 0x14, 991 IMG_DATA_FORMAT_24_8 = 0x15, 992 IMG_DATA_FORMAT_X24_8_32 = 0x16, 993 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 994 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 995 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 996 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 997 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 998 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 999 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1000 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1001 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1002 IMG_DATA_FORMAT_GB_GR = 0x20, 1003 IMG_DATA_FORMAT_BG_RG = 0x21, 1004 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1005 IMG_DATA_FORMAT_BC1 = 0x23, 1006 IMG_DATA_FORMAT_BC2 = 0x24, 1007 IMG_DATA_FORMAT_BC3 = 0x25, 1008 IMG_DATA_FORMAT_BC4 = 0x26, 1009 IMG_DATA_FORMAT_BC5 = 0x27, 1010 IMG_DATA_FORMAT_BC6 = 0x28, 1011 IMG_DATA_FORMAT_BC7 = 0x29, 1012 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1013 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1014 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1015 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1016 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1017 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1018 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1019 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1020 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1021 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1022 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1023 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1024 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1025 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1026 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1027 IMG_DATA_FORMAT_4_4 = 0x39, 1028 IMG_DATA_FORMAT_6_5_5 = 0x3a, 1029 IMG_DATA_FORMAT_1 = 0x3b, 1030 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1031 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1032 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1033 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1034 } IMG_DATA_FORMAT; 1035 typedef enum BUF_NUM_FORMAT { 1036 BUF_NUM_FORMAT_UNORM = 0x0, 1037 BUF_NUM_FORMAT_SNORM = 0x1, 1038 BUF_NUM_FORMAT_USCALED = 0x2, 1039 BUF_NUM_FORMAT_SSCALED = 0x3, 1040 BUF_NUM_FORMAT_UINT = 0x4, 1041 BUF_NUM_FORMAT_SINT = 0x5, 1042 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1043 BUF_NUM_FORMAT_FLOAT = 0x7, 1044 } BUF_NUM_FORMAT; 1045 typedef enum IMG_NUM_FORMAT { 1046 IMG_NUM_FORMAT_UNORM = 0x0, 1047 IMG_NUM_FORMAT_SNORM = 0x1, 1048 IMG_NUM_FORMAT_USCALED = 0x2, 1049 IMG_NUM_FORMAT_SSCALED = 0x3, 1050 IMG_NUM_FORMAT_UINT = 0x4, 1051 IMG_NUM_FORMAT_SINT = 0x5, 1052 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1053 IMG_NUM_FORMAT_FLOAT = 0x7, 1054 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1055 IMG_NUM_FORMAT_SRGB = 0x9, 1056 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1057 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1058 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1059 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1060 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1061 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1062 } IMG_NUM_FORMAT; 1063 typedef enum TileType { 1064 ARRAY_COLOR_TILE = 0x0, 1065 ARRAY_DEPTH_TILE = 0x1, 1066 } TileType; 1067 typedef enum NonDispTilingOrder { 1068 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1069 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1070 } NonDispTilingOrder; 1071 typedef enum MicroTileMode { 1072 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1073 ADDR_SURF_THIN_MICRO_TILING = 0x1, 1074 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1075 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1076 ADDR_SURF_THICK_MICRO_TILING = 0x4, 1077 } MicroTileMode; 1078 typedef enum TileSplit { 1079 ADDR_SURF_TILE_SPLIT_64B = 0x0, 1080 ADDR_SURF_TILE_SPLIT_128B = 0x1, 1081 ADDR_SURF_TILE_SPLIT_256B = 0x2, 1082 ADDR_SURF_TILE_SPLIT_512B = 0x3, 1083 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1084 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1085 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1086 } TileSplit; 1087 typedef enum SampleSplit { 1088 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1089 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1090 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1091 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1092 } SampleSplit; 1093 typedef enum PipeConfig { 1094 ADDR_SURF_P2 = 0x0, 1095 ADDR_SURF_P2_RESERVED0 = 0x1, 1096 ADDR_SURF_P2_RESERVED1 = 0x2, 1097 ADDR_SURF_P2_RESERVED2 = 0x3, 1098 ADDR_SURF_P4_8x16 = 0x4, 1099 ADDR_SURF_P4_16x16 = 0x5, 1100 ADDR_SURF_P4_16x32 = 0x6, 1101 ADDR_SURF_P4_32x32 = 0x7, 1102 ADDR_SURF_P8_16x16_8x16 = 0x8, 1103 ADDR_SURF_P8_16x32_8x16 = 0x9, 1104 ADDR_SURF_P8_32x32_8x16 = 0xa, 1105 ADDR_SURF_P8_16x32_16x16 = 0xb, 1106 ADDR_SURF_P8_32x32_16x16 = 0xc, 1107 ADDR_SURF_P8_32x32_16x32 = 0xd, 1108 ADDR_SURF_P8_32x64_32x32 = 0xe, 1109 ADDR_SURF_P8_RESERVED0 = 0xf, 1110 ADDR_SURF_P16_32x32_8x16 = 0x10, 1111 ADDR_SURF_P16_32x32_16x16 = 0x11, 1112 } PipeConfig; 1113 typedef enum NumBanks { 1114 ADDR_SURF_2_BANK = 0x0, 1115 ADDR_SURF_4_BANK = 0x1, 1116 ADDR_SURF_8_BANK = 0x2, 1117 ADDR_SURF_16_BANK = 0x3, 1118 } NumBanks; 1119 typedef enum BankWidth { 1120 ADDR_SURF_BANK_WIDTH_1 = 0x0, 1121 ADDR_SURF_BANK_WIDTH_2 = 0x1, 1122 ADDR_SURF_BANK_WIDTH_4 = 0x2, 1123 ADDR_SURF_BANK_WIDTH_8 = 0x3, 1124 } BankWidth; 1125 typedef enum BankHeight { 1126 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1127 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1128 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1129 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1130 } BankHeight; 1131 typedef enum BankWidthHeight { 1132 ADDR_SURF_BANK_WH_1 = 0x0, 1133 ADDR_SURF_BANK_WH_2 = 0x1, 1134 ADDR_SURF_BANK_WH_4 = 0x2, 1135 ADDR_SURF_BANK_WH_8 = 0x3, 1136 } BankWidthHeight; 1137 typedef enum MacroTileAspect { 1138 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1139 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1140 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1141 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1142 } MacroTileAspect; 1143 typedef enum GATCL1RequestType { 1144 GATCL1_TYPE_NORMAL = 0x0, 1145 GATCL1_TYPE_SHOOTDOWN = 0x1, 1146 GATCL1_TYPE_BYPASS = 0x2, 1147 } GATCL1RequestType; 1148 typedef enum TCC_CACHE_POLICIES { 1149 TCC_CACHE_POLICY_LRU = 0x0, 1150 TCC_CACHE_POLICY_STREAM = 0x1, 1151 } TCC_CACHE_POLICIES; 1152 typedef enum MTYPE { 1153 MTYPE_NC_NV = 0x0, 1154 MTYPE_NC = 0x1, 1155 MTYPE_CC = 0x2, 1156 MTYPE_UC = 0x3, 1157 } MTYPE; 1158 typedef enum PERFMON_COUNTER_MODE { 1159 PERFMON_COUNTER_MODE_ACCUM = 0x0, 1160 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1161 PERFMON_COUNTER_MODE_MAX = 0x2, 1162 PERFMON_COUNTER_MODE_DIRTY = 0x3, 1163 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1164 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1165 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1166 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1167 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1168 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1169 PERFMON_COUNTER_MODE_RESERVED = 0xf, 1170 } PERFMON_COUNTER_MODE; 1171 typedef enum PERFMON_SPM_MODE { 1172 PERFMON_SPM_MODE_OFF = 0x0, 1173 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1174 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1175 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1176 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1177 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1178 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1179 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1180 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1181 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1182 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1183 } PERFMON_SPM_MODE; 1184 typedef enum SurfaceTiling { 1185 ARRAY_LINEAR = 0x0, 1186 ARRAY_TILED = 0x1, 1187 } SurfaceTiling; 1188 typedef enum SurfaceArray { 1189 ARRAY_1D = 0x0, 1190 ARRAY_2D = 0x1, 1191 ARRAY_3D = 0x2, 1192 ARRAY_3D_SLICE = 0x3, 1193 } SurfaceArray; 1194 typedef enum ColorArray { 1195 ARRAY_2D_ALT_COLOR = 0x0, 1196 ARRAY_2D_COLOR = 0x1, 1197 ARRAY_3D_SLICE_COLOR = 0x3, 1198 } ColorArray; 1199 typedef enum DepthArray { 1200 ARRAY_2D_ALT_DEPTH = 0x0, 1201 ARRAY_2D_DEPTH = 0x1, 1202 } DepthArray; 1203 typedef enum ENUM_NUM_SIMD_PER_CU { 1204 NUM_SIMD_PER_CU = 0x4, 1205 } ENUM_NUM_SIMD_PER_CU; 1206 1207 #endif /* SMU_7_1_1_ENUM_H */ 1208