1 /* $NetBSD: smu8_hwmgr.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef _SMU8_HWMGR_H_ 27 #define _SMU8_HWMGR_H_ 28 29 #include "cgs_common.h" 30 #include "ppatomctrl.h" 31 32 #define SMU8_NUM_NBPSTATES 4 33 #define SMU8_NUM_NBPMEMORYCLOCK 2 34 #define MAX_DISPLAY_CLOCK_LEVEL 8 35 #define SMU8_MAX_HARDWARE_POWERLEVELS 8 36 #define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 37 #define SMU8_MIN_DEEP_SLEEP_SCLK 800 38 39 /* Carrizo device IDs */ 40 #define DEVICE_ID_CZ_9870 0x9870 41 #define DEVICE_ID_CZ_9874 0x9874 42 #define DEVICE_ID_CZ_9875 0x9875 43 #define DEVICE_ID_CZ_9876 0x9876 44 #define DEVICE_ID_CZ_9877 0x9877 45 46 struct smu8_dpm_entry { 47 uint32_t soft_min_clk; 48 uint32_t hard_min_clk; 49 uint32_t soft_max_clk; 50 uint32_t hard_max_clk; 51 }; 52 53 struct smu8_sys_info { 54 uint32_t bootup_uma_clock; 55 uint32_t bootup_engine_clock; 56 uint32_t dentist_vco_freq; 57 uint32_t nb_dpm_enable; 58 uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK]; 59 uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES]; 60 uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES]; 61 uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL]; 62 uint16_t bootup_nb_voltage_index; 63 uint8_t htc_tmp_lmt; 64 uint8_t htc_hyst_lmt; 65 uint32_t system_config; 66 uint32_t uma_channel_number; 67 }; 68 69 #define MAX_DISPLAYPHY_IDS 0x8 70 #define DISPLAYPHY_LANEMASK 0xF 71 #define UNKNOWN_TRANSMITTER_PHY_ID (-1) 72 73 #define DISPLAYPHY_PHYID_SHIFT 24 74 #define DISPLAYPHY_LANESELECT_SHIFT 16 75 76 #define DISPLAYPHY_RX_SELECT 0x1 77 #define DISPLAYPHY_TX_SELECT 0x2 78 #define DISPLAYPHY_CORE_SELECT 0x4 79 80 #define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \ 81 (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \ 82 ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \ 83 ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \ 84 ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \ 85 ((core) ? DISPLAYPHY_CORE_SELECT : 0)) 86 87 struct smu8_display_phy_info_entry { 88 uint8_t phy_present; 89 uint8_t active_lane_mapping; 90 uint8_t display_config_type; 91 uint8_t active_number_of_lanes; 92 }; 93 94 #define SMU8_MAX_DISPLAYPHY_IDS 10 95 96 struct smu8_display_phy_info { 97 bool display_phy_access_initialized; 98 struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS]; 99 }; 100 101 struct smu8_power_level { 102 uint32_t engineClock; 103 uint8_t vddcIndex; 104 uint8_t dsDividerIndex; 105 uint8_t ssDividerIndex; 106 uint8_t allowGnbSlow; 107 uint8_t forceNBPstate; 108 uint8_t display_wm; 109 uint8_t vce_wm; 110 uint8_t numSIMDToPowerDown; 111 uint8_t hysteresis_up; 112 uint8_t rsv[3]; 113 }; 114 115 struct smu8_uvd_clocks { 116 uint32_t vclk; 117 uint32_t dclk; 118 uint32_t vclk_low_divider; 119 uint32_t vclk_high_divider; 120 uint32_t dclk_low_divider; 121 uint32_t dclk_high_divider; 122 }; 123 124 enum smu8_pstate_previous_action { 125 DO_NOTHING = 1, 126 FORCE_HIGH, 127 CANCEL_FORCE_HIGH 128 }; 129 130 struct pp_disable_nb_ps_flags { 131 union { 132 struct { 133 uint32_t entry : 1; 134 uint32_t display : 1; 135 uint32_t driver: 1; 136 uint32_t vce : 1; 137 uint32_t uvd : 1; 138 uint32_t acp : 1; 139 uint32_t reserved: 26; 140 } bits; 141 uint32_t u32All; 142 }; 143 }; 144 145 struct smu8_power_state { 146 unsigned int magic; 147 uint32_t level; 148 struct smu8_uvd_clocks uvd_clocks; 149 uint32_t evclk; 150 uint32_t ecclk; 151 uint32_t samclk; 152 uint32_t acpclk; 153 bool need_dfs_bypass; 154 uint32_t nbps_flags; 155 uint32_t bapm_flags; 156 uint8_t dpm_0_pg_nb_ps_low; 157 uint8_t dpm_0_pg_nb_ps_high; 158 uint8_t dpm_x_nb_ps_low; 159 uint8_t dpm_x_nb_ps_high; 160 enum smu8_pstate_previous_action action; 161 struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS]; 162 struct pp_disable_nb_ps_flags disable_nb_ps_flag; 163 }; 164 165 #define DPMFlags_SCLK_Enabled 0x00000001 166 #define DPMFlags_UVD_Enabled 0x00000002 167 #define DPMFlags_VCE_Enabled 0x00000004 168 #define DPMFlags_ACP_Enabled 0x00000008 169 #define DPMFlags_ForceHighestValid 0x40000000 170 #define DPMFlags_Debug 0x80000000 171 172 #define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */ 173 #define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */ 174 #define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */ 175 176 struct cc6_settings { 177 bool cc6_setting_changed; 178 bool nb_pstate_switch_disable;/* controls NB PState switch */ 179 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 180 bool cpu_pstate_disable; 181 uint32_t cpu_pstate_separation_time; 182 }; 183 184 struct smu8_hwmgr { 185 uint32_t dpm_interval; 186 187 uint32_t voltage_drop_threshold; 188 189 uint32_t voting_rights_clients; 190 191 uint32_t disable_driver_thermal_policy; 192 193 uint32_t static_screen_threshold; 194 195 uint32_t gfx_power_gating_threshold; 196 197 uint32_t activity_hysteresis; 198 uint32_t bootup_sclk_divider; 199 uint32_t gfx_ramp_step; 200 uint32_t gfx_ramp_delay; /* in micro-seconds */ 201 202 uint32_t thermal_auto_throttling_treshold; 203 204 struct smu8_sys_info sys_info; 205 206 struct smu8_power_level boot_power_level; 207 struct smu8_power_state *smu8_current_ps; 208 struct smu8_power_state *smu8_requested_ps; 209 210 uint32_t mgcg_cgtt_local0; 211 uint32_t mgcg_cgtt_local1; 212 213 uint32_t tdr_clock; /* in 10khz unit */ 214 215 uint32_t ddi_power_gating_disabled; 216 uint32_t disable_gfx_power_gating_in_uvd; 217 uint32_t disable_nb_ps3_in_battery; 218 219 uint32_t lock_nb_ps_in_uvd_play_back; 220 221 struct smu8_display_phy_info display_phy_info; 222 uint32_t vce_slow_sclk_threshold; /* default 200mhz */ 223 uint32_t dce_slow_sclk_threshold; /* default 300mhz */ 224 uint32_t min_sclk_did; /* minimum sclk divider */ 225 226 bool disp_clk_bypass; 227 bool disp_clk_bypass_pending; 228 uint32_t bapm_enabled; 229 uint32_t clock_slow_down_freq; 230 uint32_t skip_clock_slow_down; 231 uint32_t enable_nb_ps_policy; 232 uint32_t voltage_drop_in_dce_power_gating; 233 uint32_t uvd_dpm_interval; 234 uint32_t override_dynamic_mgpg; 235 uint32_t lclk_deep_enabled; 236 237 uint32_t uvd_performance; 238 239 bool video_start; 240 bool battery_state; 241 uint32_t lowest_valid; 242 uint32_t highest_valid; 243 uint32_t high_voltage_threshold; 244 uint32_t is_nb_dpm_enabled; 245 struct cc6_settings cc6_settings; 246 uint32_t is_voltage_island_enabled; 247 248 bool pgacpinit; 249 250 uint8_t disp_config; 251 252 /* PowerTune */ 253 uint32_t power_containment_features; 254 bool cac_enabled; 255 bool disable_uvd_power_tune_feature; 256 bool enable_ba_pm_feature; 257 bool enable_tdc_limit_feature; 258 259 uint32_t sram_end; 260 uint32_t dpm_table_start; 261 uint32_t soft_regs_start; 262 263 uint8_t uvd_level_count; 264 uint8_t vce_level_count; 265 266 uint8_t acp_level_count; 267 uint8_t samu_level_count; 268 uint32_t fps_high_threshold; 269 uint32_t fps_low_threshold; 270 271 uint32_t dpm_flags; 272 struct smu8_dpm_entry sclk_dpm; 273 struct smu8_dpm_entry uvd_dpm; 274 struct smu8_dpm_entry vce_dpm; 275 struct smu8_dpm_entry acp_dpm; 276 277 uint8_t uvd_boot_level; 278 uint8_t vce_boot_level; 279 uint8_t acp_boot_level; 280 uint8_t samu_boot_level; 281 uint8_t uvd_interval; 282 uint8_t vce_interval; 283 uint8_t acp_interval; 284 uint8_t samu_interval; 285 286 uint8_t graphics_interval; 287 uint8_t graphics_therm_throttle_enable; 288 uint8_t graphics_voltage_change_enable; 289 290 uint8_t graphics_clk_slow_enable; 291 uint8_t graphics_clk_slow_divider; 292 293 uint32_t display_cac; 294 uint32_t low_sclk_interrupt_threshold; 295 296 uint32_t dram_log_addr_h; 297 uint32_t dram_log_addr_l; 298 uint32_t dram_log_phy_addr_h; 299 uint32_t dram_log_phy_addr_l; 300 uint32_t dram_log_buff_size; 301 302 bool uvd_power_gated; 303 bool vce_power_gated; 304 bool samu_power_gated; 305 bool acp_power_gated; 306 bool acp_power_up_no_dsp; 307 uint32_t active_process_mask; 308 309 uint32_t max_sclk_level; 310 uint32_t num_of_clk_entries; 311 }; 312 313 #endif /* _SMU8_HWMGR_H_ */ 314