1 /* $NetBSD: smu75.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef SMU75_H 26 #define SMU75_H 27 28 #pragma pack(push, 1) 29 30 typedef struct { 31 uint32_t high; 32 uint32_t low; 33 } data_64_t; 34 35 typedef struct { 36 data_64_t high; 37 data_64_t low; 38 } data_128_t; 39 40 #define SMU__DGPU_ONLY 41 42 #define SMU__NUM_SCLK_DPM_STATE 8 43 #define SMU__NUM_MCLK_DPM_LEVELS 4 44 #define SMU__NUM_LCLK_DPM_LEVELS 8 45 #define SMU__NUM_PCIE_DPM_LEVELS 8 46 47 #define SMU7_CONTEXT_ID_SMC 1 48 #define SMU7_CONTEXT_ID_VBIOS 2 49 50 #define SMU75_MAX_LEVELS_VDDC 16 51 #define SMU75_MAX_LEVELS_VDDGFX 16 52 #define SMU75_MAX_LEVELS_VDDCI 8 53 #define SMU75_MAX_LEVELS_MVDD 4 54 55 #define SMU_MAX_SMIO_LEVELS 4 56 57 #define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE 58 #define SMU75_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS 59 #define SMU75_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS 60 #define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS 61 #define SMU75_MAX_LEVELS_UVD 8 62 #define SMU75_MAX_LEVELS_VCE 8 63 #define SMU75_MAX_LEVELS_ACP 8 64 #define SMU75_MAX_LEVELS_SAMU 8 65 #define SMU75_MAX_ENTRIES_SMIO 32 66 67 #define DPM_NO_LIMIT 0 68 #define DPM_NO_UP 1 69 #define DPM_GO_DOWN 2 70 #define DPM_GO_UP 3 71 72 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 73 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 74 75 #define GPIO_CLAMP_MODE_VRHOT 1 76 #define GPIO_CLAMP_MODE_THERM 2 77 #define GPIO_CLAMP_MODE_DC 4 78 79 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 80 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 81 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 82 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 83 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 84 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 85 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 86 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 87 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 88 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 89 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 90 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 91 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 92 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 93 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 94 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 95 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 96 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 97 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 98 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 99 100 /* Virtualization Defines */ 101 #define CG_XDMA_MASK 0x1 102 #define CG_XDMA_SHIFT 0 103 #define CG_UVD_MASK 0x2 104 #define CG_UVD_SHIFT 1 105 #define CG_VCE_MASK 0x4 106 #define CG_VCE_SHIFT 2 107 #define CG_SAMU_MASK 0x8 108 #define CG_SAMU_SHIFT 3 109 #define CG_GFX_MASK 0x10 110 #define CG_GFX_SHIFT 4 111 #define CG_SDMA_MASK 0x20 112 #define CG_SDMA_SHIFT 5 113 #define CG_HDP_MASK 0x40 114 #define CG_HDP_SHIFT 6 115 #define CG_MC_MASK 0x80 116 #define CG_MC_SHIFT 7 117 #define CG_DRM_MASK 0x100 118 #define CG_DRM_SHIFT 8 119 #define CG_ROM_MASK 0x200 120 #define CG_ROM_SHIFT 9 121 #define CG_BIF_MASK 0x400 122 #define CG_BIF_SHIFT 10 123 124 #if defined SMU__DGPU_ONLY 125 #define SMU75_DTE_ITERATIONS 5 126 #define SMU75_DTE_SOURCES 3 127 #define SMU75_DTE_SINKS 1 128 #define SMU75_NUM_CPU_TES 0 129 #define SMU75_NUM_GPU_TES 1 130 #define SMU75_NUM_NON_TES 2 131 #define SMU75_DTE_FAN_SCALAR_MIN 0x100 132 #define SMU75_DTE_FAN_SCALAR_MAX 0x166 133 #define SMU75_DTE_FAN_TEMP_MAX 93 134 #define SMU75_DTE_FAN_TEMP_MIN 83 135 #endif 136 #define SMU75_THERMAL_INPUT_LOOP_COUNT 2 137 #define SMU75_THERMAL_CLAMP_MODE_COUNT 2 138 139 #define EXP_M1_1 93 140 #define EXP_M2_1 195759 141 #define EXP_B_1 111176531 142 143 #define EXP_M1_2 67 144 #define EXP_M2_2 153720 145 #define EXP_B_2 94415767 146 147 #define EXP_M1_3 48 148 #define EXP_M2_3 119796 149 #define EXP_B_3 79195279 150 151 #define EXP_M1_4 550 152 #define EXP_M2_4 1484190 153 #define EXP_B_4 1051432828 154 155 #define EXP_M1_5 394 156 #define EXP_M2_5 1143049 157 #define EXP_B_5 864288432 158 159 struct SMU7_HystController_Data { 160 uint16_t waterfall_up; 161 uint16_t waterfall_down; 162 uint16_t waterfall_limit; 163 uint16_t release_cnt; 164 uint16_t release_limit; 165 uint16_t spare; 166 }; 167 168 typedef struct SMU7_HystController_Data SMU7_HystController_Data; 169 170 struct SMU75_PIDController { 171 uint32_t Ki; 172 int32_t LFWindupUpperLim; 173 int32_t LFWindupLowerLim; 174 uint32_t StatePrecision; 175 uint32_t LfPrecision; 176 uint32_t LfOffset; 177 uint32_t MaxState; 178 uint32_t MaxLfFraction; 179 uint32_t StateShift; 180 }; 181 182 typedef struct SMU75_PIDController SMU75_PIDController; 183 184 struct SMU7_LocalDpmScoreboard { 185 uint32_t PercentageBusy; 186 187 int32_t PIDError; 188 int32_t PIDIntegral; 189 int32_t PIDOutput; 190 191 uint32_t SigmaDeltaAccum; 192 uint32_t SigmaDeltaOutput; 193 uint32_t SigmaDeltaLevel; 194 195 uint32_t UtilizationSetpoint; 196 197 uint8_t TdpClampMode; 198 uint8_t TdcClampMode; 199 uint8_t ThermClampMode; 200 uint8_t VoltageBusy; 201 202 int8_t CurrLevel; 203 int8_t TargLevel; 204 uint8_t LevelChangeInProgress; 205 uint8_t UpHyst; 206 207 uint8_t DownHyst; 208 uint8_t VoltageDownHyst; 209 uint8_t DpmEnable; 210 uint8_t DpmRunning; 211 212 uint8_t DpmForce; 213 uint8_t DpmForceLevel; 214 uint8_t DisplayWatermark; 215 uint8_t McArbIndex; 216 217 uint32_t MinimumPerfSclk; 218 219 uint8_t AcpiReq; 220 uint8_t AcpiAck; 221 uint8_t GfxClkSlow; 222 uint8_t GpioClampMode; 223 224 uint8_t EnableModeSwitchRLCNotification; 225 uint8_t EnabledLevelsChange; 226 uint8_t DteClampMode; 227 uint8_t FpsClampMode; 228 229 uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_GRAPHICS]; 230 uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_GRAPHICS]; 231 232 void (*TargetStateCalculator)(uint8_t); 233 void (*SavedTargetStateCalculator)(uint8_t); 234 235 uint16_t AutoDpmInterval; 236 uint16_t AutoDpmRange; 237 238 uint8_t FpsEnabled; 239 uint8_t MaxPerfLevel; 240 uint8_t AllowLowClkInterruptToHost; 241 uint8_t FpsRunning; 242 243 uint32_t MaxAllowedFrequency; 244 245 uint32_t FilteredSclkFrequency; 246 uint32_t LastSclkFrequency; 247 uint32_t FilteredSclkFrequencyCnt; 248 249 uint8_t MinPerfLevel; 250 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1 251 uint8_t ScksClampMode; 252 uint8_t padding[2]; 253 #else 254 uint8_t padding[3]; 255 #endif 256 257 uint16_t FpsAlpha; 258 uint16_t DeltaTime; 259 uint32_t CurrentFps; 260 uint32_t FilteredFps; 261 uint32_t FrameCount; 262 uint32_t FrameCountLast; 263 uint16_t FpsTargetScalar; 264 uint16_t FpsWaterfallLimitScalar; 265 uint16_t FpsAlphaScalar; 266 uint16_t spare8; 267 SMU7_HystController_Data HystControllerData; 268 }; 269 270 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 271 272 #define SMU7_MAX_VOLTAGE_CLIENTS 12 273 274 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 275 276 #define VDDC_MASK 0x00007FFF 277 #define VDDC_SHIFT 0 278 #define VDDCI_MASK 0x3FFF8000 279 #define VDDCI_SHIFT 15 280 #define PHASES_MASK 0xC0000000 281 #define PHASES_SHIFT 30 282 283 typedef uint32_t SMU_VoltageLevel; 284 285 struct SMU7_VoltageScoreboard { 286 SMU_VoltageLevel TargetVoltage; 287 uint16_t MaxVid; 288 uint8_t HighestVidOffset; 289 uint8_t CurrentVidOffset; 290 291 uint16_t CurrentVddc; 292 uint16_t CurrentVddci; 293 294 uint8_t ControllerBusy; 295 uint8_t CurrentVid; 296 uint8_t CurrentVddciVid; 297 uint8_t padding; 298 299 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 300 SMU_VoltageLevel TargetVoltageState; 301 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 302 303 uint8_t padding2; 304 uint8_t padding3; 305 uint8_t ControllerEnable; 306 uint8_t ControllerRunning; 307 uint16_t CurrentStdVoltageHiSidd; 308 uint16_t CurrentStdVoltageLoSidd; 309 uint8_t OverrideVoltage; 310 uint8_t padding4; 311 uint8_t padding5; 312 uint8_t CurrentPhases; 313 314 VoltageChangeHandler_t ChangeVddc; 315 VoltageChangeHandler_t ChangeVddci; 316 VoltageChangeHandler_t ChangePhase; 317 VoltageChangeHandler_t ChangeMvdd; 318 319 VoltageChangeHandler_t functionLinks[6]; 320 321 uint16_t * VddcFollower1; 322 int16_t Driver_OD_RequestedVidOffset1; 323 int16_t Driver_OD_RequestedVidOffset2; 324 }; 325 326 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 327 328 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 329 330 struct SMU7_PCIeLinkSpeedScoreboard { 331 uint8_t DpmEnable; 332 uint8_t DpmRunning; 333 uint8_t DpmForce; 334 uint8_t DpmForceLevel; 335 336 uint8_t CurrentLinkSpeed; 337 uint8_t EnabledLevelsChange; 338 uint16_t AutoDpmInterval; 339 340 uint16_t AutoDpmRange; 341 uint16_t AutoDpmCount; 342 343 uint8_t DpmMode; 344 uint8_t AcpiReq; 345 uint8_t AcpiAck; 346 uint8_t CurrentLinkLevel; 347 }; 348 349 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 350 351 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 352 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 353 354 #define SMU7_SCALE_I 7 355 #define SMU7_SCALE_R 12 356 357 struct SMU7_PowerScoreboard { 358 uint32_t GpuPower; 359 360 uint32_t VddcPower; 361 uint32_t VddcVoltage; 362 uint32_t VddcCurrent; 363 364 uint32_t VddciPower; 365 uint32_t VddciVoltage; 366 uint32_t VddciCurrent; 367 368 uint32_t RocPower; 369 370 uint16_t Telemetry_1_slope; 371 uint16_t Telemetry_2_slope; 372 int32_t Telemetry_1_offset; 373 int32_t Telemetry_2_offset; 374 375 uint8_t MCLK_patch_flag; 376 uint8_t reserved[3]; 377 }; 378 379 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 380 381 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 382 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 383 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 384 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 385 #define SMU7_UVD_DPM_CONFIG_MASK 0x10 386 #define SMU7_VCE_DPM_CONFIG_MASK 0x20 387 #define SMU7_ACP_DPM_CONFIG_MASK 0x40 388 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 389 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 390 391 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 392 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 393 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 394 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 395 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 396 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 397 398 struct SMU75_SoftRegisters { 399 uint32_t RefClockFrequency; 400 uint32_t PmTimerPeriod; 401 uint32_t FeatureEnables; 402 #if defined (SMU__DGPU_ONLY) 403 uint32_t PreVBlankGap; 404 uint32_t VBlankTimeout; 405 uint32_t TrainTimeGap; 406 uint32_t MvddSwitchTime; 407 uint32_t LongestAcpiTrainTime; 408 uint32_t AcpiDelay; 409 uint32_t G5TrainTime; 410 uint32_t DelayMpllPwron; 411 uint32_t VoltageChangeTimeout; 412 #endif 413 uint32_t HandshakeDisables; 414 415 uint8_t DisplayPhy1Config; 416 uint8_t DisplayPhy2Config; 417 uint8_t DisplayPhy3Config; 418 uint8_t DisplayPhy4Config; 419 420 uint8_t DisplayPhy5Config; 421 uint8_t DisplayPhy6Config; 422 uint8_t DisplayPhy7Config; 423 uint8_t DisplayPhy8Config; 424 425 uint32_t AverageGraphicsActivity; 426 uint32_t AverageMemoryActivity; 427 uint32_t AverageGioActivity; 428 429 uint8_t SClkDpmEnabledLevels; 430 uint8_t MClkDpmEnabledLevels; 431 uint8_t LClkDpmEnabledLevels; 432 uint8_t PCIeDpmEnabledLevels; 433 434 uint8_t UVDDpmEnabledLevels; 435 uint8_t SAMUDpmEnabledLevels; 436 uint8_t ACPDpmEnabledLevels; 437 uint8_t VCEDpmEnabledLevels; 438 439 uint32_t DRAM_LOG_ADDR_H; 440 uint32_t DRAM_LOG_ADDR_L; 441 uint32_t DRAM_LOG_PHY_ADDR_H; 442 uint32_t DRAM_LOG_PHY_ADDR_L; 443 uint32_t DRAM_LOG_BUFF_SIZE; 444 uint32_t UlvEnterCount; 445 uint32_t UlvTime; 446 uint32_t UcodeLoadStatus; 447 uint32_t AllowMvddSwitch; 448 uint8_t Activity_Weight; 449 uint8_t Reserved8[3]; 450 }; 451 452 typedef struct SMU75_SoftRegisters SMU75_SoftRegisters; 453 454 struct SMU75_Firmware_Header { 455 uint32_t Digest[5]; 456 uint32_t Version; 457 uint32_t HeaderSize; 458 uint32_t Flags; 459 uint32_t EntryPoint; 460 uint32_t CodeSize; 461 uint32_t ImageSize; 462 463 uint32_t Rtos; 464 uint32_t SoftRegisters; 465 uint32_t DpmTable; 466 uint32_t FanTable; 467 uint32_t CacConfigTable; 468 uint32_t CacStatusTable; 469 uint32_t mcRegisterTable; 470 uint32_t mcArbDramTimingTable; 471 uint32_t PmFuseTable; 472 uint32_t Globals; 473 uint32_t ClockStretcherTable; 474 uint32_t VftTable; 475 uint32_t Reserved1; 476 uint32_t AvfsCksOff_AvfsGbvTable; 477 uint32_t AvfsCksOff_BtcGbvTable; 478 uint32_t MM_AvfsTable; 479 uint32_t PowerSharingTable; 480 uint32_t AvfsTable; 481 uint32_t AvfsCksOffGbvTable; 482 uint32_t AvfsMeanNSigma; 483 uint32_t AvfsSclkOffsetTable; 484 uint32_t Reserved[12]; 485 uint32_t Signature; 486 }; 487 488 typedef struct SMU75_Firmware_Header SMU75_Firmware_Header; 489 490 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 491 492 enum DisplayConfig { 493 PowerDown = 1, 494 DP54x4, 495 DP54x2, 496 DP54x1, 497 DP27x4, 498 DP27x2, 499 DP27x1, 500 HDMI297, 501 HDMI162, 502 LVDS, 503 DP324x4, 504 DP324x2, 505 DP324x1 506 }; 507 508 #define MC_BLOCK_COUNT 1 509 #define CPL_BLOCK_COUNT 5 510 #define SE_BLOCK_COUNT 15 511 #define GC_BLOCK_COUNT 24 512 513 struct SMU7_Local_Cac { 514 uint8_t BlockId; 515 uint8_t SignalId; 516 uint8_t Threshold; 517 uint8_t Padding; 518 }; 519 520 typedef struct SMU7_Local_Cac SMU7_Local_Cac; 521 522 struct SMU7_Local_Cac_Table { 523 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 524 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 525 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 526 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 527 }; 528 529 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 530 531 #pragma pack(pop) 532 533 #define CG_SYS_BITMASK_FIRST_BIT 0 534 #define CG_SYS_BITMASK_LAST_BIT 10 535 #define CG_SYS_BIF_MGLS_SHIFT 0 536 #define CG_SYS_ROM_SHIFT 1 537 #define CG_SYS_MC_MGCG_SHIFT 2 538 #define CG_SYS_MC_MGLS_SHIFT 3 539 #define CG_SYS_SDMA_MGCG_SHIFT 4 540 #define CG_SYS_SDMA_MGLS_SHIFT 5 541 #define CG_SYS_DRM_MGCG_SHIFT 6 542 #define CG_SYS_HDP_MGCG_SHIFT 7 543 #define CG_SYS_HDP_MGLS_SHIFT 8 544 #define CG_SYS_DRM_MGLS_SHIFT 9 545 #define CG_SYS_BIF_MGCG_SHIFT 10 546 547 #define CG_SYS_BIF_MGLS_MASK 0x1 548 #define CG_SYS_ROM_MASK 0x2 549 #define CG_SYS_MC_MGCG_MASK 0x4 550 #define CG_SYS_MC_MGLS_MASK 0x8 551 #define CG_SYS_SDMA_MGCG_MASK 0x10 552 #define CG_SYS_SDMA_MGLS_MASK 0x20 553 #define CG_SYS_DRM_MGCG_MASK 0x40 554 #define CG_SYS_HDP_MGCG_MASK 0x80 555 #define CG_SYS_HDP_MGLS_MASK 0x100 556 #define CG_SYS_DRM_MGLS_MASK 0x200 557 #define CG_SYS_BIF_MGCG_MASK 0x400 558 559 #define CG_GFX_BITMASK_FIRST_BIT 16 560 #define CG_GFX_BITMASK_LAST_BIT 24 561 562 #define CG_GFX_CGCG_SHIFT 16 563 #define CG_GFX_CGLS_SHIFT 17 564 #define CG_CPF_MGCG_SHIFT 18 565 #define CG_RLC_MGCG_SHIFT 19 566 #define CG_GFX_OTHERS_MGCG_SHIFT 20 567 #define CG_GFX_3DCG_SHIFT 21 568 #define CG_GFX_3DLS_SHIFT 22 569 #define CG_GFX_RLC_LS_SHIFT 23 570 #define CG_GFX_CP_LS_SHIFT 24 571 572 #define CG_GFX_CGCG_MASK 0x00010000 573 #define CG_GFX_CGLS_MASK 0x00020000 574 #define CG_CPF_MGCG_MASK 0x00040000 575 #define CG_RLC_MGCG_MASK 0x00080000 576 #define CG_GFX_OTHERS_MGCG_MASK 0x00100000 577 #define CG_GFX_3DCG_MASK 0x00200000 578 #define CG_GFX_3DLS_MASK 0x00400000 579 #define CG_GFX_RLC_LS_MASK 0x00800000 580 #define CG_GFX_CP_LS_MASK 0x01000000 581 582 583 #define VRCONF_VDDC_MASK 0x000000FF 584 #define VRCONF_VDDC_SHIFT 0 585 #define VRCONF_VDDGFX_MASK 0x0000FF00 586 #define VRCONF_VDDGFX_SHIFT 8 587 #define VRCONF_VDDCI_MASK 0x00FF0000 588 #define VRCONF_VDDCI_SHIFT 16 589 #define VRCONF_MVDD_MASK 0xFF000000 590 #define VRCONF_MVDD_SHIFT 24 591 592 #define VR_MERGED_WITH_VDDC 0 593 #define VR_SVI2_PLANE_1 1 594 #define VR_SVI2_PLANE_2 2 595 #define VR_SMIO_PATTERN_1 3 596 #define VR_SMIO_PATTERN_2 4 597 #define VR_STATIC_VOLTAGE 5 598 599 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4 600 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4 601 602 #define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 603 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 604 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 605 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 606 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 607 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 608 609 struct SMU_ClockStretcherDataTableEntry { 610 uint8_t minVID; 611 uint8_t maxVID; 612 613 uint16_t setting; 614 }; 615 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 616 617 struct SMU_ClockStretcherDataTable { 618 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 619 }; 620 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 621 622 struct SMU_CKS_LOOKUPTableEntry { 623 uint16_t minFreq; 624 uint16_t maxFreq; 625 626 uint8_t setting; 627 uint8_t padding[3]; 628 }; 629 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 630 631 struct SMU_CKS_LOOKUPTable { 632 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 633 }; 634 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 635 636 struct AgmAvfsData_t { 637 uint16_t avgPsmCount[28]; 638 uint16_t minPsmCount[28]; 639 }; 640 typedef struct AgmAvfsData_t AgmAvfsData_t; 641 642 enum VFT_COLUMNS { 643 SCLK0, 644 SCLK1, 645 SCLK2, 646 SCLK3, 647 SCLK4, 648 SCLK5, 649 SCLK6, 650 SCLK7, 651 652 NUM_VFT_COLUMNS 653 }; 654 enum { 655 SCS_FUSE_T0, 656 SCS_FUSE_T1, 657 NUM_SCS_FUSE_TEMPERATURE 658 }; 659 enum { 660 SCKS_ON, 661 SCKS_OFF, 662 NUM_SCKS_STATE_TYPES 663 }; 664 665 #define VFT_TABLE_DEFINED 666 667 #define TEMP_RANGE_MAXSTEPS 12 668 struct VFT_CELL_t { 669 uint16_t Voltage; 670 }; 671 672 typedef struct VFT_CELL_t VFT_CELL_t; 673 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1 674 struct SCS_CELL_t { 675 uint16_t PsmCnt[NUM_SCKS_STATE_TYPES]; 676 }; 677 typedef struct SCS_CELL_t SCS_CELL_t; 678 #endif 679 680 struct VFT_TABLE_t { 681 VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; 682 uint16_t AvfsGbv [NUM_VFT_COLUMNS]; 683 uint16_t BtcGbv [NUM_VFT_COLUMNS]; 684 int16_t Temperature [TEMP_RANGE_MAXSTEPS]; 685 686 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1 687 SCS_CELL_t ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; 688 #endif 689 690 uint8_t NumTemperatureSteps; 691 uint8_t padding[3]; 692 }; 693 typedef struct VFT_TABLE_t VFT_TABLE_t; 694 695 #define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2 696 #define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2 697 698 struct GB_VDROOP_TABLE_t { 699 int32_t a0; 700 int32_t a1; 701 int32_t a2; 702 uint32_t spare; 703 }; 704 typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t; 705 706 struct SMU_QuadraticCoeffs { 707 int32_t m1; 708 int32_t b; 709 710 int16_t m2; 711 uint8_t m1_shift; 712 uint8_t m2_shift; 713 }; 714 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; 715 716 struct AVFS_Margin_t { 717 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 718 }; 719 typedef struct AVFS_Margin_t AVFS_Margin_t; 720 721 struct AVFS_CksOff_Gbv_t { 722 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 723 }; 724 typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t; 725 726 struct AVFS_CksOff_AvfsGbv_t { 727 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 728 }; 729 typedef struct AVFS_CksOff_AvfsGbv_t AVFS_CksOff_AvfsGbv_t; 730 731 struct AVFS_CksOff_BtcGbv_t { 732 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 733 }; 734 typedef struct AVFS_CksOff_BtcGbv_t AVFS_CksOff_BtcGbv_t; 735 736 struct AVFS_meanNsigma_t { 737 uint32_t Aconstant[3]; 738 uint16_t DC_tol_sigma; 739 uint16_t Platform_mean; 740 uint16_t Platform_sigma; 741 uint16_t PSM_Age_CompFactor; 742 uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS]; 743 }; 744 typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t; 745 746 struct AVFS_Sclk_Offset_t { 747 uint16_t Sclk_Offset[8]; 748 }; 749 typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t; 750 751 struct Power_Sharing_t { 752 uint32_t EnergyCounter; 753 uint32_t EngeryThreshold; 754 uint64_t AM_SCLK_CNT; 755 uint64_t AM_0_BUSY_CNT; 756 }; 757 typedef struct Power_Sharing_t Power_Sharing_t; 758 759 760 #endif 761 762 763