1 /* $NetBSD: smu_ucode_xfer_vi.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU_UCODE_XFER_VI_H 27 #define SMU_UCODE_XFER_VI_H 28 29 #define SMU_DRAMData_TOC_VERSION 1 30 #define MAX_IH_REGISTER_COUNT 65535 31 #define SMU_DIGEST_SIZE_BYTES 20 32 #define SMU_FB_SIZE_BYTES 1048576 33 #define SMU_MAX_ENTRIES 12 34 35 #define UCODE_ID_SMU 0 36 #define UCODE_ID_SDMA0 1 37 #define UCODE_ID_SDMA1 2 38 #define UCODE_ID_CP_CE 3 39 #define UCODE_ID_CP_PFP 4 40 #define UCODE_ID_CP_ME 5 41 #define UCODE_ID_CP_MEC 6 42 #define UCODE_ID_CP_MEC_JT1 7 43 #define UCODE_ID_CP_MEC_JT2 8 44 #define UCODE_ID_GMCON_RENG 9 45 #define UCODE_ID_RLC_G 10 46 #define UCODE_ID_IH_REG_RESTORE 11 47 #define UCODE_ID_VBIOS 12 48 #define UCODE_ID_MISC_METADATA 13 49 #define UCODE_ID_SMU_SK 14 50 #define UCODE_ID_RLC_SCRATCH 32 51 #define UCODE_ID_RLC_SRM_ARAM 33 52 #define UCODE_ID_RLC_SRM_DRAM 34 53 #define UCODE_ID_MEC_STORAGE 35 54 #define UCODE_ID_VBIOS_PARAMETERS 36 55 #define UCODE_META_DATA 0xFF 56 57 #define UCODE_ID_SMU_MASK 0x00000001 58 #define UCODE_ID_SDMA0_MASK 0x00000002 59 #define UCODE_ID_SDMA1_MASK 0x00000004 60 #define UCODE_ID_CP_CE_MASK 0x00000008 61 #define UCODE_ID_CP_PFP_MASK 0x00000010 62 #define UCODE_ID_CP_ME_MASK 0x00000020 63 #define UCODE_ID_CP_MEC_MASK 0x00000040 64 #define UCODE_ID_CP_MEC_JT1_MASK 0x00000080 65 #define UCODE_ID_CP_MEC_JT2_MASK 0x00000100 66 #define UCODE_ID_GMCON_RENG_MASK 0x00000200 67 #define UCODE_ID_RLC_G_MASK 0x00000400 68 #define UCODE_ID_IH_REG_RESTORE_MASK 0x00000800 69 #define UCODE_ID_VBIOS_MASK 0x00001000 70 71 #define UCODE_FLAG_UNHALT_MASK 0x1 72 73 struct SMU_Entry { 74 #ifndef __BIG_ENDIAN 75 uint16_t id; 76 uint16_t version; 77 uint32_t image_addr_high; 78 uint32_t image_addr_low; 79 uint32_t meta_data_addr_high; 80 uint32_t meta_data_addr_low; 81 uint32_t data_size_byte; 82 uint16_t flags; 83 uint16_t num_register_entries; 84 #else 85 uint16_t version; 86 uint16_t id; 87 uint32_t image_addr_high; 88 uint32_t image_addr_low; 89 uint32_t meta_data_addr_high; 90 uint32_t meta_data_addr_low; 91 uint32_t data_size_byte; 92 uint16_t num_register_entries; 93 uint16_t flags; 94 #endif 95 }; 96 97 struct SMU_DRAMData_TOC { 98 uint32_t structure_version; 99 uint32_t num_entries; 100 struct SMU_Entry entry[SMU_MAX_ENTRIES]; 101 }; 102 103 #endif 104