1 /* $NetBSD: nouveau_nvkm_engine_disp_sorgf119.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_sorgf119.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29 #include "ior.h"
30
31 #include <subdev/timer.h>
32
33 void
gf119_sor_dp_watermark(struct nvkm_ior * sor,int head,u8 watermark)34 gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark)
35 {
36 struct nvkm_device *device = sor->disp->engine.subdev.device;
37 const u32 hoff = head * 0x800;
38 nvkm_mask(device, 0x616610 + hoff, 0x0800003f, 0x08000000 | watermark);
39 }
40
41 void
gf119_sor_dp_audio_sym(struct nvkm_ior * sor,int head,u16 h,u32 v)42 gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
43 {
44 struct nvkm_device *device = sor->disp->engine.subdev.device;
45 const u32 hoff = head * 0x800;
46 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, h);
47 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v);
48 }
49
50 void
gf119_sor_dp_audio(struct nvkm_ior * sor,int head,bool enable)51 gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
52 {
53 struct nvkm_device *device = sor->disp->engine.subdev.device;
54 const u32 hoff = 0x800 * head;
55 const u32 data = 0x80000000 | (0x00000001 * enable);
56 const u32 mask = 0x8000000d;
57 nvkm_mask(device, 0x616618 + hoff, mask, data);
58 nvkm_msec(device, 2000,
59 if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000))
60 break;
61 );
62 }
63
64 void
gf119_sor_dp_vcpi(struct nvkm_ior * sor,int head,u8 slot,u8 slot_nr,u16 pbn,u16 aligned)65 gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head,
66 u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
67 {
68 struct nvkm_device *device = sor->disp->engine.subdev.device;
69 const u32 hoff = head * 0x800;
70
71 nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
72 nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn);
73 }
74
75 void
gf119_sor_dp_drive(struct nvkm_ior * sor,int ln,int pc,int dc,int pe,int pu)76 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
77 {
78 struct nvkm_device *device = sor->disp->engine.subdev.device;
79 const u32 loff = nv50_sor_link(sor);
80 const u32 shift = sor->func->dp.lanes[ln] * 8;
81 u32 data[4];
82
83 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
84 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
85 data[2] = nvkm_rd32(device, 0x61c130 + loff);
86 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)
87 data[2] = (data[2] & ~0x0000ff00) | (pu << 8);
88 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
89 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
90 nvkm_wr32(device, 0x61c130 + loff, data[2]);
91 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
92 nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift));
93 }
94
95 void
gf119_sor_dp_pattern(struct nvkm_ior * sor,int pattern)96 gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
97 {
98 struct nvkm_device *device = sor->disp->engine.subdev.device;
99 const u32 soff = nv50_ior_base(sor);
100 nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
101 }
102
103 int
gf119_sor_dp_links(struct nvkm_ior * sor,struct nvkm_i2c_aux * aux)104 gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
105 {
106 struct nvkm_device *device = sor->disp->engine.subdev.device;
107 const u32 soff = nv50_ior_base(sor);
108 const u32 loff = nv50_sor_link(sor);
109 u32 dpctrl = 0x00000000;
110 u32 clksor = 0x00000000;
111
112 clksor |= sor->dp.bw << 18;
113 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
114 if (sor->dp.mst)
115 dpctrl |= 0x40000000;
116 if (sor->dp.ef)
117 dpctrl |= 0x00004000;
118
119 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
120 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
121 return 0;
122 }
123
124 void
gf119_sor_clock(struct nvkm_ior * sor)125 gf119_sor_clock(struct nvkm_ior *sor)
126 {
127 struct nvkm_device *device = sor->disp->engine.subdev.device;
128 const u32 soff = nv50_ior_base(sor);
129 u32 div1 = sor->asy.link == 3;
130 u32 div2 = sor->asy.link == 3;
131 if (sor->asy.proto == TMDS) {
132 const u32 speed = sor->tmds.high_speed ? 0x14 : 0x0a;
133 nvkm_mask(device, 0x612300 + soff, 0x007c0000, speed << 18);
134 if (sor->tmds.high_speed)
135 div2 = 1;
136 }
137 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1);
138 }
139
140 void
gf119_sor_state(struct nvkm_ior * sor,struct nvkm_ior_state * state)141 gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
142 {
143 struct nvkm_device *device = sor->disp->engine.subdev.device;
144 const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20;
145 u32 ctrl = nvkm_rd32(device, 0x640200 + coff);
146
147 state->proto_evo = (ctrl & 0x00000f00) >> 8;
148 switch (state->proto_evo) {
149 case 0: state->proto = LVDS; state->link = 1; break;
150 case 1: state->proto = TMDS; state->link = 1; break;
151 case 2: state->proto = TMDS; state->link = 2; break;
152 case 5: state->proto = TMDS; state->link = 3; break;
153 case 8: state->proto = DP; state->link = 1; break;
154 case 9: state->proto = DP; state->link = 2; break;
155 default:
156 state->proto = UNKNOWN;
157 break;
158 }
159
160 state->head = ctrl & 0x0000000f;
161 }
162
163 static const struct nvkm_ior_func
164 gf119_sor = {
165 .state = gf119_sor_state,
166 .power = nv50_sor_power,
167 .clock = gf119_sor_clock,
168 .hdmi = {
169 .ctrl = gf119_hdmi_ctrl,
170 },
171 .dp = {
172 .lanes = { 2, 1, 0, 3 },
173 .links = gf119_sor_dp_links,
174 .power = g94_sor_dp_power,
175 .pattern = gf119_sor_dp_pattern,
176 .drive = gf119_sor_dp_drive,
177 .vcpi = gf119_sor_dp_vcpi,
178 .audio = gf119_sor_dp_audio,
179 .audio_sym = gf119_sor_dp_audio_sym,
180 .watermark = gf119_sor_dp_watermark,
181 },
182 .hda = {
183 .hpd = gf119_hda_hpd,
184 .eld = gf119_hda_eld,
185 },
186 };
187
188 int
gf119_sor_new(struct nvkm_disp * disp,int id)189 gf119_sor_new(struct nvkm_disp *disp, int id)
190 {
191 return nvkm_ior_new_(&gf119_sor, disp, SOR, id);
192 }
193
194 int
gf119_sor_cnt(struct nvkm_disp * disp,unsigned long * pmask)195 gf119_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask)
196 {
197 struct nvkm_device *device = disp->engine.subdev.device;
198 *pmask = (nvkm_rd32(device, 0x612004) & 0x0000ff00) >> 8;
199 return 8;
200 }
201