1 /* $NetBSD: nouveau_nvkm_subdev_pmu_gk104.c,v 1.3 2021/12/18 23:45:41 riastradh Exp $ */
2
3 /*
4 * Copyright 2013 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_pmu_gk104.c,v 1.3 2021/12/18 23:45:41 riastradh Exp $");
28
29 #define gf119_pmu_code gk104_pmu_code
30 #define gf119_pmu_data gk104_pmu_data
31 #include "priv.h"
32 #include "fuc/gf119.fuc4.h"
33
34 #include <core/option.h>
35 #include <subdev/fuse.h>
36 #include <subdev/timer.h>
37
38 static void
magic_(struct nvkm_device * device,u32 ctrl,int size)39 magic_(struct nvkm_device *device, u32 ctrl, int size)
40 {
41 nvkm_wr32(device, 0x00c800, 0x00000000);
42 nvkm_wr32(device, 0x00c808, 0x00000000);
43 nvkm_wr32(device, 0x00c800, ctrl);
44 nvkm_msec(device, 2000,
45 if (nvkm_rd32(device, 0x00c800) & 0x40000000) {
46 while (size--)
47 nvkm_wr32(device, 0x00c804, 0x00000000);
48 break;
49 }
50 );
51 nvkm_wr32(device, 0x00c800, 0x00000000);
52 }
53
54 static void
magic(struct nvkm_device * device,u32 ctrl)55 magic(struct nvkm_device *device, u32 ctrl)
56 {
57 magic_(device, 0x8000a41f | ctrl, 6);
58 magic_(device, 0x80000421 | ctrl, 1);
59 }
60
61 static void
gk104_pmu_pgob(struct nvkm_pmu * pmu,bool enable)62 gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
63 {
64 struct nvkm_device *device = pmu->subdev.device;
65
66 if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001))
67 return;
68
69 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
70 nvkm_rd32(device, 0x000200);
71 nvkm_mask(device, 0x000200, 0x08000000, 0x08000000);
72 msleep(50);
73
74 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002);
75 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
76 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
77
78 nvkm_mask(device, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
79 msleep(50);
80
81 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000);
82 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
83 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
84
85 nvkm_mask(device, 0x000200, 0x08000000, 0x00000000);
86 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
87 nvkm_rd32(device, 0x000200);
88
89 if (nvkm_boolopt(device->cfgopt, "War00C800_0", true)) {
90 switch (device->chipset) {
91 case 0xe4:
92 magic(device, 0x04000000);
93 magic(device, 0x06000000);
94 magic(device, 0x0c000000);
95 magic(device, 0x0e000000);
96 break;
97 case 0xe6:
98 magic(device, 0x02000000);
99 magic(device, 0x04000000);
100 magic(device, 0x0a000000);
101 break;
102 case 0xe7:
103 magic(device, 0x02000000);
104 break;
105 default:
106 break;
107 }
108 }
109 }
110
111 static const struct nvkm_pmu_func
112 gk104_pmu = {
113 .flcn = >215_pmu_flcn,
114 .code.data = gk104_pmu_code,
115 .code.size = sizeof(gk104_pmu_code),
116 .data.data = gk104_pmu_data,
117 .data.size = sizeof(gk104_pmu_data),
118 .enabled = gf100_pmu_enabled,
119 .reset = gf100_pmu_reset,
120 .init = gt215_pmu_init,
121 .fini = gt215_pmu_fini,
122 .intr = gt215_pmu_intr,
123 .send = gt215_pmu_send,
124 .recv = gt215_pmu_recv,
125 .pgob = gk104_pmu_pgob,
126 };
127
128 static const struct nvkm_pmu_fwif
129 gk104_pmu_fwif[] = {
130 { -1, gf100_pmu_nofw, &gk104_pmu },
131 {}
132 };
133
134 int
gk104_pmu_new(struct nvkm_device * device,int index,struct nvkm_pmu ** ppmu)135 gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
136 {
137 return nvkm_pmu_new_(gk104_pmu_fwif, device, index, ppmu);
138 }
139