1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11/ { 12 cmn_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 18 cmn_refclk1: clock-cmnrefclk1 { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <0>; 22 }; 23}; 24 25&cbass_main { 26 msmc_ram: sram@70000000 { 27 compatible = "mmio-sram"; 28 reg = <0x0 0x70000000 0x0 0x800000>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 32 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 35 }; 36 }; 37 38 scm_conf: scm-conf@100000 { 39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0x0 0x0 0x00100000 0x1c000>; 44 45 serdes_ln_ctrl: mux@4080 { 46 compatible = "mmio-mux"; 47 reg = <0x00004080 0x50>; 48 #mux-control-cells = <1>; 49 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 50 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 51 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 52 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 53 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 54 /* SERDES4 lane0/1/2/3 select */ 55 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 56 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 57 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 58 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 59 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 60 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 61 }; 62 63 usb_serdes_mux: mux-controller@4000 { 64 compatible = "mmio-mux"; 65 #mux-control-cells = <1>; 66 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 67 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 68 }; 69 }; 70 71 gic500: interrupt-controller@1800000 { 72 compatible = "arm,gic-v3"; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 #interrupt-cells = <3>; 77 interrupt-controller; 78 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 79 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 80 81 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 82 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 83 84 gic_its: msi-controller@1820000 { 85 compatible = "arm,gic-v3-its"; 86 reg = <0x00 0x01820000 0x00 0x10000>; 87 socionext,synquacer-pre-its = <0x1000000 0x400000>; 88 msi-controller; 89 #msi-cells = <1>; 90 }; 91 }; 92 93 main_gpio_intr: interrupt-controller@a00000 { 94 compatible = "ti,sci-intr"; 95 reg = <0x00 0x00a00000 0x00 0x800>; 96 ti,intr-trigger-type = <1>; 97 interrupt-controller; 98 interrupt-parent = <&gic500>; 99 #interrupt-cells = <1>; 100 ti,sci = <&dmsc>; 101 ti,sci-dev-id = <131>; 102 ti,interrupt-ranges = <8 392 56>; 103 }; 104 105 main_navss: bus@30000000 { 106 compatible = "simple-mfd"; 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 110 dma-coherent; 111 dma-ranges; 112 113 ti,sci-dev-id = <199>; 114 115 main_navss_intr: interrupt-controller@310e0000 { 116 compatible = "ti,sci-intr"; 117 reg = <0x0 0x310e0000 0x0 0x4000>; 118 ti,intr-trigger-type = <4>; 119 interrupt-controller; 120 interrupt-parent = <&gic500>; 121 #interrupt-cells = <1>; 122 ti,sci = <&dmsc>; 123 ti,sci-dev-id = <213>; 124 ti,interrupt-ranges = <0 64 64>, 125 <64 448 64>, 126 <128 672 64>; 127 }; 128 129 main_udmass_inta: interrupt-controller@33d00000 { 130 compatible = "ti,sci-inta"; 131 reg = <0x0 0x33d00000 0x0 0x100000>; 132 interrupt-controller; 133 interrupt-parent = <&main_navss_intr>; 134 msi-controller; 135 #interrupt-cells = <0>; 136 ti,sci = <&dmsc>; 137 ti,sci-dev-id = <209>; 138 ti,interrupt-ranges = <0 0 256>; 139 }; 140 141 secure_proxy_main: mailbox@32c00000 { 142 compatible = "ti,am654-secure-proxy"; 143 #mbox-cells = <1>; 144 reg-names = "target_data", "rt", "scfg"; 145 reg = <0x00 0x32c00000 0x00 0x100000>, 146 <0x00 0x32400000 0x00 0x100000>, 147 <0x00 0x32800000 0x00 0x100000>; 148 interrupt-names = "rx_011"; 149 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 smmu0: iommu@36600000 { 153 compatible = "arm,smmu-v3"; 154 reg = <0x0 0x36600000 0x0 0x100000>; 155 interrupt-parent = <&gic500>; 156 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 157 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 158 interrupt-names = "eventq", "gerror"; 159 #iommu-cells = <1>; 160 }; 161 162 hwspinlock: spinlock@30e00000 { 163 compatible = "ti,am654-hwspinlock"; 164 reg = <0x00 0x30e00000 0x00 0x1000>; 165 #hwlock-cells = <1>; 166 }; 167 168 mailbox0_cluster0: mailbox@31f80000 { 169 compatible = "ti,am654-mailbox"; 170 reg = <0x00 0x31f80000 0x00 0x200>; 171 #mbox-cells = <1>; 172 ti,mbox-num-users = <4>; 173 ti,mbox-num-fifos = <16>; 174 interrupt-parent = <&main_navss_intr>; 175 }; 176 177 mailbox0_cluster1: mailbox@31f81000 { 178 compatible = "ti,am654-mailbox"; 179 reg = <0x00 0x31f81000 0x00 0x200>; 180 #mbox-cells = <1>; 181 ti,mbox-num-users = <4>; 182 ti,mbox-num-fifos = <16>; 183 interrupt-parent = <&main_navss_intr>; 184 }; 185 186 mailbox0_cluster2: mailbox@31f82000 { 187 compatible = "ti,am654-mailbox"; 188 reg = <0x00 0x31f82000 0x00 0x200>; 189 #mbox-cells = <1>; 190 ti,mbox-num-users = <4>; 191 ti,mbox-num-fifos = <16>; 192 interrupt-parent = <&main_navss_intr>; 193 }; 194 195 mailbox0_cluster3: mailbox@31f83000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f83000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 }; 203 204 mailbox0_cluster4: mailbox@31f84000 { 205 compatible = "ti,am654-mailbox"; 206 reg = <0x00 0x31f84000 0x00 0x200>; 207 #mbox-cells = <1>; 208 ti,mbox-num-users = <4>; 209 ti,mbox-num-fifos = <16>; 210 interrupt-parent = <&main_navss_intr>; 211 }; 212 213 mailbox0_cluster5: mailbox@31f85000 { 214 compatible = "ti,am654-mailbox"; 215 reg = <0x00 0x31f85000 0x00 0x200>; 216 #mbox-cells = <1>; 217 ti,mbox-num-users = <4>; 218 ti,mbox-num-fifos = <16>; 219 interrupt-parent = <&main_navss_intr>; 220 }; 221 222 mailbox0_cluster6: mailbox@31f86000 { 223 compatible = "ti,am654-mailbox"; 224 reg = <0x00 0x31f86000 0x00 0x200>; 225 #mbox-cells = <1>; 226 ti,mbox-num-users = <4>; 227 ti,mbox-num-fifos = <16>; 228 interrupt-parent = <&main_navss_intr>; 229 }; 230 231 mailbox0_cluster7: mailbox@31f87000 { 232 compatible = "ti,am654-mailbox"; 233 reg = <0x00 0x31f87000 0x00 0x200>; 234 #mbox-cells = <1>; 235 ti,mbox-num-users = <4>; 236 ti,mbox-num-fifos = <16>; 237 interrupt-parent = <&main_navss_intr>; 238 }; 239 240 mailbox0_cluster8: mailbox@31f88000 { 241 compatible = "ti,am654-mailbox"; 242 reg = <0x00 0x31f88000 0x00 0x200>; 243 #mbox-cells = <1>; 244 ti,mbox-num-users = <4>; 245 ti,mbox-num-fifos = <16>; 246 interrupt-parent = <&main_navss_intr>; 247 }; 248 249 mailbox0_cluster9: mailbox@31f89000 { 250 compatible = "ti,am654-mailbox"; 251 reg = <0x00 0x31f89000 0x00 0x200>; 252 #mbox-cells = <1>; 253 ti,mbox-num-users = <4>; 254 ti,mbox-num-fifos = <16>; 255 interrupt-parent = <&main_navss_intr>; 256 }; 257 258 mailbox0_cluster10: mailbox@31f8a000 { 259 compatible = "ti,am654-mailbox"; 260 reg = <0x00 0x31f8a000 0x00 0x200>; 261 #mbox-cells = <1>; 262 ti,mbox-num-users = <4>; 263 ti,mbox-num-fifos = <16>; 264 interrupt-parent = <&main_navss_intr>; 265 }; 266 267 mailbox0_cluster11: mailbox@31f8b000 { 268 compatible = "ti,am654-mailbox"; 269 reg = <0x00 0x31f8b000 0x00 0x200>; 270 #mbox-cells = <1>; 271 ti,mbox-num-users = <4>; 272 ti,mbox-num-fifos = <16>; 273 interrupt-parent = <&main_navss_intr>; 274 }; 275 276 main_ringacc: ringacc@3c000000 { 277 compatible = "ti,am654-navss-ringacc"; 278 reg = <0x0 0x3c000000 0x0 0x400000>, 279 <0x0 0x38000000 0x0 0x400000>, 280 <0x0 0x31120000 0x0 0x100>, 281 <0x0 0x33000000 0x0 0x40000>; 282 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 283 ti,num-rings = <1024>; 284 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 285 ti,sci = <&dmsc>; 286 ti,sci-dev-id = <211>; 287 msi-parent = <&main_udmass_inta>; 288 }; 289 290 main_udmap: dma-controller@31150000 { 291 compatible = "ti,j721e-navss-main-udmap"; 292 reg = <0x0 0x31150000 0x0 0x100>, 293 <0x0 0x34000000 0x0 0x100000>, 294 <0x0 0x35000000 0x0 0x100000>; 295 reg-names = "gcfg", "rchanrt", "tchanrt"; 296 msi-parent = <&main_udmass_inta>; 297 #dma-cells = <1>; 298 299 ti,sci = <&dmsc>; 300 ti,sci-dev-id = <212>; 301 ti,ringacc = <&main_ringacc>; 302 303 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 304 <0x0f>, /* TX_HCHAN */ 305 <0x10>; /* TX_UHCHAN */ 306 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 307 <0x0b>, /* RX_HCHAN */ 308 <0x0c>; /* RX_UHCHAN */ 309 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 310 }; 311 312 cpts@310d0000 { 313 compatible = "ti,j721e-cpts"; 314 reg = <0x0 0x310d0000 0x0 0x400>; 315 reg-names = "cpts"; 316 clocks = <&k3_clks 201 1>; 317 clock-names = "cpts"; 318 interrupts-extended = <&main_navss_intr 391>; 319 interrupt-names = "cpts"; 320 ti,cpts-periodic-outputs = <6>; 321 ti,cpts-ext-ts-inputs = <8>; 322 }; 323 }; 324 325 main_crypto: crypto@4e00000 { 326 compatible = "ti,j721e-sa2ul"; 327 reg = <0x0 0x4e00000 0x0 0x1200>; 328 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 329 #address-cells = <2>; 330 #size-cells = <2>; 331 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 332 333 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 334 <&main_udmap 0x4001>; 335 dma-names = "tx", "rx1", "rx2"; 336 dma-coherent; 337 338 rng: rng@4e10000 { 339 compatible = "inside-secure,safexcel-eip76"; 340 reg = <0x0 0x4e10000 0x0 0x7d>; 341 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&k3_clks 264 1>; 343 }; 344 }; 345 346 main_pmx0: pinctrl@11c000 { 347 compatible = "pinctrl-single"; 348 /* Proxy 0 addressing */ 349 reg = <0x0 0x11c000 0x0 0x2b4>; 350 #pinctrl-cells = <1>; 351 pinctrl-single,register-width = <32>; 352 pinctrl-single,function-mask = <0xffffffff>; 353 }; 354 355 serdes_wiz0: wiz@5000000 { 356 compatible = "ti,j721e-wiz-16g"; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 360 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 361 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 362 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 363 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 364 num-lanes = <2>; 365 #reset-cells = <1>; 366 ranges = <0x5000000 0x0 0x5000000 0x10000>; 367 368 wiz0_pll0_refclk: pll0-refclk { 369 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 370 #clock-cells = <0>; 371 assigned-clocks = <&wiz0_pll0_refclk>; 372 assigned-clock-parents = <&k3_clks 292 11>; 373 }; 374 375 wiz0_pll1_refclk: pll1-refclk { 376 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 377 #clock-cells = <0>; 378 assigned-clocks = <&wiz0_pll1_refclk>; 379 assigned-clock-parents = <&k3_clks 292 0>; 380 }; 381 382 wiz0_refclk_dig: refclk-dig { 383 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 384 #clock-cells = <0>; 385 assigned-clocks = <&wiz0_refclk_dig>; 386 assigned-clock-parents = <&k3_clks 292 11>; 387 }; 388 389 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 390 clocks = <&wiz0_refclk_dig>; 391 #clock-cells = <0>; 392 }; 393 394 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 395 clocks = <&wiz0_pll1_refclk>; 396 #clock-cells = <0>; 397 }; 398 399 serdes0: serdes@5000000 { 400 compatible = "ti,sierra-phy-t0"; 401 reg-names = "serdes"; 402 reg = <0x5000000 0x10000>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 #clock-cells = <1>; 406 resets = <&serdes_wiz0 0>; 407 reset-names = "sierra_reset"; 408 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 409 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 410 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 411 "pll0_refclk", "pll1_refclk"; 412 }; 413 }; 414 415 serdes_wiz1: wiz@5010000 { 416 compatible = "ti,j721e-wiz-16g"; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 421 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 422 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 423 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 424 num-lanes = <2>; 425 #reset-cells = <1>; 426 ranges = <0x5010000 0x0 0x5010000 0x10000>; 427 428 wiz1_pll0_refclk: pll0-refclk { 429 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 430 #clock-cells = <0>; 431 assigned-clocks = <&wiz1_pll0_refclk>; 432 assigned-clock-parents = <&k3_clks 293 13>; 433 }; 434 435 wiz1_pll1_refclk: pll1-refclk { 436 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 437 #clock-cells = <0>; 438 assigned-clocks = <&wiz1_pll1_refclk>; 439 assigned-clock-parents = <&k3_clks 293 0>; 440 }; 441 442 wiz1_refclk_dig: refclk-dig { 443 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 444 #clock-cells = <0>; 445 assigned-clocks = <&wiz1_refclk_dig>; 446 assigned-clock-parents = <&k3_clks 293 13>; 447 }; 448 449 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 450 clocks = <&wiz1_refclk_dig>; 451 #clock-cells = <0>; 452 }; 453 454 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 455 clocks = <&wiz1_pll1_refclk>; 456 #clock-cells = <0>; 457 }; 458 459 serdes1: serdes@5010000 { 460 compatible = "ti,sierra-phy-t0"; 461 reg-names = "serdes"; 462 reg = <0x5010000 0x10000>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 #clock-cells = <1>; 466 resets = <&serdes_wiz1 0>; 467 reset-names = "sierra_reset"; 468 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 469 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 470 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 471 "pll0_refclk", "pll1_refclk"; 472 }; 473 }; 474 475 serdes_wiz2: wiz@5020000 { 476 compatible = "ti,j721e-wiz-16g"; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 480 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 481 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 482 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 483 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 484 num-lanes = <2>; 485 #reset-cells = <1>; 486 ranges = <0x5020000 0x0 0x5020000 0x10000>; 487 488 wiz2_pll0_refclk: pll0-refclk { 489 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 490 #clock-cells = <0>; 491 assigned-clocks = <&wiz2_pll0_refclk>; 492 assigned-clock-parents = <&k3_clks 294 11>; 493 }; 494 495 wiz2_pll1_refclk: pll1-refclk { 496 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 497 #clock-cells = <0>; 498 assigned-clocks = <&wiz2_pll1_refclk>; 499 assigned-clock-parents = <&k3_clks 294 0>; 500 }; 501 502 wiz2_refclk_dig: refclk-dig { 503 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 504 #clock-cells = <0>; 505 assigned-clocks = <&wiz2_refclk_dig>; 506 assigned-clock-parents = <&k3_clks 294 11>; 507 }; 508 509 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 510 clocks = <&wiz2_refclk_dig>; 511 #clock-cells = <0>; 512 }; 513 514 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 515 clocks = <&wiz2_pll1_refclk>; 516 #clock-cells = <0>; 517 }; 518 519 serdes2: serdes@5020000 { 520 compatible = "ti,sierra-phy-t0"; 521 reg-names = "serdes"; 522 reg = <0x5020000 0x10000>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 #clock-cells = <1>; 526 resets = <&serdes_wiz2 0>; 527 reset-names = "sierra_reset"; 528 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 529 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 530 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 531 "pll0_refclk", "pll1_refclk"; 532 }; 533 }; 534 535 serdes_wiz3: wiz@5030000 { 536 compatible = "ti,j721e-wiz-16g"; 537 #address-cells = <1>; 538 #size-cells = <1>; 539 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 541 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 542 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 543 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 544 num-lanes = <2>; 545 #reset-cells = <1>; 546 ranges = <0x5030000 0x0 0x5030000 0x10000>; 547 548 wiz3_pll0_refclk: pll0-refclk { 549 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 550 #clock-cells = <0>; 551 assigned-clocks = <&wiz3_pll0_refclk>; 552 assigned-clock-parents = <&k3_clks 295 9>; 553 }; 554 555 wiz3_pll1_refclk: pll1-refclk { 556 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 557 #clock-cells = <0>; 558 assigned-clocks = <&wiz3_pll1_refclk>; 559 assigned-clock-parents = <&k3_clks 295 0>; 560 }; 561 562 wiz3_refclk_dig: refclk-dig { 563 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 564 #clock-cells = <0>; 565 assigned-clocks = <&wiz3_refclk_dig>; 566 assigned-clock-parents = <&k3_clks 295 9>; 567 }; 568 569 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 570 clocks = <&wiz3_refclk_dig>; 571 #clock-cells = <0>; 572 }; 573 574 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 575 clocks = <&wiz3_pll1_refclk>; 576 #clock-cells = <0>; 577 }; 578 579 serdes3: serdes@5030000 { 580 compatible = "ti,sierra-phy-t0"; 581 reg-names = "serdes"; 582 reg = <0x5030000 0x10000>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 #clock-cells = <1>; 586 resets = <&serdes_wiz3 0>; 587 reset-names = "sierra_reset"; 588 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 589 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 590 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 591 "pll0_refclk", "pll1_refclk"; 592 }; 593 }; 594 595 pcie0_rc: pcie@2900000 { 596 compatible = "ti,j721e-pcie-host"; 597 reg = <0x00 0x02900000 0x00 0x1000>, 598 <0x00 0x02907000 0x00 0x400>, 599 <0x00 0x0d000000 0x00 0x00800000>, 600 <0x00 0x10000000 0x00 0x00001000>; 601 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 602 interrupt-names = "link_state"; 603 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 604 device_type = "pci"; 605 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 606 max-link-speed = <3>; 607 num-lanes = <2>; 608 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 609 clocks = <&k3_clks 239 1>; 610 clock-names = "fck"; 611 #address-cells = <3>; 612 #size-cells = <2>; 613 bus-range = <0x0 0xf>; 614 vendor-id = <0x104c>; 615 device-id = <0xb00d>; 616 msi-map = <0x0 &gic_its 0x0 0x10000>; 617 dma-coherent; 618 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 619 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 620 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 621 }; 622 623 pcie0_ep: pcie-ep@2900000 { 624 compatible = "ti,j721e-pcie-ep"; 625 reg = <0x00 0x02900000 0x00 0x1000>, 626 <0x00 0x02907000 0x00 0x400>, 627 <0x00 0x0d000000 0x00 0x00800000>, 628 <0x00 0x10000000 0x00 0x08000000>; 629 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 630 interrupt-names = "link_state"; 631 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 632 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 633 max-link-speed = <3>; 634 num-lanes = <2>; 635 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 636 clocks = <&k3_clks 239 1>; 637 clock-names = "fck"; 638 max-functions = /bits/ 8 <6>; 639 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 640 dma-coherent; 641 }; 642 643 pcie1_rc: pcie@2910000 { 644 compatible = "ti,j721e-pcie-host"; 645 reg = <0x00 0x02910000 0x00 0x1000>, 646 <0x00 0x02917000 0x00 0x400>, 647 <0x00 0x0d800000 0x00 0x00800000>, 648 <0x00 0x18000000 0x00 0x00001000>; 649 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 650 interrupt-names = "link_state"; 651 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 652 device_type = "pci"; 653 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 654 max-link-speed = <3>; 655 num-lanes = <2>; 656 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 657 clocks = <&k3_clks 240 1>; 658 clock-names = "fck"; 659 #address-cells = <3>; 660 #size-cells = <2>; 661 bus-range = <0x0 0xf>; 662 vendor-id = <0x104c>; 663 device-id = <0xb00d>; 664 msi-map = <0x0 &gic_its 0x10000 0x10000>; 665 dma-coherent; 666 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 667 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 668 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 669 }; 670 671 pcie1_ep: pcie-ep@2910000 { 672 compatible = "ti,j721e-pcie-ep"; 673 reg = <0x00 0x02910000 0x00 0x1000>, 674 <0x00 0x02917000 0x00 0x400>, 675 <0x00 0x0d800000 0x00 0x00800000>, 676 <0x00 0x18000000 0x00 0x08000000>; 677 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 678 interrupt-names = "link_state"; 679 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 680 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 681 max-link-speed = <3>; 682 num-lanes = <2>; 683 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 684 clocks = <&k3_clks 240 1>; 685 clock-names = "fck"; 686 max-functions = /bits/ 8 <6>; 687 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 688 dma-coherent; 689 }; 690 691 pcie2_rc: pcie@2920000 { 692 compatible = "ti,j721e-pcie-host"; 693 reg = <0x00 0x02920000 0x00 0x1000>, 694 <0x00 0x02927000 0x00 0x400>, 695 <0x00 0x0e000000 0x00 0x00800000>, 696 <0x44 0x00000000 0x00 0x00001000>; 697 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 698 interrupt-names = "link_state"; 699 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 700 device_type = "pci"; 701 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 702 max-link-speed = <3>; 703 num-lanes = <2>; 704 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 705 clocks = <&k3_clks 241 1>; 706 clock-names = "fck"; 707 #address-cells = <3>; 708 #size-cells = <2>; 709 bus-range = <0x0 0xf>; 710 vendor-id = <0x104c>; 711 device-id = <0xb00d>; 712 msi-map = <0x0 &gic_its 0x20000 0x10000>; 713 dma-coherent; 714 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 715 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 716 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 717 }; 718 719 pcie2_ep: pcie-ep@2920000 { 720 compatible = "ti,j721e-pcie-ep"; 721 reg = <0x00 0x02920000 0x00 0x1000>, 722 <0x00 0x02927000 0x00 0x400>, 723 <0x00 0x0e000000 0x00 0x00800000>, 724 <0x44 0x00000000 0x00 0x08000000>; 725 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 726 interrupt-names = "link_state"; 727 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 728 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 729 max-link-speed = <3>; 730 num-lanes = <2>; 731 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 732 clocks = <&k3_clks 241 1>; 733 clock-names = "fck"; 734 max-functions = /bits/ 8 <6>; 735 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 736 dma-coherent; 737 }; 738 739 pcie3_rc: pcie@2930000 { 740 compatible = "ti,j721e-pcie-host"; 741 reg = <0x00 0x02930000 0x00 0x1000>, 742 <0x00 0x02937000 0x00 0x400>, 743 <0x00 0x0e800000 0x00 0x00800000>, 744 <0x44 0x10000000 0x00 0x00001000>; 745 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 746 interrupt-names = "link_state"; 747 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 748 device_type = "pci"; 749 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 750 max-link-speed = <3>; 751 num-lanes = <2>; 752 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 753 clocks = <&k3_clks 242 1>; 754 clock-names = "fck"; 755 #address-cells = <3>; 756 #size-cells = <2>; 757 bus-range = <0x0 0xf>; 758 vendor-id = <0x104c>; 759 device-id = <0xb00d>; 760 msi-map = <0x0 &gic_its 0x30000 0x10000>; 761 dma-coherent; 762 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 763 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 764 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 765 }; 766 767 pcie3_ep: pcie-ep@2930000 { 768 compatible = "ti,j721e-pcie-ep"; 769 reg = <0x00 0x02930000 0x00 0x1000>, 770 <0x00 0x02937000 0x00 0x400>, 771 <0x00 0x0e800000 0x00 0x00800000>, 772 <0x44 0x10000000 0x00 0x08000000>; 773 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 774 interrupt-names = "link_state"; 775 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 776 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 777 max-link-speed = <3>; 778 num-lanes = <2>; 779 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 780 clocks = <&k3_clks 242 1>; 781 clock-names = "fck"; 782 max-functions = /bits/ 8 <6>; 783 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; 784 dma-coherent; 785 #address-cells = <2>; 786 #size-cells = <2>; 787 }; 788 789 main_uart0: serial@2800000 { 790 compatible = "ti,j721e-uart", "ti,am654-uart"; 791 reg = <0x00 0x02800000 0x00 0x100>; 792 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 793 clock-frequency = <48000000>; 794 current-speed = <115200>; 795 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 796 clocks = <&k3_clks 146 0>; 797 clock-names = "fclk"; 798 }; 799 800 main_uart1: serial@2810000 { 801 compatible = "ti,j721e-uart", "ti,am654-uart"; 802 reg = <0x00 0x02810000 0x00 0x100>; 803 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 804 clock-frequency = <48000000>; 805 current-speed = <115200>; 806 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 807 clocks = <&k3_clks 278 0>; 808 clock-names = "fclk"; 809 }; 810 811 main_uart2: serial@2820000 { 812 compatible = "ti,j721e-uart", "ti,am654-uart"; 813 reg = <0x00 0x02820000 0x00 0x100>; 814 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 815 clock-frequency = <48000000>; 816 current-speed = <115200>; 817 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 818 clocks = <&k3_clks 279 0>; 819 clock-names = "fclk"; 820 }; 821 822 main_uart3: serial@2830000 { 823 compatible = "ti,j721e-uart", "ti,am654-uart"; 824 reg = <0x00 0x02830000 0x00 0x100>; 825 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 826 clock-frequency = <48000000>; 827 current-speed = <115200>; 828 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 829 clocks = <&k3_clks 280 0>; 830 clock-names = "fclk"; 831 }; 832 833 main_uart4: serial@2840000 { 834 compatible = "ti,j721e-uart", "ti,am654-uart"; 835 reg = <0x00 0x02840000 0x00 0x100>; 836 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 837 clock-frequency = <48000000>; 838 current-speed = <115200>; 839 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 840 clocks = <&k3_clks 281 0>; 841 clock-names = "fclk"; 842 }; 843 844 main_uart5: serial@2850000 { 845 compatible = "ti,j721e-uart", "ti,am654-uart"; 846 reg = <0x00 0x02850000 0x00 0x100>; 847 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 848 clock-frequency = <48000000>; 849 current-speed = <115200>; 850 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 851 clocks = <&k3_clks 282 0>; 852 clock-names = "fclk"; 853 }; 854 855 main_uart6: serial@2860000 { 856 compatible = "ti,j721e-uart", "ti,am654-uart"; 857 reg = <0x00 0x02860000 0x00 0x100>; 858 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 859 clock-frequency = <48000000>; 860 current-speed = <115200>; 861 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 862 clocks = <&k3_clks 283 0>; 863 clock-names = "fclk"; 864 }; 865 866 main_uart7: serial@2870000 { 867 compatible = "ti,j721e-uart", "ti,am654-uart"; 868 reg = <0x00 0x02870000 0x00 0x100>; 869 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 870 clock-frequency = <48000000>; 871 current-speed = <115200>; 872 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&k3_clks 284 0>; 874 clock-names = "fclk"; 875 }; 876 877 main_uart8: serial@2880000 { 878 compatible = "ti,j721e-uart", "ti,am654-uart"; 879 reg = <0x00 0x02880000 0x00 0x100>; 880 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 881 clock-frequency = <48000000>; 882 current-speed = <115200>; 883 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&k3_clks 285 0>; 885 clock-names = "fclk"; 886 }; 887 888 main_uart9: serial@2890000 { 889 compatible = "ti,j721e-uart", "ti,am654-uart"; 890 reg = <0x00 0x02890000 0x00 0x100>; 891 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 892 clock-frequency = <48000000>; 893 current-speed = <115200>; 894 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 895 clocks = <&k3_clks 286 0>; 896 clock-names = "fclk"; 897 }; 898 899 main_gpio0: gpio@600000 { 900 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 901 reg = <0x0 0x00600000 0x0 0x100>; 902 gpio-controller; 903 #gpio-cells = <2>; 904 interrupt-parent = <&main_gpio_intr>; 905 interrupts = <256>, <257>, <258>, <259>, 906 <260>, <261>, <262>, <263>; 907 interrupt-controller; 908 #interrupt-cells = <2>; 909 ti,ngpio = <128>; 910 ti,davinci-gpio-unbanked = <0>; 911 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 912 clocks = <&k3_clks 105 0>; 913 clock-names = "gpio"; 914 }; 915 916 main_gpio1: gpio@601000 { 917 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 918 reg = <0x0 0x00601000 0x0 0x100>; 919 gpio-controller; 920 #gpio-cells = <2>; 921 interrupt-parent = <&main_gpio_intr>; 922 interrupts = <288>, <289>, <290>; 923 interrupt-controller; 924 #interrupt-cells = <2>; 925 ti,ngpio = <36>; 926 ti,davinci-gpio-unbanked = <0>; 927 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 928 clocks = <&k3_clks 106 0>; 929 clock-names = "gpio"; 930 }; 931 932 main_gpio2: gpio@610000 { 933 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 934 reg = <0x0 0x00610000 0x0 0x100>; 935 gpio-controller; 936 #gpio-cells = <2>; 937 interrupt-parent = <&main_gpio_intr>; 938 interrupts = <264>, <265>, <266>, <267>, 939 <268>, <269>, <270>, <271>; 940 interrupt-controller; 941 #interrupt-cells = <2>; 942 ti,ngpio = <128>; 943 ti,davinci-gpio-unbanked = <0>; 944 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 945 clocks = <&k3_clks 107 0>; 946 clock-names = "gpio"; 947 }; 948 949 main_gpio3: gpio@611000 { 950 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 951 reg = <0x0 0x00611000 0x0 0x100>; 952 gpio-controller; 953 #gpio-cells = <2>; 954 interrupt-parent = <&main_gpio_intr>; 955 interrupts = <292>, <293>, <294>; 956 interrupt-controller; 957 #interrupt-cells = <2>; 958 ti,ngpio = <36>; 959 ti,davinci-gpio-unbanked = <0>; 960 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 961 clocks = <&k3_clks 108 0>; 962 clock-names = "gpio"; 963 }; 964 965 main_gpio4: gpio@620000 { 966 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 967 reg = <0x0 0x00620000 0x0 0x100>; 968 gpio-controller; 969 #gpio-cells = <2>; 970 interrupt-parent = <&main_gpio_intr>; 971 interrupts = <272>, <273>, <274>, <275>, 972 <276>, <277>, <278>, <279>; 973 interrupt-controller; 974 #interrupt-cells = <2>; 975 ti,ngpio = <128>; 976 ti,davinci-gpio-unbanked = <0>; 977 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 978 clocks = <&k3_clks 109 0>; 979 clock-names = "gpio"; 980 }; 981 982 main_gpio5: gpio@621000 { 983 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 984 reg = <0x0 0x00621000 0x0 0x100>; 985 gpio-controller; 986 #gpio-cells = <2>; 987 interrupt-parent = <&main_gpio_intr>; 988 interrupts = <296>, <297>, <298>; 989 interrupt-controller; 990 #interrupt-cells = <2>; 991 ti,ngpio = <36>; 992 ti,davinci-gpio-unbanked = <0>; 993 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 994 clocks = <&k3_clks 110 0>; 995 clock-names = "gpio"; 996 }; 997 998 main_gpio6: gpio@630000 { 999 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1000 reg = <0x0 0x00630000 0x0 0x100>; 1001 gpio-controller; 1002 #gpio-cells = <2>; 1003 interrupt-parent = <&main_gpio_intr>; 1004 interrupts = <280>, <281>, <282>, <283>, 1005 <284>, <285>, <286>, <287>; 1006 interrupt-controller; 1007 #interrupt-cells = <2>; 1008 ti,ngpio = <128>; 1009 ti,davinci-gpio-unbanked = <0>; 1010 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1011 clocks = <&k3_clks 111 0>; 1012 clock-names = "gpio"; 1013 }; 1014 1015 main_gpio7: gpio@631000 { 1016 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1017 reg = <0x0 0x00631000 0x0 0x100>; 1018 gpio-controller; 1019 #gpio-cells = <2>; 1020 interrupt-parent = <&main_gpio_intr>; 1021 interrupts = <300>, <301>, <302>; 1022 interrupt-controller; 1023 #interrupt-cells = <2>; 1024 ti,ngpio = <36>; 1025 ti,davinci-gpio-unbanked = <0>; 1026 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1027 clocks = <&k3_clks 112 0>; 1028 clock-names = "gpio"; 1029 }; 1030 1031 main_sdhci0: mmc@4f80000 { 1032 compatible = "ti,j721e-sdhci-8bit"; 1033 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1034 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1035 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1036 clock-names = "clk_ahb", "clk_xin"; 1037 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1038 assigned-clocks = <&k3_clks 91 1>; 1039 assigned-clock-parents = <&k3_clks 91 2>; 1040 bus-width = <8>; 1041 mmc-hs200-1_8v; 1042 mmc-ddr-1_8v; 1043 ti,otap-del-sel-legacy = <0xf>; 1044 ti,otap-del-sel-mmc-hs = <0xf>; 1045 ti,otap-del-sel-ddr52 = <0x5>; 1046 ti,otap-del-sel-hs200 = <0x6>; 1047 ti,otap-del-sel-hs400 = <0x0>; 1048 ti,itap-del-sel-legacy = <0x10>; 1049 ti,itap-del-sel-mmc-hs = <0xa>; 1050 ti,itap-del-sel-ddr52 = <0x3>; 1051 ti,trm-icp = <0x8>; 1052 ti,strobe-sel = <0x77>; 1053 dma-coherent; 1054 }; 1055 1056 main_sdhci1: mmc@4fb0000 { 1057 compatible = "ti,j721e-sdhci-4bit"; 1058 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1059 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1060 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1061 clock-names = "clk_ahb", "clk_xin"; 1062 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1063 assigned-clocks = <&k3_clks 92 0>; 1064 assigned-clock-parents = <&k3_clks 92 1>; 1065 ti,otap-del-sel-legacy = <0x0>; 1066 ti,otap-del-sel-sd-hs = <0xf>; 1067 ti,otap-del-sel-sdr12 = <0xf>; 1068 ti,otap-del-sel-sdr25 = <0xf>; 1069 ti,otap-del-sel-sdr50 = <0xc>; 1070 ti,otap-del-sel-ddr50 = <0xc>; 1071 ti,itap-del-sel-legacy = <0x0>; 1072 ti,itap-del-sel-sd-hs = <0x0>; 1073 ti,itap-del-sel-sdr12 = <0x0>; 1074 ti,itap-del-sel-sdr25 = <0x0>; 1075 ti,itap-del-sel-ddr50 = <0x2>; 1076 ti,trm-icp = <0x8>; 1077 ti,clkbuf-sel = <0x7>; 1078 dma-coherent; 1079 sdhci-caps-mask = <0x2 0x0>; 1080 }; 1081 1082 main_sdhci2: mmc@4f98000 { 1083 compatible = "ti,j721e-sdhci-4bit"; 1084 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1085 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1086 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1087 clock-names = "clk_ahb", "clk_xin"; 1088 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1089 assigned-clocks = <&k3_clks 93 0>; 1090 assigned-clock-parents = <&k3_clks 93 1>; 1091 ti,otap-del-sel-legacy = <0x0>; 1092 ti,otap-del-sel-sd-hs = <0xf>; 1093 ti,otap-del-sel-sdr12 = <0xf>; 1094 ti,otap-del-sel-sdr25 = <0xf>; 1095 ti,otap-del-sel-sdr50 = <0xc>; 1096 ti,otap-del-sel-ddr50 = <0xc>; 1097 ti,itap-del-sel-legacy = <0x0>; 1098 ti,itap-del-sel-sd-hs = <0x0>; 1099 ti,itap-del-sel-sdr12 = <0x0>; 1100 ti,itap-del-sel-sdr25 = <0x0>; 1101 ti,itap-del-sel-ddr50 = <0x2>; 1102 ti,trm-icp = <0x8>; 1103 ti,clkbuf-sel = <0x7>; 1104 dma-coherent; 1105 sdhci-caps-mask = <0x2 0x0>; 1106 }; 1107 1108 usbss0: cdns-usb@4104000 { 1109 compatible = "ti,j721e-usb"; 1110 reg = <0x00 0x4104000 0x00 0x100>; 1111 dma-coherent; 1112 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1113 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1114 clock-names = "ref", "lpm"; 1115 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1116 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1117 #address-cells = <2>; 1118 #size-cells = <2>; 1119 ranges; 1120 1121 usb0: usb@6000000 { 1122 compatible = "cdns,usb3"; 1123 reg = <0x00 0x6000000 0x00 0x10000>, 1124 <0x00 0x6010000 0x00 0x10000>, 1125 <0x00 0x6020000 0x00 0x10000>; 1126 reg-names = "otg", "xhci", "dev"; 1127 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1128 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1129 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1130 interrupt-names = "host", 1131 "peripheral", 1132 "otg"; 1133 maximum-speed = "super-speed"; 1134 dr_mode = "otg"; 1135 }; 1136 }; 1137 1138 usbss1: cdns-usb@4114000 { 1139 compatible = "ti,j721e-usb"; 1140 reg = <0x00 0x4114000 0x00 0x100>; 1141 dma-coherent; 1142 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1143 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1144 clock-names = "ref", "lpm"; 1145 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1146 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1147 #address-cells = <2>; 1148 #size-cells = <2>; 1149 ranges; 1150 1151 usb1: usb@6400000 { 1152 compatible = "cdns,usb3"; 1153 reg = <0x00 0x6400000 0x00 0x10000>, 1154 <0x00 0x6410000 0x00 0x10000>, 1155 <0x00 0x6420000 0x00 0x10000>; 1156 reg-names = "otg", "xhci", "dev"; 1157 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1158 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1159 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1160 interrupt-names = "host", 1161 "peripheral", 1162 "otg"; 1163 maximum-speed = "super-speed"; 1164 dr_mode = "otg"; 1165 }; 1166 }; 1167 1168 main_i2c0: i2c@2000000 { 1169 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1170 reg = <0x0 0x2000000 0x0 0x100>; 1171 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clock-names = "fck"; 1175 clocks = <&k3_clks 187 0>; 1176 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1177 }; 1178 1179 main_i2c1: i2c@2010000 { 1180 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1181 reg = <0x0 0x2010000 0x0 0x100>; 1182 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 clock-names = "fck"; 1186 clocks = <&k3_clks 188 0>; 1187 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1188 }; 1189 1190 main_i2c2: i2c@2020000 { 1191 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1192 reg = <0x0 0x2020000 0x0 0x100>; 1193 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 clock-names = "fck"; 1197 clocks = <&k3_clks 189 0>; 1198 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1199 }; 1200 1201 main_i2c3: i2c@2030000 { 1202 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1203 reg = <0x0 0x2030000 0x0 0x100>; 1204 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 clock-names = "fck"; 1208 clocks = <&k3_clks 190 0>; 1209 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1210 }; 1211 1212 main_i2c4: i2c@2040000 { 1213 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1214 reg = <0x0 0x2040000 0x0 0x100>; 1215 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 clock-names = "fck"; 1219 clocks = <&k3_clks 191 0>; 1220 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1221 }; 1222 1223 main_i2c5: i2c@2050000 { 1224 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1225 reg = <0x0 0x2050000 0x0 0x100>; 1226 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 clock-names = "fck"; 1230 clocks = <&k3_clks 192 0>; 1231 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1232 }; 1233 1234 main_i2c6: i2c@2060000 { 1235 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1236 reg = <0x0 0x2060000 0x0 0x100>; 1237 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 clock-names = "fck"; 1241 clocks = <&k3_clks 193 0>; 1242 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1243 }; 1244 1245 ufs_wrapper: ufs-wrapper@4e80000 { 1246 compatible = "ti,j721e-ufs"; 1247 reg = <0x0 0x4e80000 0x0 0x100>; 1248 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1249 clocks = <&k3_clks 277 1>; 1250 assigned-clocks = <&k3_clks 277 1>; 1251 assigned-clock-parents = <&k3_clks 277 4>; 1252 ranges; 1253 #address-cells = <2>; 1254 #size-cells = <2>; 1255 1256 ufs@4e84000 { 1257 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1258 reg = <0x0 0x4e84000 0x0 0x10000>; 1259 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1260 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1261 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1262 clock-names = "core_clk", "phy_clk", "ref_clk"; 1263 dma-coherent; 1264 }; 1265 }; 1266 1267 dss: dss@4a00000 { 1268 compatible = "ti,j721e-dss"; 1269 reg = 1270 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1271 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1272 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1273 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1274 1275 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1276 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1277 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1278 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1279 1280 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1281 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1282 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1283 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1284 1285 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1286 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1287 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1288 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1289 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1290 1291 reg-names = "common_m", "common_s0", 1292 "common_s1", "common_s2", 1293 "vidl1", "vidl2","vid1","vid2", 1294 "ovr1", "ovr2", "ovr3", "ovr4", 1295 "vp1", "vp2", "vp3", "vp4", 1296 "wb"; 1297 1298 clocks = <&k3_clks 152 0>, 1299 <&k3_clks 152 1>, 1300 <&k3_clks 152 4>, 1301 <&k3_clks 152 9>, 1302 <&k3_clks 152 13>; 1303 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1304 1305 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1306 1307 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1311 interrupt-names = "common_m", 1312 "common_s0", 1313 "common_s1", 1314 "common_s2"; 1315 1316 dss_ports: ports { 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 }; 1320 }; 1321 1322 mcasp0: mcasp@2b00000 { 1323 compatible = "ti,am33xx-mcasp-audio"; 1324 reg = <0x0 0x02b00000 0x0 0x2000>, 1325 <0x0 0x02b08000 0x0 0x1000>; 1326 reg-names = "mpu","dat"; 1327 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupt-names = "tx", "rx"; 1330 1331 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1332 dma-names = "tx", "rx"; 1333 1334 clocks = <&k3_clks 174 1>; 1335 clock-names = "fck"; 1336 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1337 }; 1338 1339 mcasp1: mcasp@2b10000 { 1340 compatible = "ti,am33xx-mcasp-audio"; 1341 reg = <0x0 0x02b10000 0x0 0x2000>, 1342 <0x0 0x02b18000 0x0 0x1000>; 1343 reg-names = "mpu","dat"; 1344 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1346 interrupt-names = "tx", "rx"; 1347 1348 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1349 dma-names = "tx", "rx"; 1350 1351 clocks = <&k3_clks 175 1>; 1352 clock-names = "fck"; 1353 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1354 }; 1355 1356 mcasp2: mcasp@2b20000 { 1357 compatible = "ti,am33xx-mcasp-audio"; 1358 reg = <0x0 0x02b20000 0x0 0x2000>, 1359 <0x0 0x02b28000 0x0 0x1000>; 1360 reg-names = "mpu","dat"; 1361 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1363 interrupt-names = "tx", "rx"; 1364 1365 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1366 dma-names = "tx", "rx"; 1367 1368 clocks = <&k3_clks 176 1>; 1369 clock-names = "fck"; 1370 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1371 }; 1372 1373 mcasp3: mcasp@2b30000 { 1374 compatible = "ti,am33xx-mcasp-audio"; 1375 reg = <0x0 0x02b30000 0x0 0x2000>, 1376 <0x0 0x02b38000 0x0 0x1000>; 1377 reg-names = "mpu","dat"; 1378 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1380 interrupt-names = "tx", "rx"; 1381 1382 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1383 dma-names = "tx", "rx"; 1384 1385 clocks = <&k3_clks 177 1>; 1386 clock-names = "fck"; 1387 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1388 }; 1389 1390 mcasp4: mcasp@2b40000 { 1391 compatible = "ti,am33xx-mcasp-audio"; 1392 reg = <0x0 0x02b40000 0x0 0x2000>, 1393 <0x0 0x02b48000 0x0 0x1000>; 1394 reg-names = "mpu","dat"; 1395 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1397 interrupt-names = "tx", "rx"; 1398 1399 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1400 dma-names = "tx", "rx"; 1401 1402 clocks = <&k3_clks 178 1>; 1403 clock-names = "fck"; 1404 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1405 }; 1406 1407 mcasp5: mcasp@2b50000 { 1408 compatible = "ti,am33xx-mcasp-audio"; 1409 reg = <0x0 0x02b50000 0x0 0x2000>, 1410 <0x0 0x02b58000 0x0 0x1000>; 1411 reg-names = "mpu","dat"; 1412 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1414 interrupt-names = "tx", "rx"; 1415 1416 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1417 dma-names = "tx", "rx"; 1418 1419 clocks = <&k3_clks 179 1>; 1420 clock-names = "fck"; 1421 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1422 }; 1423 1424 mcasp6: mcasp@2b60000 { 1425 compatible = "ti,am33xx-mcasp-audio"; 1426 reg = <0x0 0x02b60000 0x0 0x2000>, 1427 <0x0 0x02b68000 0x0 0x1000>; 1428 reg-names = "mpu","dat"; 1429 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1431 interrupt-names = "tx", "rx"; 1432 1433 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1434 dma-names = "tx", "rx"; 1435 1436 clocks = <&k3_clks 180 1>; 1437 clock-names = "fck"; 1438 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1439 }; 1440 1441 mcasp7: mcasp@2b70000 { 1442 compatible = "ti,am33xx-mcasp-audio"; 1443 reg = <0x0 0x02b70000 0x0 0x2000>, 1444 <0x0 0x02b78000 0x0 0x1000>; 1445 reg-names = "mpu","dat"; 1446 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1448 interrupt-names = "tx", "rx"; 1449 1450 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1451 dma-names = "tx", "rx"; 1452 1453 clocks = <&k3_clks 181 1>; 1454 clock-names = "fck"; 1455 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1456 }; 1457 1458 mcasp8: mcasp@2b80000 { 1459 compatible = "ti,am33xx-mcasp-audio"; 1460 reg = <0x0 0x02b80000 0x0 0x2000>, 1461 <0x0 0x02b88000 0x0 0x1000>; 1462 reg-names = "mpu","dat"; 1463 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1465 interrupt-names = "tx", "rx"; 1466 1467 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1468 dma-names = "tx", "rx"; 1469 1470 clocks = <&k3_clks 182 1>; 1471 clock-names = "fck"; 1472 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1473 }; 1474 1475 mcasp9: mcasp@2b90000 { 1476 compatible = "ti,am33xx-mcasp-audio"; 1477 reg = <0x0 0x02b90000 0x0 0x2000>, 1478 <0x0 0x02b98000 0x0 0x1000>; 1479 reg-names = "mpu","dat"; 1480 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1482 interrupt-names = "tx", "rx"; 1483 1484 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1485 dma-names = "tx", "rx"; 1486 1487 clocks = <&k3_clks 183 1>; 1488 clock-names = "fck"; 1489 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1490 }; 1491 1492 mcasp10: mcasp@2ba0000 { 1493 compatible = "ti,am33xx-mcasp-audio"; 1494 reg = <0x0 0x02ba0000 0x0 0x2000>, 1495 <0x0 0x02ba8000 0x0 0x1000>; 1496 reg-names = "mpu","dat"; 1497 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1499 interrupt-names = "tx", "rx"; 1500 1501 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1502 dma-names = "tx", "rx"; 1503 1504 clocks = <&k3_clks 184 1>; 1505 clock-names = "fck"; 1506 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1507 }; 1508 1509 mcasp11: mcasp@2bb0000 { 1510 compatible = "ti,am33xx-mcasp-audio"; 1511 reg = <0x0 0x02bb0000 0x0 0x2000>, 1512 <0x0 0x02bb8000 0x0 0x1000>; 1513 reg-names = "mpu","dat"; 1514 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1516 interrupt-names = "tx", "rx"; 1517 1518 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1519 dma-names = "tx", "rx"; 1520 1521 clocks = <&k3_clks 185 1>; 1522 clock-names = "fck"; 1523 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1524 }; 1525 1526 watchdog0: watchdog@2200000 { 1527 compatible = "ti,j7-rti-wdt"; 1528 reg = <0x0 0x2200000 0x0 0x100>; 1529 clocks = <&k3_clks 252 1>; 1530 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1531 assigned-clocks = <&k3_clks 252 1>; 1532 assigned-clock-parents = <&k3_clks 252 5>; 1533 }; 1534 1535 watchdog1: watchdog@2210000 { 1536 compatible = "ti,j7-rti-wdt"; 1537 reg = <0x0 0x2210000 0x0 0x100>; 1538 clocks = <&k3_clks 253 1>; 1539 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1540 assigned-clocks = <&k3_clks 253 1>; 1541 assigned-clock-parents = <&k3_clks 253 5>; 1542 }; 1543 1544 main_r5fss0: r5fss@5c00000 { 1545 compatible = "ti,j721e-r5fss"; 1546 ti,cluster-mode = <1>; 1547 #address-cells = <1>; 1548 #size-cells = <1>; 1549 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1550 <0x5d00000 0x00 0x5d00000 0x20000>; 1551 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1552 1553 main_r5fss0_core0: r5f@5c00000 { 1554 compatible = "ti,j721e-r5f"; 1555 reg = <0x5c00000 0x00008000>, 1556 <0x5c10000 0x00008000>; 1557 reg-names = "atcm", "btcm"; 1558 ti,sci = <&dmsc>; 1559 ti,sci-dev-id = <245>; 1560 ti,sci-proc-ids = <0x06 0xff>; 1561 resets = <&k3_reset 245 1>; 1562 firmware-name = "j7-main-r5f0_0-fw"; 1563 ti,atcm-enable = <1>; 1564 ti,btcm-enable = <1>; 1565 ti,loczrama = <1>; 1566 }; 1567 1568 main_r5fss0_core1: r5f@5d00000 { 1569 compatible = "ti,j721e-r5f"; 1570 reg = <0x5d00000 0x00008000>, 1571 <0x5d10000 0x00008000>; 1572 reg-names = "atcm", "btcm"; 1573 ti,sci = <&dmsc>; 1574 ti,sci-dev-id = <246>; 1575 ti,sci-proc-ids = <0x07 0xff>; 1576 resets = <&k3_reset 246 1>; 1577 firmware-name = "j7-main-r5f0_1-fw"; 1578 ti,atcm-enable = <1>; 1579 ti,btcm-enable = <1>; 1580 ti,loczrama = <1>; 1581 }; 1582 }; 1583 1584 main_r5fss1: r5fss@5e00000 { 1585 compatible = "ti,j721e-r5fss"; 1586 ti,cluster-mode = <1>; 1587 #address-cells = <1>; 1588 #size-cells = <1>; 1589 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1590 <0x5f00000 0x00 0x5f00000 0x20000>; 1591 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1592 1593 main_r5fss1_core0: r5f@5e00000 { 1594 compatible = "ti,j721e-r5f"; 1595 reg = <0x5e00000 0x00008000>, 1596 <0x5e10000 0x00008000>; 1597 reg-names = "atcm", "btcm"; 1598 ti,sci = <&dmsc>; 1599 ti,sci-dev-id = <247>; 1600 ti,sci-proc-ids = <0x08 0xff>; 1601 resets = <&k3_reset 247 1>; 1602 firmware-name = "j7-main-r5f1_0-fw"; 1603 ti,atcm-enable = <1>; 1604 ti,btcm-enable = <1>; 1605 ti,loczrama = <1>; 1606 }; 1607 1608 main_r5fss1_core1: r5f@5f00000 { 1609 compatible = "ti,j721e-r5f"; 1610 reg = <0x5f00000 0x00008000>, 1611 <0x5f10000 0x00008000>; 1612 reg-names = "atcm", "btcm"; 1613 ti,sci = <&dmsc>; 1614 ti,sci-dev-id = <248>; 1615 ti,sci-proc-ids = <0x09 0xff>; 1616 resets = <&k3_reset 248 1>; 1617 firmware-name = "j7-main-r5f1_1-fw"; 1618 ti,atcm-enable = <1>; 1619 ti,btcm-enable = <1>; 1620 ti,loczrama = <1>; 1621 }; 1622 }; 1623 1624 c66_0: dsp@4d80800000 { 1625 compatible = "ti,j721e-c66-dsp"; 1626 reg = <0x4d 0x80800000 0x00 0x00048000>, 1627 <0x4d 0x80e00000 0x00 0x00008000>, 1628 <0x4d 0x80f00000 0x00 0x00008000>; 1629 reg-names = "l2sram", "l1pram", "l1dram"; 1630 ti,sci = <&dmsc>; 1631 ti,sci-dev-id = <142>; 1632 ti,sci-proc-ids = <0x03 0xff>; 1633 resets = <&k3_reset 142 1>; 1634 firmware-name = "j7-c66_0-fw"; 1635 }; 1636 1637 c66_1: dsp@4d81800000 { 1638 compatible = "ti,j721e-c66-dsp"; 1639 reg = <0x4d 0x81800000 0x00 0x00048000>, 1640 <0x4d 0x81e00000 0x00 0x00008000>, 1641 <0x4d 0x81f00000 0x00 0x00008000>; 1642 reg-names = "l2sram", "l1pram", "l1dram"; 1643 ti,sci = <&dmsc>; 1644 ti,sci-dev-id = <143>; 1645 ti,sci-proc-ids = <0x04 0xff>; 1646 resets = <&k3_reset 143 1>; 1647 firmware-name = "j7-c66_1-fw"; 1648 }; 1649 1650 c71_0: dsp@64800000 { 1651 compatible = "ti,j721e-c71-dsp"; 1652 reg = <0x00 0x64800000 0x00 0x00080000>, 1653 <0x00 0x64e00000 0x00 0x0000c000>; 1654 reg-names = "l2sram", "l1dram"; 1655 ti,sci = <&dmsc>; 1656 ti,sci-dev-id = <15>; 1657 ti,sci-proc-ids = <0x30 0xff>; 1658 resets = <&k3_reset 15 1>; 1659 firmware-name = "j7-c71_0-fw"; 1660 }; 1661 1662 icssg0: icssg@b000000 { 1663 compatible = "ti,j721e-icssg"; 1664 reg = <0x00 0xb000000 0x00 0x80000>; 1665 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 1666 #address-cells = <1>; 1667 #size-cells = <1>; 1668 ranges = <0x0 0x00 0x0b000000 0x100000>; 1669 1670 icssg0_mem: memories@0 { 1671 reg = <0x0 0x2000>, 1672 <0x2000 0x2000>, 1673 <0x10000 0x10000>; 1674 reg-names = "dram0", "dram1", 1675 "shrdram2"; 1676 }; 1677 1678 icssg0_cfg: cfg@26000 { 1679 compatible = "ti,pruss-cfg", "syscon"; 1680 reg = <0x26000 0x200>; 1681 #address-cells = <1>; 1682 #size-cells = <1>; 1683 ranges = <0x0 0x26000 0x2000>; 1684 1685 clocks { 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 1689 icssg0_coreclk_mux: coreclk-mux@3c { 1690 reg = <0x3c>; 1691 #clock-cells = <0>; 1692 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 1693 <&k3_clks 119 1>; /* icssg0_iclk */ 1694 assigned-clocks = <&icssg0_coreclk_mux>; 1695 assigned-clock-parents = <&k3_clks 119 1>; 1696 }; 1697 1698 icssg0_iepclk_mux: iepclk-mux@30 { 1699 reg = <0x30>; 1700 #clock-cells = <0>; 1701 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 1702 <&icssg0_coreclk_mux>; /* core_clk */ 1703 assigned-clocks = <&icssg0_iepclk_mux>; 1704 assigned-clock-parents = <&icssg0_coreclk_mux>; 1705 }; 1706 }; 1707 }; 1708 1709 icssg0_mii_rt: mii-rt@32000 { 1710 compatible = "ti,pruss-mii", "syscon"; 1711 reg = <0x32000 0x100>; 1712 }; 1713 1714 icssg0_mii_g_rt: mii-g-rt@33000 { 1715 compatible = "ti,pruss-mii-g", "syscon"; 1716 reg = <0x33000 0x1000>; 1717 }; 1718 1719 icssg0_intc: interrupt-controller@20000 { 1720 compatible = "ti,icssg-intc"; 1721 reg = <0x20000 0x2000>; 1722 interrupt-controller; 1723 #interrupt-cells = <3>; 1724 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1732 interrupt-names = "host_intr0", "host_intr1", 1733 "host_intr2", "host_intr3", 1734 "host_intr4", "host_intr5", 1735 "host_intr6", "host_intr7"; 1736 }; 1737 1738 pru0_0: pru@34000 { 1739 compatible = "ti,j721e-pru"; 1740 reg = <0x34000 0x3000>, 1741 <0x22000 0x100>, 1742 <0x22400 0x100>; 1743 reg-names = "iram", "control", "debug"; 1744 firmware-name = "j7-pru0_0-fw"; 1745 }; 1746 1747 rtu0_0: rtu@4000 { 1748 compatible = "ti,j721e-rtu"; 1749 reg = <0x4000 0x2000>, 1750 <0x23000 0x100>, 1751 <0x23400 0x100>; 1752 reg-names = "iram", "control", "debug"; 1753 firmware-name = "j7-rtu0_0-fw"; 1754 }; 1755 1756 tx_pru0_0: txpru@a000 { 1757 compatible = "ti,j721e-tx-pru"; 1758 reg = <0xa000 0x1800>, 1759 <0x25000 0x100>, 1760 <0x25400 0x100>; 1761 reg-names = "iram", "control", "debug"; 1762 firmware-name = "j7-txpru0_0-fw"; 1763 }; 1764 1765 pru0_1: pru@38000 { 1766 compatible = "ti,j721e-pru"; 1767 reg = <0x38000 0x3000>, 1768 <0x24000 0x100>, 1769 <0x24400 0x100>; 1770 reg-names = "iram", "control", "debug"; 1771 firmware-name = "j7-pru0_1-fw"; 1772 }; 1773 1774 rtu0_1: rtu@6000 { 1775 compatible = "ti,j721e-rtu"; 1776 reg = <0x6000 0x2000>, 1777 <0x23800 0x100>, 1778 <0x23c00 0x100>; 1779 reg-names = "iram", "control", "debug"; 1780 firmware-name = "j7-rtu0_1-fw"; 1781 }; 1782 1783 tx_pru0_1: txpru@c000 { 1784 compatible = "ti,j721e-tx-pru"; 1785 reg = <0xc000 0x1800>, 1786 <0x25800 0x100>, 1787 <0x25c00 0x100>; 1788 reg-names = "iram", "control", "debug"; 1789 firmware-name = "j7-txpru0_1-fw"; 1790 }; 1791 1792 icssg0_mdio: mdio@32400 { 1793 compatible = "ti,davinci_mdio"; 1794 reg = <0x32400 0x100>; 1795 clocks = <&k3_clks 119 1>; 1796 clock-names = "fck"; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 bus_freq = <1000000>; 1800 }; 1801 }; 1802 1803 icssg1: icssg@b100000 { 1804 compatible = "ti,j721e-icssg"; 1805 reg = <0x00 0xb100000 0x00 0x80000>; 1806 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 1807 #address-cells = <1>; 1808 #size-cells = <1>; 1809 ranges = <0x0 0x00 0x0b100000 0x100000>; 1810 1811 icssg1_mem: memories@b100000 { 1812 reg = <0x0 0x2000>, 1813 <0x2000 0x2000>, 1814 <0x10000 0x10000>; 1815 reg-names = "dram0", "dram1", 1816 "shrdram2"; 1817 }; 1818 1819 icssg1_cfg: cfg@26000 { 1820 compatible = "ti,pruss-cfg", "syscon"; 1821 reg = <0x26000 0x200>; 1822 #address-cells = <1>; 1823 #size-cells = <1>; 1824 ranges = <0x0 0x26000 0x2000>; 1825 1826 clocks { 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 1830 icssg1_coreclk_mux: coreclk-mux@3c { 1831 reg = <0x3c>; 1832 #clock-cells = <0>; 1833 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 1834 <&k3_clks 120 4>; /* icssg1_iclk */ 1835 assigned-clocks = <&icssg1_coreclk_mux>; 1836 assigned-clock-parents = <&k3_clks 120 4>; 1837 }; 1838 1839 icssg1_iepclk_mux: iepclk-mux@30 { 1840 reg = <0x30>; 1841 #clock-cells = <0>; 1842 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 1843 <&icssg1_coreclk_mux>; /* core_clk */ 1844 assigned-clocks = <&icssg1_iepclk_mux>; 1845 assigned-clock-parents = <&icssg1_coreclk_mux>; 1846 }; 1847 }; 1848 }; 1849 1850 icssg1_mii_rt: mii-rt@32000 { 1851 compatible = "ti,pruss-mii", "syscon"; 1852 reg = <0x32000 0x100>; 1853 }; 1854 1855 icssg1_mii_g_rt: mii-g-rt@33000 { 1856 compatible = "ti,pruss-mii-g", "syscon"; 1857 reg = <0x33000 0x1000>; 1858 }; 1859 1860 icssg1_intc: interrupt-controller@20000 { 1861 compatible = "ti,icssg-intc"; 1862 reg = <0x20000 0x2000>; 1863 interrupt-controller; 1864 #interrupt-cells = <3>; 1865 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1873 interrupt-names = "host_intr0", "host_intr1", 1874 "host_intr2", "host_intr3", 1875 "host_intr4", "host_intr5", 1876 "host_intr6", "host_intr7"; 1877 }; 1878 1879 pru1_0: pru@34000 { 1880 compatible = "ti,j721e-pru"; 1881 reg = <0x34000 0x4000>, 1882 <0x22000 0x100>, 1883 <0x22400 0x100>; 1884 reg-names = "iram", "control", "debug"; 1885 firmware-name = "j7-pru1_0-fw"; 1886 }; 1887 1888 rtu1_0: rtu@4000 { 1889 compatible = "ti,j721e-rtu"; 1890 reg = <0x4000 0x2000>, 1891 <0x23000 0x100>, 1892 <0x23400 0x100>; 1893 reg-names = "iram", "control", "debug"; 1894 firmware-name = "j7-rtu1_0-fw"; 1895 }; 1896 1897 tx_pru1_0: txpru@a000 { 1898 compatible = "ti,j721e-tx-pru"; 1899 reg = <0xa000 0x1800>, 1900 <0x25000 0x100>, 1901 <0x25400 0x100>; 1902 reg-names = "iram", "control", "debug"; 1903 firmware-name = "j7-txpru1_0-fw"; 1904 }; 1905 1906 pru1_1: pru@38000 { 1907 compatible = "ti,j721e-pru"; 1908 reg = <0x38000 0x4000>, 1909 <0x24000 0x100>, 1910 <0x24400 0x100>; 1911 reg-names = "iram", "control", "debug"; 1912 firmware-name = "j7-pru1_1-fw"; 1913 }; 1914 1915 rtu1_1: rtu@6000 { 1916 compatible = "ti,j721e-rtu"; 1917 reg = <0x6000 0x2000>, 1918 <0x23800 0x100>, 1919 <0x23c00 0x100>; 1920 reg-names = "iram", "control", "debug"; 1921 firmware-name = "j7-rtu1_1-fw"; 1922 }; 1923 1924 tx_pru1_1: txpru@c000 { 1925 compatible = "ti,j721e-tx-pru"; 1926 reg = <0xc000 0x1800>, 1927 <0x25800 0x100>, 1928 <0x25c00 0x100>; 1929 reg-names = "iram", "control", "debug"; 1930 firmware-name = "j7-txpru1_1-fw"; 1931 }; 1932 1933 icssg1_mdio: mdio@32400 { 1934 compatible = "ti,davinci_mdio"; 1935 reg = <0x32400 0x100>; 1936 clocks = <&k3_clks 120 4>; 1937 clock-names = "fck"; 1938 #address-cells = <1>; 1939 #size-cells = <0>; 1940 bus_freq = <1000000>; 1941 }; 1942 }; 1943}; 1944