1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __gm200_dev_boot_h__ 25 #define __gm200_dev_boot_h__ 26 #define NV_PMC_ENABLE 0x00000200 /* RW-4R */ 27 #define NV_PMC_ENABLE_PMEDIA 4:4 /* */ 28 #define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ 29 #define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ 30 #define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ 31 #define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ 32 #define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ 33 #define NV_PMC_ENABLE_PWR 13:13 /* */ 34 #define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ 35 #define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ 36 #define NV_PMC_ENABLE_PGRAPH 12:12 /* */ 37 #define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ 38 #define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ 39 #define NV_PMC_ENABLE_SEC 14:14 /* */ 40 #define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ 41 #define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ 42 #define NV_PMC_ENABLE_CE0 6:6 /* */ 43 #define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ 44 #define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ 45 #define NV_PMC_ENABLE_CE1 7:7 /* */ 46 #define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ 47 #define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ 48 #define NV_PMC_ENABLE_CE2 21:21 /* */ 49 #define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ 50 #define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ 51 #define NV_PMC_ENABLE_NVDEC 15:15 /* */ 52 #define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ 53 #define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ 54 #define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ 55 #define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ 56 #define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ 57 #define NV_PMC_ENABLE_NVENC0 18:18 /* */ 58 #define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ 59 #define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ 60 #define NV_PMC_ENABLE_NVENC1 19:19 /* */ 61 #define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ 62 #define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ 63 #endif // __gm200_dev_boot_h__ 64