1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _cl00de_h_ 25 #define _cl00de_h_ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #include "nvmisc.h" 32 #include "nvfixedtypes.h" 33 34 #define RM_USER_SHARED_DATA (0x000000de) 35 36 #define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX) 37 #define RUSD_TIMESTAMP_INVALID 0 38 39 // seq = c_0 * b_0 + c_1 * (b_0 - 1) where c_0 == open_count and c_1 == close_count 40 // When they are equal, data is valid, otherwise data is being written. 41 // b_0 == 1 mod (b_0 - 1) and b_0 - 1 == (-1) mod b_0 42 // So, c_0 == seq mod (b_0 - 1) and c_1 == (-1 * seq) mod b_0 43 // c_1 cannot be calculated quite so naively because negative modulos aren't fun, so we 44 // instead do c_1 == (b_0 - (seq mod b_0)) mod b_0 45 // 46 #define RUSD_SEQ_BASE_SHIFT 20llu 47 #define RUSD_SEQ_BASE0 (1llu << RUSD_SEQ_BASE_SHIFT) 48 #define RUSD_SEQ_BASE1 (RUSD_SEQ_BASE0 - 1llu) 49 #define RUSD_SEQ_COEFF1(x) ((RUSD_SEQ_BASE0 - ((x) % RUSD_SEQ_BASE0)) % RUSD_SEQ_BASE0) 50 #define RUSD_SEQ_COEFF0(x) ((x) % RUSD_SEQ_BASE1) 51 #define RUSD_SEQ_WRAP_SHIFT 18llu 52 #define RUSD_SEQ_WRAP_VAL (1llu << RUSD_SEQ_WRAP_SHIFT) 53 #define RUSD_SEQ_DATA_VALID(x) (RUSD_SEQ_COEFF0(x) == RUSD_SEQ_COEFF1(x)) 54 55 // 56 // Helper macros to check seq before reading RUSD. 57 // No dowhile wrap as it is using continue/break 58 // 59 #define RUSD_SEQ_CHECK1(SHARED_DATA) \ 60 NvU64 seq = (SHARED_DATA)->seq; \ 61 portAtomicMemoryFenceLoad(); \ 62 if (!RUSD_SEQ_DATA_VALID(seq)) \ 63 continue; 64 65 #define RUSD_SEQ_CHECK2(SHARED_DATA) \ 66 portAtomicMemoryFenceLoad(); \ 67 if (seq == (SHARED_DATA)->seq) \ 68 break; 69 70 enum { 71 RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0, 72 RUSD_CLK_PUBLIC_DOMAIN_MEMORY, 73 RUSD_CLK_PUBLIC_DOMAIN_VIDEO, 74 75 // Put at the end. See bug 1000230 NVML doesn't report SM frequency on Kepler 76 RUSD_CLK_PUBLIC_DOMAIN_SM, 77 RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE, 78 }; 79 80 enum { 81 RUSD_CLK_THROTTLE_REASON_GPU_IDLE = NVBIT(0), 82 RUSD_CLK_THROTTLE_REASON_APPLICATION_CLOCK_SETTING = NVBIT(1), 83 RUSD_CLK_THROTTLE_REASON_SW_POWER_CAP = NVBIT(2), 84 RUSD_CLK_THROTTLE_REASON_HW_SLOWDOWN = NVBIT(3), 85 RUSD_CLK_THROTTLE_REASON_SYNC_BOOST = NVBIT(4), 86 RUSD_CLK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN = NVBIT(5), 87 RUSD_CLK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN = NVBIT(6), 88 RUSD_CLK_THROTTLE_REASON_HW_POWER_BRAKES_SLOWDOWN = NVBIT(7), 89 RUSD_CLK_THROTTLE_REASON_DISPLAY_CLOCK_SETTING = NVBIT(8), 90 }; 91 92 typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO { 93 NvU32 targetClkMHz; 94 } RUSD_CLK_PUBLIC_DOMAIN_INFO; 95 96 typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFOS { 97 volatile NvU64 lastModifiedTimestamp; 98 RUSD_CLK_PUBLIC_DOMAIN_INFO info[RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE]; 99 } RUSD_CLK_PUBLIC_DOMAIN_INFOS; 100 101 typedef struct RUSD_PERF_DEVICE_UTILIZATION_INFO { 102 NvU8 gpuPercentBusy; 103 NvU8 memoryPercentBusy; 104 } RUSD_PERF_DEVICE_UTILIZATION_INFO; 105 106 typedef struct RUSD_PERF_DEVICE_UTILIZATION { 107 volatile NvU64 lastModifiedTimestamp; 108 RUSD_PERF_DEVICE_UTILIZATION_INFO info; 109 } RUSD_PERF_DEVICE_UTILIZATION; 110 111 typedef struct RUSD_PERF_CURRENT_PSTATE { 112 volatile NvU64 lastModifiedTimestamp; 113 NvU32 currentPstate; 114 } RUSD_PERF_CURRENT_PSTATE; 115 116 typedef struct RUSD_CLK_THROTTLE_REASON { 117 volatile NvU64 lastModifiedTimestamp; 118 NvU32 reasonMask; 119 } RUSD_CLK_THROTTLE_REASON; 120 121 typedef struct RUSD_MEM_ERROR_COUNTS { 122 NvU64 correctedVolatile; 123 NvU64 correctedAggregate; 124 NvU64 uncorrectedVolatile; 125 NvU64 uncorrectedAggregate; 126 } RUSD_MEM_ERROR_COUNTS; 127 128 #define RUSD_MEMORY_ERROR_TYPE_TOTAL 0 129 #define RUSD_MEMORY_ERROR_TYPE_DRAM 1 130 #define RUSD_MEMORY_ERROR_TYPE_SRAM 2 131 #define RUSD_MEMORY_ERROR_TYPE_COUNT 3 132 133 typedef struct RUSD_MEM_ECC { 134 volatile NvU64 lastModifiedTimestamp; 135 RUSD_MEM_ERROR_COUNTS count[RUSD_MEMORY_ERROR_TYPE_COUNT]; 136 } RUSD_MEM_ECC; 137 138 typedef struct RUSD_POWER_LIMIT_INFO { 139 NvU32 requestedmW; 140 NvU32 enforcedmW; 141 } RUSD_POWER_LIMIT_INFO; 142 143 typedef struct RUSD_ENFORCED_POWER_LIMITS { 144 volatile NvU64 lastModifiedTimestamp; 145 RUSD_POWER_LIMIT_INFO info; 146 } RUSD_POWER_LIMITS; 147 148 typedef struct RUSD_TEMPERATURE_INFO{ 149 NvTemp gpuTemperature; 150 NvTemp hbmTemperature; 151 } RUSD_TEMPERATURE_INFO; 152 153 typedef struct RUSD_TEMPERATURE { 154 volatile NvU64 lastModifiedTimestamp; 155 RUSD_TEMPERATURE_INFO info; 156 } RUSD_TEMPERATURE; 157 158 typedef struct RUSD_MEM_ROW_REMAP_INFO { 159 NvU32 histogramMax; // No remapped row is used. 160 NvU32 histogramHigh; // One remapped row is used. 161 NvU32 histogramPartial; // More than one remapped rows are used. 162 NvU32 histogramLow; // One remapped row is available. 163 NvU32 histogramNone; // All remapped rows are used. 164 165 NvU32 correctableRows; 166 NvU32 uncorrectableRows; 167 NvBool isPending; 168 NvBool hasFailureOccurred; 169 } RUSD_MEM_ROW_REMAP_INFO; 170 171 typedef struct RUSD_MEM_ROW_REMAP { 172 volatile NvU64 lastModifiedTimestamp; 173 RUSD_MEM_ROW_REMAP_INFO info; 174 } RUSD_MEM_ROW_REMAP; 175 176 typedef struct RUSD_AVG_POWER_INFO { 177 NvU32 averageGpuPower; // mW 178 NvU32 averageModulePower; // mW 179 NvU32 averageMemoryPower; // mW 180 } RUSD_AVG_POWER_INFO; 181 182 typedef struct RUSD_AVG_POWER_USAGE { 183 volatile NvU64 lastModifiedTimestamp; 184 RUSD_AVG_POWER_INFO info; 185 } RUSD_AVG_POWER_USAGE; 186 187 typedef struct RUSD_INST_POWER_INFO { 188 NvU32 instGpuPower; // mW 189 NvU32 instModulePower; // mW 190 } RUSD_INST_POWER_INFO; 191 192 typedef struct RUSD_INST_POWER_USAGE { 193 volatile NvU64 lastModifiedTimestamp; 194 RUSD_INST_POWER_INFO info; 195 } RUSD_INST_POWER_USAGE; 196 197 typedef struct NV00DE_SHARED_DATA { 198 volatile NvU64 seq; 199 200 NvU32 bar1Size; 201 NvU32 bar1AvailSize; 202 NvU64 totalPmaMemory; 203 NvU64 freePmaMemory; 204 205 // GSP polling data section 206 NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8); 207 NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_REASON clkThrottleReason, 8); 208 NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8); 209 NV_DECLARE_ALIGNED(RUSD_MEM_ECC memEcc, 8); 210 NV_DECLARE_ALIGNED(RUSD_PERF_CURRENT_PSTATE perfCurrentPstate, 8); 211 NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8); // Module Limit is not supported on Ampere/Hopper 212 NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperature, 8); 213 NV_DECLARE_ALIGNED(RUSD_MEM_ROW_REMAP memRowRemap, 8); 214 NV_DECLARE_ALIGNED(RUSD_AVG_POWER_USAGE avgPowerUsage, 8); 215 NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8); 216 } NV00DE_SHARED_DATA; 217 218 #define NV00DE_RUSD_POLL_CLOCK 0x1 219 #define NV00DE_RUSD_POLL_PERF 0x2 220 #define NV00DE_RUSD_POLL_MEMORY 0x4 221 #define NV00DE_RUSD_POLL_POWER 0x8 222 #define NV00DE_RUSD_POLL_THERMAL 0x10 223 224 typedef struct NV00DE_ALLOC_PARAMETERS { 225 NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed 226 } NV00DE_ALLOC_PARAMETERS; 227 228 #ifdef __cplusplus 229 }; /* extern "C" */ 230 #endif 231 232 #endif /* _cl00de_h_ */ 233