1 /* Definitions of target machine for GNU compiler, Argonaut ARC cpu. 2 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2004, 2005 3 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 /* ??? This is an old port, and is undoubtedly suffering from bit rot. */ 23 24 /* Things to do: 25 26 - incscc, decscc? 27 - print active compiler options in assembler output 28 */ 29 30 31 #undef ASM_SPEC 32 #undef LINK_SPEC 33 #undef STARTFILE_SPEC 34 #undef ENDFILE_SPEC 35 #undef SIZE_TYPE 36 #undef PTRDIFF_TYPE 37 #undef WCHAR_TYPE 38 #undef WCHAR_TYPE_SIZE 39 #undef ASM_OUTPUT_LABELREF 40 41 /* Print subsidiary information on the compiler version in use. */ 42 #define TARGET_VERSION fprintf (stderr, " (arc)") 43 44 /* Names to predefine in the preprocessor for this target machine. */ 45 #define TARGET_CPU_CPP_BUILTINS() \ 46 do \ 47 { \ 48 builtin_define ("__arc__"); \ 49 if (TARGET_BIG_ENDIAN) \ 50 builtin_define ("__big_endian__"); \ 51 if (arc_cpu_type == 0) \ 52 builtin_define ("__base__"); \ 53 builtin_assert ("cpu=arc"); \ 54 builtin_assert ("machine=arc"); \ 55 } while (0) 56 57 /* Pass -mmangle-cpu if we get -mcpu=*. 58 Doing it this way lets one have it on as default with -mcpu=*, 59 but also lets one turn it off with -mno-mangle-cpu. */ 60 #define CC1_SPEC "\ 61 %{mcpu=*:-mmangle-cpu} \ 62 %{EB:%{EL:%emay not use both -EB and -EL}} \ 63 %{EB:-mbig-endian} %{EL:-mlittle-endian} \ 64 " 65 66 #define ASM_SPEC "%{v} %{EB} %{EL}" 67 68 #define LINK_SPEC "%{v} %{EB} %{EL}" 69 70 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crtinit.o%s" 71 72 #define ENDFILE_SPEC "crtfini.o%s" 73 74 /* Instruction set characteristics. 75 These are internal macros, set by the appropriate -mcpu= option. */ 76 77 /* Nonzero means the cpu has a barrel shifter. */ 78 #define TARGET_SHIFTER 0 79 80 /* Which cpu we're compiling for. */ 81 extern int arc_cpu_type; 82 83 /* Check if CPU is an extension and set `arc_cpu_type' and `arc_mangle_cpu' 84 appropriately. The result should be nonzero if the cpu is recognized, 85 otherwise zero. This is intended to be redefined in a cover file. 86 This is used by arc_init. */ 87 #define ARC_EXTENSION_CPU(cpu) 0 88 89 /* Sometimes certain combinations of command options do not make 90 sense on a particular target machine. You can define a macro 91 `OVERRIDE_OPTIONS' to take account of this. This macro, if 92 defined, is executed once just after all the command options have 93 been parsed. 94 95 Don't use this macro to turn on various extra optimizations for 96 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 97 98 99 #define OVERRIDE_OPTIONS \ 100 do { \ 101 /* These need to be done at start up. It's convenient to do them here. */ \ 102 arc_init (); \ 103 } while (0) 104 105 /* Target machine storage layout. */ 106 107 /* Define this if most significant bit is lowest numbered 108 in instructions that operate on numbered bit-fields. */ 109 #define BITS_BIG_ENDIAN 1 110 111 /* Define this if most significant byte of a word is the lowest numbered. */ 112 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) 113 114 /* Define this if most significant word of a multiword number is the lowest 115 numbered. */ 116 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) 117 118 /* Define this to set the endianness to use in libgcc2.c, which can 119 not depend on target_flags. */ 120 #ifdef __big_endian__ 121 #define LIBGCC2_WORDS_BIG_ENDIAN 1 122 #else 123 #define LIBGCC2_WORDS_BIG_ENDIAN 0 124 #endif 125 126 /* Width of a word, in units (bytes). */ 127 #define UNITS_PER_WORD 4 128 129 /* Define this macro if it is advisable to hold scalars in registers 130 in a wider mode than that declared by the program. In such cases, 131 the value is constrained to be within the bounds of the declared 132 type, but kept valid in the wider mode. The signedness of the 133 extension may differ from that of the type. */ 134 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 135 if (GET_MODE_CLASS (MODE) == MODE_INT \ 136 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 137 { \ 138 (MODE) = SImode; \ 139 } 140 141 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 142 #define PARM_BOUNDARY 32 143 144 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 145 #define STACK_BOUNDARY 64 146 147 /* ALIGN FRAMES on word boundaries */ 148 #define ARC_STACK_ALIGN(LOC) (((LOC)+7) & ~7) 149 150 /* Allocation boundary (in *bits*) for the code of a function. */ 151 #define FUNCTION_BOUNDARY 32 152 153 /* Alignment of field after `int : 0' in a structure. */ 154 #define EMPTY_FIELD_BOUNDARY 32 155 156 /* Every structure's size must be a multiple of this. */ 157 #define STRUCTURE_SIZE_BOUNDARY 8 158 159 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 160 #define PCC_BITFIELD_TYPE_MATTERS 1 161 162 /* No data type wants to be aligned rounder than this. */ 163 /* This is bigger than currently necessary for the ARC. If 8 byte floats are 164 ever added it's not clear whether they'll need such alignment or not. For 165 now we assume they will. We can always relax it if necessary but the 166 reverse isn't true. */ 167 #define BIGGEST_ALIGNMENT 64 168 169 /* The best alignment to use in cases where we have a choice. */ 170 #define FASTEST_ALIGNMENT 32 171 172 /* Make strings word-aligned so strcpy from constants will be faster. */ 173 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 174 ((TREE_CODE (EXP) == STRING_CST \ 175 && (ALIGN) < FASTEST_ALIGNMENT) \ 176 ? FASTEST_ALIGNMENT : (ALIGN)) 177 178 /* Make arrays of chars word-aligned for the same reasons. */ 179 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 180 (TREE_CODE (TYPE) == ARRAY_TYPE \ 181 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 182 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 183 184 /* Set this nonzero if move instructions will actually fail to work 185 when given unaligned data. */ 186 /* On the ARC the lower address bits are masked to 0 as necessary. The chip 187 won't croak when given an unaligned address, but the insn will still fail 188 to produce the correct result. */ 189 #define STRICT_ALIGNMENT 1 190 191 /* Layout of source language data types. */ 192 193 #define SHORT_TYPE_SIZE 16 194 #define INT_TYPE_SIZE 32 195 #define LONG_TYPE_SIZE 32 196 #define LONG_LONG_TYPE_SIZE 64 197 #define FLOAT_TYPE_SIZE 32 198 #define DOUBLE_TYPE_SIZE 64 199 #define LONG_DOUBLE_TYPE_SIZE 64 200 201 /* Define this as 1 if `char' should by default be signed; else as 0. */ 202 #define DEFAULT_SIGNED_CHAR 1 203 204 #define SIZE_TYPE "long unsigned int" 205 #define PTRDIFF_TYPE "long int" 206 #define WCHAR_TYPE "short unsigned int" 207 #define WCHAR_TYPE_SIZE 16 208 209 /* Standard register usage. */ 210 211 /* Number of actual hardware registers. 212 The hardware registers are assigned numbers for the compiler 213 from 0 to just below FIRST_PSEUDO_REGISTER. 214 All registers that the compiler knows about must be given numbers, 215 even those that are not normally considered general registers. */ 216 /* Registers 61, 62, and 63 are not really registers and we needn't treat 217 them as such. We still need a register for the condition code. */ 218 #define FIRST_PSEUDO_REGISTER 62 219 220 /* 1 for registers that have pervasive standard uses 221 and are not available for the register allocator. 222 223 0-28 - general purpose registers 224 29 - ilink1 (interrupt link register) 225 30 - ilink2 (interrupt link register) 226 31 - blink (branch link register) 227 32-59 - reserved for extensions 228 60 - LP_COUNT 229 61 - condition code 230 231 For doc purposes: 232 61 - short immediate data indicator (setting flags) 233 62 - long immediate data indicator 234 63 - short immediate data indicator (not setting flags). 235 236 The general purpose registers are further broken down into: 237 0-7 - arguments/results 238 8-15 - call used 239 16-23 - call saved 240 24 - call used, static chain pointer 241 25 - call used, gptmp 242 26 - global pointer 243 27 - frame pointer 244 28 - stack pointer 245 246 By default, the extension registers are not available. */ 247 248 #define FIXED_REGISTERS \ 249 { 0, 0, 0, 0, 0, 0, 0, 0, \ 250 0, 0, 0, 0, 0, 0, 0, 0, \ 251 0, 0, 0, 0, 0, 0, 0, 0, \ 252 0, 0, 0, 1, 1, 1, 1, 0, \ 253 \ 254 1, 1, 1, 1, 1, 1, 1, 1, \ 255 1, 1, 1, 1, 1, 1, 1, 1, \ 256 1, 1, 1, 1, 1, 1, 1, 1, \ 257 1, 1, 1, 1, 1, 1 } 258 259 /* 1 for registers not available across function calls. 260 These must include the FIXED_REGISTERS and also any 261 registers that can be used without being saved. 262 The latter must include the registers where values are returned 263 and the register where structure-value addresses are passed. 264 Aside from that, you can include as many other registers as you like. */ 265 266 #define CALL_USED_REGISTERS \ 267 { 1, 1, 1, 1, 1, 1, 1, 1, \ 268 1, 1, 1, 1, 1, 1, 1, 1, \ 269 0, 0, 0, 0, 0, 0, 0, 0, \ 270 1, 1, 1, 1, 1, 1, 1, 1, \ 271 \ 272 1, 1, 1, 1, 1, 1, 1, 1, \ 273 1, 1, 1, 1, 1, 1, 1, 1, \ 274 1, 1, 1, 1, 1, 1, 1, 1, \ 275 1, 1, 1, 1, 1, 1 } 276 277 /* If defined, an initializer for a vector of integers, containing the 278 numbers of hard registers in the order in which GCC should 279 prefer to use them (from most preferred to least). */ 280 #define REG_ALLOC_ORDER \ 281 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \ 282 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 31, \ 283 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 284 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, \ 285 27, 28, 29, 30 } 286 287 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 288 #define CONDITIONAL_REGISTER_USAGE \ 289 do { \ 290 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 291 { \ 292 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 293 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 294 } \ 295 } while (0) 296 297 /* Return number of consecutive hard regs needed starting at reg REGNO 298 to hold something of mode MODE. 299 This is ordinarily the length in words of a value of mode MODE 300 but can be less for certain modes in special long registers. */ 301 #define HARD_REGNO_NREGS(REGNO, MODE) \ 302 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 303 304 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 305 extern const unsigned int arc_hard_regno_mode_ok[]; 306 extern unsigned int arc_mode_class[]; 307 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 308 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0) 309 310 /* A C expression that is nonzero if it is desirable to choose 311 register allocation so as to avoid move instructions between a 312 value of mode MODE1 and a value of mode MODE2. 313 314 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 315 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 316 MODE2)' must be zero. */ 317 318 /* Tie QI/HI/SI modes together. */ 319 #define MODES_TIEABLE_P(MODE1, MODE2) \ 320 (GET_MODE_CLASS (MODE1) == MODE_INT \ 321 && GET_MODE_CLASS (MODE2) == MODE_INT \ 322 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 323 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) 324 325 /* Register classes and constants. */ 326 327 /* Define the classes of registers for register constraints in the 328 machine description. Also define ranges of constants. 329 330 One of the classes must always be named ALL_REGS and include all hard regs. 331 If there is more than one class, another class must be named NO_REGS 332 and contain no registers. 333 334 The name GENERAL_REGS must be the name of a class (or an alias for 335 another name such as ALL_REGS). This is the class of registers 336 that is allowed by "g" or "r" in a register constraint. 337 Also, registers outside this class are allocated only when 338 instructions express preferences for them. 339 340 The classes must be numbered in nondecreasing order; that is, 341 a larger-numbered class must never be contained completely 342 in a smaller-numbered class. 343 344 For any two classes, it is very desirable that there be another 345 class that represents their union. 346 347 It is important that any condition codes have class NO_REGS. 348 See `register_operand'. */ 349 350 enum reg_class { 351 NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES 352 }; 353 354 #define N_REG_CLASSES (int) LIM_REG_CLASSES 355 356 /* Give names of register classes as strings for dump file. */ 357 #define REG_CLASS_NAMES \ 358 { "NO_REGS", "LPCOUNT_REG", "GENERAL_REGS", "ALL_REGS" } 359 360 /* Define which registers fit in which classes. 361 This is an initializer for a vector of HARD_REG_SET 362 of length N_REG_CLASSES. */ 363 364 #define REG_CLASS_CONTENTS \ 365 { {0, 0}, {0, 0x10000000}, {0xffffffff, 0xfffffff}, \ 366 {0xffffffff, 0x1fffffff} } 367 368 /* The same information, inverted: 369 Return the class number of the smallest class containing 370 reg number REGNO. This could be a conditional expression 371 or could index an array. */ 372 extern enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 373 #define REGNO_REG_CLASS(REGNO) \ 374 (arc_regno_reg_class[REGNO]) 375 376 /* The class value for index registers, and the one for base regs. */ 377 #define INDEX_REG_CLASS GENERAL_REGS 378 #define BASE_REG_CLASS GENERAL_REGS 379 380 /* Get reg_class from a letter such as appears in the machine description. */ 381 #define REG_CLASS_FROM_LETTER(C) \ 382 ((C) == 'l' ? LPCOUNT_REG /* ??? needed? */ \ 383 : NO_REGS) 384 385 /* These assume that REGNO is a hard or pseudo reg number. 386 They give nonzero only if REGNO is a hard reg of the suitable class 387 or a pseudo reg currently allocated to a suitable hard reg. 388 Since they use reg_renumber, they are safe only once reg_renumber 389 has been allocated, which happens in local-alloc.c. */ 390 #define REGNO_OK_FOR_BASE_P(REGNO) \ 391 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) 392 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 393 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) 394 395 /* Given an rtx X being reloaded into a reg required to be 396 in class CLASS, return the class of reg to actually use. 397 In general this is just CLASS; but on some machines 398 in some cases it is preferable to use a more restrictive class. */ 399 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 400 (CLASS) 401 402 /* Return the maximum number of consecutive registers 403 needed to represent mode MODE in a register of class CLASS. */ 404 #define CLASS_MAX_NREGS(CLASS, MODE) \ 405 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 406 407 /* The letters I, J, K, L, M, N, O, P in a register constraint string 408 can be used to stand for particular ranges of immediate operands. 409 This macro defines what the ranges are. 410 C is the letter, and VALUE is a constant value. 411 Return 1 if VALUE is in the range specified by C. */ 412 /* 'I' is used for short immediates (always signed). 413 'J' is used for long immediates. 414 'K' is used for any constant up to 64 bits (for 64x32 situations?). */ 415 416 /* local to this file */ 417 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200) 418 /* local to this file */ 419 #define LARGE_INT(X) \ 420 ((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ 421 && (unsigned HOST_WIDE_INT)(X) <= (unsigned HOST_WIDE_INT) 0xffffffff) 422 423 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 424 ((C) == 'I' ? SMALL_INT (VALUE) \ 425 : (C) == 'J' ? LARGE_INT (VALUE) \ 426 : (C) == 'K' ? 1 \ 427 : 0) 428 429 /* Similar, but for floating constants, and defining letters G and H. 430 Here VALUE is the CONST_DOUBLE rtx itself. */ 431 /* 'G' is used for integer values for the multiplication insns where the 432 operands are extended from 4 bytes to 8 bytes. 433 'H' is used when any 64 bit constant is allowed. */ 434 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 435 ((C) == 'G' ? arc_double_limm_p (VALUE) \ 436 : (C) == 'H' ? 1 \ 437 : 0) 438 439 /* A C expression that defines the optional machine-dependent constraint 440 letters that can be used to segregate specific types of operands, 441 usually memory references, for the target machine. It should return 1 if 442 VALUE corresponds to the operand type represented by the constraint letter 443 C. If C is not defined as an extra constraint, the value returned should 444 be 0 regardless of VALUE. */ 445 /* ??? This currently isn't used. Waiting for PIC. */ 446 #if 0 447 #define EXTRA_CONSTRAINT(VALUE, C) \ 448 ((C) == 'R' ? (SYMBOL_REF_FUNCTION_P (VALUE) || GET_CODE (VALUE) == LABEL_REF) \ 449 : 0) 450 #endif 451 452 /* Stack layout and stack pointer usage. */ 453 454 /* Define this macro if pushing a word onto the stack moves the stack 455 pointer to a smaller address. */ 456 #define STACK_GROWS_DOWNWARD 457 458 /* Define this to nonzero if the nominal address of the stack frame 459 is at the high-address end of the local variables; 460 that is, each additional local variable allocated 461 goes at a more negative offset in the frame. */ 462 #define FRAME_GROWS_DOWNWARD 1 463 464 /* Offset within stack frame to start allocating local variables at. 465 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 466 first local allocated. Otherwise, it is the offset to the BEGINNING 467 of the first local allocated. */ 468 #define STARTING_FRAME_OFFSET 0 469 470 /* Offset from the stack pointer register to the first location at which 471 outgoing arguments are placed. */ 472 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET (0) 473 474 /* Offset of first parameter from the argument pointer register value. */ 475 /* 4 bytes for each of previous fp, return address, and previous gp. 476 4 byte reserved area for future considerations. */ 477 #define FIRST_PARM_OFFSET(FNDECL) 16 478 479 /* A C expression whose value is RTL representing the address in a 480 stack frame where the pointer to the caller's frame is stored. 481 Assume that FRAMEADDR is an RTL expression for the address of the 482 stack frame itself. 483 484 If you don't define this macro, the default is to return the value 485 of FRAMEADDR--that is, the stack frame address is also the address 486 of the stack word that points to the previous frame. */ 487 /* ??? unfinished */ 488 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/ 489 490 /* A C expression whose value is RTL representing the value of the 491 return address for the frame COUNT steps up from the current frame. 492 FRAMEADDR is the frame pointer of the COUNT frame, or the frame 493 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' 494 is defined. */ 495 /* The current return address is in r31. The return address of anything 496 farther back is at [%fp,4]. */ 497 #if 0 /* The default value should work. */ 498 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 499 (((COUNT) == -1) \ 500 ? gen_rtx_REG (Pmode, 31) \ 501 : copy_to_reg (gen_rtx_MEM (Pmode, \ 502 memory_address (Pmode, \ 503 plus_constant ((FRAME), \ 504 UNITS_PER_WORD))))) 505 #endif 506 507 /* Register to use for pushing function arguments. */ 508 #define STACK_POINTER_REGNUM 28 509 510 /* Base register for access to local variables of the function. */ 511 #define FRAME_POINTER_REGNUM 27 512 513 /* Base register for access to arguments of the function. */ 514 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 515 516 /* Register in which static-chain is passed to a function. This must 517 not be a register used by the prologue. */ 518 #define STATIC_CHAIN_REGNUM 24 519 520 /* A C expression which is nonzero if a function must have and use a 521 frame pointer. This expression is evaluated in the reload pass. 522 If its value is nonzero the function will have a frame pointer. */ 523 #define FRAME_POINTER_REQUIRED \ 524 (current_function_calls_alloca) 525 526 /* C statement to store the difference between the frame pointer 527 and the stack pointer values immediately after the function prologue. */ 528 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 529 ((VAR) = arc_compute_frame_size (get_frame_size ())) 530 531 /* Function argument passing. */ 532 533 /* If defined, the maximum amount of space required for outgoing 534 arguments will be computed and placed into the variable 535 `current_function_outgoing_args_size'. No space will be pushed 536 onto the stack for each call; instead, the function prologue should 537 increase the stack frame size by this amount. */ 538 #define ACCUMULATE_OUTGOING_ARGS 1 539 540 /* Value is the number of bytes of arguments automatically 541 popped when returning from a subroutine call. 542 FUNDECL is the declaration node of the function (as a tree), 543 FUNTYPE is the data type of the function (as a tree), 544 or for a library call it is an identifier node for the subroutine name. 545 SIZE is the number of bytes of arguments passed on the stack. */ 546 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 547 548 /* Define a data type for recording info about an argument list 549 during the scan of that argument list. This data type should 550 hold all necessary information about the function itself 551 and about the args processed so far, enough to enable macros 552 such as FUNCTION_ARG to determine where the next arg should go. */ 553 #define CUMULATIVE_ARGS int 554 555 /* Initialize a variable CUM of type CUMULATIVE_ARGS 556 for a call to a function whose data type is FNTYPE. 557 For a library call, FNTYPE is 0. */ 558 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 559 ((CUM) = 0) 560 561 /* The number of registers used for parameter passing. Local to this file. */ 562 #define MAX_ARC_PARM_REGS 8 563 564 /* 1 if N is a possible register number for function argument passing. */ 565 #define FUNCTION_ARG_REGNO_P(N) \ 566 ((unsigned) (N) < MAX_ARC_PARM_REGS) 567 568 /* The ROUND_ADVANCE* macros are local to this file. */ 569 /* Round SIZE up to a word boundary. */ 570 #define ROUND_ADVANCE(SIZE) \ 571 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 572 573 /* Round arg MODE/TYPE up to the next word boundary. */ 574 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 575 ((MODE) == BLKmode \ 576 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 577 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) 578 579 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 580 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \ 581 ((((MODE) == BLKmode ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) \ 582 > BITS_PER_WORD) \ 583 ? (((CUM) + 1) & ~1) \ 584 : (CUM)) 585 586 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 587 a reg. This includes arguments that have to be passed by reference as the 588 pointer to them is passed in a reg if one is available (and that is what 589 we're given). 590 This macro is only used in this file. */ 591 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 592 ((CUM) < MAX_ARC_PARM_REGS \ 593 && ((ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ 594 + ROUND_ADVANCE_ARG ((MODE), (TYPE)) \ 595 <= MAX_ARC_PARM_REGS))) 596 597 /* Determine where to put an argument to a function. 598 Value is zero to push the argument on the stack, 599 or a hard register in which to store the argument. 600 601 MODE is the argument's machine mode. 602 TYPE is the data type of the argument (as a tree). 603 This is null for libcalls where that information may 604 not be available. 605 CUM is a variable of type CUMULATIVE_ARGS which gives info about 606 the preceding args and about the function being called. 607 NAMED is nonzero if this argument is a named parameter 608 (otherwise it is an extra parameter matching an ellipsis). */ 609 /* On the ARC the first MAX_ARC_PARM_REGS args are normally in registers 610 and the rest are pushed. */ 611 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 612 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 613 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \ 614 : 0) 615 616 /* Update the data in CUM to advance over an argument 617 of mode MODE and data type TYPE. 618 (TYPE is null for libcalls where that information may not be available.) */ 619 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 620 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ 621 + ROUND_ADVANCE_ARG ((MODE), (TYPE)))) 622 623 /* If defined, a C expression that gives the alignment boundary, in bits, 624 of an argument with the specified mode and type. If it is not defined, 625 PARM_BOUNDARY is used for all arguments. */ 626 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 627 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ 628 ? PARM_BOUNDARY \ 629 : 2 * PARM_BOUNDARY) 630 631 /* Function results. */ 632 633 /* Define how to find the value returned by a function. 634 VALTYPE is the data type of the value (as a tree). 635 If the precise function being called is known, FUNC is its FUNCTION_DECL; 636 otherwise, FUNC is 0. */ 637 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 638 639 /* Define how to find the value returned by a library function 640 assuming the value has mode MODE. */ 641 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 642 643 /* 1 if N is a possible register number for a function value 644 as seen by the caller. */ 645 /* ??? What about r1 in DI/DF values. */ 646 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 647 648 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ 649 #define DEFAULT_PCC_STRUCT_RETURN 0 650 651 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 652 the stack pointer does not matter. The value is tested only in 653 functions that have frame pointers. 654 No definition is equivalent to always zero. */ 655 #define EXIT_IGNORE_STACK 0 656 657 /* Epilogue delay slots. */ 658 #define DELAY_SLOTS_FOR_EPILOGUE arc_delay_slots_for_epilogue () 659 660 #define ELIGIBLE_FOR_EPILOGUE_DELAY(TRIAL, SLOTS_FILLED) \ 661 arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED) 662 663 /* Output assembler code to FILE to increment profiler label # LABELNO 664 for profiling a function entry. */ 665 #define FUNCTION_PROFILER(FILE, LABELNO) 666 667 /* Trampolines. */ 668 /* ??? This doesn't work yet because GCC will use as the address of a nested 669 function the address of the trampoline. We need to use that address 670 right shifted by 2. It looks like we'll need PSImode after all. :-( */ 671 672 /* Output assembler code for a block containing the constant parts 673 of a trampoline, leaving space for the variable parts. */ 674 /* On the ARC, the trampoline is quite simple as we have 32 bit immediate 675 constants. 676 677 mov r24,STATIC 678 j.nd FUNCTION 679 */ 680 #define TRAMPOLINE_TEMPLATE(FILE) \ 681 do { \ 682 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x631f7c00)); \ 683 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 684 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x381f0000)); \ 685 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 686 } while (0) 687 688 /* Length in units of the trampoline for entering a nested function. */ 689 #define TRAMPOLINE_SIZE 16 690 691 /* Emit RTL insns to initialize the variable parts of a trampoline. 692 FNADDR is an RTX for the address of the function's pure code. 693 CXT is an RTX for the static chain value for the function. */ 694 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 695 do { \ 696 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), CXT); \ 697 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), FNADDR); \ 698 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)))); \ 699 } while (0) 700 701 /* Addressing modes, and classification of registers for them. */ 702 703 /* Maximum number of registers that can appear in a valid memory address. */ 704 /* The `ld' insn allows 2, but the `st' insn only allows 1. */ 705 #define MAX_REGS_PER_ADDRESS 1 706 707 /* We have pre inc/dec (load/store with update). */ 708 #define HAVE_PRE_INCREMENT 1 709 #define HAVE_PRE_DECREMENT 1 710 711 /* Recognize any constant value that is a valid address. */ 712 #define CONSTANT_ADDRESS_P(X) \ 713 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 714 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST) 715 716 /* Nonzero if the constant value X is a legitimate general operand. 717 We can handle any 32 or 64 bit constant. */ 718 /* "1" should work since the largest constant should be a 64 bit critter. */ 719 /* ??? Not sure what to do for 64x32 compiler. */ 720 #define LEGITIMATE_CONSTANT_P(X) 1 721 722 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 723 and check its validity for a certain class. 724 We have two alternate definitions for each of them. 725 The usual definition accepts all pseudo regs; the other rejects 726 them unless they have been allocated suitable hard regs. 727 The symbol REG_OK_STRICT causes the latter definition to be used. 728 729 Most source files want to accept pseudo regs in the hope that 730 they will get allocated to the class that the insn wants them to be in. 731 Source files for reload pass need to be strict. 732 After reload, it makes no difference, since pseudo regs have 733 been eliminated by then. */ 734 735 #ifndef REG_OK_STRICT 736 737 /* Nonzero if X is a hard reg that can be used as an index 738 or if it is a pseudo reg. */ 739 #define REG_OK_FOR_INDEX_P(X) \ 740 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32) 741 /* Nonzero if X is a hard reg that can be used as a base reg 742 or if it is a pseudo reg. */ 743 #define REG_OK_FOR_BASE_P(X) \ 744 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32) 745 746 #else 747 748 /* Nonzero if X is a hard reg that can be used as an index. */ 749 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 750 /* Nonzero if X is a hard reg that can be used as a base reg. */ 751 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 752 753 #endif 754 755 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 756 that is a valid memory address for an instruction. 757 The MODE argument is the machine mode for the MEM expression 758 that wants to use this address. */ 759 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm] 760 but the `st' insn only allows [reg],[reg+shimm],[limm]. 761 The only thing we can do is only allow the most strict case `st' and hope 762 other parts optimize out the restrictions for `ld'. */ 763 764 /* local to this file */ 765 #define RTX_OK_FOR_BASE_P(X) \ 766 (REG_P (X) && REG_OK_FOR_BASE_P (X)) 767 768 /* local to this file */ 769 #define RTX_OK_FOR_INDEX_P(X) \ 770 (0 && /*???*/ REG_P (X) && REG_OK_FOR_INDEX_P (X)) 771 772 /* local to this file */ 773 /* ??? Loads can handle any constant, stores can only handle small ones. */ 774 #define RTX_OK_FOR_OFFSET_P(X) \ 775 (GET_CODE (X) == CONST_INT && SMALL_INT (INTVAL (X))) 776 777 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ 778 (GET_CODE (X) == PLUS \ 779 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ 780 && (RTX_OK_FOR_INDEX_P (XEXP (X, 1)) \ 781 || RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))) 782 783 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 784 { if (RTX_OK_FOR_BASE_P (X)) \ 785 goto ADDR; \ 786 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \ 787 goto ADDR; \ 788 if (GET_CODE (X) == CONST_INT && LARGE_INT (INTVAL (X))) \ 789 goto ADDR; \ 790 if (GET_CODE (X) == SYMBOL_REF \ 791 || GET_CODE (X) == LABEL_REF \ 792 || GET_CODE (X) == CONST) \ 793 goto ADDR; \ 794 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 795 /* We're restricted here by the `st' insn. */ \ 796 && RTX_OK_FOR_BASE_P (XEXP ((X), 0))) \ 797 goto ADDR; \ 798 } 799 800 /* Go to LABEL if ADDR (a legitimate address expression) 801 has an effect that depends on the machine mode it is used for. */ 802 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 803 { if (GET_CODE (ADDR) == PRE_DEC) \ 804 goto LABEL; \ 805 if (GET_CODE (ADDR) == PRE_INC) \ 806 goto LABEL; \ 807 } 808 809 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 810 return the mode to be used for the comparison. */ 811 #define SELECT_CC_MODE(OP, X, Y) \ 812 arc_select_cc_mode (OP, X, Y) 813 814 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 815 floating point inequality comparison. */ 816 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 817 818 /* Costs. */ 819 820 /* Compute extra cost of moving data between one register class 821 and another. */ 822 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2 823 824 /* Compute the cost of moving data between registers and memory. */ 825 /* Memory is 3 times as expensive as registers. 826 ??? Is that the right way to look at it? */ 827 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 828 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) 829 830 /* The cost of a branch insn. */ 831 /* ??? What's the right value here? Branches are certainly more 832 expensive than reg->reg moves. */ 833 #define BRANCH_COST 2 834 835 /* Nonzero if access to memory by bytes is slow and undesirable. 836 For RISC chips, it means that access to memory by bytes is no 837 better than access by words when possible, so grab a whole word 838 and maybe make use of that. */ 839 #define SLOW_BYTE_ACCESS 1 840 841 /* Define this macro if it is as good or better to call a constant 842 function address than to call an address kept in a register. */ 843 /* On the ARC, calling through registers is slow. */ 844 #define NO_FUNCTION_CSE 845 846 /* Section selection. */ 847 /* WARNING: These section names also appear in dwarfout.c. */ 848 849 /* The names of the text, data, and readonly-data sections are runtime 850 selectable. */ 851 852 #define ARC_SECTION_FORMAT "\t.section %s" 853 #define ARC_DEFAULT_TEXT_SECTION ".text" 854 #define ARC_DEFAULT_DATA_SECTION ".data" 855 #define ARC_DEFAULT_RODATA_SECTION ".rodata" 856 857 extern const char *arc_text_section, *arc_data_section, *arc_rodata_section; 858 859 /* initfini.c uses this in an asm. */ 860 #if defined (CRT_INIT) || defined (CRT_FINI) 861 #define TEXT_SECTION_ASM_OP "\t.section .text" 862 #else 863 #define TEXT_SECTION_ASM_OP arc_text_section 864 #endif 865 #define DATA_SECTION_ASM_OP arc_data_section 866 867 #undef READONLY_DATA_SECTION_ASM_OP 868 #define READONLY_DATA_SECTION_ASM_OP arc_rodata_section 869 870 #define BSS_SECTION_ASM_OP "\t.section .bss" 871 872 /* Define this macro if jump tables (for tablejump insns) should be 873 output in the text section, along with the assembler instructions. 874 Otherwise, the readonly data section is used. 875 This macro is irrelevant if there is no separate readonly data section. */ 876 /*#define JUMP_TABLES_IN_TEXT_SECTION*/ 877 878 /* For DWARF. Marginally different than default so output is "prettier" 879 (and consistent with above). */ 880 #define PUSHSECTION_ASM_OP "\t.section " 881 882 /* Tell crtstuff.c we're using ELF. */ 883 #define OBJECT_FORMAT_ELF 884 885 /* PIC */ 886 887 /* The register number of the register used to address a table of static 888 data addresses in memory. In some cases this register is defined by a 889 processor's ``application binary interface'' (ABI). When this macro 890 is defined, RTL is generated for this register once, as with the stack 891 pointer and frame pointer registers. If this macro is not defined, it 892 is up to the machine-dependent files to allocate such a register (if 893 necessary). */ 894 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 26 : INVALID_REGNUM) 895 896 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 897 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 898 is not defined. */ 899 /* This register is call-saved on the ARC. */ 900 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 901 902 /* A C expression that is nonzero if X is a legitimate immediate 903 operand on the target machine when generating position independent code. 904 You can assume that X satisfies CONSTANT_P, so you need not 905 check this. You can also assume `flag_pic' is true, so you need not 906 check it either. You need not define this macro if all constants 907 (including SYMBOL_REF) can be immediate operands when generating 908 position independent code. */ 909 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/ 910 911 /* Control the assembler format that we output. */ 912 913 /* A C string constant describing how to begin a comment in the target 914 assembler language. The compiler assumes that the comment will 915 end at the end of the line. */ 916 #define ASM_COMMENT_START ";" 917 918 /* Output to assembler file text saying following lines 919 may contain character constants, extra white space, comments, etc. */ 920 #define ASM_APP_ON "" 921 922 /* Output to assembler file text saying following lines 923 no longer contain unusual constructs. */ 924 #define ASM_APP_OFF "" 925 926 /* Globalizing directive for a label. */ 927 #define GLOBAL_ASM_OP "\t.global\t" 928 929 /* This is how to output a reference to a user-level label named NAME. 930 `assemble_name' uses this. */ 931 /* We mangle all user labels to provide protection from linking code 932 compiled for different cpus. */ 933 /* We work around a dwarfout.c deficiency by watching for labels from it and 934 not adding the '_' prefix nor the cpu suffix. There is a comment in 935 dwarfout.c that says it should be using (*targetm.asm_out.internal_label). */ 936 extern const char *arc_mangle_cpu; 937 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 938 do { \ 939 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \ 940 fprintf (FILE, "%s", NAME); \ 941 else \ 942 { \ 943 fputc ('_', FILE); \ 944 if (TARGET_MANGLE_CPU && arc_mangle_cpu != NULL) \ 945 fprintf (FILE, "%s_", arc_mangle_cpu); \ 946 fprintf (FILE, "%s", NAME); \ 947 } \ 948 } while (0) 949 950 /* Assembler pseudo-op to equate one value with another. */ 951 /* ??? This is needed because dwarfout.c provides a default definition too 952 late for defaults.h (which contains the default definition of ASM_OUTPUT_DEF 953 that we use). */ 954 #define SET_ASM_OP "\t.set\t" 955 956 /* How to refer to registers in assembler output. 957 This sequence is indexed by compiler's hard-register-number (see above). */ 958 #define REGISTER_NAMES \ 959 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 960 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 961 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 962 "r24", "r25", "r26", "fp", "sp", "ilink1", "ilink2", "blink", \ 963 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 964 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 965 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 966 "r56", "r57", "r58", "r59", "lp_count", "cc"} 967 968 /* Entry to the insn conditionalizer. */ 969 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 970 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS) 971 972 /* A C expression which evaluates to true if CODE is a valid 973 punctuation character for use in the `PRINT_OPERAND' macro. */ 974 extern char arc_punct_chars[256]; 975 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 976 arc_punct_chars[(unsigned char) (CHAR)] 977 978 /* Print operand X (an rtx) in assembler syntax to file FILE. 979 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 980 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 981 #define PRINT_OPERAND(FILE, X, CODE) \ 982 arc_print_operand (FILE, X, CODE) 983 984 /* A C compound statement to output to stdio stream STREAM the 985 assembler syntax for an instruction operand that is a memory 986 reference whose address is ADDR. ADDR is an RTL expression. */ 987 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 988 arc_print_operand_address (FILE, ADDR) 989 990 /* This is how to output an element of a case-vector that is absolute. */ 991 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 992 do { \ 993 char label[30]; \ 994 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 995 fprintf (FILE, "\t.word %%st("); \ 996 assemble_name (FILE, label); \ 997 fprintf (FILE, ")\n"); \ 998 } while (0) 999 1000 /* This is how to output an element of a case-vector that is relative. */ 1001 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1002 do { \ 1003 char label[30]; \ 1004 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1005 fprintf (FILE, "\t.word %%st("); \ 1006 assemble_name (FILE, label); \ 1007 fprintf (FILE, "-"); \ 1008 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 1009 assemble_name (FILE, label); \ 1010 fprintf (FILE, ")\n"); \ 1011 } while (0) 1012 1013 /* The desired alignment for the location counter at the beginning 1014 of a loop. */ 1015 /* On the ARC, align loops to 32 byte boundaries (cache line size) 1016 if -malign-loops. */ 1017 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) 1018 1019 /* This is how to output an assembler line 1020 that says to advance the location counter 1021 to a multiple of 2**LOG bytes. */ 1022 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1023 do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0) 1024 1025 /* Debugging information. */ 1026 1027 /* Generate DBX and DWARF debugging information. */ 1028 #define DBX_DEBUGGING_INFO 1 1029 1030 /* Prefer STABS (for now). */ 1031 #undef PREFERRED_DEBUGGING_TYPE 1032 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG 1033 1034 /* Turn off splitting of long stabs. */ 1035 #define DBX_CONTIN_LENGTH 0 1036 1037 /* Miscellaneous. */ 1038 1039 /* Specify the machine mode that this machine uses 1040 for the index in the tablejump instruction. */ 1041 #define CASE_VECTOR_MODE Pmode 1042 1043 /* Define if operations between registers always perform the operation 1044 on the full register even if a narrower mode is specified. */ 1045 #define WORD_REGISTER_OPERATIONS 1046 1047 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1048 will either zero-extend or sign-extend. The value of this macro should 1049 be the code that says which one of the two operations is implicitly 1050 done, UNKNOWN if none. */ 1051 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1052 1053 /* Max number of bytes we can move from memory to memory 1054 in one reasonably fast instruction. */ 1055 #define MOVE_MAX 4 1056 1057 /* Define this to be nonzero if shift instructions ignore all but the low-order 1058 few bits. */ 1059 #define SHIFT_COUNT_TRUNCATED 1 1060 1061 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1062 is done just by pretending it is already truncated. */ 1063 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1064 1065 /* Specify the machine mode that pointers have. 1066 After generation of rtl, the compiler makes no further distinction 1067 between pointers and any other objects of this machine mode. */ 1068 /* ??? The arc doesn't have full 32 bit pointers, but making this PSImode has 1069 its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does 1070 one do it without getting excess code?). Try to avoid it. */ 1071 #define Pmode SImode 1072 1073 /* A function address in a call instruction. */ 1074 #define FUNCTION_MODE SImode 1075 1076 /* alloca should avoid clobbering the old register save area. */ 1077 /* ??? Not defined in tm.texi. */ 1078 #define SETJMP_VIA_SAVE_AREA 1079 1080 /* Define the information needed to generate branch and scc insns. This is 1081 stored from the compare operation. Note that we can't use "rtx" here 1082 since it hasn't been defined! */ 1083 extern struct rtx_def *arc_compare_op0, *arc_compare_op1; 1084 1085 /* ARC function types. */ 1086 enum arc_function_type { 1087 ARC_FUNCTION_UNKNOWN, ARC_FUNCTION_NORMAL, 1088 /* These are interrupt handlers. The name corresponds to the register 1089 name that contains the return address. */ 1090 ARC_FUNCTION_ILINK1, ARC_FUNCTION_ILINK2 1091 }; 1092 #define ARC_INTERRUPT_P(TYPE) \ 1093 ((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2) 1094 /* Compute the type of a function from its DECL. */ 1095 1096 1097 /* Implement `va_start' for varargs and stdarg. */ 1098 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1099 arc_va_start (valist, nextarg) 1100