1add_llvm_component_group(AMDGPU)
2
3set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
4
5tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
6tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
7tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
8tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
9tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
10tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
11tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
12tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
13tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
14tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
15tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
16tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
17
18set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
19tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
20tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
21              -combiners="AMDGPUPreLegalizerCombinerHelper")
22tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
23              -combiners="AMDGPUPostLegalizerCombinerHelper")
24tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
25              -combiners="AMDGPURegBankCombinerHelper")
26
27set(LLVM_TARGET_DEFINITIONS R600.td)
28tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
29tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
30tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
31tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
32tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
33tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
34tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
35tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
36
37add_public_tablegen_target(AMDGPUCommonTableGen)
38
39set(LLVM_TARGET_DEFINITIONS InstCombineTables.td)
40tablegen(LLVM InstCombineTables.inc -gen-searchable-tables)
41add_public_tablegen_target(InstCombineTableGen)
42
43add_llvm_target(AMDGPUCodeGen
44  AMDGPUAliasAnalysis.cpp
45  AMDGPUAlwaysInlinePass.cpp
46  AMDGPUAnnotateKernelFeatures.cpp
47  AMDGPUAttributor.cpp
48  AMDGPUAnnotateUniformValues.cpp
49  AMDGPUArgumentUsageInfo.cpp
50  AMDGPUAsmPrinter.cpp
51  AMDGPUAtomicOptimizer.cpp
52  AMDGPUCallLowering.cpp
53  AMDGPUCodeGenPrepare.cpp
54  AMDGPUExportClustering.cpp
55  AMDGPUFixFunctionBitcasts.cpp
56  AMDGPUFrameLowering.cpp
57  AMDGPUHSAMetadataStreamer.cpp
58  AMDGPUInstCombineIntrinsic.cpp
59  AMDGPUInstrInfo.cpp
60  AMDGPUInstructionSelector.cpp
61  AMDGPUISelDAGToDAG.cpp
62  AMDGPUISelLowering.cpp
63  AMDGPUGlobalISelUtils.cpp
64  AMDGPULateCodeGenPrepare.cpp
65  AMDGPULegalizerInfo.cpp
66  AMDGPULibCalls.cpp
67  AMDGPULibFunc.cpp
68  AMDGPULowerIntrinsics.cpp
69  AMDGPULowerKernelArguments.cpp
70  AMDGPULowerKernelAttributes.cpp
71  AMDGPULowerModuleLDSPass.cpp
72  AMDGPUMachineCFGStructurizer.cpp
73  AMDGPUMachineFunction.cpp
74  AMDGPUMachineModuleInfo.cpp
75  AMDGPUMacroFusion.cpp
76  AMDGPUMCInstLower.cpp
77  AMDGPUMIRFormatter.cpp
78  AMDGPUOpenCLEnqueuedBlockLowering.cpp
79  AMDGPUPostLegalizerCombiner.cpp
80  AMDGPUPreLegalizerCombiner.cpp
81  AMDGPUPromoteAlloca.cpp
82  AMDGPUPropagateAttributes.cpp
83  AMDGPURegBankCombiner.cpp
84  AMDGPURegisterBankInfo.cpp
85  AMDGPUReplaceLDSUseWithPointer.cpp
86  AMDGPURewriteOutArguments.cpp
87  AMDGPUSubtarget.cpp
88  AMDGPUTargetMachine.cpp
89  AMDGPUTargetObjectFile.cpp
90  AMDGPUTargetTransformInfo.cpp
91  AMDGPUUnifyDivergentExitNodes.cpp
92  AMDGPUUnifyMetadata.cpp
93  AMDGPUPerfHintAnalysis.cpp
94  AMDILCFGStructurizer.cpp
95  AMDGPUPrintfRuntimeBinding.cpp
96  AMDGPUResourceUsageAnalysis.cpp
97  GCNHazardRecognizer.cpp
98  GCNIterativeScheduler.cpp
99  GCNMinRegStrategy.cpp
100  GCNRegPressure.cpp
101  GCNSchedStrategy.cpp
102  R600AsmPrinter.cpp
103  R600ClauseMergePass.cpp
104  R600ControlFlowFinalizer.cpp
105  R600EmitClauseMarkers.cpp
106  R600ExpandSpecialInstrs.cpp
107  R600FrameLowering.cpp
108  R600InstrInfo.cpp
109  R600ISelLowering.cpp
110  R600MachineFunctionInfo.cpp
111  R600MachineScheduler.cpp
112  R600OpenCLImageTypeLoweringPass.cpp
113  R600OptimizeVectorRegisters.cpp
114  R600Packetizer.cpp
115  R600RegisterInfo.cpp
116  SIAnnotateControlFlow.cpp
117  SIFixSGPRCopies.cpp
118  SIFixVGPRCopies.cpp
119  SIPreAllocateWWMRegs.cpp
120  SIFoldOperands.cpp
121  SIFormMemoryClauses.cpp
122  SIFrameLowering.cpp
123  SIInsertHardClauses.cpp
124  SILateBranchLowering.cpp
125  SIInsertWaitcnts.cpp
126  SIInstrInfo.cpp
127  SIISelLowering.cpp
128  SILoadStoreOptimizer.cpp
129  SILowerControlFlow.cpp
130  SILowerI1Copies.cpp
131  SILowerSGPRSpills.cpp
132  SIMachineFunctionInfo.cpp
133  SIMachineScheduler.cpp
134  SIMemoryLegalizer.cpp
135  SIOptimizeExecMasking.cpp
136  SIOptimizeExecMaskingPreRA.cpp
137  SIOptimizeVGPRLiveRange.cpp
138  SIPeepholeSDWA.cpp
139  SIPostRABundler.cpp
140  SIPreEmitPeephole.cpp
141  SIProgramInfo.cpp
142  SIRegisterInfo.cpp
143  SIShrinkInstructions.cpp
144  SIWholeQuadMode.cpp
145  GCNILPSched.cpp
146  GCNNSAReassign.cpp
147  GCNDPPCombine.cpp
148  GCNPreRAOptimizations.cpp
149  SIModeRegister.cpp
150
151  LINK_COMPONENTS
152  Analysis
153  AsmPrinter
154  CodeGen
155  Core
156  IPO
157  MC
158  Passes
159  AMDGPUDesc
160  AMDGPUInfo
161  AMDGPUUtils
162  Scalar
163  SelectionDAG
164  Support
165  Target
166  TransformUtils
167  Vectorize
168  GlobalISel
169  BinaryFormat
170  MIRParser
171
172  ADD_TO_COMPONENT
173  AMDGPU
174  )
175
176add_subdirectory(AsmParser)
177add_subdirectory(Disassembler)
178add_subdirectory(MCTargetDesc)
179add_subdirectory(TargetInfo)
180add_subdirectory(Utils)
181