1# $OpenBSD: Makefile,v 1.7 2021/12/17 14:55:44 patrick Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm/llvm
6
7HDRS=	AArch64GenAsmMatcher.inc \
8	AArch64GenAsmWriter.inc \
9	AArch64GenAsmWriter1.inc \
10	AArch64GenCallingConv.inc \
11	AArch64GenDAGISel.inc \
12	AArch64GenDisassemblerTables.inc \
13	AArch64GenFastISel.inc \
14	AArch64GenGlobalISel.inc \
15	AArch64GenO0PreLegalizeGICombiner.inc \
16	AArch64GenPreLegalizeGICombiner.inc \
17	AArch64GenPostLegalizeGICombiner.inc \
18	AArch64GenPostLegalizeGILowering.inc \
19	AArch64GenInstrInfo.inc \
20	AArch64GenMCCodeEmitter.inc \
21	AArch64GenMCPseudoLowering.inc \
22	AArch64GenRegisterBank.inc \
23	AArch64GenRegisterInfo.inc \
24	AArch64GenSubtargetInfo.inc \
25	AArch64GenSystemOperands.inc \
26	AArch64GenExegesis.inc
27
28all: ${HDRS}
29
30install:
31	@# Nothing here so far ...
32
33clean cleandir:
34	rm -f ${HDRS}
35
36AArch64GenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
37	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
38		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
39		-o ${.TARGET} ${.ALLSRC}
40
41AArch64GenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
42	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
43		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
44		-o ${.TARGET} ${.ALLSRC}
45
46AArch64GenAsmWriter1.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
47	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
48		-asmwriternum=1 -I${LLVM_SRCS}/include \
49		-I${LLVM_SRCS}/lib/Target/AArch64 -o ${.TARGET} ${.ALLSRC}
50
51AArch64GenCallingConv.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
52	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
53		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
54		-o ${.TARGET} ${.ALLSRC}
55
56AArch64GenDAGISel.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
57	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
58		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
59		-o ${.TARGET} ${.ALLSRC}
60
61AArch64GenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
62	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
63		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
64		-o ${.TARGET} ${.ALLSRC}
65
66AArch64GenFastISel.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
67	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \
68		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
69		-o ${.TARGET} ${.ALLSRC}
70
71AArch64GenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
72	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
73		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
74		-o ${.TARGET} ${.ALLSRC}
75
76AArch64GenO0PreLegalizeGICombiner.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
77	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
78		-combiners="AArch64O0PreLegalizerCombinerHelper" \
79		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
80		-o ${.TARGET} ${.ALLSRC}
81
82AArch64GenPreLegalizeGICombiner.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
83	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
84		-combiners="AArch64PreLegalizerCombinerHelper" \
85		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
86		-o ${.TARGET} ${.ALLSRC}
87
88AArch64GenPostLegalizeGICombiner.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
89	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
90		-combiners="AArch64PostLegalizerCombinerHelper" \
91		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
92		-o ${.TARGET} ${.ALLSRC}
93
94AArch64GenPostLegalizeGILowering.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
95	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
96		-combiners="AArch64PostLegalizerLoweringHelper" \
97		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
98		-o ${.TARGET} ${.ALLSRC}
99
100AArch64GenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
101	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
102		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
103		-o ${.TARGET} ${.ALLSRC}
104
105AArch64GenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
106	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
107		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
108		-o ${.TARGET} ${.ALLSRC}
109
110AArch64GenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
111	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
112		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
113		-o ${.TARGET} ${.ALLSRC}
114
115AArch64GenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
116	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
117		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
118		-o ${.TARGET} ${.ALLSRC}
119
120AArch64GenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
121	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
122		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
123		-o ${.TARGET} ${.ALLSRC}
124
125AArch64GenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
126	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
127		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
128		-o ${.TARGET} ${.ALLSRC}
129
130AArch64GenSystemOperands.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
131	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
132		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
133		-o ${.TARGET} ${.ALLSRC}
134
135AArch64GenExegesis.inc: ${LLVM_SRCS}/lib/Target/AArch64/AArch64.td
136	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-exegesis \
137		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AArch64 \
138		-o ${.TARGET} ${.ALLSRC}
139
140.include <bsd.obj.mk>
141