1# $OpenBSD: Makefile,v 1.5 2023/11/16 15:05:44 robert Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm/llvm
6
7HDRS=	AMDGPUGenAsmMatcher.inc \
8	AMDGPUGenAsmWriter.inc \
9	AMDGPUGenCallingConv.inc \
10	AMDGPUGenDAGISel.inc \
11	AMDGPUGenDisassemblerTables.inc \
12	AMDGPUGenInstrInfo.inc \
13	AMDGPUGenMCCodeEmitter.inc \
14	AMDGPUGenMCPseudoLowering.inc \
15	AMDGPUGenRegisterBank.inc \
16	AMDGPUGenRegisterInfo.inc \
17	AMDGPUGenSearchableTables.inc \
18	AMDGPUGenSubtargetInfo.inc
19
20HDRS+=	AMDGPUGenGlobalISel.inc \
21	AMDGPUGenPreLegalizeGICombiner.inc \
22	AMDGPUGenPostLegalizeGICombiner.inc \
23	AMDGPUGenRegBankGICombiner.inc
24
25HDRS+=	R600GenAsmWriter.inc \
26	R600GenCallingConv.inc \
27	R600GenDAGISel.inc \
28	R600GenDFAPacketizer.inc \
29	R600GenInstrInfo.inc \
30	R600GenMCCodeEmitter.inc \
31	R600GenRegisterInfo.inc \
32	R600GenSubtargetInfo.inc
33
34HDRS+=	InstCombineTables.inc
35
36.if ${MACHINE_CPU} == "i386"
37.NOTPARALLEL: ${HDRS}
38.endif
39
40all: ${HDRS}
41
42install:
43	@# Nothing here so far ...
44
45clean cleandir:
46	rm -f ${HDRS}
47
48AMDGPUGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
49	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
50		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
51		-o ${.TARGET} ${.ALLSRC}
52AMDGPUGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
53	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
54		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
55		-o ${.TARGET} ${.ALLSRC}
56AMDGPUGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
57	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
58		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
59		-o ${.TARGET} ${.ALLSRC}
60AMDGPUGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
61	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
62		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
63		-o ${.TARGET} ${.ALLSRC}
64AMDGPUGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
65	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
66		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
67		-o ${.TARGET} ${.ALLSRC}
68AMDGPUGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
69	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
70		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
71		-o ${.TARGET} ${.ALLSRC}
72AMDGPUGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
73	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
74		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
75		-o ${.TARGET} ${.ALLSRC}
76AMDGPUGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
77	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
78		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
79		-o ${.TARGET} ${.ALLSRC}
80AMDGPUGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
81	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
82		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
83		-o ${.TARGET} ${.ALLSRC}
84AMDGPUGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
85	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
86		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
87		-o ${.TARGET} ${.ALLSRC}
88AMDGPUGenSearchableTables.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
89	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
90		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
91		-o ${.TARGET} ${.ALLSRC}
92AMDGPUGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
93	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
94		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
95		-o ${.TARGET} ${.ALLSRC}
96
97AMDGPUGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPUGISel.td
98	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
99		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
100		-o ${.TARGET} ${.ALLSRC}
101AMDGPUGenPreLegalizeGICombiner.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPUGISel.td
102	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
103		-combiners="AMDGPUPreLegalizerCombinerHelper" \
104		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
105		-o ${.TARGET} ${.ALLSRC}
106AMDGPUGenPostLegalizeGICombiner.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPUGISel.td
107	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
108		-combiners="AMDGPUPostLegalizerCombinerHelper" \
109		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
110		-o ${.TARGET} ${.ALLSRC}
111AMDGPUGenRegBankGICombiner.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPUGISel.td
112	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
113		-combiners="AMDGPURegBankCombinerHelper" \
114		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
115		-o ${.TARGET} ${.ALLSRC}
116
117R600GenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
118	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
119		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
120		-o ${.TARGET} ${.ALLSRC}
121R600GenCallingConv.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
122	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
123		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
124		-o ${.TARGET} ${.ALLSRC}
125R600GenDAGISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
126	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
127		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
128		-o ${.TARGET} ${.ALLSRC}
129R600GenDFAPacketizer.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
130	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dfa-packetizer \
131		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
132		-o ${.TARGET} ${.ALLSRC}
133R600GenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
134	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
135		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
136		-o ${.TARGET} ${.ALLSRC}
137R600GenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
138	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
139		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
140		-o ${.TARGET} ${.ALLSRC}
141R600GenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
142	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
143		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
144		-o ${.TARGET} ${.ALLSRC}
145R600GenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
146	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
147		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
148		-o ${.TARGET} ${.ALLSRC}
149
150InstCombineTables.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/InstCombineTables.td
151	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
152		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
153		-o ${.TARGET} ${.ALLSRC}
154
155.include <bsd.obj.mk>
156