1# $OpenBSD: Makefile,v 1.3 2023/11/11 18:35:36 robert Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm/llvm
6
7HDRS=	RISCVGenAsmMatcher.inc \
8	RISCVGenAsmWriter.inc \
9	RISCVGenCompressInstEmitter.inc \
10	RISCVGenDAGISel.inc \
11	RISCVGenDisassemblerTables.inc \
12	RISCVGenGlobalISel.inc \
13	RISCVGenInstrInfo.inc \
14	RISCVGenMCCodeEmitter.inc \
15	RISCVGenMCPseudoLowering.inc \
16	RISCVGenRegisterBank.inc \
17	RISCVGenRegisterInfo.inc \
18	RISCVGenSearchableTables.inc \
19	RISCVGenSubtargetInfo.inc
20
21all: ${HDRS}
22
23install:
24	@# Nothing here so far ...
25
26clean cleandir:
27	rm -f ${HDRS}
28
29RISCVGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
30	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
31		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
32		-o ${.TARGET} ${.ALLSRC}
33
34RISCVGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
35	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
36		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
37		-o ${.TARGET} ${.ALLSRC}
38
39RISCVGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
40	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
41		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
42		-o ${.TARGET} ${.ALLSRC}
43
44RISCVGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
45	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
46		-I${LLVM_SRCS}/include \
47		-I${LLVM_SRCS}/lib/Target/RISCV -o ${.TARGET} ${.ALLSRC}
48
49RISCVGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
50	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
51		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
52		-o ${.TARGET} ${.ALLSRC}
53
54RISCVGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
55	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
56		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
57		-o ${.TARGET} ${.ALLSRC}
58
59RISCVGenFastISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
60	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \
61		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
62		-o ${.TARGET} ${.ALLSRC}
63
64RISCVGenCompressInstEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
65	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-compress-inst-emitter \
66		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
67		-o ${.TARGET} ${.ALLSRC}
68
69RISCVGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
70	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
71		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
72		-o ${.TARGET} ${.ALLSRC}
73
74RISCVGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
75	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
76		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
77		-o ${.TARGET} ${.ALLSRC}
78
79RISCVGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
80	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
81		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
82		-o ${.TARGET} ${.ALLSRC}
83
84RISCVGenSearchableTables.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
85	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
86		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
87		-o ${.TARGET} ${.ALLSRC}
88
89RISCVGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
90	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
91		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
92		-o ${.TARGET} ${.ALLSRC}
93
94RISCVGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
95	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
96		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
97		-o ${.TARGET} ${.ALLSRC}
98
99RISCVGenCompressInstEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
100	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen --gen-compress-inst-emitter \
101		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
102		-o ${.TARGET} ${.ALLSRC}
103
104RISCVGenGICombiner.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
105	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
106		-combiners="RISCVPreLegalizerCombinerHelper" \
107		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
108		-o ${.TARGET} ${.ALLSRC}
109
110.include <bsd.obj.mk>
111