1# $OpenBSD: Makefile,v 1.1 2021/04/29 05:32:01 drahn Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm/llvm
6
7HDRS=	RISCVGenAsmMatcher.inc RISCVGenAsmWriter.inc \
8	RISCVGenCallingConv.inc RISCVGenDAGISel.inc \
9	RISCVGenDisassemblerTables.inc \
10	RISCVGenInstrInfo.inc RISCVGenRegisterInfo.inc \
11	RISCVGenSubtargetInfo.inc \
12	RISCVGenMCCodeEmitter.inc RISCVGenMCPseudoLowering.inc \
13	RISCVGenSystemOperands.inc RISCVGenRegisterBank.inc \
14	RISCVGenGlobalISel.inc RISCVGenCompressInstEmitter.inc
15
16# RISCVGenGICombiner.inc  RISCVGenFastISel.inc
17
18all: ${HDRS}
19
20install:
21	@# Nothing here so far ...
22
23clean cleandir:
24	rm -f ${HDRS}
25
26RISCVGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
27	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
28		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
29		-o ${.TARGET} ${.ALLSRC}
30
31RISCVGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
32	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
33		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
34		-o ${.TARGET} ${.ALLSRC}
35
36RISCVGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
37	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
38		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
39		-o ${.TARGET} ${.ALLSRC}
40
41RISCVGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
42	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
43		-I${LLVM_SRCS}/include \
44		-I${LLVM_SRCS}/lib/Target/RISCV -o ${.TARGET} ${.ALLSRC}
45
46RISCVGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
47	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
48		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
49		-o ${.TARGET} ${.ALLSRC}
50
51RISCVGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
52	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
53		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
54		-o ${.TARGET} ${.ALLSRC}
55
56RISCVGenFastISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
57	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \
58		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
59		-o ${.TARGET} ${.ALLSRC}
60
61RISCVGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
62	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
63		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
64		-o ${.TARGET} ${.ALLSRC}
65
66RISCVGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
67	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
68		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
69		-o ${.TARGET} ${.ALLSRC}
70
71RISCVGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
72	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
73		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
74		-o ${.TARGET} ${.ALLSRC}
75
76RISCVGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
77	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
78		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
79		-o ${.TARGET} ${.ALLSRC}
80
81RISCVGenSystemOperands.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
82	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
83		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
84		-o ${.TARGET} ${.ALLSRC}
85
86RISCVGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
87	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
88		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
89		-o ${.TARGET} ${.ALLSRC}
90
91RISCVGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
92	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
93		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
94		-o ${.TARGET} ${.ALLSRC}
95
96RISCVGenCompressInstEmitter.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
97	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen --gen-compress-inst-emitter \
98		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
99		-o ${.TARGET} ${.ALLSRC}
100
101RISCVGenGICombiner.inc: ${LLVM_SRCS}/lib/Target/RISCV/RISCV.td
102	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel-combiner \
103		-combiners="RISCVPreLegalizerCombinerHelper" \
104		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/RISCV \
105		-o ${.TARGET} ${.ALLSRC}
106
107.include <bsd.obj.mk>
108