1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 3 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com). 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8 This file is part of GNU CC. 9 10 GNU CC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GNU CC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GNU CC; see the file COPYING. If not, write to 22 the Free Software Foundation, 59 Temple Place - Suite 330, 23 Boston, MA 02111-1307, USA. */ 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 29 /* #define SPARC_BI_ARCH */ 30 31 /* Macro used later in this file to determine default architecture. */ 32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 33 34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 35 architectures to compile for. We allow targets to choose compile time or 36 runtime selection. */ 37 #ifdef IN_LIBGCC2 38 #if defined(__sparcv9) || defined(__arch64__) 39 #define TARGET_ARCH32 0 40 #else 41 #define TARGET_ARCH32 1 42 #endif /* sparc64 */ 43 #else 44 #ifdef SPARC_BI_ARCH 45 #define TARGET_ARCH32 (! TARGET_64BIT) 46 #else 47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 48 #endif /* SPARC_BI_ARCH */ 49 #endif /* IN_LIBGCC2 */ 50 #define TARGET_ARCH64 (! TARGET_ARCH32) 51 52 /* Code model selection. 53 -mcmodel is used to select the v9 code model. 54 Different code models aren't supported for v7/8 code. 55 56 TARGET_CM_32: 32 bit address space, top 32 bits = 0, 57 pointers are 32 bits. Note that this isn't intended 58 to imply a v7/8 abi. 59 60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0, 61 avoid generating %uhi and %ulo terms, 62 pointers are 64 bits. 63 64 TARGET_CM_MEDMID: 64 bit address space. 65 The executable must be in the low 16 TB of memory. 66 This corresponds to the low 44 bits, and the %[hml]44 67 relocs are used. The text segment has a maximum size 68 of 31 bits. 69 70 TARGET_CM_MEDANY: 64 bit address space. 71 The text and data segments have a maximum size of 31 72 bits and may be located anywhere. The maximum offset 73 from any instruction to the label _GLOBAL_OFFSET_TABLE_ 74 is 31 bits. 75 76 TARGET_CM_EMBMEDANY: 64 bit address space. 77 The text and data segments have a maximum size of 31 bits 78 and may be located anywhere. Register %g4 contains 79 the start address of the data segment. 80 */ 81 82 enum cmodel { 83 CM_32, 84 CM_MEDLOW, 85 CM_MEDMID, 86 CM_MEDANY, 87 CM_EMBMEDANY 88 }; 89 90 /* Value of -mcmodel specified by user. */ 91 extern const char *sparc_cmodel_string; 92 /* One of CM_FOO. */ 93 extern enum cmodel sparc_cmodel; 94 95 /* V9 code model selection. */ 96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 100 101 #define SPARC_DEFAULT_CMODEL CM_32 102 103 /* This is call-clobbered in the normal ABI, but is reserved in the 104 home grown (aka upward compatible) embedded ABI. */ 105 #define EMBMEDANY_BASE_REG "%g4" 106 107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 108 and specified by the user via --with-cpu=foo. 109 This specifies the cpu implementation, not the architecture size. */ 110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 111 capable cpu's. */ 112 #define TARGET_CPU_sparc 0 113 #define TARGET_CPU_v7 0 /* alias for previous */ 114 #define TARGET_CPU_sparclet 1 115 #define TARGET_CPU_sparclite 2 116 #define TARGET_CPU_v8 3 /* generic v8 implementation */ 117 #define TARGET_CPU_supersparc 4 118 #define TARGET_CPU_hypersparc 5 119 #define TARGET_CPU_sparc86x 6 120 #define TARGET_CPU_sparclite86x 6 121 #define TARGET_CPU_v9 7 /* generic v9 implementation */ 122 #define TARGET_CPU_sparcv9 7 /* alias */ 123 #define TARGET_CPU_sparc64 7 /* alias */ 124 #define TARGET_CPU_ultrasparc 8 125 #define TARGET_CPU_ultrasparc3 9 126 127 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 128 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 129 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 130 131 #define CPP_CPU32_DEFAULT_SPEC "" 132 #define ASM_CPU32_DEFAULT_SPEC "" 133 134 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 135 /* ??? What does Sun's CC pass? */ 136 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 137 /* ??? It's not clear how other assemblers will handle this, so by default 138 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 139 is handled in sol2.h. */ 140 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 141 #endif 142 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 143 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 144 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 145 #endif 146 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 147 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 148 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 149 #endif 150 151 #else 152 153 #define CPP_CPU64_DEFAULT_SPEC "" 154 #define ASM_CPU64_DEFAULT_SPEC "" 155 156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 157 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 158 #define CPP_CPU32_DEFAULT_SPEC "" 159 #define ASM_CPU32_DEFAULT_SPEC "" 160 #endif 161 162 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 163 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 164 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 165 #endif 166 167 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 168 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 169 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 170 #endif 171 172 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 173 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 174 #define ASM_CPU32_DEFAULT_SPEC "" 175 #endif 176 177 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 178 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 179 #define ASM_CPU32_DEFAULT_SPEC "" 180 #endif 181 182 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 183 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 184 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 185 #endif 186 187 #endif 188 189 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 190 #error Unrecognized value in TARGET_CPU_DEFAULT. 191 #endif 192 193 #ifdef SPARC_BI_ARCH 194 195 #define CPP_CPU_DEFAULT_SPEC \ 196 (DEFAULT_ARCH32_P ? "\ 197 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 198 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 199 " : "\ 200 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 201 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 202 ") 203 #define ASM_CPU_DEFAULT_SPEC \ 204 (DEFAULT_ARCH32_P ? "\ 205 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 206 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 207 " : "\ 208 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 209 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 210 ") 211 212 #else /* !SPARC_BI_ARCH */ 213 214 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 215 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 216 217 #endif /* !SPARC_BI_ARCH */ 218 219 /* Define macros to distinguish architectures. */ 220 221 /* Common CPP definitions used by CPP_SPEC amongst the various targets 222 for handling -mcpu=xxx switches. */ 223 #define CPP_CPU_SPEC "\ 224 %{msoft-float:-D_SOFT_FLOAT} \ 225 %{mcypress:} \ 226 %{msparclite:-D__sparclite__} \ 227 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 228 %{mv8:-D__sparc_v8__} \ 229 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 230 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 231 %{mcpu=sparclite:-D__sparclite__} \ 232 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 233 %{mcpu=v8:-D__sparc_v8__} \ 234 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 235 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 236 %{mcpu=sparclite86x:-D__sparclite86x__} \ 237 %{mcpu=v9:-D__sparc_v9__} \ 238 %{mcpu=ultrasparc:-D__sparc_v9__} \ 239 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 240 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ 241 " 242 243 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses 244 the right varags.h file when bootstrapping. */ 245 /* ??? It's not clear what value we want to use for -Acpu/machine for 246 sparc64 in 32 bit environments, so for now we only use `sparc64' in 247 64 bit environments. */ 248 249 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc" 250 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64" 251 252 #define CPP_ARCH_DEFAULT_SPEC \ 253 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 254 255 #define CPP_ARCH_SPEC "\ 256 %{m32:%(cpp_arch32)} \ 257 %{m64:%(cpp_arch64)} \ 258 %{!m32:%{!m64:%(cpp_arch_default)}} \ 259 " 260 261 /* Macros to distinguish endianness. */ 262 #define CPP_ENDIAN_SPEC "\ 263 %{mlittle-endian:-D__LITTLE_ENDIAN__} \ 264 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" 265 266 /* Macros to distinguish the particular subtarget. */ 267 #define CPP_SUBTARGET_SPEC "" 268 269 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" 270 271 /* Prevent error on `-sun4' and `-target sun4' options. */ 272 /* This used to translate -dalign to -malign, but that is no good 273 because it can't turn off the usual meaning of making debugging dumps. */ 274 /* Translate old style -m<cpu> into new style -mcpu=<cpu>. 275 ??? Delete support for -m<cpu> for 2.9. */ 276 277 #define CC1_SPEC "\ 278 %{sun4:} %{target:} \ 279 %{mcypress:-mcpu=cypress} \ 280 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ 281 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ 282 " 283 284 /* Override in target specific files. */ 285 #define ASM_CPU_SPEC "\ 286 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 287 %{msparclite:-Asparclite} \ 288 %{mf930:-Asparclite} %{mf934:-Asparclite} \ 289 %{mcpu=sparclite:-Asparclite} \ 290 %{mcpu=sparclite86x:-Asparclite} \ 291 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 292 %{mv8plus:-Av8plus} \ 293 %{mcpu=v9:-Av9} \ 294 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 295 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 296 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ 297 " 298 299 /* Word size selection, among other things. 300 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 301 302 #define ASM_ARCH32_SPEC "-32" 303 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 304 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 305 #else 306 #define ASM_ARCH64_SPEC "-64" 307 #endif 308 #define ASM_ARCH_DEFAULT_SPEC \ 309 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 310 311 #define ASM_ARCH_SPEC "\ 312 %{m32:%(asm_arch32)} \ 313 %{m64:%(asm_arch64)} \ 314 %{!m32:%{!m64:%(asm_arch_default)}} \ 315 " 316 317 #ifdef HAVE_AS_RELAX_OPTION 318 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 319 #else 320 #define ASM_RELAX_SPEC "" 321 #endif 322 323 /* Special flags to the Sun-4 assembler when using pipe for input. */ 324 325 #define ASM_SPEC "\ 326 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \ 327 %(asm_cpu) %(asm_relax)" 328 329 /* This macro defines names of additional specifications to put in the specs 330 that can be used in various specifications like CC1_SPEC. Its definition 331 is an initializer with a subgrouping for each command option. 332 333 Each subgrouping contains a string constant, that defines the 334 specification name, and a string constant that used by the GNU CC driver 335 program. 336 337 Do not define this macro if it does not need to do anything. */ 338 339 #define EXTRA_SPECS \ 340 { "cpp_cpu", CPP_CPU_SPEC }, \ 341 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 342 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 343 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 344 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 345 { "cpp_arch", CPP_ARCH_SPEC }, \ 346 { "cpp_endian", CPP_ENDIAN_SPEC }, \ 347 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 348 { "asm_cpu", ASM_CPU_SPEC }, \ 349 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 350 { "asm_arch32", ASM_ARCH32_SPEC }, \ 351 { "asm_arch64", ASM_ARCH64_SPEC }, \ 352 { "asm_relax", ASM_RELAX_SPEC }, \ 353 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 354 { "asm_arch", ASM_ARCH_SPEC }, \ 355 SUBTARGET_EXTRA_SPECS 356 357 #define SUBTARGET_EXTRA_SPECS 358 359 /* Because libgcc can generate references back to libc (via .umul etc.) we have 360 to list libc again after the second libgcc. */ 361 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 362 363 364 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 365 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 366 367 /* ??? This should be 32 bits for v9 but what can we do? */ 368 #define WCHAR_TYPE "short unsigned int" 369 #define WCHAR_TYPE_SIZE 16 370 371 /* Show we can debug even without a frame pointer. */ 372 #define CAN_DEBUG_WITHOUT_FP 373 374 #define OVERRIDE_OPTIONS sparc_override_options () 375 376 /* Generate DBX debugging information. */ 377 378 #define DBX_DEBUGGING_INFO 1 379 380 /* Run-time compilation parameters selecting different hardware subsets. */ 381 382 extern int target_flags; 383 384 /* Nonzero if we should generate code to use the fpu. */ 385 #define MASK_FPU 1 386 #define TARGET_FPU (target_flags & MASK_FPU) 387 388 /* Nonzero if we should assume that double pointers might be unaligned. 389 This can happen when linking gcc compiled code with other compilers, 390 because the ABI only guarantees 4 byte alignment. */ 391 #define MASK_UNALIGNED_DOUBLES 4 392 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) 393 394 /* Nonzero means that we should generate code for a v8 sparc. */ 395 #define MASK_V8 0x8 396 #define TARGET_V8 (target_flags & MASK_V8) 397 398 /* Nonzero means that we should generate code for a sparclite. 399 This enables the sparclite specific instructions, but does not affect 400 whether FPU instructions are emitted. */ 401 #define MASK_SPARCLITE 0x10 402 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) 403 404 /* Nonzero if we're compiling for the sparclet. */ 405 #define MASK_SPARCLET 0x20 406 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET) 407 408 /* Nonzero if we're compiling for v9 sparc. 409 Note that v9's can run in 32 bit mode so this doesn't necessarily mean 410 the word size is 64. */ 411 #define MASK_V9 0x40 412 #define TARGET_V9 (target_flags & MASK_V9) 413 414 /* Nonzero to generate code that uses the instructions deprecated in 415 the v9 architecture. This option only applies to v9 systems. */ 416 /* ??? This isn't user selectable yet. It's used to enable such insns 417 on 32 bit v9 systems and for the moment they're permanently disabled 418 on 64 bit v9 systems. */ 419 #define MASK_DEPRECATED_V8_INSNS 0x80 420 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS) 421 422 /* Mask of all CPU selection flags. */ 423 #define MASK_ISA \ 424 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 425 426 /* Nonzero means don't pass `-assert pure-text' to the linker. */ 427 #define MASK_IMPURE_TEXT 0x100 428 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) 429 430 /* Nonzero means that we should generate code using a flat register window 431 model, i.e. no save/restore instructions are generated, which is 432 compatible with normal sparc code. 433 The frame pointer is %i7 instead of %fp. */ 434 #define MASK_FLAT 0x200 435 #define TARGET_FLAT (target_flags & MASK_FLAT) 436 437 /* Nonzero means use the registers that the SPARC ABI reserves for 438 application software. This must be the default to coincide with the 439 setting in FIXED_REGISTERS. */ 440 #define MASK_APP_REGS 0x400 441 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) 442 443 /* Option to select how quad word floating point is implemented. 444 When TARGET_HARD_QUAD is true, we use the hardware quad instructions. 445 Otherwise, we use the SPARC ABI quad library functions. */ 446 #define MASK_HARD_QUAD 0x800 447 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) 448 449 /* Nonzero on little-endian machines. */ 450 /* ??? Little endian support currently only exists for sparclet-aout and 451 sparc64-elf configurations. May eventually want to expand the support 452 to all targets, but for now it's kept local to only those two. */ 453 #define MASK_LITTLE_ENDIAN 0x1000 454 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN) 455 456 /* 0x2000, 0x4000 are unused */ 457 458 /* Nonzero if pointers are 64 bits. */ 459 #define MASK_PTR64 0x8000 460 #define TARGET_PTR64 (target_flags & MASK_PTR64) 461 462 /* Nonzero if generating code to run in a 64 bit environment. 463 This is intended to only be used by TARGET_ARCH{32,64} as they are the 464 mechanism used to control compile time or run time selection. */ 465 #define MASK_64BIT 0x10000 466 #define TARGET_64BIT (target_flags & MASK_64BIT) 467 468 /* 0x20000,0x40000 unused */ 469 470 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by 471 adding 2047 to %sp. This option is for v9 only and is the default. */ 472 #define MASK_STACK_BIAS 0x80000 473 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) 474 475 /* 0x100000,0x200000 unused */ 476 477 /* Nonzero means -m{,no-}fpu was passed on the command line. */ 478 #define MASK_FPU_SET 0x400000 479 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET) 480 481 /* Use the UltraSPARC Visual Instruction Set extensions. */ 482 #define MASK_VIS 0x1000000 483 #define TARGET_VIS (target_flags & MASK_VIS) 484 485 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of 486 the current out and global registers and Linux 2.2+ as well. */ 487 #define MASK_V8PLUS 0x2000000 488 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS) 489 490 /* Force a the fastest alignment on structures to take advantage of 491 faster copies. */ 492 #define MASK_FASTER_STRUCTS 0x4000000 493 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS) 494 495 /* Use IEEE quad long double. */ 496 #define MASK_LONG_DOUBLE_128 0x8000000 497 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128) 498 499 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. 500 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y 501 to get high 32 bits. False in V8+ or V9 because multiply stores 502 a 64 bit result in a register. */ 503 504 #define TARGET_HARD_MUL32 \ 505 ((TARGET_V8 || TARGET_SPARCLITE \ 506 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ 507 && ! TARGET_V8PLUS && TARGET_ARCH32) 508 509 #define TARGET_HARD_MUL \ 510 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ 511 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) 512 513 514 /* Macro to define tables used to set the flags. 515 This is a list in braces of pairs in braces, 516 each pair being { "NAME", VALUE } 517 where VALUE is the bits to set or minus the bits to clear. 518 An empty string NAME is used to identify the default VALUE. */ 519 520 #define TARGET_SWITCHES \ 521 { {"fpu", MASK_FPU | MASK_FPU_SET, \ 522 N_("Use hardware fp") }, \ 523 {"no-fpu", -MASK_FPU, \ 524 N_("Do not use hardware fp") }, \ 525 {"no-fpu", MASK_FPU_SET, NULL, }, \ 526 {"hard-float", MASK_FPU | MASK_FPU_SET, \ 527 N_("Use hardware fp") }, \ 528 {"soft-float", -MASK_FPU, \ 529 N_("Do not use hardware fp") }, \ 530 {"soft-float", MASK_FPU_SET, NULL }, \ 531 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \ 532 N_("Assume possible double misalignment") }, \ 533 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \ 534 N_("Assume all doubles are aligned") }, \ 535 {"impure-text", MASK_IMPURE_TEXT, \ 536 N_("Pass -assert pure-text to linker") }, \ 537 {"no-impure-text", -MASK_IMPURE_TEXT, \ 538 N_("Do not pass -assert pure-text to linker") }, \ 539 {"flat", MASK_FLAT, \ 540 N_("Use flat register window model") }, \ 541 {"no-flat", -MASK_FLAT, \ 542 N_("Do not use flat register window model") }, \ 543 {"app-regs", MASK_APP_REGS, \ 544 N_("Use ABI reserved registers") }, \ 545 {"no-app-regs", -MASK_APP_REGS, \ 546 N_("Do not use ABI reserved registers") }, \ 547 {"hard-quad-float", MASK_HARD_QUAD, \ 548 N_("Use hardware quad fp instructions") }, \ 549 {"soft-quad-float", -MASK_HARD_QUAD, \ 550 N_("Do not use hardware quad fp instructions") }, \ 551 {"v8plus", MASK_V8PLUS, \ 552 N_("Compile for v8plus ABI") }, \ 553 {"no-v8plus", -MASK_V8PLUS, \ 554 N_("Do not compile for v8plus ABI") }, \ 555 {"vis", MASK_VIS, \ 556 N_("Utilize Visual Instruction Set") }, \ 557 {"no-vis", -MASK_VIS, \ 558 N_("Do not utilize Visual Instruction Set") }, \ 559 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ 560 {"cypress", 0, \ 561 N_("Optimize for Cypress processors") }, \ 562 {"sparclite", 0, \ 563 N_("Optimize for SPARCLite processors") }, \ 564 {"f930", 0, \ 565 N_("Optimize for F930 processors") }, \ 566 {"f934", 0, \ 567 N_("Optimize for F934 processors") }, \ 568 {"v8", 0, \ 569 N_("Use V8 SPARC ISA") }, \ 570 {"supersparc", 0, \ 571 N_("Optimize for SuperSPARC processors") }, \ 572 /* End of deprecated options. */ \ 573 {"ptr64", MASK_PTR64, \ 574 N_("Pointers are 64-bit") }, \ 575 {"ptr32", -MASK_PTR64, \ 576 N_("Pointers are 32-bit") }, \ 577 {"32", -MASK_64BIT, \ 578 N_("Use 32-bit ABI") }, \ 579 {"64", MASK_64BIT, \ 580 N_("Use 64-bit ABI") }, \ 581 {"stack-bias", MASK_STACK_BIAS, \ 582 N_("Use stack bias") }, \ 583 {"no-stack-bias", -MASK_STACK_BIAS, \ 584 N_("Do not use stack bias") }, \ 585 {"faster-structs", MASK_FASTER_STRUCTS, \ 586 N_("Use structs on stronger alignment for double-word copies") }, \ 587 {"no-faster-structs", -MASK_FASTER_STRUCTS, \ 588 N_("Do not use structs on stronger alignment for double-word copies") }, \ 589 {"relax", 0, \ 590 N_("Optimize tail call instructions in assembler and linker") }, \ 591 {"no-relax", 0, \ 592 N_("Do not optimize tail call instructions in assembler or linker") }, \ 593 SUBTARGET_SWITCHES \ 594 { "", TARGET_DEFAULT, ""}} 595 596 /* MASK_APP_REGS must always be the default because that's what 597 FIXED_REGISTERS is set to and -ffixed- is processed before 598 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ 599 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 600 601 /* This is meant to be redefined in target specific files. */ 602 #define SUBTARGET_SWITCHES 603 604 /* Processor type. 605 These must match the values for the cpu attribute in sparc.md. */ 606 enum processor_type { 607 PROCESSOR_V7, 608 PROCESSOR_CYPRESS, 609 PROCESSOR_V8, 610 PROCESSOR_SUPERSPARC, 611 PROCESSOR_SPARCLITE, 612 PROCESSOR_F930, 613 PROCESSOR_F934, 614 PROCESSOR_HYPERSPARC, 615 PROCESSOR_SPARCLITE86X, 616 PROCESSOR_SPARCLET, 617 PROCESSOR_TSC701, 618 PROCESSOR_V9, 619 PROCESSOR_ULTRASPARC, 620 PROCESSOR_ULTRASPARC3 621 }; 622 623 /* This is set from -m{cpu,tune}=xxx. */ 624 extern enum processor_type sparc_cpu; 625 626 /* Recast the cpu class to be the cpu attribute. 627 Every file includes us, but not every file includes insn-attr.h. */ 628 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 629 630 #define TARGET_OPTIONS \ 631 { \ 632 { "cpu=", &sparc_select[1].string, \ 633 N_("Use features of and schedule code for given CPU") }, \ 634 { "tune=", &sparc_select[2].string, \ 635 N_("Schedule code for given CPU") }, \ 636 { "cmodel=", &sparc_cmodel_string, \ 637 N_("Use given SPARC code model") }, \ 638 SUBTARGET_OPTIONS \ 639 } 640 641 /* This is meant to be redefined in target specific files. */ 642 #define SUBTARGET_OPTIONS 643 644 /* sparc_select[0] is reserved for the default cpu. */ 645 struct sparc_cpu_select 646 { 647 const char *string; 648 const char *const name; 649 const int set_tune_p; 650 const int set_arch_p; 651 }; 652 653 extern struct sparc_cpu_select sparc_select[]; 654 655 /* target machine storage layout */ 656 657 /* Define this if most significant bit is lowest numbered 658 in instructions that operate on numbered bit-fields. */ 659 #define BITS_BIG_ENDIAN 1 660 661 /* Define this if most significant byte of a word is the lowest numbered. */ 662 #define BYTES_BIG_ENDIAN 1 663 664 /* Define this if most significant word of a multiword number is the lowest 665 numbered. */ 666 #define WORDS_BIG_ENDIAN 1 667 668 /* Define this to set the endianness to use in libgcc2.c, which can 669 not depend on target_flags. */ 670 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) 671 #define LIBGCC2_WORDS_BIG_ENDIAN 0 672 #else 673 #define LIBGCC2_WORDS_BIG_ENDIAN 1 674 #endif 675 676 #define MAX_BITS_PER_WORD 64 677 678 /* Width of a word, in units (bytes). */ 679 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 680 #ifdef IN_LIBGCC2 681 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 682 #else 683 #define MIN_UNITS_PER_WORD 4 684 #endif 685 686 /* Now define the sizes of the C data types. */ 687 688 #define SHORT_TYPE_SIZE 16 689 #define INT_TYPE_SIZE 32 690 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 691 #define LONG_LONG_TYPE_SIZE 64 692 #define FLOAT_TYPE_SIZE 32 693 #define DOUBLE_TYPE_SIZE 64 694 695 #ifdef SPARC_BI_ARCH 696 #define MAX_LONG_TYPE_SIZE 64 697 #endif 698 699 #if 0 700 /* ??? This does not work in SunOS 4.x, so it is not enabled here. 701 Instead, it is enabled in sol2.h, because it does work under Solaris. */ 702 /* Define for support of TFmode long double. 703 SPARC ABI says that long double is 4 words. */ 704 #define LONG_DOUBLE_TYPE_SIZE 128 705 #endif 706 707 /* Width in bits of a pointer. 708 See also the macro `Pmode' defined below. */ 709 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 710 711 /* If we have to extend pointers (only when TARGET_ARCH64 and not 712 TARGET_PTR64), we want to do it unsigned. This macro does nothing 713 if ptr_mode and Pmode are the same. */ 714 #define POINTERS_EXTEND_UNSIGNED 1 715 716 /* A macro to update MODE and UNSIGNEDP when an object whose type 717 is TYPE and which has the specified mode and signedness is to be 718 stored in a register. This macro is only called when TYPE is a 719 scalar type. */ 720 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 721 if (TARGET_ARCH64 \ 722 && GET_MODE_CLASS (MODE) == MODE_INT \ 723 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 724 (MODE) = DImode; 725 726 /* Define this macro if the promotion described by PROMOTE_MODE 727 should also be done for outgoing function arguments. */ 728 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op 729 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test 730 for this value. */ 731 #define PROMOTE_FUNCTION_ARGS 732 733 /* Define this macro if the promotion described by PROMOTE_MODE 734 should also be done for the return value of functions. 735 If this macro is defined, FUNCTION_VALUE must perform the same 736 promotions done by PROMOTE_MODE. */ 737 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op 738 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test 739 for this value. */ 740 #define PROMOTE_FUNCTION_RETURN 741 742 /* Define this macro if the promotion described by PROMOTE_MODE 743 should _only_ be performed for outgoing function arguments or 744 function return values, as specified by PROMOTE_FUNCTION_ARGS 745 and PROMOTE_FUNCTION_RETURN, respectively. */ 746 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op 747 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test 748 for this value. For TARGET_ARCH64 we need it, as we don't have instructions 749 for arithmetic operations which do zero/sign extension at the same time, 750 so without this we end up with a srl/sra after every assignment to an 751 user variable, which means very very bad code. */ 752 #define PROMOTE_FOR_CALL_ONLY 753 754 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 755 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 756 757 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 758 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 759 760 /* ALIGN FRAMES on double word boundaries */ 761 762 #define SPARC_STACK_ALIGN(LOC) \ 763 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 764 765 /* Allocation boundary (in *bits*) for the code of a function. */ 766 #define FUNCTION_BOUNDARY 32 767 768 /* Alignment of field after `int : 0' in a structure. */ 769 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 770 771 /* Every structure's size must be a multiple of this. */ 772 #define STRUCTURE_SIZE_BOUNDARY 8 773 774 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 775 #define PCC_BITFIELD_TYPE_MATTERS 1 776 777 /* No data type wants to be aligned rounder than this. */ 778 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 779 780 /* The best alignment to use in cases where we have a choice. */ 781 #define FASTEST_ALIGNMENT 64 782 783 /* Define this macro as an expression for the alignment of a structure 784 (given by STRUCT as a tree node) if the alignment computed in the 785 usual way is COMPUTED and the alignment explicitly specified was 786 SPECIFIED. 787 788 The default is to use SPECIFIED if it is larger; otherwise, use 789 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 790 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 791 (TARGET_FASTER_STRUCTS ? \ 792 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 793 || TREE_CODE (STRUCT) == UNION_TYPE \ 794 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 795 && TYPE_FIELDS (STRUCT) != 0 \ 796 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 797 : MAX ((COMPUTED), (SPECIFIED))) \ 798 : MAX ((COMPUTED), (SPECIFIED))) 799 800 /* Make strings word-aligned so strcpy from constants will be faster. */ 801 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 802 ((TREE_CODE (EXP) == STRING_CST \ 803 && (ALIGN) < FASTEST_ALIGNMENT) \ 804 ? FASTEST_ALIGNMENT : (ALIGN)) 805 806 /* Make arrays of chars word-aligned for the same reasons. */ 807 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 808 (TREE_CODE (TYPE) == ARRAY_TYPE \ 809 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 810 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 811 812 /* Set this nonzero if move instructions will actually fail to work 813 when given unaligned data. */ 814 #define STRICT_ALIGNMENT 1 815 816 /* Things that must be doubleword aligned cannot go in the text section, 817 because the linker fails to align the text section enough! 818 Put them in the data section. This macro is only used in this file. */ 819 #define MAX_TEXT_ALIGN 32 820 821 /* This forces all variables and constants to the data section when PIC. 822 This is because the SunOS 4 shared library scheme thinks everything in 823 text is a function, and patches the address to point to a loader stub. */ 824 /* This is defined to zero for every system which doesn't use the a.out object 825 file format. */ 826 #ifndef SUNOS4_SHARED_LIBRARIES 827 #define SUNOS4_SHARED_LIBRARIES 0 828 #endif 829 830 /* Standard register usage. */ 831 832 /* Number of actual hardware registers. 833 The hardware registers are assigned numbers for the compiler 834 from 0 to just below FIRST_PSEUDO_REGISTER. 835 All registers that the compiler knows about must be given numbers, 836 even those that are not normally considered general registers. 837 838 SPARC has 32 integer registers and 32 floating point registers. 839 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not 840 accessible. We still account for them to simplify register computations 841 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 842 32+32+32+4 == 100. 843 Register 100 is used as the integer condition code register. 844 Register 101 is used as the soft frame pointer register. */ 845 846 #define FIRST_PSEUDO_REGISTER 102 847 848 #define SPARC_FIRST_FP_REG 32 849 /* Additional V9 fp regs. */ 850 #define SPARC_FIRST_V9_FP_REG 64 851 #define SPARC_LAST_V9_FP_REG 95 852 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 853 #define SPARC_FIRST_V9_FCC_REG 96 854 #define SPARC_LAST_V9_FCC_REG 99 855 /* V8 fcc reg. */ 856 #define SPARC_FCC_REG 96 857 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 858 #define SPARC_ICC_REG 100 859 860 /* Nonzero if REGNO is an fp reg. */ 861 #define SPARC_FP_REG_P(REGNO) \ 862 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 863 864 /* Argument passing regs. */ 865 #define SPARC_OUTGOING_INT_ARG_FIRST 8 866 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 867 #define SPARC_FP_ARG_FIRST 32 868 869 /* 1 for registers that have pervasive standard uses 870 and are not available for the register allocator. 871 872 On non-v9 systems: 873 g1 is free to use as temporary. 874 g2-g4 are reserved for applications. Gcc normally uses them as 875 temporaries, but this can be disabled via the -mno-app-regs option. 876 g5 through g7 are reserved for the operating system. 877 878 On v9 systems: 879 g1,g5 are free to use as temporaries, and are free to use between calls 880 if the call is to an external function via the PLT. 881 g4 is free to use as a temporary in the non-embedded case. 882 g4 is reserved in the embedded case. 883 g2-g3 are reserved for applications. Gcc normally uses them as 884 temporaries, but this can be disabled via the -mno-app-regs option. 885 g6-g7 are reserved for the operating system (or application in 886 embedded case). 887 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 888 currently be a fixed register until this pattern is rewritten. 889 Register 1 is also used when restoring call-preserved registers in large 890 stack frames. 891 892 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 893 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 894 */ 895 896 #define FIXED_REGISTERS \ 897 {1, 0, 2, 2, 2, 2, 1, 1, \ 898 0, 0, 0, 0, 0, 0, 1, 0, \ 899 0, 0, 0, 0, 0, 0, 0, 0, \ 900 0, 0, 0, 0, 0, 0, 1, 1, \ 901 \ 902 0, 0, 0, 0, 0, 0, 0, 0, \ 903 0, 0, 0, 0, 0, 0, 0, 0, \ 904 0, 0, 0, 0, 0, 0, 0, 0, \ 905 0, 0, 0, 0, 0, 0, 0, 0, \ 906 \ 907 0, 0, 0, 0, 0, 0, 0, 0, \ 908 0, 0, 0, 0, 0, 0, 0, 0, \ 909 0, 0, 0, 0, 0, 0, 0, 0, \ 910 0, 0, 0, 0, 0, 0, 0, 0, \ 911 \ 912 0, 0, 0, 0, 0, 1} 913 914 /* 1 for registers not available across function calls. 915 These must include the FIXED_REGISTERS and also any 916 registers that can be used without being saved. 917 The latter must include the registers where values are returned 918 and the register where structure-value addresses are passed. 919 Aside from that, you can include as many other registers as you like. */ 920 921 #define CALL_USED_REGISTERS \ 922 {1, 1, 1, 1, 1, 1, 1, 1, \ 923 1, 1, 1, 1, 1, 1, 1, 1, \ 924 0, 0, 0, 0, 0, 0, 0, 0, \ 925 0, 0, 0, 0, 0, 0, 1, 1, \ 926 \ 927 1, 1, 1, 1, 1, 1, 1, 1, \ 928 1, 1, 1, 1, 1, 1, 1, 1, \ 929 1, 1, 1, 1, 1, 1, 1, 1, \ 930 1, 1, 1, 1, 1, 1, 1, 1, \ 931 \ 932 1, 1, 1, 1, 1, 1, 1, 1, \ 933 1, 1, 1, 1, 1, 1, 1, 1, \ 934 1, 1, 1, 1, 1, 1, 1, 1, \ 935 1, 1, 1, 1, 1, 1, 1, 1, \ 936 \ 937 1, 1, 1, 1, 1, 1} 938 939 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that 940 they won't be allocated. */ 941 942 #define CONDITIONAL_REGISTER_USAGE \ 943 do \ 944 { \ 945 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 946 { \ 947 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 948 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 949 } \ 950 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ 951 /* then honor it. */ \ 952 if (TARGET_ARCH32 && fixed_regs[5]) \ 953 fixed_regs[5] = 1; \ 954 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ 955 fixed_regs[5] = 0; \ 956 if (! TARGET_V9) \ 957 { \ 958 int regno; \ 959 for (regno = SPARC_FIRST_V9_FP_REG; \ 960 regno <= SPARC_LAST_V9_FP_REG; \ 961 regno++) \ 962 fixed_regs[regno] = 1; \ 963 /* %fcc0 is used by v8 and v9. */ \ 964 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ 965 regno <= SPARC_LAST_V9_FCC_REG; \ 966 regno++) \ 967 fixed_regs[regno] = 1; \ 968 } \ 969 if (! TARGET_FPU) \ 970 { \ 971 int regno; \ 972 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ 973 fixed_regs[regno] = 1; \ 974 } \ 975 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ 976 /* then honor it. Likewise with g3 and g4. */ \ 977 if (fixed_regs[2] == 2) \ 978 fixed_regs[2] = ! TARGET_APP_REGS; \ 979 if (fixed_regs[3] == 2) \ 980 fixed_regs[3] = ! TARGET_APP_REGS; \ 981 if (TARGET_ARCH32 && fixed_regs[4] == 2) \ 982 fixed_regs[4] = ! TARGET_APP_REGS; \ 983 else if (TARGET_CM_EMBMEDANY) \ 984 fixed_regs[4] = 1; \ 985 else if (fixed_regs[4] == 2) \ 986 fixed_regs[4] = 0; \ 987 if (TARGET_FLAT) \ 988 { \ 989 int regno; \ 990 /* Let the compiler believe the frame pointer is still \ 991 %fp, but output it as %i7. */ \ 992 fixed_regs[31] = 1; \ 993 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \ 994 /* Disable leaf functions */ \ 995 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \ 996 /* Make LEAF_REG_REMAP a noop. */ \ 997 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ 998 leaf_reg_remap [regno] = regno; \ 999 } \ 1000 } \ 1001 while (0) 1002 1003 /* Return number of consecutive hard regs needed starting at reg REGNO 1004 to hold something of mode MODE. 1005 This is ordinarily the length in words of a value of mode MODE 1006 but can be less for certain modes in special long registers. 1007 1008 On SPARC, ordinary registers hold 32 bits worth; 1009 this means both integer and floating point registers. 1010 On v9, integer regs hold 64 bits worth; floating point regs hold 1011 32 bits worth (this includes the new fp regs as even the odd ones are 1012 included in the hard register count). */ 1013 1014 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1015 (TARGET_ARCH64 \ 1016 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ 1017 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 1018 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 1019 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1020 1021 /* Due to the ARCH64 descrepancy above we must override this next 1022 macro too. */ 1023 #define REGMODE_NATURAL_SIZE(MODE) \ 1024 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) 1025 1026 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1027 See sparc.c for how we initialize this. */ 1028 extern const int *hard_regno_mode_classes; 1029 extern int sparc_mode_class[]; 1030 1031 /* ??? Because of the funny way we pass parameters we should allow certain 1032 ??? types of float/complex values to be in integer registers during 1033 ??? RTL generation. This only matters on arch32. */ 1034 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1035 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 1036 1037 /* Value is 1 if it is a good idea to tie two pseudo registers 1038 when one has mode MODE1 and one has mode MODE2. 1039 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1040 for any hard reg, then this must be 0 for correct output. 1041 1042 For V9: SFmode can't be combined with other float modes, because they can't 1043 be allocated to the %d registers. Also, DFmode won't fit in odd %f 1044 registers, but SFmode will. */ 1045 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1046 ((MODE1) == (MODE2) \ 1047 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 1048 && (! TARGET_V9 \ 1049 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 1050 || (MODE1 != SFmode && MODE2 != SFmode))))) 1051 1052 /* Specify the registers used for certain standard purposes. 1053 The values of these macros are register numbers. */ 1054 1055 /* SPARC pc isn't overloaded on a register that the compiler knows about. */ 1056 /* #define PC_REGNUM */ 1057 1058 /* Register to use for pushing function arguments. */ 1059 #define STACK_POINTER_REGNUM 14 1060 1061 /* The stack bias (amount by which the hardware register is offset by). */ 1062 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 1063 1064 /* Actual top-of-stack address is 92/176 greater than the contents of the 1065 stack pointer register for !v9/v9. That is: 1066 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 1067 address, and 6*4 bytes for the 6 register parameters. 1068 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 1069 parameter regs. */ 1070 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 1071 1072 /* Base register for access to local variables of the function. */ 1073 #define HARD_FRAME_POINTER_REGNUM 30 1074 1075 /* The soft frame pointer does not have the stack bias applied. */ 1076 #define FRAME_POINTER_REGNUM 101 1077 1078 /* Given the stack bias, the stack pointer isn't actually aligned. */ 1079 #define INIT_EXPANDERS \ 1080 do { \ 1081 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \ 1082 { \ 1083 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 1084 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 1085 } \ 1086 } while (0) 1087 1088 /* Value should be nonzero if functions must have frame pointers. 1089 Zero means the frame pointer need not be set up (and parms 1090 may be accessed via the stack pointer) in functions that seem suitable. 1091 This is computed in `reload', in reload1.c. 1092 Used in flow.c, global.c, and reload1.c. 1093 1094 Being a non-leaf function does not mean a frame pointer is needed in the 1095 flat window model. However, the debugger won't be able to backtrace through 1096 us with out it. */ 1097 #define FRAME_POINTER_REQUIRED \ 1098 (TARGET_FLAT \ 1099 ? (current_function_calls_alloca \ 1100 || !leaf_function_p ()) \ 1101 : ! (leaf_function_p () && only_leaf_regs_used ())) 1102 1103 /* Base register for access to arguments of the function. */ 1104 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 1105 1106 /* Register in which static-chain is passed to a function. This must 1107 not be a register used by the prologue. */ 1108 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 1109 1110 /* Register which holds offset table for position-independent 1111 data references. */ 1112 1113 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) 1114 1115 /* Pick a default value we can notice from override_options: 1116 !v9: Default is on. 1117 v9: Default is off. */ 1118 1119 #define DEFAULT_PCC_STRUCT_RETURN -1 1120 1121 /* SPARC ABI says that quad-precision floats and all structures are returned 1122 in memory. 1123 For v9: unions <= 32 bytes in size are returned in int regs, 1124 structures up to 32 bytes are returned in int and fp regs. */ 1125 1126 #define RETURN_IN_MEMORY(TYPE) \ 1127 (TARGET_ARCH32 \ 1128 ? (TYPE_MODE (TYPE) == BLKmode \ 1129 || TYPE_MODE (TYPE) == TFmode \ 1130 || TYPE_MODE (TYPE) == TCmode) \ 1131 : (TYPE_MODE (TYPE) == BLKmode \ 1132 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32)) 1133 1134 /* Functions which return large structures get the address 1135 to place the wanted value at offset 64 from the frame. 1136 Must reserve 64 bytes for the in and local registers. 1137 v9: Functions which return large structures get the address to place the 1138 wanted value from an invisible first argument. */ 1139 /* Used only in other #defines in this file. */ 1140 #define STRUCT_VALUE_OFFSET 64 1141 1142 #define STRUCT_VALUE \ 1143 (TARGET_ARCH64 \ 1144 ? 0 \ 1145 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ 1146 STRUCT_VALUE_OFFSET))) 1147 1148 #define STRUCT_VALUE_INCOMING \ 1149 (TARGET_ARCH64 \ 1150 ? 0 \ 1151 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \ 1152 STRUCT_VALUE_OFFSET))) 1153 1154 /* Define the classes of registers for register constraints in the 1155 machine description. Also define ranges of constants. 1156 1157 One of the classes must always be named ALL_REGS and include all hard regs. 1158 If there is more than one class, another class must be named NO_REGS 1159 and contain no registers. 1160 1161 The name GENERAL_REGS must be the name of a class (or an alias for 1162 another name such as ALL_REGS). This is the class of registers 1163 that is allowed by "g" or "r" in a register constraint. 1164 Also, registers outside this class are allocated only when 1165 instructions express preferences for them. 1166 1167 The classes must be numbered in nondecreasing order; that is, 1168 a larger-numbered class must never be contained completely 1169 in a smaller-numbered class. 1170 1171 For any two classes, it is very desirable that there be another 1172 class that represents their union. */ 1173 1174 /* The SPARC has various kinds of registers: general, floating point, 1175 and condition codes [well, it has others as well, but none that we 1176 care directly about]. 1177 1178 For v9 we must distinguish between the upper and lower floating point 1179 registers because the upper ones can't hold SFmode values. 1180 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 1181 satisfying a group need for a class will also satisfy a single need for 1182 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 1183 regs. 1184 1185 It is important that one class contains all the general and all the standard 1186 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 1187 because reg_class_record() will bias the selection in favor of fp regs, 1188 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 1189 because FP_REGS > GENERAL_REGS. 1190 1191 It is also important that one class contain all the general and all the 1192 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS 1193 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause 1194 allocate_reload_reg() to bypass it causing an abort because the compiler 1195 thinks it doesn't have a spill reg when in fact it does. 1196 1197 v9 also has 4 floating point condition code registers. Since we don't 1198 have a class that is the union of FPCC_REGS with either of the others, 1199 it is important that it appear first. Otherwise the compiler will die 1200 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 1201 constraints. 1202 1203 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 1204 may try to use it to hold an SImode value. See register_operand. 1205 ??? Should %fcc[0123] be handled similarly? 1206 */ 1207 1208 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 1209 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 1210 ALL_REGS, LIM_REG_CLASSES }; 1211 1212 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1213 1214 /* Give names of register classes as strings for dump file. */ 1215 1216 #define REG_CLASS_NAMES \ 1217 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 1218 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 1219 "ALL_REGS" } 1220 1221 /* Define which registers fit in which classes. 1222 This is an initializer for a vector of HARD_REG_SET 1223 of length N_REG_CLASSES. */ 1224 1225 #define REG_CLASS_CONTENTS \ 1226 {{0, 0, 0, 0}, /* NO_REGS */ \ 1227 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 1228 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 1229 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 1230 {0, -1, 0, 0}, /* FP_REGS */ \ 1231 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 1232 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 1233 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 1234 {-1, -1, -1, 0x3f}} /* ALL_REGS */ 1235 1236 /* Defines invalid mode changes. Borrowed from pa64-regs.h. 1237 1238 SImode loads to floating-point registers are not zero-extended. 1239 The definition for LOAD_EXTEND_OP specifies that integer loads 1240 narrower than BITS_PER_WORD will be zero-extended. As a result, 1241 we inhibit changes from SImode unless they are to a mode that is 1242 identical in size. */ 1243 1244 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1245 (TARGET_ARCH64 \ 1246 && (FROM) == SImode \ 1247 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1248 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 1249 1250 /* The same information, inverted: 1251 Return the class number of the smallest class containing 1252 reg number REGNO. This could be a conditional expression 1253 or could index an array. */ 1254 1255 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 1256 1257 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 1258 1259 /* This is the order in which to allocate registers normally. 1260 1261 We put %f0-%f7 last among the float registers, so as to make it more 1262 likely that a pseudo-register which dies in the float return register 1263 area will get allocated to the float return register, thus saving a move 1264 instruction at the end of the function. 1265 1266 Similarly for integer return value registers. 1267 1268 We know in this case that we will not end up with a leaf function. 1269 1270 The register allocater is given the global and out registers first 1271 because these registers are call clobbered and thus less useful to 1272 global register allocation. 1273 1274 Next we list the local and in registers. They are not call clobbered 1275 and thus very useful for global register allocation. We list the input 1276 registers before the locals so that it is more likely the incoming 1277 arguments received in those registers can just stay there and not be 1278 reloaded. */ 1279 1280 #define REG_ALLOC_ORDER \ 1281 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1282 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1283 15, /* %o7 */ \ 1284 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1285 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 1286 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1287 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1288 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1289 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1290 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1291 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1292 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1293 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1294 96, 97, 98, 99, /* %fcc0-3 */ \ 1295 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ 1296 1297 /* This is the order in which to allocate registers for 1298 leaf functions. If all registers can fit in the global and 1299 output registers, then we have the possibility of having a leaf 1300 function. 1301 1302 The macro actually mentioned the input registers first, 1303 because they get renumbered into the output registers once 1304 we know really do have a leaf function. 1305 1306 To be more precise, this register allocation order is used 1307 when %o7 is found to not be clobbered right before register 1308 allocation. Normally, the reason %o7 would be clobbered is 1309 due to a call which could not be transformed into a sibling 1310 call. 1311 1312 As a consequence, it is possible to use the leaf register 1313 allocation order and not end up with a leaf function. We will 1314 not get suboptimal register allocation in that case because by 1315 definition of being potentially leaf, there were no function 1316 calls. Therefore, allocation order within the local register 1317 window is not critical like it is when we do have function calls. */ 1318 1319 #define REG_LEAF_ALLOC_ORDER \ 1320 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1321 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 1322 15, /* %o7 */ \ 1323 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1324 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1325 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1326 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1327 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1328 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1329 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1330 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1331 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1332 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1333 96, 97, 98, 99, /* %fcc0-3 */ \ 1334 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 1335 1336 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 1337 1338 extern char sparc_leaf_regs[]; 1339 #define LEAF_REGISTERS sparc_leaf_regs 1340 1341 extern char leaf_reg_remap[]; 1342 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1343 1344 /* The class value for index registers, and the one for base regs. */ 1345 #define INDEX_REG_CLASS GENERAL_REGS 1346 #define BASE_REG_CLASS GENERAL_REGS 1347 1348 /* Local macro to handle the two v9 classes of FP regs. */ 1349 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1350 1351 /* Get reg_class from a letter such as appears in the machine description. 1352 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the 1353 .md file for v8 and v9. 1354 'd' and 'b' are used for single and double precision VIS operations, 1355 if TARGET_VIS. 1356 'h' is used for V8+ 64 bit global and out registers. */ 1357 1358 #define REG_CLASS_FROM_LETTER(C) \ 1359 (TARGET_V9 \ 1360 ? ((C) == 'f' ? FP_REGS \ 1361 : (C) == 'e' ? EXTRA_FP_REGS \ 1362 : (C) == 'c' ? FPCC_REGS \ 1363 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ 1364 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ 1365 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ 1366 : NO_REGS) \ 1367 : ((C) == 'f' ? FP_REGS \ 1368 : (C) == 'e' ? FP_REGS \ 1369 : (C) == 'c' ? FPCC_REGS \ 1370 : NO_REGS)) 1371 1372 /* The letters I, J, K, L and M in a register constraint string 1373 can be used to stand for particular ranges of immediate operands. 1374 This macro defines what the ranges are. 1375 C is the letter, and VALUE is a constant value. 1376 Return 1 if VALUE is in the range specified by C. 1377 1378 `I' is used for the range of constants an insn can actually contain. 1379 `J' is used for the range which is just zero (since that is R0). 1380 `K' is used for constants which can be loaded with a single sethi insn. 1381 `L' is used for the range of constants supported by the movcc insns. 1382 `M' is used for the range of constants supported by the movrcc insns. 1383 `N' is like K, but for constants wider than 32 bits. 1384 `O' is used for the range which is just 4096. */ 1385 1386 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1387 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1388 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1389 /* 10 and 11 bit immediates are only used for a few specific insns. 1390 SMALL_INT is used throughout the port so we continue to use it. */ 1391 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1392 /* 13 bit immediate, considering only the low 32 bits */ 1393 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \ 1394 (INTVAL (X), SImode))) 1395 #define SPARC_SETHI_P(X) \ 1396 (((unsigned HOST_WIDE_INT) (X) \ 1397 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1398 #define SPARC_SETHI32_P(X) \ 1399 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1400 1401 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1402 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ 1403 : (C) == 'J' ? (VALUE) == 0 \ 1404 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \ 1405 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ 1406 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ 1407 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ 1408 : (C) == 'O' ? (VALUE) == 4096 \ 1409 : 0) 1410 1411 /* Similar, but for floating constants, and defining letters G and H. 1412 Here VALUE is the CONST_DOUBLE rtx itself. */ 1413 1414 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1415 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \ 1416 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1417 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \ 1418 : 0) 1419 1420 /* Given an rtx X being reloaded into a reg required to be 1421 in class CLASS, return the class of reg to actually use. 1422 In general this is just CLASS; but on some machines 1423 in some cases it is preferable to use a more restrictive class. */ 1424 /* - We can't load constants into FP registers. 1425 - We can't load FP constants into integer registers when soft-float, 1426 because there is no soft-float pattern with a r/F constraint. 1427 - We can't load FP constants into integer registers for TFmode unless 1428 it is 0.0L, because there is no movtf pattern with a r/F constraint. 1429 - Try and reload integer constants (symbolic or otherwise) back into 1430 registers directly, rather than having them dumped to memory. */ 1431 1432 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1433 (CONSTANT_P (X) \ 1434 ? ((FP_REG_CLASS_P (CLASS) \ 1435 || (CLASS) == GENERAL_OR_FP_REGS \ 1436 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ 1437 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1438 && ! TARGET_FPU) \ 1439 || (GET_MODE (X) == TFmode \ 1440 && ! fp_zero_operand (X, TFmode))) \ 1441 ? NO_REGS \ 1442 : (!FP_REG_CLASS_P (CLASS) \ 1443 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ 1444 ? GENERAL_REGS \ 1445 : (CLASS)) \ 1446 : (CLASS)) 1447 1448 /* Return the register class of a scratch register needed to load IN into 1449 a register of class CLASS in MODE. 1450 1451 We need a temporary when loading/storing a HImode/QImode value 1452 between memory and the FPU registers. This can happen when combine puts 1453 a paradoxical subreg in a float/fix conversion insn. 1454 1455 We need a temporary when loading/storing a DFmode value between 1456 unaligned memory and the upper FPU registers. */ 1457 1458 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1459 ((FP_REG_CLASS_P (CLASS) \ 1460 && ((MODE) == HImode || (MODE) == QImode) \ 1461 && (GET_CODE (IN) == MEM \ 1462 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1463 && true_regnum (IN) == -1))) \ 1464 ? GENERAL_REGS \ 1465 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1466 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1467 && ! mem_min_alignment ((IN), 8)) \ 1468 ? FP_REGS \ 1469 : (((TARGET_CM_MEDANY \ 1470 && symbolic_operand ((IN), (MODE))) \ 1471 || (TARGET_CM_EMBMEDANY \ 1472 && text_segment_operand ((IN), (MODE)))) \ 1473 && !flag_pic) \ 1474 ? GENERAL_REGS \ 1475 : NO_REGS) 1476 1477 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1478 ((FP_REG_CLASS_P (CLASS) \ 1479 && ((MODE) == HImode || (MODE) == QImode) \ 1480 && (GET_CODE (IN) == MEM \ 1481 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1482 && true_regnum (IN) == -1))) \ 1483 ? GENERAL_REGS \ 1484 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1485 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1486 && ! mem_min_alignment ((IN), 8)) \ 1487 ? FP_REGS \ 1488 : (((TARGET_CM_MEDANY \ 1489 && symbolic_operand ((IN), (MODE))) \ 1490 || (TARGET_CM_EMBMEDANY \ 1491 && text_segment_operand ((IN), (MODE)))) \ 1492 && !flag_pic) \ 1493 ? GENERAL_REGS \ 1494 : NO_REGS) 1495 1496 /* On SPARC it is not possible to directly move data between 1497 GENERAL_REGS and FP_REGS. */ 1498 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1499 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1500 1501 /* Return the stack location to use for secondary memory needed reloads. 1502 We want to use the reserved location just below the frame pointer. 1503 However, we must ensure that there is a frame, so use assign_stack_local 1504 if the frame size is zero. */ 1505 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1506 (get_frame_size () == 0 \ 1507 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ 1508 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \ 1509 STARTING_FRAME_OFFSET))) 1510 1511 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1512 because the movsi and movsf patterns don't handle r/f moves. 1513 For v8 we copy the default definition. */ 1514 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1515 (TARGET_ARCH64 \ 1516 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1517 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1518 : MODE) \ 1519 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1520 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1521 : MODE)) 1522 1523 /* Return the maximum number of consecutive registers 1524 needed to represent mode MODE in a register of class CLASS. */ 1525 /* On SPARC, this is the size of MODE in words. */ 1526 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1527 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1528 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1529 1530 /* Stack layout; function entry, exit and calling. */ 1531 1532 /* Define the number of register that can hold parameters. 1533 This macro is only used in other macro definitions below and in sparc.c. 1534 MODE is the mode of the argument. 1535 !v9: All args are passed in %o0-%o5. 1536 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values. 1537 See the description in sparc.c. */ 1538 #define NPARM_REGS(MODE) \ 1539 (TARGET_ARCH64 \ 1540 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \ 1541 : 6) 1542 1543 /* Define this if pushing a word on the stack 1544 makes the stack pointer a smaller address. */ 1545 #define STACK_GROWS_DOWNWARD 1546 1547 /* Define this if the nominal address of the stack frame 1548 is at the high-address end of the local variables; 1549 that is, each additional local variable allocated 1550 goes at a more negative offset in the frame. */ 1551 #define FRAME_GROWS_DOWNWARD 1552 1553 /* Offset within stack frame to start allocating local variables at. 1554 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1555 first local allocated. Otherwise, it is the offset to the BEGINNING 1556 of the first local allocated. */ 1557 /* This allows space for one TFmode floating point value. */ 1558 #define STARTING_FRAME_OFFSET \ 1559 (TARGET_ARCH64 ? -16 \ 1560 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1561 1562 /* If we generate an insn to push BYTES bytes, 1563 this says how many the stack pointer really advances by. 1564 On SPARC, don't define this because there are no push insns. */ 1565 /* #define PUSH_ROUNDING(BYTES) */ 1566 1567 /* Offset of first parameter from the argument pointer register value. 1568 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1569 even if this function isn't going to use it. 1570 v9: This is 128 for the ins and locals. */ 1571 #define FIRST_PARM_OFFSET(FNDECL) \ 1572 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1573 1574 /* Offset from the argument pointer register value to the CFA. 1575 This is different from FIRST_PARM_OFFSET because the register window 1576 comes between the CFA and the arguments. */ 1577 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1578 1579 /* When a parameter is passed in a register, stack space is still 1580 allocated for it. 1581 !v9: All 6 possible integer registers have backing store allocated. 1582 v9: Only space for the arguments passed is allocated. */ 1583 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1584 meaning to the backend. Further, we need to be able to detect if a 1585 varargs/unprototyped function is called, as they may want to spill more 1586 registers than we've provided space. Ugly, ugly. So for now we retain 1587 all 6 slots even for v9. */ 1588 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1589 1590 /* Definitions for register elimination. */ 1591 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */ 1592 1593 #define ELIMINABLE_REGS \ 1594 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1595 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1596 1597 /* The way this is structured, we can't eliminate SFP in favor of SP 1598 if the frame pointer is required: we want to use the SFP->HFP elimination 1599 in that case. But the test in update_eliminables doesn't know we are 1600 assuming below that we only do the former elimination. */ 1601 #define CAN_ELIMINATE(FROM, TO) \ 1602 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED) 1603 1604 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1605 do { \ 1606 (OFFSET) = 0; \ 1607 if ((TO) == STACK_POINTER_REGNUM) \ 1608 { \ 1609 /* Note, we always pretend that this is a leaf function \ 1610 because if it's not, there's no point in trying to \ 1611 eliminate the frame pointer. If it is a leaf \ 1612 function, we guessed right! */ \ 1613 if (TARGET_FLAT) \ 1614 (OFFSET) = \ 1615 sparc_flat_compute_frame_size (get_frame_size ()); \ 1616 else \ 1617 (OFFSET) = compute_frame_size (get_frame_size (), 1); \ 1618 } \ 1619 (OFFSET) += SPARC_STACK_BIAS; \ 1620 } while (0) 1621 1622 /* Keep the stack pointer constant throughout the function. 1623 This is both an optimization and a necessity: longjmp 1624 doesn't behave itself when the stack pointer moves within 1625 the function! */ 1626 #define ACCUMULATE_OUTGOING_ARGS 1 1627 1628 /* Value is the number of bytes of arguments automatically 1629 popped when returning from a subroutine call. 1630 FUNDECL is the declaration node of the function (as a tree), 1631 FUNTYPE is the data type of the function (as a tree), 1632 or for a library call it is an identifier node for the subroutine name. 1633 SIZE is the number of bytes of arguments passed on the stack. */ 1634 1635 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1636 1637 /* Some subroutine macros specific to this machine. 1638 When !TARGET_FPU, put float return values in the general registers, 1639 since we don't have any fp registers. */ 1640 #define BASE_RETURN_VALUE_REG(MODE) \ 1641 (TARGET_ARCH64 \ 1642 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ 1643 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) 1644 1645 #define BASE_OUTGOING_VALUE_REG(MODE) \ 1646 (TARGET_ARCH64 \ 1647 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ 1648 : TARGET_FLAT ? 8 : 24) \ 1649 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ 1650 : (TARGET_FLAT ? 8 : 24))) 1651 1652 #define BASE_PASSING_ARG_REG(MODE) \ 1653 (TARGET_ARCH64 \ 1654 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ 1655 : 8) 1656 1657 /* ??? FIXME -- seems wrong for v9 structure passing... */ 1658 #define BASE_INCOMING_ARG_REG(MODE) \ 1659 (TARGET_ARCH64 \ 1660 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ 1661 : TARGET_FLAT ? 8 : 24) \ 1662 : (TARGET_FLAT ? 8 : 24)) 1663 1664 /* Define this macro if the target machine has "register windows". This 1665 C expression returns the register number as seen by the called function 1666 corresponding to register number OUT as seen by the calling function. 1667 Return OUT if register number OUT is not an outbound register. */ 1668 1669 #define INCOMING_REGNO(OUT) \ 1670 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1671 1672 /* Define this macro if the target machine has "register windows". This 1673 C expression returns the register number as seen by the calling function 1674 corresponding to register number IN as seen by the called function. 1675 Return IN if register number IN is not an inbound register. */ 1676 1677 #define OUTGOING_REGNO(IN) \ 1678 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1679 1680 /* Define this macro if the target machine has register windows. This 1681 C expression returns true if the register is call-saved but is in the 1682 register window. */ 1683 1684 #define LOCAL_REGNO(REGNO) \ 1685 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31) 1686 1687 /* Define how to find the value returned by a function. 1688 VALTYPE is the data type of the value (as a tree). 1689 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1690 otherwise, FUNC is 0. */ 1691 1692 /* On SPARC the value is found in the first "output" register. */ 1693 1694 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1695 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) 1696 1697 /* But the called function leaves it in the first "input" register. */ 1698 1699 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1700 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) 1701 1702 /* Define how to find the value returned by a library function 1703 assuming the value has mode MODE. */ 1704 1705 #define LIBCALL_VALUE(MODE) \ 1706 function_value (NULL_TREE, (MODE), 1) 1707 1708 /* 1 if N is a possible register number for a function value 1709 as seen by the caller. 1710 On SPARC, the first "output" reg is used for integer values, 1711 and the first floating point register is used for floating point values. */ 1712 1713 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1714 1715 /* Define the size of space to allocate for the return value of an 1716 untyped_call. */ 1717 1718 #define APPLY_RESULT_SIZE 16 1719 1720 /* 1 if N is a possible register number for function argument passing. 1721 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1722 1723 #define FUNCTION_ARG_REGNO_P(N) \ 1724 (TARGET_ARCH64 \ 1725 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1726 : ((N) >= 8 && (N) <= 13)) 1727 1728 /* Define a data type for recording info about an argument list 1729 during the scan of that argument list. This data type should 1730 hold all necessary information about the function itself 1731 and about the args processed so far, enough to enable macros 1732 such as FUNCTION_ARG to determine where the next arg should go. 1733 1734 On SPARC (!v9), this is a single integer, which is a number of words 1735 of arguments scanned so far (including the invisible argument, 1736 if any, which holds the structure-value-address). 1737 Thus 7 or more means all following args should go on the stack. 1738 1739 For v9, we also need to know whether a prototype is present. */ 1740 1741 struct sparc_args { 1742 int words; /* number of words passed so far */ 1743 int prototype_p; /* nonzero if a prototype is present */ 1744 int libcall_p; /* nonzero if a library call */ 1745 }; 1746 #define CUMULATIVE_ARGS struct sparc_args 1747 1748 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1749 for a call to a function whose data type is FNTYPE. 1750 For a library call, FNTYPE is 0. */ 1751 1752 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1753 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT)); 1754 1755 /* Update the data in CUM to advance over an argument 1756 of mode MODE and data type TYPE. 1757 TYPE is null for libcalls where that information may not be available. */ 1758 1759 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1760 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) 1761 1762 /* Nonzero if we do not know how to pass TYPE solely in registers. */ 1763 1764 #define MUST_PASS_IN_STACK(MODE,TYPE) \ 1765 ((TYPE) != 0 \ 1766 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1767 || TREE_ADDRESSABLE (TYPE))) 1768 1769 /* Determine where to put an argument to a function. 1770 Value is zero to push the argument on the stack, 1771 or a hard register in which to store the argument. 1772 1773 MODE is the argument's machine mode. 1774 TYPE is the data type of the argument (as a tree). 1775 This is null for libcalls where that information may 1776 not be available. 1777 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1778 the preceding args and about the function being called. 1779 NAMED is nonzero if this argument is a named parameter 1780 (otherwise it is an extra parameter matching an ellipsis). */ 1781 1782 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1783 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) 1784 1785 /* Define where a function finds its arguments. 1786 This is different from FUNCTION_ARG because of register windows. */ 1787 1788 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1789 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) 1790 1791 /* For an arg passed partly in registers and partly in memory, 1792 this is the number of registers used. 1793 For args passed entirely in registers or entirely in memory, zero. */ 1794 1795 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1796 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED)) 1797 1798 /* A C expression that indicates when an argument must be passed by reference. 1799 If nonzero for an argument, a copy of that argument is made in memory and a 1800 pointer to the argument is passed instead of the argument itself. 1801 The pointer is passed in whatever way is appropriate for passing a pointer 1802 to that type. */ 1803 1804 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1805 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) 1806 1807 /* If defined, a C expression which determines whether, and in which direction, 1808 to pad out an argument with extra space. The value should be of type 1809 `enum direction': either `upward' to pad above the argument, 1810 `downward' to pad below, or `none' to inhibit padding. */ 1811 1812 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1813 function_arg_padding ((MODE), (TYPE)) 1814 1815 /* If defined, a C expression that gives the alignment boundary, in bits, 1816 of an argument with the specified mode and type. If it is not defined, 1817 PARM_BOUNDARY is used for all arguments. 1818 For sparc64, objects requiring 16 byte alignment are passed that way. */ 1819 1820 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1821 ((TARGET_ARCH64 \ 1822 && (GET_MODE_ALIGNMENT (MODE) == 128 \ 1823 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ 1824 ? 128 : PARM_BOUNDARY) 1825 1826 /* Define the information needed to generate branch and scc insns. This is 1827 stored from the compare operation. Note that we can't use "rtx" here 1828 since it hasn't been defined! */ 1829 1830 extern GTY(()) rtx sparc_compare_op0; 1831 extern GTY(()) rtx sparc_compare_op1; 1832 1833 1834 /* Generate the special assembly code needed to tell the assembler whatever 1835 it might need to know about the return value of a function. 1836 1837 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1838 information to the assembler relating to peephole optimization (done in 1839 the assembler). */ 1840 1841 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1842 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1843 1844 /* Output the special assembly code needed to tell the assembler some 1845 register is used as global register variable. 1846 1847 SPARC 64bit psABI declares registers %g2 and %g3 as application 1848 registers and %g6 and %g7 as OS registers. Any object using them 1849 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1850 and how they are used (scratch or some global variable). 1851 Linker will then refuse to link together objects which use those 1852 registers incompatibly. 1853 1854 Unless the registers are used for scratch, two different global 1855 registers cannot be declared to the same name, so in the unlikely 1856 case of a global register variable occupying more than one register 1857 we prefix the second and following registers with .gnu.part1. etc. */ 1858 1859 extern char sparc_hard_reg_printed[8]; 1860 1861 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 1862 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1863 do { \ 1864 if (TARGET_ARCH64) \ 1865 { \ 1866 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1867 int reg; \ 1868 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1869 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1870 { \ 1871 if (reg == (REGNO)) \ 1872 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1873 else \ 1874 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1875 reg, reg - (REGNO), (NAME)); \ 1876 sparc_hard_reg_printed[reg] = 1; \ 1877 } \ 1878 } \ 1879 } while (0) 1880 #endif 1881 1882 1883 /* Emit rtl for profiling. */ 1884 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1885 1886 /* All the work done in PROFILE_HOOK, but still required. */ 1887 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1888 1889 /* Set the name of the mcount function for the system. */ 1890 #define MCOUNT_FUNCTION "*mcount" 1891 1892 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1893 the stack pointer does not matter. The value is tested only in 1894 functions that have frame pointers. 1895 No definition is equivalent to always zero. */ 1896 1897 #define EXIT_IGNORE_STACK \ 1898 (get_frame_size () != 0 \ 1899 || current_function_calls_alloca || current_function_outgoing_args_size) 1900 1901 #define DELAY_SLOTS_FOR_EPILOGUE \ 1902 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1) 1903 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ 1904 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ 1905 : eligible_for_epilogue_delay (trial, slots_filled)) 1906 1907 /* Define registers used by the epilogue and return instruction. */ 1908 #define EPILOGUE_USES(REGNO) \ 1909 (!TARGET_FLAT && REGNO == 31) 1910 1911 /* Length in units of the trampoline for entering a nested function. */ 1912 1913 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1914 1915 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ 1916 1917 /* Emit RTL insns to initialize the variable parts of a trampoline. 1918 FNADDR is an RTX for the address of the function's pure code. 1919 CXT is an RTX for the static chain value for the function. */ 1920 1921 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1922 if (TARGET_ARCH64) \ 1923 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1924 else \ 1925 sparc_initialize_trampoline (TRAMP, FNADDR, CXT) 1926 1927 /* Generate necessary RTL for __builtin_saveregs(). */ 1928 1929 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs () 1930 1931 /* Implement `va_start' for varargs and stdarg. */ 1932 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1933 sparc_va_start (valist, nextarg) 1934 1935 /* Implement `va_arg'. */ 1936 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1937 sparc_va_arg (valist, type) 1938 1939 /* Define this macro if the location where a function argument is passed 1940 depends on whether or not it is a named argument. 1941 1942 This macro controls how the NAMED argument to FUNCTION_ARG 1943 is set for varargs and stdarg functions. With this macro defined, 1944 the NAMED argument is always true for named arguments, and false for 1945 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS 1946 is defined, then all arguments are treated as named. Otherwise, all named 1947 arguments except the last are treated as named. 1948 For the v9 we want NAMED to mean what it says it means. */ 1949 1950 #define STRICT_ARGUMENT_NAMING TARGET_V9 1951 1952 /* We do not allow sibling calls if -mflat, nor 1953 we do not allow indirect calls to be optimized into sibling calls. 1954 1955 Also, on sparc 32-bit we cannot emit a sibling call when the 1956 current function returns a structure. This is because the "unimp 1957 after call" convention would cause the callee to return to the 1958 wrong place. The generic code already disallows cases where the 1959 function being called returns a structure. 1960 1961 It may seem strange how this last case could occur. Usually there 1962 is code after the call which jumps to epilogue code which dumps the 1963 return value into the struct return area. That ought to invalidate 1964 the sibling call right? Well, in the c++ case we can end up passing 1965 the pointer to the struct return area to a constructor (which returns 1966 void) and then nothing else happens. Such a sibling call would look 1967 valid without the added check here. */ 1968 #define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1969 (DECL \ 1970 && ! TARGET_FLAT \ 1971 && (TARGET_ARCH64 || ! current_function_returns_struct)) 1972 1973 /* Generate RTL to flush the register windows so as to make arbitrary frames 1974 available. */ 1975 #define SETUP_FRAME_ADDRESSES() \ 1976 emit_insn (gen_flush_register_windows ()) 1977 1978 /* Given an rtx for the address of a frame, 1979 return an rtx for the address of the word in the frame 1980 that holds the dynamic chain--the previous frame's address. 1981 ??? -mflat support? */ 1982 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1983 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1984 1985 /* The return address isn't on the stack, it is in a register, so we can't 1986 access it from the current frame pointer. We can access it from the 1987 previous frame pointer though by reading a value from the register window 1988 save area. */ 1989 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1990 1991 /* This is the offset of the return address to the true next instruction to be 1992 executed for the current function. */ 1993 #define RETURN_ADDR_OFFSET \ 1994 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) 1995 1996 /* The current return address is in %i7. The return address of anything 1997 farther back is in the register window save area at [%fp+60]. */ 1998 /* ??? This ignores the fact that the actual return address is +8 for normal 1999 returns, and +12 for structure returns. */ 2000 #define RETURN_ADDR_RTX(count, frame) \ 2001 ((count == -1) \ 2002 ? gen_rtx_REG (Pmode, 31) \ 2003 : gen_rtx_MEM (Pmode, \ 2004 memory_address (Pmode, plus_constant (frame, \ 2005 15 * UNITS_PER_WORD \ 2006 + SPARC_STACK_BIAS)))) 2007 2008 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 2009 +12, but always using +8 is close enough for frame unwind purposes. 2010 Actually, just using %o7 is close enough for unwinding, but %o7+8 2011 is something you can return to. */ 2012 #define INCOMING_RETURN_ADDR_RTX \ 2013 plus_constant (gen_rtx_REG (word_mode, 15), 8) 2014 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) 2015 2016 /* The offset from the incoming value of %sp to the top of the stack frame 2017 for the current function. On sparc64, we have to account for the stack 2018 bias if present. */ 2019 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 2020 2021 /* Describe how we implement __builtin_eh_return. */ 2022 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 2023 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ 2024 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ 2025 2026 /* Select a format to encode pointers in exception handling data. CODE 2027 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2028 true if the symbol may be affected by dynamic relocations. 2029 2030 If assembler and linker properly support .uaword %r_disp32(foo), 2031 then use PC relative 32-bit relocations instead of absolute relocs 2032 for shared libraries. On sparc64, use pc relative 32-bit relocs even 2033 for binaries, to save memory. 2034 2035 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 2036 symbol %r_disp32() is against was not local, but .hidden. In that 2037 case, we have to use DW_EH_PE_absptr for pic personality. */ 2038 #ifdef HAVE_AS_SPARC_UA_PCREL 2039 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 2040 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 2041 (flag_pic \ 2042 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2043 : ((TARGET_ARCH64 && ! GLOBAL) \ 2044 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 2045 : DW_EH_PE_absptr)) 2046 #else 2047 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 2048 (flag_pic \ 2049 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 2050 : ((TARGET_ARCH64 && ! GLOBAL) \ 2051 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 2052 : DW_EH_PE_absptr)) 2053 #endif 2054 2055 /* Emit a PC-relative relocation. */ 2056 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 2057 do { \ 2058 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 2059 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 2060 assemble_name (FILE, LABEL); \ 2061 fputc (')', FILE); \ 2062 } while (0) 2063 #endif 2064 2065 /* Addressing modes, and classification of registers for them. */ 2066 2067 /* #define HAVE_POST_INCREMENT 0 */ 2068 /* #define HAVE_POST_DECREMENT 0 */ 2069 2070 /* #define HAVE_PRE_DECREMENT 0 */ 2071 /* #define HAVE_PRE_INCREMENT 0 */ 2072 2073 /* Macros to check register numbers against specific register classes. */ 2074 2075 /* These assume that REGNO is a hard or pseudo reg number. 2076 They give nonzero only if REGNO is a hard reg of the suitable class 2077 or a pseudo reg currently allocated to a suitable hard reg. 2078 Since they use reg_renumber, they are safe only once reg_renumber 2079 has been allocated, which happens in local-alloc.c. */ 2080 2081 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 2082 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ 2083 || (REGNO) == FRAME_POINTER_REGNUM \ 2084 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 2085 2086 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 2087 2088 #define REGNO_OK_FOR_FP_P(REGNO) \ 2089 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 2090 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 2091 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 2092 (TARGET_V9 \ 2093 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 2094 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 2095 2096 /* Now macros that check whether X is a register and also, 2097 strictly, whether it is in a specified class. 2098 2099 These macros are specific to the SPARC, and may be used only 2100 in code for printing assembler insns and in conditions for 2101 define_optimization. */ 2102 2103 /* 1 if X is an fp register. */ 2104 2105 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 2106 2107 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ 2108 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) 2109 2110 /* Maximum number of registers that can appear in a valid memory address. */ 2111 2112 #define MAX_REGS_PER_ADDRESS 2 2113 2114 /* Recognize any constant value that is a valid address. 2115 When PIC, we do not accept an address that would require a scratch reg 2116 to load into a register. */ 2117 2118 #define CONSTANT_ADDRESS_P(X) \ 2119 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 2120 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 2121 || (GET_CODE (X) == CONST \ 2122 && ! (flag_pic && pic_address_needs_scratch (X)))) 2123 2124 /* Define this, so that when PIC, reload won't try to reload invalid 2125 addresses which require two reload registers. */ 2126 2127 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) 2128 2129 /* Nonzero if the constant value X is a legitimate general operand. 2130 Anything can be made to work except floating point constants. 2131 If TARGET_VIS, 0.0 can be made to work as well. */ 2132 2133 #define LEGITIMATE_CONSTANT_P(X) \ 2134 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \ 2135 (TARGET_VIS && \ 2136 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \ 2137 GET_MODE (X) == TFmode) && \ 2138 fp_zero_operand (X, GET_MODE (X)))) 2139 2140 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2141 and check its validity for a certain class. 2142 We have two alternate definitions for each of them. 2143 The usual definition accepts all pseudo regs; the other rejects 2144 them unless they have been allocated suitable hard regs. 2145 The symbol REG_OK_STRICT causes the latter definition to be used. 2146 2147 Most source files want to accept pseudo regs in the hope that 2148 they will get allocated to the class that the insn wants them to be in. 2149 Source files for reload pass need to be strict. 2150 After reload, it makes no difference, since pseudo regs have 2151 been eliminated by then. */ 2152 2153 /* Optional extra constraints for this machine. 2154 2155 'Q' handles floating point constants which can be moved into 2156 an integer register with a single sethi instruction. 2157 2158 'R' handles floating point constants which can be moved into 2159 an integer register with a single mov instruction. 2160 2161 'S' handles floating point constants which can be moved into 2162 an integer register using a high/lo_sum sequence. 2163 2164 'T' handles memory addresses where the alignment is known to 2165 be at least 8 bytes. 2166 2167 `U' handles all pseudo registers or a hard even numbered 2168 integer register, needed for ldd/std instructions. 2169 2170 'W' handles the memory operand when moving operands in/out 2171 of 'e' constraint floating point registers. */ 2172 2173 #ifndef REG_OK_STRICT 2174 2175 /* Nonzero if X is a hard reg that can be used as an index 2176 or if it is a pseudo reg. */ 2177 #define REG_OK_FOR_INDEX_P(X) \ 2178 (REGNO (X) < 32 \ 2179 || REGNO (X) == FRAME_POINTER_REGNUM \ 2180 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2181 2182 /* Nonzero if X is a hard reg that can be used as a base reg 2183 or if it is a pseudo reg. */ 2184 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) 2185 2186 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. 2187 'W' is like 'T' but is assumed true on arch64. 2188 2189 Remember to accept pseudo-registers for memory constraints if reload is 2190 in progress. */ 2191 2192 #define EXTRA_CONSTRAINT(OP, C) \ 2193 sparc_extra_constraint_check(OP, C, 0) 2194 2195 #else 2196 2197 /* Nonzero if X is a hard reg that can be used as an index. */ 2198 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 2199 /* Nonzero if X is a hard reg that can be used as a base reg. */ 2200 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 2201 2202 #define EXTRA_CONSTRAINT(OP, C) \ 2203 sparc_extra_constraint_check(OP, C, 1) 2204 2205 #endif 2206 2207 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 2208 2209 #ifdef HAVE_AS_OFFSETABLE_LO10 2210 #define USE_AS_OFFSETABLE_LO10 1 2211 #else 2212 #define USE_AS_OFFSETABLE_LO10 0 2213 #endif 2214 2215 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2216 that is a valid memory address for an instruction. 2217 The MODE argument is the machine mode for the MEM expression 2218 that wants to use this address. 2219 2220 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 2221 ordinarily. This changes a bit when generating PIC. 2222 2223 If you change this, execute "rm explow.o recog.o reload.o". */ 2224 2225 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) 2226 2227 #define RTX_OK_FOR_BASE_P(X) \ 2228 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 2229 || (GET_CODE (X) == SUBREG \ 2230 && GET_CODE (SUBREG_REG (X)) == REG \ 2231 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 2232 2233 #define RTX_OK_FOR_INDEX_P(X) \ 2234 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 2235 || (GET_CODE (X) == SUBREG \ 2236 && GET_CODE (SUBREG_REG (X)) == REG \ 2237 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 2238 2239 #define RTX_OK_FOR_OFFSET_P(X) \ 2240 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) 2241 2242 #define RTX_OK_FOR_OLO10_P(X) \ 2243 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) 2244 2245 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2246 { if (RTX_OK_FOR_BASE_P (X)) \ 2247 goto ADDR; \ 2248 else if (GET_CODE (X) == PLUS) \ 2249 { \ 2250 register rtx op0 = XEXP (X, 0); \ 2251 register rtx op1 = XEXP (X, 1); \ 2252 if (flag_pic && op0 == pic_offset_table_rtx) \ 2253 { \ 2254 if (RTX_OK_FOR_BASE_P (op1)) \ 2255 goto ADDR; \ 2256 else if (flag_pic == 1 \ 2257 && GET_CODE (op1) != REG \ 2258 && GET_CODE (op1) != LO_SUM \ 2259 && GET_CODE (op1) != MEM \ 2260 && (! SYMBOLIC_CONST (op1) \ 2261 || MODE == Pmode) \ 2262 && (GET_CODE (op1) != CONST_INT \ 2263 || SMALL_INT (op1))) \ 2264 goto ADDR; \ 2265 } \ 2266 else if (RTX_OK_FOR_BASE_P (op0)) \ 2267 { \ 2268 if ((RTX_OK_FOR_INDEX_P (op1) \ 2269 /* We prohibit REG + REG for TFmode when \ 2270 there are no instructions which accept \ 2271 REG+REG instructions. We do this \ 2272 because REG+REG is not an offsetable \ 2273 address. If we get the situation \ 2274 in reload where source and destination \ 2275 of a movtf pattern are both MEMs with \ 2276 REG+REG address, then only one of them \ 2277 gets converted to an offsetable \ 2278 address. */ \ 2279 && (MODE != TFmode \ 2280 || (TARGET_FPU && TARGET_ARCH64 \ 2281 && TARGET_V9 \ 2282 && TARGET_HARD_QUAD)) \ 2283 /* We prohibit REG + REG on ARCH32 if \ 2284 not optimizing for DFmode/DImode \ 2285 because then mem_min_alignment is \ 2286 likely to be zero after reload and the \ 2287 forced split would lack a matching \ 2288 splitter pattern. */ \ 2289 && (TARGET_ARCH64 || optimize \ 2290 || (MODE != DFmode \ 2291 && MODE != DImode))) \ 2292 || RTX_OK_FOR_OFFSET_P (op1)) \ 2293 goto ADDR; \ 2294 } \ 2295 else if (RTX_OK_FOR_BASE_P (op1)) \ 2296 { \ 2297 if ((RTX_OK_FOR_INDEX_P (op0) \ 2298 /* See the previous comment. */ \ 2299 && (MODE != TFmode \ 2300 || (TARGET_FPU && TARGET_ARCH64 \ 2301 && TARGET_V9 \ 2302 && TARGET_HARD_QUAD)) \ 2303 && (TARGET_ARCH64 || optimize \ 2304 || (MODE != DFmode \ 2305 && MODE != DImode))) \ 2306 || RTX_OK_FOR_OFFSET_P (op0)) \ 2307 goto ADDR; \ 2308 } \ 2309 else if (USE_AS_OFFSETABLE_LO10 \ 2310 && GET_CODE (op0) == LO_SUM \ 2311 && TARGET_ARCH64 \ 2312 && ! TARGET_CM_MEDMID \ 2313 && RTX_OK_FOR_OLO10_P (op1)) \ 2314 { \ 2315 register rtx op00 = XEXP (op0, 0); \ 2316 register rtx op01 = XEXP (op0, 1); \ 2317 if (RTX_OK_FOR_BASE_P (op00) \ 2318 && CONSTANT_P (op01)) \ 2319 goto ADDR; \ 2320 } \ 2321 else if (USE_AS_OFFSETABLE_LO10 \ 2322 && GET_CODE (op1) == LO_SUM \ 2323 && TARGET_ARCH64 \ 2324 && ! TARGET_CM_MEDMID \ 2325 && RTX_OK_FOR_OLO10_P (op0)) \ 2326 { \ 2327 register rtx op10 = XEXP (op1, 0); \ 2328 register rtx op11 = XEXP (op1, 1); \ 2329 if (RTX_OK_FOR_BASE_P (op10) \ 2330 && CONSTANT_P (op11)) \ 2331 goto ADDR; \ 2332 } \ 2333 } \ 2334 else if (GET_CODE (X) == LO_SUM) \ 2335 { \ 2336 register rtx op0 = XEXP (X, 0); \ 2337 register rtx op1 = XEXP (X, 1); \ 2338 if (RTX_OK_FOR_BASE_P (op0) \ 2339 && CONSTANT_P (op1) \ 2340 /* We can't allow TFmode, because an offset \ 2341 greater than or equal to the alignment (8) \ 2342 may cause the LO_SUM to overflow if !v9. */\ 2343 && (MODE != TFmode || TARGET_V9)) \ 2344 goto ADDR; \ 2345 } \ 2346 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ 2347 goto ADDR; \ 2348 } 2349 2350 /* Go to LABEL if ADDR (a legitimate address expression) 2351 has an effect that depends on the machine mode it is used for. 2352 2353 In PIC mode, 2354 2355 (mem:HI [%l7+a]) 2356 2357 is not equivalent to 2358 2359 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) 2360 2361 because [%l7+a+1] is interpreted as the address of (a+1). */ 2362 2363 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2364 { \ 2365 if (flag_pic == 1) \ 2366 { \ 2367 if (GET_CODE (ADDR) == PLUS) \ 2368 { \ 2369 rtx op0 = XEXP (ADDR, 0); \ 2370 rtx op1 = XEXP (ADDR, 1); \ 2371 if (op0 == pic_offset_table_rtx \ 2372 && SYMBOLIC_CONST (op1)) \ 2373 goto LABEL; \ 2374 } \ 2375 } \ 2376 } 2377 2378 /* Try machine-dependent ways of modifying an illegitimate address 2379 to be legitimate. If we find one, return the new, valid address. 2380 This macro is used in only one place: `memory_address' in explow.c. 2381 2382 OLDX is the address as it was before break_out_memory_refs was called. 2383 In some cases it is useful to look at this to decide what needs to be done. 2384 2385 MODE and WIN are passed so that this macro can use 2386 GO_IF_LEGITIMATE_ADDRESS. 2387 2388 It is always safe for this macro to do nothing. It exists to recognize 2389 opportunities to optimize the output. */ 2390 2391 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 2392 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2393 { rtx sparc_x = (X); \ 2394 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ 2395 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \ 2396 force_operand (XEXP (X, 0), NULL_RTX)); \ 2397 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ 2398 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 2399 force_operand (XEXP (X, 1), NULL_RTX)); \ 2400 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ 2401 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ 2402 XEXP (X, 1)); \ 2403 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ 2404 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 2405 force_operand (XEXP (X, 1), NULL_RTX)); \ 2406 if (sparc_x != (X) && memory_address_p (MODE, X)) \ 2407 goto WIN; \ 2408 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ 2409 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ 2410 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 2411 copy_to_mode_reg (Pmode, XEXP (X, 1))); \ 2412 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ 2413 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \ 2414 copy_to_mode_reg (Pmode, XEXP (X, 0))); \ 2415 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 2416 || GET_CODE (X) == LABEL_REF) \ 2417 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \ 2418 if (memory_address_p (MODE, X)) \ 2419 goto WIN; } 2420 2421 /* Try a machine-dependent way of reloading an illegitimate address 2422 operand. If we find one, push the reload and jump to WIN. This 2423 macro is used in only one place: `find_reloads_address' in reload.c. 2424 2425 For SPARC 32, we wish to handle addresses by splitting them into 2426 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 2427 This cuts the number of extra insns by one. 2428 2429 Do nothing when generating PIC code and the address is a 2430 symbolic operand or requires a scratch register. */ 2431 2432 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2433 do { \ 2434 /* Decompose SImode constants into hi+lo_sum. We do have to \ 2435 rerecognize what we produce, so be careful. */ \ 2436 if (CONSTANT_P (X) \ 2437 && (MODE != TFmode || TARGET_ARCH64) \ 2438 && GET_MODE (X) == SImode \ 2439 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ 2440 && ! (flag_pic \ 2441 && (symbolic_operand (X, Pmode) \ 2442 || pic_address_needs_scratch (X))) \ 2443 && sparc_cmodel <= CM_MEDLOW) \ 2444 { \ 2445 X = gen_rtx_LO_SUM (GET_MODE (X), \ 2446 gen_rtx_HIGH (GET_MODE (X), X), X); \ 2447 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 2448 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 2449 OPNUM, TYPE); \ 2450 goto WIN; \ 2451 } \ 2452 /* ??? 64-bit reloads. */ \ 2453 } while (0) 2454 2455 /* Specify the machine mode that this machine uses 2456 for the index in the tablejump instruction. */ 2457 /* If we ever implement any of the full models (such as CM_FULLANY), 2458 this has to be DImode in that case */ 2459 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2460 #define CASE_VECTOR_MODE \ 2461 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 2462 #else 2463 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 2464 we have to sign extend which slows things down. */ 2465 #define CASE_VECTOR_MODE \ 2466 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 2467 #endif 2468 2469 /* Define as C expression which evaluates to nonzero if the tablejump 2470 instruction expects the table to contain offsets from the address of the 2471 table. 2472 Do not define this if the table should contain absolute addresses. */ 2473 /* #define CASE_VECTOR_PC_RELATIVE 1 */ 2474 2475 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2476 #define DEFAULT_SIGNED_CHAR 1 2477 2478 /* Max number of bytes we can move from memory to memory 2479 in one reasonably fast instruction. */ 2480 #define MOVE_MAX 8 2481 2482 #if 0 /* Sun 4 has matherr, so this is no good. */ 2483 /* This is the value of the error code EDOM for this machine, 2484 used by the sqrt instruction. */ 2485 #define TARGET_EDOM 33 2486 2487 /* This is how to refer to the variable errno. */ 2488 #define GEN_ERRNO_RTX \ 2489 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno")) 2490 #endif /* 0 */ 2491 2492 /* Define if operations between registers always perform the operation 2493 on the full register even if a narrower mode is specified. */ 2494 #define WORD_REGISTER_OPERATIONS 2495 2496 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2497 will either zero-extend or sign-extend. The value of this macro should 2498 be the code that says which one of the two operations is implicitly 2499 done, NIL if none. */ 2500 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2501 2502 /* Nonzero if access to memory by bytes is slow and undesirable. 2503 For RISC chips, it means that access to memory by bytes is no 2504 better than access by words when possible, so grab a whole word 2505 and maybe make use of that. */ 2506 #define SLOW_BYTE_ACCESS 1 2507 2508 /* We assume that the store-condition-codes instructions store 0 for false 2509 and some other value for true. This is the value stored for true. */ 2510 2511 #define STORE_FLAG_VALUE 1 2512 2513 /* When a prototype says `char' or `short', really pass an `int'. */ 2514 #define PROMOTE_PROTOTYPES (TARGET_ARCH32) 2515 2516 /* Define this to be nonzero if shift instructions ignore all but the low-order 2517 few bits. */ 2518 #define SHIFT_COUNT_TRUNCATED 1 2519 2520 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2521 is done just by pretending it is already truncated. */ 2522 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2523 2524 /* Specify the machine mode that pointers have. 2525 After generation of rtl, the compiler makes no further distinction 2526 between pointers and any other objects of this machine mode. */ 2527 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 2528 2529 /* Generate calls to memcpy, memcmp and memset. */ 2530 #define TARGET_MEM_FUNCTIONS 2531 2532 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2533 return the mode to be used for the comparison. For floating-point, 2534 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2535 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2536 processing is needed. */ 2537 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 2538 2539 /* Return nonzero if MODE implies a floating point inequality can be 2540 reversed. For SPARC this is always true because we have a full 2541 compliment of ordered and unordered comparisons, but until generic 2542 code knows how to reverse it correctly we keep the old definition. */ 2543 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 2544 2545 /* A function address in a call instruction for indexing purposes. */ 2546 #define FUNCTION_MODE Pmode 2547 2548 /* Define this if addresses of constant functions 2549 shouldn't be put through pseudo regs where they can be cse'd. 2550 Desirable on machines where ordinary constants are expensive 2551 but a CALL with constant address is cheap. */ 2552 #define NO_FUNCTION_CSE 2553 2554 /* alloca should avoid clobbering the old register save area. */ 2555 #define SETJMP_VIA_SAVE_AREA 2556 2557 /* Define subroutines to call to handle multiply and divide. 2558 Use the subroutines that Sun's library provides. 2559 The `*' prevents an underscore from being prepended by the compiler. */ 2560 2561 #define DIVSI3_LIBCALL "*.div" 2562 #define UDIVSI3_LIBCALL "*.udiv" 2563 #define MODSI3_LIBCALL "*.rem" 2564 #define UMODSI3_LIBCALL "*.urem" 2565 /* .umul is a little faster than .mul. */ 2566 #define MULSI3_LIBCALL "*.umul" 2567 2568 /* Define library calls for quad FP operations. These are all part of the 2569 SPARC 32bit ABI. */ 2570 #define ADDTF3_LIBCALL "_Q_add" 2571 #define SUBTF3_LIBCALL "_Q_sub" 2572 #define NEGTF2_LIBCALL "_Q_neg" 2573 #define MULTF3_LIBCALL "_Q_mul" 2574 #define DIVTF3_LIBCALL "_Q_div" 2575 #define FLOATSITF2_LIBCALL "_Q_itoq" 2576 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" 2577 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" 2578 #define EXTENDSFTF2_LIBCALL "_Q_stoq" 2579 #define TRUNCTFSF2_LIBCALL "_Q_qtos" 2580 #define EXTENDDFTF2_LIBCALL "_Q_dtoq" 2581 #define TRUNCTFDF2_LIBCALL "_Q_qtod" 2582 #define EQTF2_LIBCALL "_Q_feq" 2583 #define NETF2_LIBCALL "_Q_fne" 2584 #define GTTF2_LIBCALL "_Q_fgt" 2585 #define GETF2_LIBCALL "_Q_fge" 2586 #define LTTF2_LIBCALL "_Q_flt" 2587 #define LETF2_LIBCALL "_Q_fle" 2588 2589 /* These functions were added in SCD 2.3, so not necessarily all targets 2590 support them. */ 2591 #define FLOATDITF2_LIBCALL "_Q_lltoq" 2592 #define FIX_TRUNCTFDI2_LIBCALL "_Q_qtoll" 2593 #define FIXUNS_TRUNCTFDI2_LIBCALL "_Q_qtoull" 2594 2595 #define DITF_CONVERSION_LIBFUNCS 0 2596 2597 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 2598 that the inputs are fully consumed before the output memory is clobbered. */ 2599 2600 #define TARGET_BUGGY_QP_LIB 0 2601 2602 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because 2603 with soft-float, the SFmode and DFmode sqrt instructions will be absent, 2604 and the compiler will notice and try to use the TFmode sqrt instruction 2605 for calls to the builtin function sqrt, but this fails. */ 2606 #define INIT_TARGET_OPTABS \ 2607 do { \ 2608 if (TARGET_ARCH32) \ 2609 { \ 2610 add_optab->handlers[(int) TFmode].libfunc \ 2611 = init_one_libfunc (ADDTF3_LIBCALL); \ 2612 sub_optab->handlers[(int) TFmode].libfunc \ 2613 = init_one_libfunc (SUBTF3_LIBCALL); \ 2614 neg_optab->handlers[(int) TFmode].libfunc \ 2615 = init_one_libfunc (NEGTF2_LIBCALL); \ 2616 smul_optab->handlers[(int) TFmode].libfunc \ 2617 = init_one_libfunc (MULTF3_LIBCALL); \ 2618 sdiv_optab->handlers[(int) TFmode].libfunc \ 2619 = init_one_libfunc (DIVTF3_LIBCALL); \ 2620 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \ 2621 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \ 2622 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \ 2623 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \ 2624 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \ 2625 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \ 2626 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \ 2627 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \ 2628 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \ 2629 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \ 2630 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \ 2631 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \ 2632 fixunstfsi_libfunc \ 2633 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \ 2634 if (DITF_CONVERSION_LIBFUNCS) \ 2635 { \ 2636 floatditf_libfunc = init_one_libfunc (FLOATDITF2_LIBCALL); \ 2637 fixtfdi_libfunc = init_one_libfunc (FIX_TRUNCTFDI2_LIBCALL);\ 2638 fixunstfdi_libfunc \ 2639 = init_one_libfunc (FIXUNS_TRUNCTFDI2_LIBCALL); \ 2640 } \ 2641 if (TARGET_FPU) \ 2642 sqrt_optab->handlers[(int) TFmode].libfunc \ 2643 = init_one_libfunc ("_Q_sqrt"); \ 2644 } \ 2645 if (TARGET_ARCH64) \ 2646 { \ 2647 /* In the SPARC 64bit ABI, these libfuncs do not exist in the \ 2648 library. Make sure the compiler does not emit calls to them \ 2649 by accident. */ \ 2650 sdiv_optab->handlers[(int) SImode].libfunc = NULL; \ 2651 udiv_optab->handlers[(int) SImode].libfunc = NULL; \ 2652 smod_optab->handlers[(int) SImode].libfunc = NULL; \ 2653 umod_optab->handlers[(int) SImode].libfunc = NULL; \ 2654 smul_optab->handlers[(int) SImode].libfunc = NULL; \ 2655 } \ 2656 INIT_SUBTARGET_OPTABS; \ 2657 } while (0) 2658 2659 /* This is meant to be redefined in the host dependent files */ 2660 #define INIT_SUBTARGET_OPTABS 2661 2662 /* Nonzero if a floating point comparison library call for 2663 mode MODE that will return a boolean value. Zero if one 2664 of the libgcc2 functions is used. */ 2665 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 2666 2667 /* Compute extra cost of moving data between one register class 2668 and another. */ 2669 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) 2670 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2671 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ 2672 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ 2673 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ 2674 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2675 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2) 2676 2677 /* Provide the cost of a branch. For pre-v9 processors we use 2678 a value of 3 to take into account the potential annulling of 2679 the delay slot (which ends up being a bubble in the pipeline slot) 2680 plus a cycle to take into consideration the instruction cache 2681 effects. 2682 2683 On v9 and later, which have branch prediction facilities, we set 2684 it to the depth of the pipeline as that is the cost of a 2685 mispredicted branch. */ 2686 2687 #define BRANCH_COST \ 2688 ((sparc_cpu == PROCESSOR_V9 \ 2689 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 2690 ? 7 \ 2691 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2692 ? 9 : 3)) 2693 2694 /* The cases that RTX_COSTS handles. */ 2695 2696 #define RTX_COSTS_CASES \ 2697 case PLUS: case MINUS: case ABS: case NEG: \ 2698 case FLOAT: case UNSIGNED_FLOAT: \ 2699 case FIX: case UNSIGNED_FIX: \ 2700 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \ 2701 case SQRT: \ 2702 case COMPARE: case IF_THEN_ELSE: \ 2703 case MEM: \ 2704 case MULT: case DIV: case UDIV: case MOD: case UMOD: \ 2705 case CONST_INT: case HIGH: case CONST: \ 2706 case LABEL_REF: case SYMBOL_REF: case CONST_DOUBLE: 2707 2708 /* Provide the costs of a rtl expression. This is in the body of a 2709 switch on CODE. */ 2710 2711 #define RTX_COSTS(X,CODE,OUTER_CODE) \ 2712 RTX_COSTS_CASES \ 2713 return sparc_rtx_costs(X,CODE,OUTER_CODE); 2714 2715 #define ADDRESS_COST(RTX) 1 2716 2717 #define PREFETCH_BLOCK \ 2718 ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2719 || sparc_cpu == PROCESSOR_ULTRASPARC3) \ 2720 ? 64 : 32) 2721 2722 #define SIMULTANEOUS_PREFETCHES \ 2723 ((sparc_cpu == PROCESSOR_ULTRASPARC) \ 2724 ? 2 \ 2725 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2726 ? 8 : 3)) 2727 2728 /* Control the assembler format that we output. */ 2729 2730 /* Output at beginning of assembler file. */ 2731 2732 #define ASM_FILE_START(file) 2733 2734 /* A C string constant describing how to begin a comment in the target 2735 assembler language. The compiler assumes that the comment will end at 2736 the end of the line. */ 2737 2738 #define ASM_COMMENT_START "!" 2739 2740 /* Output to assembler file text saying following lines 2741 may contain character constants, extra white space, comments, etc. */ 2742 2743 #define ASM_APP_ON "" 2744 2745 /* Output to assembler file text saying following lines 2746 no longer contain unusual constructs. */ 2747 2748 #define ASM_APP_OFF "" 2749 2750 /* ??? Try to make the style consistent here (_OP?). */ 2751 2752 #define ASM_FLOAT ".single" 2753 #define ASM_DOUBLE ".double" 2754 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ 2755 2756 /* How to refer to registers in assembler output. 2757 This sequence is indexed by compiler's hard-register-number (see above). */ 2758 2759 #define REGISTER_NAMES \ 2760 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2761 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2762 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2763 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2764 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2765 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2766 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2767 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2768 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2769 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2770 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2771 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2772 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } 2773 2774 /* Define additional names for use in asm clobbers and asm declarations. */ 2775 2776 #define ADDITIONAL_REGISTER_NAMES \ 2777 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 2778 2779 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 2780 can run past this up to a continuation point. Once we used 1500, but 2781 a single entry in C++ can run more than 500 bytes, due to the length of 2782 mangled symbol names. dbxout.c should really be fixed to do 2783 continuations when they are actually needed instead of trying to 2784 guess... */ 2785 #define DBX_CONTIN_LENGTH 1000 2786 2787 /* This is how to output a command to make the user-level label named NAME 2788 defined for reference from other files. */ 2789 2790 /* Globalizing directive for a label. */ 2791 #define GLOBAL_ASM_OP "\t.global " 2792 2793 /* The prefix to add to user-visible assembler symbols. */ 2794 2795 #define USER_LABEL_PREFIX "_" 2796 2797 /* This is how to output a definition of an internal numbered label where 2798 PREFIX is the class of label and NUM is the number within the class. */ 2799 2800 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 2801 fprintf (FILE, "%s%d:\n", PREFIX, NUM) 2802 2803 /* This is how to store into the string LABEL 2804 the symbol_ref name of an internal numbered label where 2805 PREFIX is the class of label and NUM is the number within the class. 2806 This is suitable for output with `assemble_name'. */ 2807 2808 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2809 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 2810 2811 /* This is how we hook in and defer the case-vector until the end of 2812 the function. */ 2813 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 2814 sparc_defer_case_vector ((LAB),(VEC), 0) 2815 2816 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 2817 sparc_defer_case_vector ((LAB),(VEC), 1) 2818 2819 /* This is how to output an element of a case-vector that is absolute. */ 2820 2821 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2822 do { \ 2823 char label[30]; \ 2824 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 2825 if (CASE_VECTOR_MODE == SImode) \ 2826 fprintf (FILE, "\t.word\t"); \ 2827 else \ 2828 fprintf (FILE, "\t.xword\t"); \ 2829 assemble_name (FILE, label); \ 2830 fputc ('\n', FILE); \ 2831 } while (0) 2832 2833 /* This is how to output an element of a case-vector that is relative. 2834 (SPARC uses such vectors only when generating PIC.) */ 2835 2836 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2837 do { \ 2838 char label[30]; \ 2839 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 2840 if (CASE_VECTOR_MODE == SImode) \ 2841 fprintf (FILE, "\t.word\t"); \ 2842 else \ 2843 fprintf (FILE, "\t.xword\t"); \ 2844 assemble_name (FILE, label); \ 2845 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 2846 fputc ('-', FILE); \ 2847 assemble_name (FILE, label); \ 2848 fputc ('\n', FILE); \ 2849 } while (0) 2850 2851 /* This is what to output before and after case-vector (both 2852 relative and absolute). If .subsection -1 works, we put case-vectors 2853 at the beginning of the current section. */ 2854 2855 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2856 2857 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 2858 fprintf(FILE, "\t.subsection\t-1\n") 2859 2860 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 2861 fprintf(FILE, "\t.previous\n") 2862 2863 #endif 2864 2865 /* This is how to output an assembler line 2866 that says to advance the location counter 2867 to a multiple of 2**LOG bytes. */ 2868 2869 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2870 if ((LOG) != 0) \ 2871 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2872 2873 /* This is how to output an assembler line that says to advance 2874 the location counter to a multiple of 2**LOG bytes using the 2875 "nop" instruction as padding. */ 2876 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 2877 if ((LOG) != 0) \ 2878 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) 2879 2880 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2881 fprintf (FILE, "\t.skip %u\n", (SIZE)) 2882 2883 /* This says how to output an assembler line 2884 to define a global common symbol. */ 2885 2886 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 2887 ( fputs ("\t.common ", (FILE)), \ 2888 assemble_name ((FILE), (NAME)), \ 2889 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) 2890 2891 /* This says how to output an assembler line to define a local common 2892 symbol. */ 2893 2894 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2895 ( fputs ("\t.reserve ", (FILE)), \ 2896 assemble_name ((FILE), (NAME)), \ 2897 fprintf ((FILE), ",%u,\"bss\",%u\n", \ 2898 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 2899 2900 /* A C statement (sans semicolon) to output to the stdio stream 2901 FILE the assembler definition of uninitialized global DECL named 2902 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 2903 Try to use asm_output_aligned_bss to implement this macro. */ 2904 2905 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2906 do { \ 2907 fputs (".globl ", (FILE)); \ 2908 assemble_name ((FILE), (NAME)); \ 2909 fputs ("\n", (FILE)); \ 2910 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 2911 } while (0) 2912 2913 /* Store in OUTPUT a string (made with alloca) containing 2914 an assembler-name for a local static variable named NAME. 2915 LABELNO is an integer which is different for each call. */ 2916 2917 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2918 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2919 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2920 2921 #define IDENT_ASM_OP "\t.ident\t" 2922 2923 /* Output #ident as a .ident. */ 2924 2925 #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2926 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); 2927 2928 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2929 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_') 2930 2931 /* Print operand X (an rtx) in assembler syntax to file FILE. 2932 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2933 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2934 2935 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2936 2937 /* Print a memory address as an operand to reference that memory location. */ 2938 2939 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2940 { register rtx base, index = 0; \ 2941 int offset = 0; \ 2942 register rtx addr = ADDR; \ 2943 if (GET_CODE (addr) == REG) \ 2944 fputs (reg_names[REGNO (addr)], FILE); \ 2945 else if (GET_CODE (addr) == PLUS) \ 2946 { \ 2947 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2948 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2949 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2950 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2951 else \ 2952 base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2953 if (GET_CODE (base) == LO_SUM) \ 2954 { \ 2955 if (! USE_AS_OFFSETABLE_LO10 \ 2956 || TARGET_ARCH32 \ 2957 || TARGET_CM_MEDMID) \ 2958 abort (); \ 2959 output_operand (XEXP (base, 0), 0); \ 2960 fputs ("+%lo(", FILE); \ 2961 output_address (XEXP (base, 1)); \ 2962 fprintf (FILE, ")+%d", offset); \ 2963 } \ 2964 else \ 2965 { \ 2966 fputs (reg_names[REGNO (base)], FILE); \ 2967 if (index == 0) \ 2968 fprintf (FILE, "%+d", offset); \ 2969 else if (GET_CODE (index) == REG) \ 2970 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 2971 else if (GET_CODE (index) == SYMBOL_REF \ 2972 || GET_CODE (index) == CONST) \ 2973 fputc ('+', FILE), output_addr_const (FILE, index); \ 2974 else abort (); \ 2975 } \ 2976 } \ 2977 else if (GET_CODE (addr) == MINUS \ 2978 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2979 { \ 2980 output_addr_const (FILE, XEXP (addr, 0)); \ 2981 fputs ("-(", FILE); \ 2982 output_addr_const (FILE, XEXP (addr, 1)); \ 2983 fputs ("-.)", FILE); \ 2984 } \ 2985 else if (GET_CODE (addr) == LO_SUM) \ 2986 { \ 2987 output_operand (XEXP (addr, 0), 0); \ 2988 if (TARGET_CM_MEDMID) \ 2989 fputs ("+%l44(", FILE); \ 2990 else \ 2991 fputs ("+%lo(", FILE); \ 2992 output_address (XEXP (addr, 1)); \ 2993 fputc (')', FILE); \ 2994 } \ 2995 else if (flag_pic && GET_CODE (addr) == CONST \ 2996 && GET_CODE (XEXP (addr, 0)) == MINUS \ 2997 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2998 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2999 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 3000 { \ 3001 addr = XEXP (addr, 0); \ 3002 output_addr_const (FILE, XEXP (addr, 0)); \ 3003 /* Group the args of the second CONST in parenthesis. */ \ 3004 fputs ("-(", FILE); \ 3005 /* Skip past the second CONST--it does nothing for us. */\ 3006 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 3007 /* Close the parenthesis. */ \ 3008 fputc (')', FILE); \ 3009 } \ 3010 else \ 3011 { \ 3012 output_addr_const (FILE, addr); \ 3013 } \ 3014 } 3015 3016 /* Define the codes that are matched by predicates in sparc.c. */ 3017 3018 #define PREDICATE_CODES \ 3019 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 3020 {"const1_operand", {CONST_INT}}, \ 3021 {"fp_zero_operand", {CONST_DOUBLE}}, \ 3022 {"fp_register_operand", {SUBREG, REG}}, \ 3023 {"intreg_operand", {SUBREG, REG}}, \ 3024 {"fcc_reg_operand", {REG}}, \ 3025 {"fcc0_reg_operand", {REG}}, \ 3026 {"icc_or_fcc_reg_operand", {REG}}, \ 3027 {"restore_operand", {REG}}, \ 3028 {"call_operand", {MEM}}, \ 3029 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \ 3030 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \ 3031 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3032 {"symbolic_memory_operand", {SUBREG, MEM}}, \ 3033 {"label_ref_operand", {LABEL_REF}}, \ 3034 {"sp64_medium_pic_operand", {CONST}}, \ 3035 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \ 3036 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \ 3037 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ 3038 {"splittable_symbolic_memory_operand", {MEM}}, \ 3039 {"splittable_immediate_memory_operand", {MEM}}, \ 3040 {"eq_or_neq", {EQ, NE}}, \ 3041 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \ 3042 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ 3043 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ 3044 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \ 3045 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \ 3046 {"cc_arithop", {AND, IOR, XOR}}, \ 3047 {"cc_arithopn", {AND, IOR}}, \ 3048 {"arith_operand", {SUBREG, REG, CONST_INT}}, \ 3049 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \ 3050 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \ 3051 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \ 3052 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 3053 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 3054 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 3055 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 3056 {"small_int", {CONST_INT}}, \ 3057 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \ 3058 {"uns_small_int", {CONST_INT}}, \ 3059 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \ 3060 {"clobbered_register", {REG}}, \ 3061 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \ 3062 {"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \ 3063 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \ 3064 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, 3065 3066 /* The number of Pmode words for the setjmp buffer. */ 3067 #define JMP_BUF_SIZE 12 3068 3069 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic) 3070