1 /* $OpenBSD: k1x-pstate.c,v 1.11 2021/08/11 18:31:48 tb Exp $ */
2 /*
3 * Copyright (c) 2011 Bryan Steele <brynet@gmail.com>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25 /* AMD K10/K11 pstate driver */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/malloc.h>
30 #include <sys/sysctl.h>
31
32 #include <machine/cpu.h>
33 #include <machine/cpufunc.h>
34 #include <machine/bus.h>
35
36 #include "acpicpu.h"
37
38 #if NACPICPU > 0
39 #include <dev/acpi/acpidev.h>
40 #endif
41
42 extern int setperf_prio;
43
44 #define MSR_K1X_LIMIT 0xc0010061
45 #define MSR_K1X_CONTROL 0xc0010062
46 #define MSR_K1X_STATUS 0xc0010063
47 #define MSR_K1X_CONFIG 0xc0010064
48
49 /* MSR_K1X_LIMIT */
50 #define K1X_PSTATE_MAX_VAL(x) (((x) >> 4) & 0x7)
51 #define K1X_PSTATE_LIMIT(x) (((x)) & 0x7)
52
53 /* MSR_K1X_CONFIG */
54 #define K1X_FID(x) ((x) & 0x3f)
55 #define K1X_DID(x) (((x) >> 6) & 0x07)
56
57 /* Maximum pstates */
58 #define K1X_MAX_STATES 16
59
60 struct k1x_state {
61 int freq;
62 u_int8_t fid;
63 };
64
65 struct k1x_cpu_state {
66 struct k1x_state state_table[K1X_MAX_STATES];
67 u_int n_states;
68 };
69
70 struct k1x_cpu_state *k1x_current_state;
71
72 void k1x_transition(struct k1x_cpu_state *, int);
73
74 #if NACPICPU > 0
75 void k1x_acpi_init(struct k1x_cpu_state *);
76 void k1x_acpi_states(struct k1x_cpu_state *, struct acpicpu_pss *, int);
77 #endif
78
79 void
k1x_setperf(int level)80 k1x_setperf(int level)
81 {
82 u_int i = 0;
83 struct k1x_cpu_state *cstate;
84
85 cstate = k1x_current_state;
86
87 i = ((level * cstate->n_states) + 1) / 101;
88 if (i >= cstate->n_states)
89 i = cstate->n_states - 1;
90
91 k1x_transition(cstate, i);
92 }
93
94 void
k1x_transition(struct k1x_cpu_state * cstate,int level)95 k1x_transition(struct k1x_cpu_state *cstate, int level)
96 {
97 u_int64_t msr;
98 int i, cfid, fid = cstate->state_table[level].fid;
99
100 wrmsr(MSR_K1X_CONTROL, fid);
101 for (i = 0; i < 100; i++) {
102 msr = rdmsr(MSR_K1X_STATUS);
103 cfid = K1X_FID(msr);
104 if (cfid == fid)
105 break;
106 DELAY(100);
107 }
108 if (cfid == fid) {
109 cpuspeed = cstate->state_table[level].freq;
110 #if 0
111 (void)printf("Target: %d Current: %d Pstate: %d\n",
112 cstate->state_table[level].freq,
113 cpuspeed, cfid);
114 #endif
115 }
116 }
117
118 #if NACPICPU > 0
119
120 void
k1x_acpi_states(struct k1x_cpu_state * cstate,struct acpicpu_pss * pss,int nstates)121 k1x_acpi_states(struct k1x_cpu_state *cstate, struct acpicpu_pss *pss,
122 int nstates)
123 {
124 struct k1x_state state;
125 int j, n;
126 u_int32_t ctrl;
127
128 for (n = 0; n < cstate->n_states; n++) {
129 ctrl = pss[n].pss_ctrl;
130 state.fid = K1X_FID(ctrl);
131 state.freq = pss[n].pss_core_freq;
132 j = n;
133 while (j > 0 && cstate->state_table[j - 1].freq > state.freq) {
134 memcpy(&cstate->state_table[j],
135 &cstate->state_table[j - 1],
136 sizeof(struct k1x_state));
137 --j;
138 }
139 memcpy(&cstate->state_table[j], &state,
140 sizeof(struct k1x_state));
141 }
142 }
143
144 void
k1x_acpi_init(struct k1x_cpu_state * cstate)145 k1x_acpi_init(struct k1x_cpu_state *cstate)
146 {
147 struct acpicpu_pss *pss;
148
149 cstate->n_states = acpicpu_fetch_pss(&pss);
150 if (cstate->n_states == 0)
151 return;
152
153 k1x_acpi_states(cstate, pss, cstate->n_states);
154
155 return;
156 }
157
158 #endif /* NACPICPU */
159
160 void
k1x_init(struct cpu_info * ci)161 k1x_init(struct cpu_info *ci)
162 {
163 struct k1x_cpu_state *cstate;
164 struct k1x_state *state;
165 u_int i;
166
167 if (setperf_prio > 1)
168 return;
169
170 cstate = malloc(sizeof(struct k1x_cpu_state), M_DEVBUF, M_NOWAIT);
171 if (!cstate)
172 return;
173
174 cstate->n_states = 0;
175
176 #if NACPICPU > 0
177 k1x_acpi_init(cstate);
178 #endif
179 if (cstate->n_states) {
180 printf("%s: %d MHz: speeds:",
181 ci->ci_dev->dv_xname, cpuspeed);
182 for (i = cstate->n_states; i > 0; i--) {
183 state = &cstate->state_table[i-1];
184 printf(" %d", state->freq);
185 }
186 printf(" MHz\n");
187 k1x_current_state = cstate;
188 cpu_setperf = k1x_setperf;
189 setperf_prio = 1;
190 return;
191 }
192 free(cstate, M_DEVBUF, sizeof(*cstate));
193 }
194