1 /* $OpenBSD: machdep.c,v 1.672 2024/06/07 16:53:35 kettenis Exp $ */
2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*-
35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved.
36 * Copyright (c) 1992 Terrence R. Lambert.
37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
38 * All rights reserved.
39 *
40 * This code is derived from software contributed to Berkeley by
41 * William Jolitz.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. Neither the name of the University nor the names of its contributors
52 * may be used to endorse or promote products derived from this software
53 * without specific prior written permission.
54 *
55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 * SUCH DAMAGE.
66 *
67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91
68 */
69
70 #include <sys/param.h>
71 #include <sys/systm.h>
72 #include <sys/signalvar.h>
73 #include <sys/proc.h>
74 #include <sys/user.h>
75 #include <sys/exec.h>
76 #include <sys/buf.h>
77 #include <sys/reboot.h>
78 #include <sys/conf.h>
79 #include <sys/malloc.h>
80 #include <sys/msgbuf.h>
81 #include <sys/mount.h>
82 #include <sys/device.h>
83 #include <sys/extent.h>
84 #include <sys/sysctl.h>
85 #include <sys/syscallargs.h>
86 #include <sys/core.h>
87 #include <sys/kcore.h>
88 #include <sys/sensors.h>
89
90 #include <dev/cons.h>
91 #include <stand/boot/bootarg.h>
92
93 #include <net/if.h>
94 #include <uvm/uvm_extern.h>
95
96 #include <machine/bus.h>
97
98 #include <machine/cpu.h>
99 #include <machine/cpu_full.h>
100 #include <machine/cpufunc.h>
101 #include <machine/cpuvar.h>
102 #include <machine/kcore.h>
103 #include <machine/pio.h>
104 #include <machine/psl.h>
105 #include <machine/specialreg.h>
106 #include <machine/biosvar.h>
107 #include <machine/pte.h>
108 #ifdef MULTIPROCESSOR
109 #include <machine/mpbiosvar.h>
110 #endif /* MULTIPROCESSOR */
111
112 #include <dev/isa/isareg.h>
113 #include <dev/ic/i8042reg.h>
114 #include <i386/isa/isa_machdep.h>
115
116 #include "acpi.h"
117 #if NACPI > 0
118 #include <dev/acpi/acpivar.h>
119 #endif
120
121 #include "apm.h"
122 #if NAPM > 0
123 #include <machine/apmvar.h>
124 #endif
125
126 #ifdef DDB
127 #include <machine/db_machdep.h>
128 #include <ddb/db_extern.h>
129 #endif
130
131 #include "isa.h"
132 #include "isadma.h"
133 #include "npx.h"
134 #if NNPX > 0
135 extern struct proc *npxproc;
136 #endif
137
138 #include "bios.h"
139
140 #ifdef HIBERNATE
141 #include <machine/hibernate_var.h>
142 #endif /* HIBERNATE */
143
144 #include "ukbd.h"
145 #include "pckbc.h"
146 #if NPCKBC > 0 && NUKBD > 0
147 #include <dev/ic/pckbcvar.h>
148 #endif
149
150 /* #define MACHDEP_DEBUG */
151
152 #ifdef MACHDEP_DEBUG
153 #define DPRINTF(x...) do { printf(x); } while (0)
154 #else
155 #define DPRINTF(x...)
156 #endif /* MACHDEP_DEBUG */
157
158 void replacesmap(void);
159 int intr_handler(struct intrframe *, struct intrhand *);
160
161 /* the following is used externally (sysctl_hw) */
162 char machine[] = MACHINE;
163
164 /*
165 * switchto vectors
166 */
167 void (*cpu_idle_leave_fcn)(void) = NULL;
168 void (*cpu_idle_cycle_fcn)(void) = NULL;
169 void (*cpu_idle_enter_fcn)(void) = NULL;
170 void (*cpu_suspend_cycle_fcn)(void);
171
172
173 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL };
174 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL };
175 struct uvm_constraint_range *uvm_md_constraints[] = {
176 &isa_constraint,
177 &dma_constraint,
178 NULL
179 };
180
181 extern int boothowto;
182 int physmem;
183
184 struct dumpmem dumpmem[VM_PHYSSEG_MAX];
185 u_int ndumpmem;
186
187 /*
188 * These variables are needed by /sbin/savecore
189 */
190 u_long dumpmag = 0x8fca0101; /* magic number */
191 int dumpsize = 0; /* pages */
192 long dumplo = 0; /* blocks */
193
194 int cpu_class;
195
196 int i386_use_fxsave;
197 int i386_has_sse;
198 int i386_has_sse2;
199 int i386_has_xcrypt;
200
201 bootarg_t *bootargp;
202 paddr_t avail_end;
203
204 struct vm_map *exec_map = NULL;
205 struct vm_map *phys_map = NULL;
206
207 #if !defined(SMALL_KERNEL)
208 int p3_early;
209 void (*update_cpuspeed)(void) = NULL;
210 void via_update_sensor(void *args);
211 #endif
212 int kbd_reset;
213 int lid_action = 1;
214 int pwr_action = 1;
215 int forceukbd;
216
217 /*
218 * safepri is a safe priority for sleep to set for a spin-wait
219 * during autoconfiguration or after a panic.
220 */
221 int safepri = 0;
222
223 #if !defined(SMALL_KERNEL)
224 int bus_clock;
225 #endif
226 void (*setperf_setup)(struct cpu_info *);
227 int setperf_prio = 0; /* for concurrent handlers */
228
229 void (*cpusensors_setup)(struct cpu_info *);
230
231 void (*delay_func)(int) = i8254_delay;
232 void (*initclock_func)(void) = i8254_initclocks;
233 void (*startclock_func)(void) = i8254_start_both_clocks;
234
235 /*
236 * Extent maps to manage I/O and ISA memory hole space. Allocate
237 * storage for 16 regions in each, initially. Later, ioport_malloc_safe
238 * will indicate that it's safe to use malloc() to dynamically allocate
239 * region descriptors.
240 *
241 * N.B. At least two regions are _always_ allocated from the iomem
242 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM).
243 *
244 * The extent maps are not static! Machine-dependent ISA and EISA
245 * routines need access to them for bus address space allocation.
246 */
247 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
248 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
249 struct extent *ioport_ex;
250 struct extent *iomem_ex;
251 static int ioport_malloc_safe;
252
253 void dumpsys(void);
254 int cpu_dump(void);
255 void init386(paddr_t);
256 void consinit(void);
257 void (*cpuresetfn)(void);
258
259 int bus_mem_add_mapping(bus_addr_t, bus_size_t,
260 int, bus_space_handle_t *);
261
262 #ifdef APERTURE
263 int allowaperture = 0;
264 #endif
265
266 int has_rdrand;
267 int has_rdseed;
268
269 void winchip_cpu_setup(struct cpu_info *);
270 void amd_family5_setperf_setup(struct cpu_info *);
271 void amd_family5_setup(struct cpu_info *);
272 void amd_family6_setperf_setup(struct cpu_info *);
273 void amd_family6_setup(struct cpu_info *);
274 void cyrix3_setperf_setup(struct cpu_info *);
275 void cyrix3_cpu_setup(struct cpu_info *);
276 void cyrix6x86_cpu_setup(struct cpu_info *);
277 void natsem6x86_cpu_setup(struct cpu_info *);
278 void intel586_cpu_setup(struct cpu_info *);
279 void intel686_cpusensors_setup(struct cpu_info *);
280 void intel686_setperf_setup(struct cpu_info *);
281 void intel686_common_cpu_setup(struct cpu_info *);
282 void intel686_cpu_setup(struct cpu_info *);
283 void intel686_p4_cpu_setup(struct cpu_info *);
284 void intelcore_update_sensor(void *);
285 void tm86_cpu_setup(struct cpu_info *);
286 char * intel686_cpu_name(int);
287 char * cyrix3_cpu_name(int, int);
288 char * tm86_cpu_name(int);
289 void cyrix3_get_bus_clock(struct cpu_info *);
290 void p4_get_bus_clock(struct cpu_info *);
291 void p3_get_bus_clock(struct cpu_info *);
292 void p4_update_cpuspeed(void);
293 void p3_update_cpuspeed(void);
294 int pentium_cpuspeed(int *);
295 void enter_shared_special_pages(void);
296
297 static __inline u_char
cyrix_read_reg(u_char reg)298 cyrix_read_reg(u_char reg)
299 {
300 outb(0x22, reg);
301 return inb(0x23);
302 }
303
304 static __inline void
cyrix_write_reg(u_char reg,u_char data)305 cyrix_write_reg(u_char reg, u_char data)
306 {
307 outb(0x22, reg);
308 outb(0x23, data);
309 }
310
311 /*
312 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx.
313 * requires caller to provide u_int32_t regs[4] array.
314 */
315 void
cpuid(u_int32_t ax,u_int32_t * regs)316 cpuid(u_int32_t ax, u_int32_t *regs)
317 {
318 __asm volatile(
319 "cpuid\n\t"
320 "movl %%eax, 0(%2)\n\t"
321 "movl %%ebx, 4(%2)\n\t"
322 "movl %%ecx, 8(%2)\n\t"
323 "movl %%edx, 12(%2)\n\t"
324 :"=a" (ax)
325 :"0" (ax), "S" (regs)
326 :"bx", "cx", "dx");
327 }
328
329 /*
330 * Machine-dependent startup code
331 */
332 void
cpu_startup(void)333 cpu_startup(void)
334 {
335 unsigned i;
336 vaddr_t minaddr, maxaddr, va;
337 paddr_t pa;
338
339 /*
340 * Initialize error message buffer (at end of core).
341 * (space reserved in pmap_bootstrap)
342 */
343 pa = avail_end;
344 va = (vaddr_t)msgbufp;
345 for (i = 0; i < atop(MSGBUFSIZE); i++) {
346 pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE);
347 va += PAGE_SIZE;
348 pa += PAGE_SIZE;
349 }
350 pmap_update(pmap_kernel());
351 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE));
352
353 printf("%s", version);
354 startclocks();
355 rtcinit();
356
357 printf("real mem = %llu (%lluMB)\n",
358 (unsigned long long)ptoa((psize_t)physmem),
359 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U);
360
361 /*
362 * Allocate a submap for exec arguments. This map effectively
363 * limits the number of processes exec'ing at any time.
364 */
365 minaddr = vm_map_min(kernel_map);
366 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
367 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL);
368
369 /*
370 * Allocate a submap for physio
371 */
372 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
373 VM_PHYS_SIZE, 0, FALSE, NULL);
374
375 printf("avail mem = %llu (%lluMB)\n",
376 (unsigned long long)ptoa((psize_t)uvmexp.free),
377 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U);
378
379 /*
380 * Set up buffers, so they can be used to read disk labels.
381 */
382 bufinit();
383
384 /*
385 * Configure the system.
386 */
387 if (boothowto & RB_CONFIG) {
388 #ifdef BOOT_CONFIG
389 user_config();
390 #else
391 printf("kernel does not support -c; continuing..\n");
392 #endif
393 }
394 ioport_malloc_safe = 1;
395
396 #ifndef SMALL_KERNEL
397 cpu_ucode_setup();
398 #endif
399
400 /* enter the IDT and trampoline code in the u-k maps */
401 enter_shared_special_pages();
402
403 /* initialize CPU0's TSS and GDT and put them in the u-k maps */
404 cpu_enter_pages(&cpu_info_full_primary);
405 }
406
407 void
enter_shared_special_pages(void)408 enter_shared_special_pages(void)
409 {
410 extern char __kutext_start[], __kutext_end[], __kernel_kutext_phys[];
411 extern char __kudata_start[], __kudata_end[], __kernel_kudata_phys[];
412 vaddr_t va;
413 paddr_t pa;
414
415 /* idt */
416 pmap_extract(pmap_kernel(), (vaddr_t)idt, &pa);
417 pmap_enter_special((vaddr_t)idt, pa, PROT_READ, 0);
418
419 /* .kutext section */
420 va = (vaddr_t)__kutext_start;
421 pa = (paddr_t)__kernel_kutext_phys;
422 while (va < (vaddr_t)__kutext_end) {
423 pmap_enter_special(va, pa, PROT_READ | PROT_EXEC, 0);
424 DPRINTF("%s: entered kutext page va 0x%08lx pa 0x%08lx\n",
425 __func__, (unsigned long)va, (unsigned long)pa);
426 va += PAGE_SIZE;
427 pa += PAGE_SIZE;
428 }
429
430 /* .kudata section */
431 va = (vaddr_t)__kudata_start;
432 pa = (paddr_t)__kernel_kudata_phys;
433 while (va < (vaddr_t)__kudata_end) {
434 pmap_enter_special(va, pa, PROT_READ | PROT_WRITE, 0);
435 DPRINTF("%s: entered kudata page va 0x%08lx pa 0x%08lx\n",
436 __func__, (unsigned long)va, (unsigned long)pa);
437 va += PAGE_SIZE;
438 pa += PAGE_SIZE;
439 }
440 }
441
442 /*
443 * Set up proc0's TSS
444 */
445 void
i386_proc0_tss_init(void)446 i386_proc0_tss_init(void)
447 {
448 struct pcb *pcb;
449
450 curpcb = pcb = &proc0.p_addr->u_pcb;
451 pcb->pcb_cr0 = rcr0();
452 pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16;
453 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1;
454 }
455
456 #ifdef MULTIPROCESSOR
457 void
i386_init_pcb_tss(struct cpu_info * ci)458 i386_init_pcb_tss(struct cpu_info *ci)
459 {
460 struct pcb *pcb = ci->ci_idle_pcb;
461
462 pcb->pcb_cr0 = rcr0();
463 }
464 #endif /* MULTIPROCESSOR */
465
466 /*
467 * Info for CTL_HW
468 */
469 char cpu_model[120];
470
471 const char *classnames[] = {
472 "",
473 "486",
474 "586",
475 "686"
476 };
477
478 const char *modifiers[] = {
479 "",
480 "OverDrive ",
481 "Dual ",
482 ""
483 };
484
485 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
486 {
487 "GenuineIntel",
488 CPUVENDOR_INTEL,
489 "Intel",
490 /* Family 4 */
491 { {
492 CPUCLASS_486,
493 {
494 "486DX", "486DX", "486SX", "486DX2", "486SL",
495 "486SX2", 0, "486DX2 W/B",
496 "486DX4", 0, 0, 0, 0, 0, 0, 0,
497 "486" /* Default */
498 },
499 NULL
500 },
501 /* Family 5 */
502 {
503 CPUCLASS_586,
504 {
505 "Pentium (A-step)", "Pentium (P5)",
506 "Pentium (P54C)", "Pentium (P24T)",
507 "Pentium/MMX", "Pentium", 0,
508 "Pentium (P54C)", "Pentium/MMX",
509 0, 0, 0, 0, 0, 0, 0,
510 "Pentium" /* Default */
511 },
512 intel586_cpu_setup
513 },
514 /* Family 6 */
515 {
516 CPUCLASS_686,
517 {
518 "Pentium Pro", "Pentium Pro", 0,
519 "Pentium II", "Pentium Pro",
520 "Pentium II/Celeron",
521 "Celeron",
522 "Pentium III",
523 "Pentium III",
524 "Pentium M",
525 "Pentium III Xeon",
526 "Pentium III", 0,
527 "Pentium M",
528 "Core Duo/Solo", 0,
529 "Pentium Pro, II or III" /* Default */
530 },
531 intel686_cpu_setup
532 },
533 /* Family 7 */
534 {
535 CPUCLASS_686,
536 } ,
537 /* Family 8 */
538 {
539 CPUCLASS_686,
540 } ,
541 /* Family 9 */
542 {
543 CPUCLASS_686,
544 } ,
545 /* Family A */
546 {
547 CPUCLASS_686,
548 } ,
549 /* Family B */
550 {
551 CPUCLASS_686,
552 } ,
553 /* Family C */
554 {
555 CPUCLASS_686,
556 } ,
557 /* Family D */
558 {
559 CPUCLASS_686,
560 } ,
561 /* Family E */
562 {
563 CPUCLASS_686,
564 } ,
565 /* Family F */
566 {
567 CPUCLASS_686,
568 {
569 "Pentium 4", 0, 0, 0,
570 0, 0, 0, 0,
571 0, 0, 0, 0,
572 0, 0, 0, 0,
573 "Pentium 4" /* Default */
574 },
575 intel686_p4_cpu_setup
576 } }
577 },
578 {
579 "AuthenticAMD",
580 CPUVENDOR_AMD,
581 "AMD",
582 /* Family 4 */
583 { {
584 CPUCLASS_486,
585 {
586 0, 0, 0, "Am486DX2 W/T",
587 0, 0, 0, "Am486DX2 W/B",
588 "Am486DX4 W/T or Am5x86 W/T 150",
589 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0,
590 0, 0, "Am5x86 W/T 133/160",
591 "Am5x86 W/B 133/160",
592 "Am486 or Am5x86" /* Default */
593 },
594 NULL
595 },
596 /* Family 5 */
597 {
598 CPUCLASS_586,
599 {
600 "K5", "K5", "K5", "K5", 0, 0, "K6",
601 "K6", "K6-2", "K6-III", 0, 0, 0,
602 "K6-2+/III+", 0, 0,
603 "K5 or K6" /* Default */
604 },
605 amd_family5_setup
606 },
607 /* Family 6 */
608 {
609 CPUCLASS_686,
610 {
611 0, "Athlon Model 1", "Athlon Model 2",
612 "Duron Model 3",
613 "Athlon Model 4",
614 0, "Athlon XP Model 6",
615 "Duron Model 7",
616 "Athlon XP Model 8",
617 0, "Athlon XP Model 10",
618 0, 0, 0, 0, 0,
619 "K7" /* Default */
620 },
621 amd_family6_setup
622 },
623 /* Family 7 */
624 {
625 CPUCLASS_686,
626 } ,
627 /* Family 8 */
628 {
629 CPUCLASS_686,
630 } ,
631 /* Family 9 */
632 {
633 CPUCLASS_686,
634 } ,
635 /* Family A */
636 {
637 CPUCLASS_686,
638 } ,
639 /* Family B */
640 {
641 CPUCLASS_686,
642 } ,
643 /* Family C */
644 {
645 CPUCLASS_686,
646 } ,
647 /* Family D */
648 {
649 CPUCLASS_686,
650 } ,
651 /* Family E */
652 {
653 CPUCLASS_686,
654 } ,
655 /* Family F */
656 {
657 CPUCLASS_686,
658 {
659 0, 0, 0, 0, "Athlon64",
660 "Opteron or Athlon64FX", 0, 0,
661 0, 0, 0, 0, 0, 0, 0, 0,
662 "AMD64" /* DEFAULT */
663 },
664 amd_family6_setup
665 } }
666 },
667 {
668 "CyrixInstead",
669 CPUVENDOR_CYRIX,
670 "Cyrix",
671 /* Family 4 */
672 { {
673 CPUCLASS_486,
674 {
675 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0,
676 0, 0, 0, 0,
677 "486 class" /* Default */
678 },
679 NULL
680 },
681 /* Family 5 */
682 {
683 CPUCLASS_586,
684 {
685 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0,
686 0, 0, 0, 0, 0, 0,
687 "586 class" /* Default */
688 },
689 cyrix6x86_cpu_setup
690 },
691 /* Family 6 */
692 {
693 CPUCLASS_686,
694 {
695 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
696 0, 0, 0, 0,
697 "686 class" /* Default */
698 },
699 NULL
700 } }
701 },
702 {
703 "CentaurHauls",
704 CPUVENDOR_IDT,
705 "IDT",
706 /* Family 4, not available from IDT */
707 { {
708 CPUCLASS_486,
709 {
710 0, 0, 0, 0, 0, 0, 0, 0,
711 0, 0, 0, 0, 0, 0, 0, 0,
712 "486 class" /* Default */
713 },
714 NULL
715 },
716 /* Family 5 */
717 {
718 CPUCLASS_586,
719 {
720 0, 0, 0, 0, "WinChip C6", 0, 0, 0,
721 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0,
722 "WinChip" /* Default */
723 },
724 winchip_cpu_setup
725 },
726 /* Family 6 */
727 {
728 CPUCLASS_686,
729 {
730 0, 0, 0, 0, 0, 0,
731 "C3 Samuel",
732 "C3 Samuel 2/Ezra",
733 "C3 Ezra-T",
734 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0,
735 "C3" /* Default */
736 },
737 cyrix3_cpu_setup
738 } }
739 },
740 {
741 "GenuineTMx86",
742 CPUVENDOR_TRANSMETA,
743 "Transmeta",
744 /* Family 4, not available from Transmeta */
745 { {
746 CPUCLASS_486,
747 {
748 0, 0, 0, 0, 0, 0, 0, 0,
749 0, 0, 0, 0, 0, 0, 0, 0,
750 "486 class" /* Default */
751 },
752 NULL
753 },
754 /* Family 5 */
755 {
756 CPUCLASS_586,
757 {
758 0, 0, 0, 0, "TMS5x00", 0, 0,
759 0, 0, 0, 0, 0, 0, 0, 0, 0,
760 "TMS5x00" /* Default */
761 },
762 tm86_cpu_setup
763 },
764 /* Family 6, not yet available from Transmeta */
765 {
766 CPUCLASS_686,
767 {
768 0, 0, 0, 0, 0, 0, 0, 0,
769 0, 0, 0, 0, 0, 0, 0, 0,
770 "686 class" /* Default */
771 },
772 NULL
773 },
774 /* Family 7 */
775 {
776 CPUCLASS_686,
777 } ,
778 /* Family 8 */
779 {
780 CPUCLASS_686,
781 } ,
782 /* Family 9 */
783 {
784 CPUCLASS_686,
785 } ,
786 /* Family A */
787 {
788 CPUCLASS_686,
789 } ,
790 /* Family B */
791 {
792 CPUCLASS_686,
793 } ,
794 /* Family C */
795 {
796 CPUCLASS_686,
797 } ,
798 /* Family D */
799 {
800 CPUCLASS_686,
801 } ,
802 /* Family E */
803 {
804 CPUCLASS_686,
805 } ,
806 /* Family F */
807 {
808 /* Extended processor family - Transmeta Efficeon */
809 CPUCLASS_686,
810 {
811 0, 0, "TM8000", "TM8000",
812 0, 0, 0, 0,
813 0, 0, 0, 0,
814 0, 0, 0, 0,
815 "TM8000" /* Default */
816 },
817 tm86_cpu_setup
818 } }
819 },
820 {
821 "Geode by NSC",
822 CPUVENDOR_NS,
823 "National Semiconductor",
824 /* Family 4, not available from National Semiconductor */
825 { {
826 CPUCLASS_486,
827 {
828 0, 0, 0, 0, 0, 0, 0, 0,
829 0, 0, 0, 0, 0, 0, 0, 0,
830 "486 class" /* Default */
831 },
832 NULL
833 },
834 /* Family 5 */
835 {
836 CPUCLASS_586,
837 {
838 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0,
839 0, 0, 0, 0, 0, 0,
840 "586 class" /* Default */
841 },
842 natsem6x86_cpu_setup
843 } }
844 },
845 {
846 "SiS SiS SiS ",
847 CPUVENDOR_SIS,
848 "SiS",
849 /* Family 4, not available from SiS */
850 { {
851 CPUCLASS_486,
852 {
853 0, 0, 0, 0, 0, 0, 0, 0,
854 0, 0, 0, 0, 0, 0, 0, 0,
855 "486 class" /* Default */
856 },
857 NULL
858 },
859 /* Family 5 */
860 {
861 CPUCLASS_586,
862 {
863 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0,
864 0, 0, 0, 0, 0, 0,
865 "586 class" /* Default */
866 },
867 NULL
868 } }
869 }
870 };
871
872 const struct cpu_cpuid_feature i386_cpuid_features[] = {
873 { CPUID_FPU, "FPU" },
874 { CPUID_VME, "V86" },
875 { CPUID_DE, "DE" },
876 { CPUID_PSE, "PSE" },
877 { CPUID_TSC, "TSC" },
878 { CPUID_MSR, "MSR" },
879 { CPUID_PAE, "PAE" },
880 { CPUID_MCE, "MCE" },
881 { CPUID_CX8, "CX8" },
882 { CPUID_APIC, "APIC" },
883 { CPUID_SYS1, "SYS" },
884 { CPUID_SEP, "SEP" },
885 { CPUID_MTRR, "MTRR" },
886 { CPUID_PGE, "PGE" },
887 { CPUID_MCA, "MCA" },
888 { CPUID_CMOV, "CMOV" },
889 { CPUID_PAT, "PAT" },
890 { CPUID_PSE36, "PSE36" },
891 { CPUID_PSN, "PSN" },
892 { CPUID_CFLUSH, "CFLUSH" },
893 { CPUID_DS, "DS" },
894 { CPUID_ACPI, "ACPI" },
895 { CPUID_MMX, "MMX" },
896 { CPUID_FXSR, "FXSR" },
897 { CPUID_SSE, "SSE" },
898 { CPUID_SSE2, "SSE2" },
899 { CPUID_SS, "SS" },
900 { CPUID_HTT, "HTT" },
901 { CPUID_TM, "TM" },
902 { CPUID_PBE, "PBE" }
903 };
904
905 const struct cpu_cpuid_feature i386_ecpuid_features[] = {
906 { CPUID_MPC, "MPC" },
907 { CPUID_NXE, "NXE" },
908 { CPUID_MMXX, "MMXX" },
909 { CPUID_FFXSR, "FFXSR" },
910 { CPUID_PAGE1GB, "PAGE1GB" },
911 { CPUID_RDTSCP, "RDTSCP" },
912 { CPUID_LONG, "LONG" },
913 { CPUID_3DNOW2, "3DNOW2" },
914 { CPUID_3DNOW, "3DNOW" }
915 };
916
917 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = {
918 { CPUIDECX_SSE3, "SSE3" },
919 { CPUIDECX_PCLMUL, "PCLMUL" },
920 { CPUIDECX_DTES64, "DTES64" },
921 { CPUIDECX_MWAIT, "MWAIT" },
922 { CPUIDECX_DSCPL, "DS-CPL" },
923 { CPUIDECX_VMX, "VMX" },
924 { CPUIDECX_SMX, "SMX" },
925 { CPUIDECX_EST, "EST" },
926 { CPUIDECX_TM2, "TM2" },
927 { CPUIDECX_SSSE3, "SSSE3" },
928 { CPUIDECX_CNXTID, "CNXT-ID" },
929 { CPUIDECX_SDBG, "SDBG" },
930 { CPUIDECX_FMA3, "FMA3" },
931 { CPUIDECX_CX16, "CX16" },
932 { CPUIDECX_XTPR, "xTPR" },
933 { CPUIDECX_PDCM, "PDCM" },
934 { CPUIDECX_PCID, "PCID" },
935 { CPUIDECX_DCA, "DCA" },
936 { CPUIDECX_SSE41, "SSE4.1" },
937 { CPUIDECX_SSE42, "SSE4.2" },
938 { CPUIDECX_X2APIC, "x2APIC" },
939 { CPUIDECX_MOVBE, "MOVBE" },
940 { CPUIDECX_POPCNT, "POPCNT" },
941 { CPUIDECX_DEADLINE, "DEADLINE" },
942 { CPUIDECX_AES, "AES" },
943 { CPUIDECX_XSAVE, "XSAVE" },
944 { CPUIDECX_OSXSAVE, "OSXSAVE" },
945 { CPUIDECX_AVX, "AVX" },
946 { CPUIDECX_F16C, "F16C" },
947 { CPUIDECX_RDRAND, "RDRAND" },
948 { CPUIDECX_HV, "HV" },
949 };
950
951 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = {
952 { CPUIDECX_LAHF, "LAHF" },
953 { CPUIDECX_CMPLEG, "CMPLEG" },
954 { CPUIDECX_SVM, "SVM" },
955 { CPUIDECX_EAPICSP, "EAPICSP" },
956 { CPUIDECX_AMCR8, "AMCR8" },
957 { CPUIDECX_ABM, "ABM" },
958 { CPUIDECX_SSE4A, "SSE4A" },
959 { CPUIDECX_MASSE, "MASSE" },
960 { CPUIDECX_3DNOWP, "3DNOWP" },
961 { CPUIDECX_OSVW, "OSVW" },
962 { CPUIDECX_IBS, "IBS" },
963 { CPUIDECX_XOP, "XOP" },
964 { CPUIDECX_SKINIT, "SKINIT" },
965 { CPUIDECX_WDT, "WDT" },
966 { CPUIDECX_LWP, "LWP" },
967 { CPUIDECX_FMA4, "FMA4" },
968 { CPUIDECX_TCE, "TCE" },
969 { CPUIDECX_NODEID, "NODEID" },
970 { CPUIDECX_TBM, "TBM" },
971 { CPUIDECX_TOPEXT, "TOPEXT" },
972 { CPUIDECX_CPCTR, "CPCTR" },
973 { CPUIDECX_DBKP, "DBKP" },
974 { CPUIDECX_PERFTSC, "PERFTSC" },
975 { CPUIDECX_PCTRL3, "PCTRL3" },
976 { CPUIDECX_MWAITX, "MWAITX" },
977 };
978
979 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = {
980 { SEFF0EBX_FSGSBASE, "FSGSBASE" },
981 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" },
982 { SEFF0EBX_SGX, "SGX" },
983 { SEFF0EBX_BMI1, "BMI1" },
984 { SEFF0EBX_HLE, "HLE" },
985 { SEFF0EBX_AVX2, "AVX2" },
986 { SEFF0EBX_SMEP, "SMEP" },
987 { SEFF0EBX_BMI2, "BMI2" },
988 { SEFF0EBX_ERMS, "ERMS" },
989 { SEFF0EBX_INVPCID, "INVPCID" },
990 { SEFF0EBX_RTM, "RTM" },
991 { SEFF0EBX_PQM, "PQM" },
992 { SEFF0EBX_MPX, "MPX" },
993 { SEFF0EBX_AVX512F, "AVX512F" },
994 { SEFF0EBX_AVX512DQ, "AVX512DQ" },
995 { SEFF0EBX_RDSEED, "RDSEED" },
996 { SEFF0EBX_ADX, "ADX" },
997 { SEFF0EBX_SMAP, "SMAP" },
998 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" },
999 { SEFF0EBX_PCOMMIT, "PCOMMIT" },
1000 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" },
1001 { SEFF0EBX_CLWB, "CLWB" },
1002 { SEFF0EBX_PT, "PT" },
1003 { SEFF0EBX_AVX512PF, "AVX512PF" },
1004 { SEFF0EBX_AVX512ER, "AVX512ER" },
1005 { SEFF0EBX_AVX512CD, "AVX512CD" },
1006 { SEFF0EBX_SHA, "SHA" },
1007 { SEFF0EBX_AVX512BW, "AVX512BW" },
1008 { SEFF0EBX_AVX512VL, "AVX512VL" },
1009 };
1010
1011 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = {
1012 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" },
1013 { SEFF0ECX_UMIP, "UMIP" },
1014 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" },
1015 { SEFF0ECX_PKU, "PKU" },
1016 { SEFF0ECX_WAITPKG, "WAITPKG" },
1017 };
1018
1019 const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = {
1020 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" },
1021 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" },
1022 { SEFF0EDX_SRBDS_CTRL, "SRBDS_CTRL" },
1023 { SEFF0EDX_MD_CLEAR, "MD_CLEAR" },
1024 { SEFF0EDX_TSXFA, "TSXFA" },
1025 { SEFF0EDX_IBRS, "IBRS,IBPB" },
1026 { SEFF0EDX_STIBP, "STIBP" },
1027 { SEFF0EDX_L1DF, "L1DF" },
1028 /* SEFF0EDX_ARCH_CAP (not printed) */
1029 { SEFF0EDX_SSBD, "SSBD" },
1030 };
1031
1032 const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = {
1033 { TPM_SENSOR, "SENSOR" },
1034 { TPM_ARAT, "ARAT" },
1035 };
1036
1037 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = {
1038 { CPUIDEAX_VERID, "PERF" },
1039 };
1040
1041 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = {
1042 { CPUIDEDX_ITSC, "ITSC" },
1043 };
1044
1045 const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = {
1046 { XSAVE_XSAVEOPT, "XSAVEOPT" },
1047 { XSAVE_XSAVEC, "XSAVEC" },
1048 { XSAVE_XGETBV1, "XGETBV1" },
1049 { XSAVE_XSAVES, "XSAVES" },
1050 };
1051
1052 void
winchip_cpu_setup(struct cpu_info * ci)1053 winchip_cpu_setup(struct cpu_info *ci)
1054 {
1055
1056 switch ((ci->ci_signature >> 4) & 15) { /* model */
1057 case 4: /* WinChip C6 */
1058 ci->ci_feature_flags &= ~CPUID_TSC;
1059 /* Disable RDTSC instruction from user-level. */
1060 lcr4(rcr4() | CR4_TSD);
1061 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname);
1062 break;
1063 }
1064 }
1065
1066 #if !defined(SMALL_KERNEL)
1067 void
cyrix3_setperf_setup(struct cpu_info * ci)1068 cyrix3_setperf_setup(struct cpu_info *ci)
1069 {
1070 if (cpu_ecxfeature & CPUIDECX_EST) {
1071 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
1072 est_init(ci, CPUVENDOR_VIA);
1073 else
1074 printf("%s: Enhanced SpeedStep disabled by BIOS\n",
1075 ci->ci_dev->dv_xname);
1076 }
1077 }
1078 #endif
1079
1080 void
cyrix3_cpu_setup(struct cpu_info * ci)1081 cyrix3_cpu_setup(struct cpu_info *ci)
1082 {
1083 int model = (ci->ci_signature >> 4) & 15;
1084 int step = ci->ci_signature & 15;
1085
1086 u_int64_t msreg;
1087 u_int32_t regs[4];
1088 unsigned int val;
1089 #if !defined(SMALL_KERNEL)
1090 extern void (*pagezero)(void *, size_t);
1091 extern void i686_pagezero(void *, size_t);
1092
1093 pagezero = i686_pagezero;
1094
1095 setperf_setup = cyrix3_setperf_setup;
1096 #endif
1097
1098 switch (model) {
1099 /* Possible earlier models */
1100 case 0: case 1: case 2:
1101 case 3: case 4: case 5:
1102 break;
1103
1104 case 6: /* C3 Samuel 1 */
1105 case 7: /* C3 Samuel 2 or C3 Ezra */
1106 case 8: /* C3 Ezra-T */
1107 cpuid(0x80000001, regs);
1108 val = regs[3];
1109 if (val & (1U << 31)) {
1110 cpu_feature |= CPUID_3DNOW;
1111 } else {
1112 cpu_feature &= ~CPUID_3DNOW;
1113 }
1114 break;
1115
1116 case 9:
1117 if (step < 3)
1118 break;
1119 /*
1120 * C3 Nehemiah & later: fall through.
1121 */
1122
1123 case 10: /* C7-M Type A */
1124 case 13: /* C7-M Type D */
1125 case 15: /* Nano */
1126 #if !defined(SMALL_KERNEL)
1127 if (CPU_IS_PRIMARY(ci) &&
1128 (model == 10 || model == 13 || model == 15)) {
1129 /* Setup the sensors structures */
1130 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname,
1131 sizeof(ci->ci_sensordev.xname));
1132 ci->ci_sensor.type = SENSOR_TEMP;
1133 sensor_task_register(ci, via_update_sensor, 5);
1134 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor);
1135 sensordev_install(&ci->ci_sensordev);
1136 }
1137 #endif
1138
1139 default:
1140 /*
1141 * C3 Nehemiah/Esther & later models:
1142 * First we check for extended feature flags, and then
1143 * (if present) retrieve the ones at 0xC0000001. In this
1144 * bit 2 tells us if the RNG is present. Bit 3 tells us
1145 * if the RNG has been enabled. In order to use the RNG
1146 * we need 3 things: We need an RNG, we need the FXSR bit
1147 * enabled in cr4 (SSE/SSE2 stuff), and we need to have
1148 * Bit 6 of MSR 0x110B set to 1 (the default), which will
1149 * show up as bit 3 set here.
1150 */
1151 cpuid(0xC0000000, regs); /* Check for RNG */
1152 val = regs[0];
1153 if (val >= 0xC0000001) {
1154 cpuid(0xC0000001, regs);
1155 val = regs[3];
1156 } else
1157 val = 0;
1158
1159 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
1160 printf("%s:", ci->ci_dev->dv_xname);
1161
1162 /* Enable RNG if present and disabled */
1163 if (val & C3_CPUID_HAS_RNG) {
1164 extern int viac3_rnd_present;
1165
1166 if (!(val & C3_CPUID_DO_RNG)) {
1167 msreg = rdmsr(0x110B);
1168 msreg |= 0x40;
1169 wrmsr(0x110B, msreg);
1170 }
1171 viac3_rnd_present = 1;
1172 printf(" RNG");
1173 }
1174
1175 /* Enable AES engine if present and disabled */
1176 if (val & C3_CPUID_HAS_ACE) {
1177 #ifdef CRYPTO
1178 if (!(val & C3_CPUID_DO_ACE)) {
1179 msreg = rdmsr(0x1107);
1180 msreg |= (0x01 << 28);
1181 wrmsr(0x1107, msreg);
1182 }
1183 i386_has_xcrypt |= C3_HAS_AES;
1184 #endif /* CRYPTO */
1185 printf(" AES");
1186 }
1187
1188 /* Enable ACE2 engine if present and disabled */
1189 if (val & C3_CPUID_HAS_ACE2) {
1190 #ifdef CRYPTO
1191 if (!(val & C3_CPUID_DO_ACE2)) {
1192 msreg = rdmsr(0x1107);
1193 msreg |= (0x01 << 28);
1194 wrmsr(0x1107, msreg);
1195 }
1196 i386_has_xcrypt |= C3_HAS_AESCTR;
1197 #endif /* CRYPTO */
1198 printf(" AES-CTR");
1199 }
1200
1201 /* Enable SHA engine if present and disabled */
1202 if (val & C3_CPUID_HAS_PHE) {
1203 #ifdef CRYPTO
1204 if (!(val & C3_CPUID_DO_PHE)) {
1205 msreg = rdmsr(0x1107);
1206 msreg |= (0x01 << 28/**/);
1207 wrmsr(0x1107, msreg);
1208 }
1209 i386_has_xcrypt |= C3_HAS_SHA;
1210 #endif /* CRYPTO */
1211 printf(" SHA1 SHA256");
1212 }
1213
1214 /* Enable MM engine if present and disabled */
1215 if (val & C3_CPUID_HAS_PMM) {
1216 #ifdef CRYPTO
1217 if (!(val & C3_CPUID_DO_PMM)) {
1218 msreg = rdmsr(0x1107);
1219 msreg |= (0x01 << 28/**/);
1220 wrmsr(0x1107, msreg);
1221 }
1222 i386_has_xcrypt |= C3_HAS_MM;
1223 #endif /* CRYPTO */
1224 printf(" RSA");
1225 }
1226
1227 printf("\n");
1228 break;
1229 }
1230 }
1231
1232 #if !defined(SMALL_KERNEL)
1233 void
via_update_sensor(void * args)1234 via_update_sensor(void *args)
1235 {
1236 struct cpu_info *ci = (struct cpu_info *) args;
1237 u_int64_t msr;
1238
1239 switch (ci->ci_model) {
1240 case 0xa:
1241 case 0xd:
1242 msr = rdmsr(MSR_C7M_TMTEMPERATURE);
1243 break;
1244 case 0xf:
1245 msr = rdmsr(MSR_CENT_TMTEMPERATURE);
1246 break;
1247 }
1248 ci->ci_sensor.value = (msr & 0xffffff);
1249 /* micro degrees */
1250 ci->ci_sensor.value *= 1000000;
1251 ci->ci_sensor.value += 273150000;
1252 ci->ci_sensor.flags &= ~SENSOR_FINVALID;
1253 }
1254 #endif
1255
1256 void
cyrix6x86_cpu_setup(struct cpu_info * ci)1257 cyrix6x86_cpu_setup(struct cpu_info *ci)
1258 {
1259 extern int clock_broken_latch;
1260
1261 switch ((ci->ci_signature >> 4) & 15) { /* model */
1262 case -1: /* M1 w/o cpuid */
1263 case 2: /* M1 */
1264 /* set up various cyrix registers */
1265 /* Enable suspend on halt */
1266 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08);
1267 /* enable access to ccr4/ccr5 */
1268 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10);
1269 /* cyrix's workaround for the "coma bug" */
1270 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8);
1271 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f);
1272 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0);
1273 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87);
1274 /* disable access to ccr4/ccr5 */
1275 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10);
1276
1277 printf("%s: xchg bug workaround performed\n",
1278 ci->ci_dev->dv_xname);
1279 break; /* fallthrough? */
1280 case 4: /* GXm */
1281 /* Unset the TSC bit until calibrate_delay() gets fixed. */
1282 clock_broken_latch = 1;
1283 curcpu()->ci_feature_flags &= ~CPUID_TSC;
1284 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname);
1285 break;
1286 }
1287 }
1288
1289 void
natsem6x86_cpu_setup(struct cpu_info * ci)1290 natsem6x86_cpu_setup(struct cpu_info *ci)
1291 {
1292 extern int clock_broken_latch;
1293 int model = (ci->ci_signature >> 4) & 15;
1294
1295 clock_broken_latch = 1;
1296 switch (model) {
1297 case 4:
1298 cpu_feature &= ~CPUID_TSC;
1299 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname);
1300 break;
1301 }
1302 }
1303
1304 void
intel586_cpu_setup(struct cpu_info * ci)1305 intel586_cpu_setup(struct cpu_info *ci)
1306 {
1307 if (!cpu_f00f_bug) {
1308 fix_f00f();
1309 printf("%s: F00F bug workaround installed\n",
1310 ci->ci_dev->dv_xname);
1311 }
1312 }
1313
1314 #if !defined(SMALL_KERNEL)
1315 void
amd_family5_setperf_setup(struct cpu_info * ci)1316 amd_family5_setperf_setup(struct cpu_info *ci)
1317 {
1318 k6_powernow_init();
1319 }
1320 #endif
1321
1322 void
amd_family5_setup(struct cpu_info * ci)1323 amd_family5_setup(struct cpu_info *ci)
1324 {
1325 int model = (ci->ci_signature >> 4) & 15;
1326
1327 switch (model) {
1328 case 0: /* AMD-K5 Model 0 */
1329 /*
1330 * According to the AMD Processor Recognition App Note,
1331 * the AMD-K5 Model 0 uses the wrong bit to indicate
1332 * support for global PTEs, instead using bit 9 (APIC)
1333 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!).
1334 */
1335 if (cpu_feature & CPUID_APIC)
1336 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE;
1337 /*
1338 * XXX But pmap_pg_g is already initialized -- need to kick
1339 * XXX the pmap somehow. How does the MP branch do this?
1340 */
1341 break;
1342 case 12:
1343 case 13:
1344 #if !defined(SMALL_KERNEL)
1345 setperf_setup = amd_family5_setperf_setup;
1346 #endif
1347 break;
1348 }
1349 }
1350
1351 #if !defined(SMALL_KERNEL)
1352 void
amd_family6_setperf_setup(struct cpu_info * ci)1353 amd_family6_setperf_setup(struct cpu_info *ci)
1354 {
1355 int family = (ci->ci_signature >> 8) & 15;
1356
1357 switch (family) {
1358 case 6:
1359 k7_powernow_init();
1360 break;
1361 case 15:
1362 k8_powernow_init();
1363 break;
1364 }
1365 if (ci->ci_family >= 0x10)
1366 k1x_init(ci);
1367 }
1368 #endif
1369
1370 void
amd_family6_setup(struct cpu_info * ci)1371 amd_family6_setup(struct cpu_info *ci)
1372 {
1373 #if !defined(SMALL_KERNEL)
1374 int family = (ci->ci_signature >> 8) & 15;
1375 extern void (*pagezero)(void *, size_t);
1376 extern void sse2_pagezero(void *, size_t);
1377 extern void i686_pagezero(void *, size_t);
1378
1379 if (cpu_feature & CPUID_SSE2)
1380 pagezero = sse2_pagezero;
1381 else
1382 pagezero = i686_pagezero;
1383
1384 setperf_setup = amd_family6_setperf_setup;
1385
1386 if (family == 0xf) {
1387 amd64_errata(ci);
1388 }
1389 #endif
1390 }
1391
1392 #if !defined(SMALL_KERNEL)
1393 /*
1394 * Temperature read on the CPU is relative to the maximum
1395 * temperature supported by the CPU, Tj(Max).
1396 * Refer to:
1397 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf
1398 * Section 35 and
1399 * http://www.intel.com/content/dam/www/public/us/en/documents/
1400 * white-papers/cpu-monitoring-dts-peci-paper.pdf
1401 *
1402 * The temperature on Intel CPUs can be between 70 and 105 degC, since
1403 * Westmere we can read the TJmax from the die. For older CPUs we have
1404 * to guess or use undocumented MSRs. Then we subtract the temperature
1405 * portion of thermal status from max to get current temperature.
1406 */
1407 void
intelcore_update_sensor(void * args)1408 intelcore_update_sensor(void *args)
1409 {
1410 struct cpu_info *ci = (struct cpu_info *) args;
1411 u_int64_t msr;
1412 int max = 100;
1413
1414 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */
1415 if (ci->ci_model == 0x0e &&
1416 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) &
1417 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED))
1418 max = 85;
1419
1420 /*
1421 * Newer CPUs can tell you what their max temperature is.
1422 * See: '64-ia-32-architectures-software-developer-
1423 * vol-3c-part-3-manual.pdf'
1424 */
1425 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c &&
1426 ci->ci_model != 0x26 && ci->ci_model != 0x27 &&
1427 ci->ci_model != 0x35 && ci->ci_model != 0x36)
1428 max = MSR_TEMPERATURE_TARGET_TJMAX(
1429 rdmsr(MSR_TEMPERATURE_TARGET));
1430
1431 msr = rdmsr(MSR_THERM_STATUS);
1432 if (msr & MSR_THERM_STATUS_VALID_BIT) {
1433 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr);
1434 /* micro degrees */
1435 ci->ci_sensor.value *= 1000000;
1436 /* kelvin */
1437 ci->ci_sensor.value += 273150000;
1438 ci->ci_sensor.flags &= ~SENSOR_FINVALID;
1439 } else {
1440 ci->ci_sensor.value = 0;
1441 ci->ci_sensor.flags |= SENSOR_FINVALID;
1442 }
1443 }
1444
1445 void
intel686_cpusensors_setup(struct cpu_info * ci)1446 intel686_cpusensors_setup(struct cpu_info *ci)
1447 {
1448 if (!CPU_IS_PRIMARY(ci) || (ci->ci_feature_tpmflags & TPM_SENSOR) == 0)
1449 return;
1450
1451 /* Setup the sensors structures */
1452 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname,
1453 sizeof(ci->ci_sensordev.xname));
1454 ci->ci_sensor.type = SENSOR_TEMP;
1455 sensor_task_register(ci, intelcore_update_sensor, 5);
1456 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor);
1457 sensordev_install(&ci->ci_sensordev);
1458 }
1459 #endif
1460
1461 #if !defined(SMALL_KERNEL)
1462 void
intel686_setperf_setup(struct cpu_info * ci)1463 intel686_setperf_setup(struct cpu_info *ci)
1464 {
1465 int family = (ci->ci_signature >> 8) & 15;
1466 int step = ci->ci_signature & 15;
1467
1468 if (cpu_ecxfeature & CPUIDECX_EST) {
1469 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
1470 est_init(ci, CPUVENDOR_INTEL);
1471 else
1472 printf("%s: Enhanced SpeedStep disabled by BIOS\n",
1473 ci->ci_dev->dv_xname);
1474 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) ==
1475 (CPUID_ACPI | CPUID_TM))
1476 p4tcc_init(family, step);
1477 }
1478 #endif
1479
1480 void
intel686_common_cpu_setup(struct cpu_info * ci)1481 intel686_common_cpu_setup(struct cpu_info *ci)
1482 {
1483
1484 #if !defined(SMALL_KERNEL)
1485 setperf_setup = intel686_setperf_setup;
1486 cpusensors_setup = intel686_cpusensors_setup;
1487 {
1488 extern void (*pagezero)(void *, size_t);
1489 extern void sse2_pagezero(void *, size_t);
1490 extern void i686_pagezero(void *, size_t);
1491
1492 if (cpu_feature & CPUID_SSE2)
1493 pagezero = sse2_pagezero;
1494 else
1495 pagezero = i686_pagezero;
1496 }
1497 #endif
1498 /*
1499 * Make sure SYSENTER is disabled.
1500 */
1501 if (cpu_feature & CPUID_SEP)
1502 wrmsr(MSR_SYSENTER_CS, 0);
1503 }
1504
1505 void
intel686_cpu_setup(struct cpu_info * ci)1506 intel686_cpu_setup(struct cpu_info *ci)
1507 {
1508 int model = (ci->ci_signature >> 4) & 15;
1509 int step = ci->ci_signature & 15;
1510 u_quad_t msr119;
1511
1512 intel686_common_cpu_setup(ci);
1513
1514 /*
1515 * Original PPro returns SYSCALL in CPUID but is non-functional.
1516 * From Intel Application Note #485.
1517 */
1518 if ((model == 1) && (step < 3))
1519 ci->ci_feature_flags &= ~CPUID_SEP;
1520
1521 /*
1522 * Disable the Pentium3 serial number.
1523 */
1524 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) {
1525 msr119 = rdmsr(MSR_BBL_CR_CTL);
1526 msr119 |= 0x0000000000200000LL;
1527 wrmsr(MSR_BBL_CR_CTL, msr119);
1528
1529 printf("%s: disabling processor serial number\n",
1530 ci->ci_dev->dv_xname);
1531 ci->ci_feature_flags &= ~CPUID_PSN;
1532 ci->ci_level = 2;
1533 }
1534
1535 #if !defined(SMALL_KERNEL)
1536 p3_early = (model == 8 && step == 1) ? 1 : 0;
1537 update_cpuspeed = p3_update_cpuspeed;
1538 #endif
1539 }
1540
1541 void
intel686_p4_cpu_setup(struct cpu_info * ci)1542 intel686_p4_cpu_setup(struct cpu_info *ci)
1543 {
1544 intel686_common_cpu_setup(ci);
1545
1546 #if !defined(SMALL_KERNEL)
1547 update_cpuspeed = p4_update_cpuspeed;
1548 #endif
1549 }
1550
1551 void
tm86_cpu_setup(struct cpu_info * ci)1552 tm86_cpu_setup(struct cpu_info *ci)
1553 {
1554 #if !defined(SMALL_KERNEL)
1555 longrun_init();
1556 #endif
1557 }
1558
1559 char *
intel686_cpu_name(int model)1560 intel686_cpu_name(int model)
1561 {
1562 char *ret = NULL;
1563
1564 switch (model) {
1565 case 5:
1566 switch (cpu_cache_edx & 0xFF) {
1567 case 0x40:
1568 case 0x41:
1569 ret = "Celeron";
1570 break;
1571 /* 0x42 should not exist in this model. */
1572 case 0x43:
1573 ret = "Pentium II";
1574 break;
1575 case 0x44:
1576 case 0x45:
1577 ret = "Pentium II Xeon";
1578 break;
1579 }
1580 break;
1581 case 7:
1582 switch (cpu_cache_edx & 0xFF) {
1583 /* 0x40 - 0x42 should not exist in this model. */
1584 case 0x43:
1585 ret = "Pentium III";
1586 break;
1587 case 0x44:
1588 case 0x45:
1589 ret = "Pentium III Xeon";
1590 break;
1591 }
1592 break;
1593 }
1594
1595 return (ret);
1596 }
1597
1598 char *
cyrix3_cpu_name(int model,int step)1599 cyrix3_cpu_name(int model, int step)
1600 {
1601 char *name = NULL;
1602
1603 switch (model) {
1604 case 7:
1605 if (step < 8)
1606 name = "C3 Samuel 2";
1607 else
1608 name = "C3 Ezra";
1609 break;
1610 }
1611 return name;
1612 }
1613
1614 /*
1615 * Print identification for the given CPU.
1616 * XXX XXX
1617 * This is not as clean as one might like, because it references
1618 *
1619 * the "cpuid_level" and "cpu_vendor" globals.
1620 * cpuid_level isn't so bad, since both CPU's will hopefully
1621 * be of the same level.
1622 *
1623 * The Intel multiprocessor spec doesn't give us the cpu_vendor
1624 * information; however, the chance of multi-vendor SMP actually
1625 * ever *working* is sufficiently low that it's probably safe to assume
1626 * all processors are of the same vendor.
1627 */
1628 void
identifycpu(struct cpu_info * ci)1629 identifycpu(struct cpu_info *ci)
1630 {
1631 const char *name, *modifier, *vendorname, *token;
1632 int class = CPUCLASS_486, vendor, i, max;
1633 int family, model, step, modif, cachesize;
1634 const struct cpu_cpuid_nameclass *cpup = NULL;
1635 char *brandstr_from, *brandstr_to;
1636 char *cpu_device = ci->ci_dev->dv_xname;
1637 int skipspace;
1638 extern uint32_t cpu_meltdown;
1639 uint64_t msr, nmsr;
1640
1641 if (cpuid_level == -1) {
1642 name = "486DX";
1643 vendor = CPUVENDOR_INTEL;
1644 vendorname = "Intel";
1645 model = -1;
1646 step = -1;
1647 class = CPUCLASS_486;
1648 ci->cpu_setup = NULL;
1649 modifier = "";
1650 token = "";
1651 } else {
1652 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]);
1653 modif = (ci->ci_signature >> 12) & 3;
1654 family = (ci->ci_signature >> 8) & 15;
1655 ci->ci_family = family;
1656 model = (ci->ci_signature >> 4) & 15;
1657 ci->ci_model = model;
1658 step = ci->ci_signature & 15;
1659 #ifdef CPUDEBUG
1660 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n",
1661 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx,
1662 cpu_cache_ecx, cpu_cache_edx);
1663 #endif
1664 if (family < CPU_MINFAMILY)
1665 panic("identifycpu: strange family value");
1666
1667 for (i = 0; i < max; i++) {
1668 if (!strncmp(cpu_vendor,
1669 i386_cpuid_cpus[i].cpu_id, 12)) {
1670 cpup = &i386_cpuid_cpus[i];
1671 break;
1672 }
1673 }
1674
1675 if (cpup == NULL) {
1676 vendor = CPUVENDOR_UNKNOWN;
1677 if (cpu_vendor[0] != '\0')
1678 vendorname = &cpu_vendor[0];
1679 else
1680 vendorname = "Unknown";
1681 if (family > CPU_MAXFAMILY)
1682 family = CPU_MAXFAMILY;
1683 class = family - 3;
1684 if (class > CPUCLASS_686)
1685 class = CPUCLASS_686;
1686 modifier = "";
1687 name = "";
1688 token = "";
1689 ci->cpu_setup = NULL;
1690 } else {
1691 token = cpup->cpu_id;
1692 vendor = cpup->cpu_vendor;
1693 vendorname = cpup->cpu_vendorname;
1694 /*
1695 * Special hack for the VIA C3 series.
1696 *
1697 * VIA bought Centaur Technology from IDT in Aug 1999
1698 * and marketed the processors as VIA Cyrix III/C3.
1699 */
1700 if (vendor == CPUVENDOR_IDT && family >= 6) {
1701 vendor = CPUVENDOR_VIA;
1702 vendorname = "VIA";
1703 }
1704 modifier = modifiers[modif];
1705 if (family > CPU_MAXFAMILY) {
1706 family = CPU_MAXFAMILY;
1707 model = CPU_DEFMODEL;
1708 } else if (model > CPU_MAXMODEL)
1709 model = CPU_DEFMODEL;
1710 i = family - CPU_MINFAMILY;
1711
1712 /* store extended family/model values for later use */
1713 if ((vendor == CPUVENDOR_INTEL &&
1714 (family == 0x6 || family == 0xf)) ||
1715 (vendor == CPUVENDOR_AMD && family == 0xf)) {
1716 ci->ci_family += (ci->ci_signature >> 20) &
1717 0xff;
1718 ci->ci_model += ((ci->ci_signature >> 16) &
1719 0x0f) << 4;
1720 }
1721
1722 /* Special hack for the PentiumII/III series. */
1723 if (vendor == CPUVENDOR_INTEL && family == 6 &&
1724 (model == 5 || model == 7)) {
1725 name = intel686_cpu_name(model);
1726 /* Special hack for the VIA C3 series. */
1727 } else if (vendor == CPUVENDOR_VIA && family == 6 &&
1728 model == 7) {
1729 name = cyrix3_cpu_name(model, step);
1730 /* Special hack for the TMS5x00 series. */
1731 } else if (vendor == CPUVENDOR_TRANSMETA &&
1732 family == 5 && model == 4) {
1733 name = tm86_cpu_name(model);
1734 } else
1735 name = cpup->cpu_family[i].cpu_models[model];
1736 if (name == NULL) {
1737 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL];
1738 if (name == NULL)
1739 name = "";
1740 }
1741 class = cpup->cpu_family[i].cpu_class;
1742 ci->cpu_setup = cpup->cpu_family[i].cpu_setup;
1743 }
1744 }
1745
1746 /* Find the amount of on-chip L2 cache. */
1747 cachesize = -1;
1748 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) {
1749 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 };
1750
1751 if ((cpu_cache_edx & 0xFF) >= 0x40 &&
1752 (cpu_cache_edx & 0xFF) <= 0x45)
1753 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40];
1754 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) {
1755 u_int regs[4];
1756 cpuid(0x80000000, regs);
1757
1758 if (regs[0] >= 0x80000006) {
1759 cpuid(0x80000006, regs);
1760 cachesize = (regs[2] >> 16);
1761 }
1762 }
1763
1764 if (ci->ci_feature_flags & CPUID_CFLUSH) {
1765 u_int regs[4];
1766
1767 /* to get the cacheline size you must do cpuid
1768 * with eax 0x01
1769 */
1770
1771 cpuid(0x01, regs);
1772 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8;
1773 }
1774
1775 if (vendor == CPUVENDOR_INTEL) {
1776 /*
1777 * PIII, Core Solo and Core Duo CPUs have known
1778 * errata stating:
1779 * "Page with PAT set to WC while associated MTRR is UC
1780 * may consolidate to UC".
1781 * Because of this it is best we just fallback to mtrrs
1782 * in this case.
1783 */
1784 if (ci->ci_family == 6 && ci->ci_model < 15)
1785 ci->ci_feature_flags &= ~CPUID_PAT;
1786 }
1787
1788 /* Remove leading, trailing and duplicated spaces from cpu_brandstr */
1789 brandstr_from = brandstr_to = cpu_brandstr;
1790 skipspace = 1;
1791 while (*brandstr_from != '\0') {
1792 if (!skipspace || *brandstr_from != ' ') {
1793 skipspace = 0;
1794 *(brandstr_to++) = *brandstr_from;
1795 }
1796 if (*brandstr_from == ' ')
1797 skipspace = 1;
1798 brandstr_from++;
1799 }
1800 if (skipspace && brandstr_to > cpu_brandstr)
1801 brandstr_to--;
1802 *brandstr_to = '\0';
1803
1804 if (cpu_brandstr[0] == '\0') {
1805 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */,
1806 "%s %s%s", vendorname, modifier, name);
1807 }
1808
1809 if (cachesize > -1) {
1810 snprintf(cpu_model, sizeof(cpu_model),
1811 "%s (%s%s%s%s-class, %dKB L2 cache)",
1812 cpu_brandstr,
1813 ((*token) ? "\"" : ""), ((*token) ? token : ""),
1814 ((*token) ? "\" " : ""), classnames[class], cachesize);
1815 } else {
1816 snprintf(cpu_model, sizeof(cpu_model),
1817 "%s (%s%s%s%s-class)",
1818 cpu_brandstr,
1819 ((*token) ? "\"" : ""), ((*token) ? token : ""),
1820 ((*token) ? "\" " : ""), classnames[class]);
1821 }
1822
1823 printf("%s: %s", cpu_device, cpu_model);
1824
1825 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) {
1826 /* Has TSC, check if it's constant */
1827 switch (vendor) {
1828 case CPUVENDOR_INTEL:
1829 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) ||
1830 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) {
1831 ci->ci_flags |= CPUF_CONST_TSC;
1832 }
1833 break;
1834 case CPUVENDOR_VIA:
1835 if (ci->ci_model >= 0x0f) {
1836 ci->ci_flags |= CPUF_CONST_TSC;
1837 }
1838 break;
1839 }
1840 calibrate_cyclecounter();
1841 if (cpuspeed > 994) {
1842 int ghz, fr;
1843
1844 ghz = (cpuspeed + 9) / 1000;
1845 fr = ((cpuspeed + 9) / 10 ) % 100;
1846 if (fr)
1847 printf(" %d.%02d GHz", ghz, fr);
1848 else
1849 printf(" %d GHz", ghz);
1850 } else {
1851 printf(" %d MHz", cpuspeed);
1852 }
1853 }
1854
1855 if (cpuid_level != -1)
1856 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model,
1857 step);
1858
1859 if ((cpu_ecxfeature & CPUIDECX_HV) == 0) {
1860 uint64_t level = 0;
1861 uint32_t dummy;
1862
1863 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
1864 ci->ci_family >= 0x0f) {
1865 level = rdmsr(MSR_PATCH_LEVEL);
1866 } else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
1867 ci->ci_family >= 6) {
1868 wrmsr(MSR_BIOS_SIGN, 0);
1869 CPUID(1, dummy, dummy, dummy, dummy);
1870 level = rdmsr(MSR_BIOS_SIGN) >> 32;
1871 }
1872 if (level != 0)
1873 printf(", patch %08llx", level);
1874 }
1875
1876 printf("\n");
1877
1878 if (ci->ci_feature_flags) {
1879 int numbits = 0;
1880
1881 printf("%s: ", cpu_device);
1882 max = sizeof(i386_cpuid_features) /
1883 sizeof(i386_cpuid_features[0]);
1884 for (i = 0; i < max; i++) {
1885 if (ci->ci_feature_flags &
1886 i386_cpuid_features[i].feature_bit) {
1887 printf("%s%s", (numbits == 0 ? "" : ","),
1888 i386_cpuid_features[i].feature_name);
1889 numbits++;
1890 }
1891 }
1892 max = sizeof(i386_cpuid_ecxfeatures)
1893 / sizeof(i386_cpuid_ecxfeatures[0]);
1894 for (i = 0; i < max; i++) {
1895 if (cpu_ecxfeature &
1896 i386_cpuid_ecxfeatures[i].feature_bit) {
1897 printf("%s%s", (numbits == 0 ? "" : ","),
1898 i386_cpuid_ecxfeatures[i].feature_name);
1899 numbits++;
1900 }
1901 }
1902 for (i = 0; i < nitems(i386_ecpuid_features); i++) {
1903 if (ecpu_feature &
1904 i386_ecpuid_features[i].feature_bit) {
1905 printf("%s%s", (numbits == 0 ? "" : ","),
1906 i386_ecpuid_features[i].feature_name);
1907 numbits++;
1908 }
1909 }
1910 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) {
1911 if (ecpu_ecxfeature &
1912 i386_ecpuid_ecxfeatures[i].feature_bit) {
1913 printf("%s%s", (numbits == 0 ? "" : ","),
1914 i386_ecpuid_ecxfeatures[i].feature_name);
1915 numbits++;
1916 }
1917 }
1918 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) {
1919 if (cpu_perf_eax &
1920 i386_cpuid_eaxperf[i].feature_bit) {
1921 printf("%s%s", (numbits == 0 ? "" : ","),
1922 i386_cpuid_eaxperf[i].feature_name);
1923 numbits++;
1924 }
1925 }
1926 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) {
1927 if (cpu_apmi_edx &
1928 i386_cpuid_edxapmi[i].feature_bit) {
1929 printf("%s%s", (numbits == 0 ? "" : ","),
1930 i386_cpuid_edxapmi[i].feature_name);
1931 numbits++;
1932 }
1933 }
1934
1935 if (cpuid_level >= 0x07) {
1936 u_int dummy;
1937
1938 /* "Structured Extended Feature Flags" */
1939 CPUID_LEAF(0x7, 0, dummy,
1940 ci->ci_feature_sefflags_ebx,
1941 ci->ci_feature_sefflags_ecx,
1942 ci->ci_feature_sefflags_edx);
1943 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++)
1944 if (ci->ci_feature_sefflags_ebx &
1945 cpu_seff0_ebxfeatures[i].feature_bit)
1946 printf("%s%s",
1947 (numbits == 0 ? "" : ","),
1948 cpu_seff0_ebxfeatures[i].feature_name);
1949 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++)
1950 if (ci->ci_feature_sefflags_ecx &
1951 cpu_seff0_ecxfeatures[i].feature_bit)
1952 printf("%s%s",
1953 (numbits == 0 ? "" : ","),
1954 cpu_seff0_ecxfeatures[i].feature_name);
1955 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++)
1956 if (ci->ci_feature_sefflags_edx &
1957 cpu_seff0_edxfeatures[i].feature_bit)
1958 printf("%s%s",
1959 (numbits == 0 ? "" : ","),
1960 cpu_seff0_edxfeatures[i].feature_name);
1961 }
1962
1963 if (!strcmp(cpu_vendor, "GenuineIntel") &&
1964 cpuid_level >= 0x06 ) {
1965 u_int dummy;
1966
1967 CPUID(0x06, ci->ci_feature_tpmflags, dummy,
1968 dummy, dummy);
1969 max = nitems(cpu_tpm_eaxfeatures);
1970 for (i = 0; i < max; i++)
1971 if (ci->ci_feature_tpmflags &
1972 cpu_tpm_eaxfeatures[i].feature_bit)
1973 printf(",%s", cpu_tpm_eaxfeatures[i].feature_name);
1974 }
1975
1976 /* xsave subfeatures */
1977 if (cpuid_level >= 0xd) {
1978 uint32_t dummy, val;
1979
1980 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy);
1981 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++)
1982 if (val & cpu_xsave_extfeatures[i].feature_bit)
1983 printf(",%s",
1984 cpu_xsave_extfeatures[i].feature_name);
1985 }
1986
1987 if (cpu_meltdown)
1988 printf(",MELTDOWN");
1989
1990 printf("\n");
1991 }
1992
1993 /*
1994 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques
1995 * for Managing Speculation on AMD Processors"
1996 *
1997 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch
1998 * serializing instruction.
1999 *
2000 * This MSR is available on all AMD families >= 10h, except 11h
2001 * where LFENCE is always serializing.
2002 */
2003 if (!strcmp(cpu_vendor, "AuthenticAMD")) {
2004 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) {
2005 nmsr = msr = rdmsr(MSR_DE_CFG);
2006 nmsr |= DE_CFG_SERIALIZE_LFENCE;
2007 if (msr != nmsr)
2008 wrmsr(MSR_DE_CFG, nmsr);
2009 }
2010 if (family == 0x17 && ci->ci_model >= 0x31 &&
2011 (cpu_ecxfeature & CPUIDECX_HV) == 0) {
2012 nmsr = msr = rdmsr(MSR_DE_CFG);
2013 nmsr |= DE_CFG_SERIALIZE_9;
2014 if (msr != nmsr)
2015 wrmsr(MSR_DE_CFG, nmsr);
2016 }
2017 }
2018
2019 /*
2020 * Attempt to disable Silicon Debug and lock the configuration
2021 * if it's enabled and unlocked.
2022 */
2023 if (!strcmp(cpu_vendor, "GenuineIntel") &&
2024 (cpu_ecxfeature & CPUIDECX_SDBG)) {
2025 uint64_t msr;
2026
2027 msr = rdmsr(IA32_DEBUG_INTERFACE);
2028 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) &&
2029 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) {
2030 msr &= IA32_DEBUG_INTERFACE_MASK;
2031 msr |= IA32_DEBUG_INTERFACE_LOCK;
2032 wrmsr(IA32_DEBUG_INTERFACE, msr);
2033 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE)
2034 printf("%s: cannot disable silicon debug\n",
2035 cpu_device);
2036 }
2037
2038 if (CPU_IS_PRIMARY(ci)) {
2039 if (cpu_ecxfeature & CPUIDECX_RDRAND)
2040 has_rdrand = 1;
2041 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED)
2042 has_rdseed = 1;
2043 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP)
2044 replacesmap();
2045 }
2046
2047 #ifndef SMALL_KERNEL
2048 if (cpuspeed != 0 && cpu_cpuspeed == NULL)
2049 cpu_cpuspeed = pentium_cpuspeed;
2050 #endif
2051
2052 cpu_class = class;
2053
2054 ci->cpu_class = class;
2055
2056 /*
2057 * Enable ring 0 write protection.
2058 */
2059 lcr0(rcr0() | CR0_WP);
2060
2061 /*
2062 * If we have FXSAVE/FXRESTOR, use them.
2063 */
2064 if (cpu_feature & CPUID_FXSR) {
2065 i386_use_fxsave = 1;
2066 lcr4(rcr4() | CR4_OSFXSR);
2067
2068 /*
2069 * If we have SSE/SSE2, enable XMM exceptions, and
2070 * notify userland.
2071 */
2072 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) {
2073 if (cpu_feature & CPUID_SSE)
2074 i386_has_sse = 1;
2075 if (cpu_feature & CPUID_SSE2)
2076 i386_has_sse2 = 1;
2077 lcr4(rcr4() | CR4_OSXMMEXCPT);
2078 }
2079 } else
2080 i386_use_fxsave = 0;
2081
2082 }
2083
2084 char *
tm86_cpu_name(int model)2085 tm86_cpu_name(int model)
2086 {
2087 u_int32_t regs[4];
2088 char *name = NULL;
2089
2090 cpuid(0x80860001, regs);
2091
2092 switch (model) {
2093 case 4:
2094 if (((regs[1] >> 16) & 0xff) >= 0x3)
2095 name = "TMS5800";
2096 else
2097 name = "TMS5600";
2098 }
2099
2100 return name;
2101 }
2102
2103 #ifndef SMALL_KERNEL
2104 void
cyrix3_get_bus_clock(struct cpu_info * ci)2105 cyrix3_get_bus_clock(struct cpu_info *ci)
2106 {
2107 u_int64_t msr;
2108 int bus;
2109
2110 msr = rdmsr(MSR_EBL_CR_POWERON);
2111 bus = (msr >> 18) & 0x3;
2112 switch (bus) {
2113 case 0:
2114 bus_clock = BUS100;
2115 break;
2116 case 1:
2117 bus_clock = BUS133;
2118 break;
2119 case 2:
2120 bus_clock = BUS200;
2121 break;
2122 case 3:
2123 bus_clock = BUS166;
2124 break;
2125 }
2126 }
2127
2128 void
p4_get_bus_clock(struct cpu_info * ci)2129 p4_get_bus_clock(struct cpu_info *ci)
2130 {
2131 u_int64_t msr;
2132 int model, bus;
2133
2134 model = (ci->ci_signature >> 4) & 15;
2135 msr = rdmsr(MSR_EBC_FREQUENCY_ID);
2136 if (model < 2) {
2137 bus = (msr >> 21) & 0x7;
2138 switch (bus) {
2139 case 0:
2140 bus_clock = BUS100;
2141 break;
2142 case 1:
2143 bus_clock = BUS133;
2144 break;
2145 default:
2146 printf("%s: unknown Pentium 4 (model %d) "
2147 "EBC_FREQUENCY_ID value %d\n",
2148 ci->ci_dev->dv_xname, model, bus);
2149 break;
2150 }
2151 } else {
2152 bus = (msr >> 16) & 0x7;
2153 switch (bus) {
2154 case 0:
2155 bus_clock = (model == 2) ? BUS100 : BUS266;
2156 break;
2157 case 1:
2158 bus_clock = BUS133;
2159 break;
2160 case 2:
2161 bus_clock = BUS200;
2162 break;
2163 case 3:
2164 bus_clock = BUS166;
2165 break;
2166 default:
2167 printf("%s: unknown Pentium 4 (model %d) "
2168 "EBC_FREQUENCY_ID value %d\n",
2169 ci->ci_dev->dv_xname, model, bus);
2170 break;
2171 }
2172 }
2173 }
2174
2175 void
p3_get_bus_clock(struct cpu_info * ci)2176 p3_get_bus_clock(struct cpu_info *ci)
2177 {
2178 u_int64_t msr;
2179 int bus;
2180
2181 switch (ci->ci_model) {
2182 case 0x9: /* Pentium M (130 nm, Banias) */
2183 bus_clock = BUS100;
2184 break;
2185 case 0xd: /* Pentium M (90 nm, Dothan) */
2186 msr = rdmsr(MSR_FSB_FREQ);
2187 bus = (msr >> 0) & 0x7;
2188 switch (bus) {
2189 case 0:
2190 bus_clock = BUS100;
2191 break;
2192 case 1:
2193 bus_clock = BUS133;
2194 break;
2195 default:
2196 printf("%s: unknown Pentium M FSB_FREQ value %d",
2197 ci->ci_dev->dv_xname, bus);
2198 goto print_msr;
2199 }
2200 break;
2201 case 0x15: /* EP80579 no FSB */
2202 break;
2203 case 0xe: /* Core Duo/Solo */
2204 case 0xf: /* Core Xeon */
2205 case 0x16: /* 65nm Celeron */
2206 case 0x17: /* Core 2 Extreme/45nm Xeon */
2207 case 0x1d: /* Xeon MP 7400 */
2208 msr = rdmsr(MSR_FSB_FREQ);
2209 bus = (msr >> 0) & 0x7;
2210 switch (bus) {
2211 case 5:
2212 bus_clock = BUS100;
2213 break;
2214 case 1:
2215 bus_clock = BUS133;
2216 break;
2217 case 3:
2218 bus_clock = BUS166;
2219 break;
2220 case 2:
2221 bus_clock = BUS200;
2222 break;
2223 case 0:
2224 bus_clock = BUS266;
2225 break;
2226 case 4:
2227 bus_clock = BUS333;
2228 break;
2229 default:
2230 printf("%s: unknown Core FSB_FREQ value %d",
2231 ci->ci_dev->dv_xname, bus);
2232 goto print_msr;
2233 }
2234 break;
2235 case 0x1c: /* Atom */
2236 case 0x26: /* Atom Z6xx */
2237 case 0x36: /* Atom [DN]2xxx */
2238 msr = rdmsr(MSR_FSB_FREQ);
2239 bus = (msr >> 0) & 0x7;
2240 switch (bus) {
2241 case 5:
2242 bus_clock = BUS100;
2243 break;
2244 case 1:
2245 bus_clock = BUS133;
2246 break;
2247 case 3:
2248 bus_clock = BUS166;
2249 break;
2250 case 2:
2251 bus_clock = BUS200;
2252 break;
2253 default:
2254 printf("%s: unknown Atom FSB_FREQ value %d",
2255 ci->ci_dev->dv_xname, bus);
2256 goto print_msr;
2257 }
2258 break;
2259 case 0x1: /* Pentium Pro, model 1 */
2260 case 0x3: /* Pentium II, model 3 */
2261 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */
2262 case 0x6: /* Celeron, model 6 */
2263 case 0x7: /* Pentium III, III Xeon, model 7 */
2264 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */
2265 case 0xa: /* Pentium III Xeon, model A */
2266 case 0xb: /* Pentium III, model B */
2267 msr = rdmsr(MSR_EBL_CR_POWERON);
2268 bus = (msr >> 18) & 0x3;
2269 switch (bus) {
2270 case 0:
2271 bus_clock = BUS66;
2272 break;
2273 case 1:
2274 bus_clock = BUS133;
2275 break;
2276 case 2:
2277 bus_clock = BUS100;
2278 break;
2279 default:
2280 printf("%s: unknown i686 EBL_CR_POWERON value %d",
2281 ci->ci_dev->dv_xname, bus);
2282 goto print_msr;
2283 }
2284 break;
2285 default:
2286 /* no FSB on modern Intel processors */
2287 break;
2288 }
2289 return;
2290 print_msr:
2291 /*
2292 * Show the EBL_CR_POWERON MSR, so we'll at least have
2293 * some extra information, such as clock ratio, etc.
2294 */
2295 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON));
2296 }
2297
2298 void
p4_update_cpuspeed(void)2299 p4_update_cpuspeed(void)
2300 {
2301 struct cpu_info *ci;
2302 u_int64_t msr;
2303 int mult;
2304
2305 ci = curcpu();
2306 p4_get_bus_clock(ci);
2307
2308 if (bus_clock == 0) {
2309 printf("p4_update_cpuspeed: unknown bus clock\n");
2310 return;
2311 }
2312
2313 msr = rdmsr(MSR_EBC_FREQUENCY_ID);
2314 mult = ((msr >> 24) & 0xff);
2315
2316 cpuspeed = (bus_clock * mult) / 100;
2317 }
2318
2319 void
p3_update_cpuspeed(void)2320 p3_update_cpuspeed(void)
2321 {
2322 struct cpu_info *ci;
2323 u_int64_t msr;
2324 int mult;
2325 const u_int8_t mult_code[] = {
2326 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 };
2327
2328 ci = curcpu();
2329 p3_get_bus_clock(ci);
2330
2331 if (bus_clock == 0) {
2332 printf("p3_update_cpuspeed: unknown bus clock\n");
2333 return;
2334 }
2335
2336 msr = rdmsr(MSR_EBL_CR_POWERON);
2337 mult = (msr >> 22) & 0xf;
2338 mult = mult_code[mult];
2339 if (!p3_early)
2340 mult += ((msr >> 27) & 0x1) * 40;
2341
2342 cpuspeed = (bus_clock * mult) / 1000;
2343 }
2344
2345 int
pentium_cpuspeed(int * freq)2346 pentium_cpuspeed(int *freq)
2347 {
2348 *freq = cpuspeed;
2349 return (0);
2350 }
2351 #endif /* !SMALL_KERNEL */
2352
2353 /*
2354 * Send an interrupt to process.
2355 *
2356 * Stack is set up to allow sigcode stored
2357 * in u. to call routine, followed by kcall
2358 * to sigreturn routine below. After sigreturn
2359 * resets the signal mask, the stack, and the
2360 * frame pointer, it returns to the user
2361 * specified pc, psl.
2362 */
2363 int
sendsig(sig_t catcher,int sig,sigset_t mask,const siginfo_t * ksip,int info,int onstack)2364 sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,
2365 int info, int onstack)
2366 {
2367 struct proc *p = curproc;
2368 struct trapframe *tf = p->p_md.md_regs;
2369 struct sigframe *fp, frame;
2370 register_t sp;
2371
2372 /*
2373 * Build the argument list for the signal handler.
2374 */
2375 bzero(&frame, sizeof(frame));
2376 frame.sf_signum = sig;
2377
2378 /*
2379 * Allocate space for the signal handler context.
2380 */
2381 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 &&
2382 !sigonstack(tf->tf_esp) && onstack)
2383 sp = trunc_page((vaddr_t)p->p_sigstk.ss_sp + p->p_sigstk.ss_size);
2384 else
2385 sp = tf->tf_esp;
2386
2387 frame.sf_sc.sc_fpstate = NULL;
2388 if (p->p_md.md_flags & MDP_USEDFPU) {
2389 npxsave_proc(p, 1);
2390 sp -= sizeof(union savefpu);
2391 sp &= ~0xf; /* for XMM regs */
2392 frame.sf_sc.sc_fpstate = (void *)sp;
2393 if (copyout(&p->p_addr->u_pcb.pcb_savefpu,
2394 (void *)sp, sizeof(union savefpu)))
2395 return 1;
2396
2397 /* Signal handlers get a completely clean FP state */
2398 p->p_md.md_flags &= ~MDP_USEDFPU;
2399 }
2400
2401 fp = (struct sigframe *)sp - 1;
2402 frame.sf_scp = &fp->sf_sc;
2403 frame.sf_sip = NULL;
2404 frame.sf_handler = catcher;
2405
2406 /*
2407 * Build the signal context to be used by sigreturn.
2408 */
2409 frame.sf_sc.sc_err = tf->tf_err;
2410 frame.sf_sc.sc_trapno = tf->tf_trapno;
2411 frame.sf_sc.sc_mask = mask;
2412 frame.sf_sc.sc_fs = tf->tf_fs;
2413 frame.sf_sc.sc_gs = tf->tf_gs;
2414 frame.sf_sc.sc_es = tf->tf_es;
2415 frame.sf_sc.sc_ds = tf->tf_ds;
2416 frame.sf_sc.sc_eflags = tf->tf_eflags;
2417 frame.sf_sc.sc_edi = tf->tf_edi;
2418 frame.sf_sc.sc_esi = tf->tf_esi;
2419 frame.sf_sc.sc_ebp = tf->tf_ebp;
2420 frame.sf_sc.sc_ebx = tf->tf_ebx;
2421 frame.sf_sc.sc_edx = tf->tf_edx;
2422 frame.sf_sc.sc_ecx = tf->tf_ecx;
2423 frame.sf_sc.sc_eax = tf->tf_eax;
2424 frame.sf_sc.sc_eip = tf->tf_eip;
2425 frame.sf_sc.sc_cs = tf->tf_cs;
2426 frame.sf_sc.sc_esp = tf->tf_esp;
2427 frame.sf_sc.sc_ss = tf->tf_ss;
2428
2429 if (info) {
2430 frame.sf_sip = &fp->sf_si;
2431 frame.sf_si = *ksip;
2432 }
2433
2434 /* XXX don't copyout siginfo if not needed? */
2435 frame.sf_sc.sc_cookie = (long)&fp->sf_sc ^ p->p_p->ps_sigcookie;
2436 if (copyout(&frame, fp, sizeof(frame)) != 0)
2437 return 1;
2438
2439 /*
2440 * Build context to run handler in.
2441 */
2442 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL);
2443 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL);
2444 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL);
2445 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL);
2446 tf->tf_eip = p->p_p->ps_sigcode;
2447 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL);
2448 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC);
2449 tf->tf_esp = (int)fp;
2450 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL);
2451
2452 return 0;
2453 }
2454
2455 /*
2456 * System call to cleanup state after a signal
2457 * has been taken. Reset signal mask and
2458 * stack state from context left by sendsig (above).
2459 * Return to previous pc and psl as specified by
2460 * context left by sendsig. Check carefully to
2461 * make sure that the user has not modified the
2462 * psl to gain improper privileges or to cause
2463 * a machine fault.
2464 */
2465 int
sys_sigreturn(struct proc * p,void * v,register_t * retval)2466 sys_sigreturn(struct proc *p, void *v, register_t *retval)
2467 {
2468 struct sys_sigreturn_args /* {
2469 syscallarg(struct sigcontext *) sigcntxp;
2470 } */ *uap = v;
2471 struct sigcontext ksc, *scp = SCARG(uap, sigcntxp);
2472 struct trapframe *tf = p->p_md.md_regs;
2473 int error;
2474
2475 if (PROC_PC(p) != p->p_p->ps_sigcoderet) {
2476 sigexit(p, SIGILL);
2477 return (EPERM);
2478 }
2479
2480 if ((error = copyin((caddr_t)scp, &ksc, sizeof(*scp))))
2481 return (error);
2482
2483 if (ksc.sc_cookie != ((long)scp ^ p->p_p->ps_sigcookie)) {
2484 sigexit(p, SIGILL);
2485 return (EFAULT);
2486 }
2487
2488 /* Prevent reuse of the sigcontext cookie */
2489 ksc.sc_cookie = 0;
2490 (void)copyout(&ksc.sc_cookie, (caddr_t)scp +
2491 offsetof(struct sigcontext, sc_cookie), sizeof (ksc.sc_cookie));
2492
2493 /*
2494 * Restore signal ksc.
2495 */
2496 /*
2497 * Check for security violations. If we're returning to
2498 * protected mode, the CPU will validate the segment registers
2499 * automatically and generate a trap on violations. We handle
2500 * the trap, rather than doing all of the checking here.
2501 */
2502 if (((ksc.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 ||
2503 !USERMODE(ksc.sc_cs, ksc.sc_eflags))
2504 return (EINVAL);
2505
2506 tf->tf_fs = ksc.sc_fs;
2507 tf->tf_gs = ksc.sc_gs;
2508 tf->tf_es = ksc.sc_es;
2509 tf->tf_ds = ksc.sc_ds;
2510 tf->tf_eflags = ksc.sc_eflags;
2511 tf->tf_edi = ksc.sc_edi;
2512 tf->tf_esi = ksc.sc_esi;
2513 tf->tf_ebp = ksc.sc_ebp;
2514 tf->tf_ebx = ksc.sc_ebx;
2515 tf->tf_edx = ksc.sc_edx;
2516 tf->tf_ecx = ksc.sc_ecx;
2517 tf->tf_eax = ksc.sc_eax;
2518 tf->tf_eip = ksc.sc_eip;
2519 tf->tf_cs = ksc.sc_cs;
2520 tf->tf_esp = ksc.sc_esp;
2521 tf->tf_ss = ksc.sc_ss;
2522
2523 if (p->p_md.md_flags & MDP_USEDFPU)
2524 npxsave_proc(p, 0);
2525
2526 if (ksc.sc_fpstate) {
2527 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu;
2528
2529 if ((error = copyin(ksc.sc_fpstate, sfp, sizeof(*sfp))))
2530 return (error);
2531 if (i386_use_fxsave)
2532 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask;
2533 p->p_md.md_flags |= MDP_USEDFPU;
2534 }
2535
2536 p->p_sigmask = ksc.sc_mask & ~sigcantmask;
2537
2538 return (EJUSTRETURN);
2539 }
2540
2541 #ifdef MULTIPROCESSOR
2542 /* force a CPU into the kernel, whether or not it's idle */
2543 void
cpu_kick(struct cpu_info * ci)2544 cpu_kick(struct cpu_info *ci)
2545 {
2546 /* only need to kick other CPUs */
2547 if (ci != curcpu()) {
2548 if (cpu_mwait_size > 0) {
2549 /*
2550 * If not idling, then send an IPI, else
2551 * just clear the "keep idling" bit.
2552 */
2553 if ((ci->ci_mwait & MWAIT_IN_IDLE) == 0)
2554 i386_send_ipi(ci, I386_IPI_NOP);
2555 else
2556 atomic_clearbits_int(&ci->ci_mwait,
2557 MWAIT_KEEP_IDLING);
2558 } else {
2559 /* no mwait, so need an IPI */
2560 i386_send_ipi(ci, I386_IPI_NOP);
2561 }
2562 }
2563 }
2564 #endif
2565
2566 /*
2567 * Notify the current process (p) that it has a signal pending,
2568 * process as soon as possible.
2569 */
2570 void
signotify(struct proc * p)2571 signotify(struct proc *p)
2572 {
2573 aston(p);
2574 cpu_kick(p->p_cpu);
2575 }
2576
2577 #ifdef MULTIPROCESSOR
2578 void
cpu_unidle(struct cpu_info * ci)2579 cpu_unidle(struct cpu_info *ci)
2580 {
2581 if (cpu_mwait_size > 0 && (ci->ci_mwait & MWAIT_ONLY)) {
2582 /*
2583 * Just clear the "keep idling" bit; if it wasn't
2584 * idling then we didn't need to do anything anyway.
2585 */
2586 atomic_clearbits_int(&ci->ci_mwait, MWAIT_KEEP_IDLING);
2587 return;
2588 }
2589
2590 if (ci != curcpu())
2591 i386_send_ipi(ci, I386_IPI_NOP);
2592 }
2593 #endif
2594
2595 int waittime = -1;
2596 struct pcb dumppcb;
2597
2598 __dead void
boot(int howto)2599 boot(int howto)
2600 {
2601 if ((howto & RB_POWERDOWN) != 0)
2602 lid_action = 0;
2603
2604 if ((howto & RB_RESET) != 0)
2605 goto doreset;
2606
2607 if (cold) {
2608 if ((howto & RB_USERREQ) == 0)
2609 howto |= RB_HALT;
2610 goto haltsys;
2611 }
2612
2613 boothowto = howto;
2614 if ((howto & RB_NOSYNC) == 0 && waittime < 0) {
2615 waittime = 0;
2616 vfs_shutdown(curproc);
2617
2618 if ((howto & RB_TIMEBAD) == 0) {
2619 resettodr();
2620 } else {
2621 printf("WARNING: not updating battery clock\n");
2622 }
2623 }
2624 if_downall();
2625
2626 uvm_shutdown();
2627 splhigh();
2628 cold = 1;
2629
2630 if ((howto & RB_DUMP) != 0)
2631 dumpsys();
2632
2633 haltsys:
2634 config_suspend_all(DVACT_POWERDOWN);
2635
2636 #ifdef MULTIPROCESSOR
2637 i386_broadcast_ipi(I386_IPI_HALT);
2638 #endif
2639
2640 if ((howto & RB_HALT) != 0) {
2641 #if NACPI > 0 && !defined(SMALL_KERNEL)
2642 extern int acpi_enabled;
2643
2644 if (acpi_enabled) {
2645 delay(500000);
2646 if ((howto & RB_POWERDOWN) != 0)
2647 acpi_powerdown();
2648 }
2649 #endif
2650
2651 #if NAPM > 0
2652 if ((howto & RB_POWERDOWN) != 0) {
2653 int rv;
2654
2655 printf("\nAttempting to power down...\n");
2656 /*
2657 * Turn off, if we can. But try to turn disk off and
2658 * wait a bit first--some disk drives are slow to
2659 * clean up and users have reported disk corruption.
2660 *
2661 * If apm_set_powstate() fails the first time, don't
2662 * try to turn the system off.
2663 */
2664 delay(500000);
2665 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF);
2666 delay(500000);
2667 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF);
2668 if (rv == 0 || rv == ENXIO) {
2669 delay(500000);
2670 (void) apm_set_powstate(APM_DEV_ALLDEVS,
2671 APM_SYS_OFF);
2672 }
2673 }
2674 #endif
2675 printf("\n");
2676 printf("The operating system has halted.\n");
2677 printf("Please press any key to reboot.\n\n");
2678 cnpollc(1); /* for proper keyboard command handling */
2679 cngetc();
2680 cnpollc(0);
2681 }
2682
2683 doreset:
2684 printf("rebooting...\n");
2685 cpu_reset();
2686 for (;;)
2687 continue;
2688 /* NOTREACHED */
2689 }
2690
2691 /*
2692 * This is called by configure to set dumplo and dumpsize.
2693 * Dumps always skip the first block of disk space
2694 * in case there might be a disk label stored there.
2695 * If there is extra space, put dump at the end to
2696 * reduce the chance that swapping trashes it.
2697 */
2698 void
dumpconf(void)2699 dumpconf(void)
2700 {
2701 int nblks; /* size of dump area */
2702 int i;
2703
2704 if (dumpdev == NODEV ||
2705 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0)
2706 return;
2707 if (nblks <= ctod(1))
2708 return;
2709
2710 /* Always skip the first block, in case there is a label there. */
2711 if (dumplo < ctod(1))
2712 dumplo = ctod(1);
2713
2714 for (i = 0; i < ndumpmem; i++)
2715 dumpsize = max(dumpsize, dumpmem[i].end);
2716
2717 /* Put dump at end of partition, and make it fit. */
2718 if (dumpsize > dtoc(nblks - dumplo - 1))
2719 dumpsize = dtoc(nblks - dumplo - 1);
2720 if (dumplo < nblks - ctod(dumpsize) - 1)
2721 dumplo = nblks - ctod(dumpsize) - 1;
2722 }
2723
2724 /*
2725 * cpu_dump: dump machine-dependent kernel core dump headers.
2726 */
2727 int
cpu_dump(void)2728 cpu_dump(void)
2729 {
2730 int (*dump)(dev_t, daddr_t, caddr_t, size_t);
2731 long buf[dbtob(1) / sizeof (long)];
2732 kcore_seg_t *segp;
2733
2734 dump = bdevsw[major(dumpdev)].d_dump;
2735
2736 segp = (kcore_seg_t *)buf;
2737
2738 /*
2739 * Generate a segment header.
2740 */
2741 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU);
2742 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp));
2743
2744 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1)));
2745 }
2746
2747 /*
2748 * Doadump comes here after turning off memory management and
2749 * getting on the dump stack, either when called above, or by
2750 * the auto-restart code.
2751 */
2752 static vaddr_t dumpspace;
2753
2754 vaddr_t
reserve_dumppages(vaddr_t p)2755 reserve_dumppages(vaddr_t p)
2756 {
2757
2758 dumpspace = p;
2759 return (p + PAGE_SIZE);
2760 }
2761
2762 void
dumpsys(void)2763 dumpsys(void)
2764 {
2765 u_int i, j, npg;
2766 int maddr;
2767 daddr_t blkno;
2768 int (*dump)(dev_t, daddr_t, caddr_t, size_t);
2769 int error;
2770 char *str;
2771 extern int msgbufmapped;
2772
2773 /* Save registers. */
2774 savectx(&dumppcb);
2775
2776 msgbufmapped = 0; /* don't record dump msgs in msgbuf */
2777 if (dumpdev == NODEV)
2778 return;
2779
2780 /*
2781 * For dumps during autoconfiguration,
2782 * if dump device has already configured...
2783 */
2784 if (dumpsize == 0)
2785 dumpconf();
2786 if (dumplo < 0)
2787 return;
2788 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo);
2789
2790 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev);
2791 printf("dump ");
2792 if (error == -1) {
2793 printf("area unavailable\n");
2794 return;
2795 }
2796
2797 #if 0 /* XXX this doesn't work. grr. */
2798 /* toss any characters present prior to dump */
2799 while (sget() != NULL); /*syscons and pccons differ */
2800 #endif
2801
2802 /* scan through the dumpmem list */
2803 dump = bdevsw[major(dumpdev)].d_dump;
2804 error = cpu_dump();
2805 for (i = 0; !error && i < ndumpmem; i++) {
2806
2807 npg = dumpmem[i].end - dumpmem[i].start;
2808 maddr = ptoa(dumpmem[i].start);
2809 blkno = dumplo + btodb(maddr) + 1;
2810 #if 0
2811 printf("(%d %lld %d) ", maddr, (long long)blkno, npg);
2812 #endif
2813 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) {
2814
2815 /* Print out how many MBs we have more to go. */
2816 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG)
2817 printf("%ld ",
2818 (ptoa(dumpsize) - maddr) / (1024 * 1024));
2819 #if 0
2820 printf("(%x %lld) ", maddr, (long long)blkno);
2821 #endif
2822 pmap_enter(pmap_kernel(), dumpspace, maddr,
2823 PROT_READ, PMAP_WIRED);
2824 if ((error = (*dump)(dumpdev, blkno,
2825 (caddr_t)dumpspace, NBPG)))
2826 break;
2827
2828 #if 0 /* XXX this doesn't work. grr. */
2829 /* operator aborting dump? */
2830 if (sget() != NULL) {
2831 error = EINTR;
2832 break;
2833 }
2834 #endif
2835 }
2836 }
2837
2838 switch (error) {
2839
2840 case 0: str = "succeeded\n\n"; break;
2841 case ENXIO: str = "device bad\n\n"; break;
2842 case EFAULT: str = "device not ready\n\n"; break;
2843 case EINVAL: str = "area improper\n\n"; break;
2844 case EIO: str = "i/o error\n\n"; break;
2845 case EINTR: str = "aborted from console\n\n"; break;
2846 default: str = "error %d\n\n"; break;
2847 }
2848 printf(str, error);
2849
2850 delay(5000000); /* 5 seconds */
2851 }
2852
2853 /*
2854 * Clear registers on exec
2855 */
2856 void
setregs(struct proc * p,struct exec_package * pack,u_long stack,struct ps_strings * arginfo)2857 setregs(struct proc *p, struct exec_package *pack, u_long stack,
2858 struct ps_strings *arginfo)
2859 {
2860 struct pcb *pcb = &p->p_addr->u_pcb;
2861 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map);
2862 struct trapframe *tf = p->p_md.md_regs;
2863
2864 #if NNPX > 0
2865 /* If we were using the FPU, forget about it. */
2866 if (pcb->pcb_fpcpu != NULL)
2867 npxsave_proc(p, 0);
2868 p->p_md.md_flags &= ~MDP_USEDFPU;
2869 #endif
2870
2871 initcodesegment(&pmap->pm_codeseg);
2872 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0,
2873 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1);
2874 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0,
2875 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1);
2876
2877 /*
2878 * And update the GDT since we return to the user process
2879 * by leaving the syscall (we don't do another pmap_activate()).
2880 */
2881 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg;
2882 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS];
2883 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS];
2884
2885 /*
2886 * And reset the hiexec marker in the pmap.
2887 */
2888 pmap->pm_hiexec = 0;
2889
2890 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL);
2891 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL);
2892 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL);
2893 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL);
2894 tf->tf_edi = 0;
2895 tf->tf_esi = 0;
2896 tf->tf_ebp = 0;
2897 tf->tf_ebx = (int)p->p_p->ps_strings;
2898 tf->tf_edx = 0;
2899 tf->tf_ecx = 0;
2900 tf->tf_eax = 0;
2901 tf->tf_eip = pack->ep_entry;
2902 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL);
2903 tf->tf_eflags = PSL_USERSET;
2904 tf->tf_esp = stack;
2905 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL);
2906 }
2907
2908 /*
2909 * Initialize segments and descriptor tables
2910 */
2911
2912 /* IDT is now a full page, so we can map it in u-k */
2913 union {
2914 struct gate_descriptor idt[NIDT];
2915 char align[PAGE_SIZE];
2916 } _idt_region __aligned(PAGE_SIZE);
2917 #define idt_region _idt_region.idt
2918 struct gate_descriptor *idt = idt_region;
2919
2920 extern struct user *proc0paddr;
2921
2922 void
setgate(struct gate_descriptor * gd,void * func,int args,int type,int dpl,int seg)2923 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl,
2924 int seg)
2925 {
2926
2927 gd->gd_looffset = (int)func;
2928 gd->gd_selector = GSEL(seg, SEL_KPL);
2929 gd->gd_stkcpy = args;
2930 gd->gd_xx = 0;
2931 gd->gd_type = type;
2932 gd->gd_dpl = dpl;
2933 gd->gd_p = 1;
2934 gd->gd_hioffset = (int)func >> 16;
2935 }
2936
2937 void
unsetgate(struct gate_descriptor * gd)2938 unsetgate(struct gate_descriptor *gd)
2939 {
2940 gd->gd_p = 0;
2941 gd->gd_hioffset = 0;
2942 gd->gd_looffset = 0;
2943 gd->gd_selector = 0;
2944 gd->gd_xx = 0;
2945 gd->gd_stkcpy = 0;
2946 gd->gd_type = 0;
2947 gd->gd_dpl = 0;
2948 }
2949
2950 void
setregion(struct region_descriptor * rd,void * base,size_t limit)2951 setregion(struct region_descriptor *rd, void *base, size_t limit)
2952 {
2953 rd->rd_limit = (int)limit;
2954 rd->rd_base = (int)base;
2955 }
2956
2957 void
initcodesegment(struct segment_descriptor * cs)2958 initcodesegment(struct segment_descriptor *cs)
2959 {
2960 if (cpu_pae) {
2961 /*
2962 * When code execution is managed using NX feature
2963 * in pmapae.c, GUCODE_SEL should cover userland.
2964 */
2965 setsegment(cs, 0, atop(VM_MAXUSER_ADDRESS - 1),
2966 SDT_MEMERA, SEL_UPL, 1, 1);
2967 } else {
2968 /*
2969 * For pmap.c's non-PAE/NX line-in-the-sand execution, reset
2970 * the code segment limit to I386_MAX_EXE_ADDR in the pmap;
2971 * this gets copied into the GDT for GUCODE_SEL by
2972 * pmap_activate(). Similarly, reset the base of each of
2973 * the two thread data segments to zero in the pcb; they'll
2974 * get copied into the GDT for GUFS_SEL and GUGS_SEL.
2975 */
2976 setsegment(cs, 0, atop(I386_MAX_EXE_ADDR - 1),
2977 SDT_MEMERA, SEL_UPL, 1, 1);
2978 }
2979 }
2980
2981 void
setsegment(struct segment_descriptor * sd,void * base,size_t limit,int type,int dpl,int def32,int gran)2982 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type,
2983 int dpl, int def32, int gran)
2984 {
2985
2986 sd->sd_lolimit = (int)limit;
2987 sd->sd_lobase = (int)base;
2988 sd->sd_type = type;
2989 sd->sd_dpl = dpl;
2990 sd->sd_p = 1;
2991 sd->sd_hilimit = (int)limit >> 16;
2992 sd->sd_xx = 0;
2993 sd->sd_def32 = def32;
2994 sd->sd_gran = gran;
2995 sd->sd_hibase = (int)base >> 24;
2996 }
2997
2998 #define IDTVEC(name) __CONCAT(X, name)
2999 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
3000 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm),
3001 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page),
3002 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk),
3003 IDTVEC(simd);
3004
3005 extern int IDTVEC(f00f_redirect);
3006
3007 int cpu_f00f_bug = 0;
3008
3009 void
fix_f00f(void)3010 fix_f00f(void)
3011 {
3012 struct region_descriptor region;
3013 vaddr_t va;
3014 paddr_t pa;
3015 void *p;
3016
3017 /* Allocate two new pages */
3018 va = (vaddr_t)km_alloc(NBPG*2, &kv_any, &kp_zero, &kd_waitok);
3019 p = (void *)(va + NBPG - 7*sizeof(*idt));
3020
3021 /* Copy over old IDT */
3022 bcopy(idt, p, sizeof(idt_region));
3023 idt = p;
3024
3025 /* Fix up paging redirect */
3026 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386IGT, SEL_KPL,
3027 GCODE_SEL);
3028
3029 /* Map first page RO */
3030 pmap_pte_setbits(va, 0, PG_RW);
3031
3032 /* add k-u read-only mappings XXX old IDT stays in place */
3033 /* XXX hshoexer: are f00f affected CPUs affected by meltdown? */
3034 pmap_extract(pmap_kernel(), va, &pa);
3035 pmap_enter_special(va, pa, PROT_READ, 0);
3036 pmap_extract(pmap_kernel(), va + PAGE_SIZE, &pa);
3037 pmap_enter_special(va + PAGE_SIZE, pa, PROT_READ, 0);
3038
3039 /* Reload idtr */
3040 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1);
3041 lidt(®ion);
3042
3043 /* Tell the rest of the world */
3044 cpu_f00f_bug = 1;
3045 }
3046
3047 #ifdef MULTIPROCESSOR
3048 void
cpu_init_idt(void)3049 cpu_init_idt(void)
3050 {
3051 struct region_descriptor region;
3052 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1);
3053 lidt(®ion);
3054 }
3055 #endif /* MULTIPROCESSOR */
3056
3057 void
init386(paddr_t first_avail)3058 init386(paddr_t first_avail)
3059 {
3060 int i, kb;
3061 struct region_descriptor region;
3062 bios_memmap_t *im;
3063
3064 proc0.p_addr = proc0paddr;
3065 cpu_info_primary.ci_self = &cpu_info_primary;
3066 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb;
3067 cpu_info_primary.ci_tss = &cpu_info_full_primary.cif_tss;
3068 cpu_info_primary.ci_nmi_tss = &cpu_info_full_primary.cif_nmi_tss;
3069 cpu_info_primary.ci_gdt = (void *)&cpu_info_full_primary.cif_gdt;
3070
3071 /* make bootstrap gdt gates and memory segments */
3072 setsegment(&cpu_info_primary.ci_gdt[GCODE_SEL].sd, 0, 0xfffff,
3073 SDT_MEMERA, SEL_KPL, 1, 1);
3074 setsegment(&cpu_info_primary.ci_gdt[GICODE_SEL].sd, 0, 0xfffff,
3075 SDT_MEMERA, SEL_KPL, 1, 1);
3076 setsegment(&cpu_info_primary.ci_gdt[GDATA_SEL].sd, 0, 0xfffff,
3077 SDT_MEMRWA, SEL_KPL, 1, 1);
3078 setsegment(&cpu_info_primary.ci_gdt[GUCODE_SEL].sd, 0,
3079 atop(I386_MAX_EXE_ADDR) - 1, SDT_MEMERA, SEL_UPL, 1, 1);
3080 setsegment(&cpu_info_primary.ci_gdt[GUDATA_SEL].sd, 0,
3081 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1);
3082 setsegment(&cpu_info_primary.ci_gdt[GCPU_SEL].sd, &cpu_info_primary,
3083 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0);
3084 setsegment(&cpu_info_primary.ci_gdt[GUFS_SEL].sd, 0,
3085 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1);
3086 setsegment(&cpu_info_primary.ci_gdt[GUGS_SEL].sd, 0,
3087 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1);
3088 setsegment(&cpu_info_primary.ci_gdt[GTSS_SEL].sd,
3089 cpu_info_primary.ci_tss, sizeof(struct i386tss)-1,
3090 SDT_SYS386TSS, SEL_KPL, 0, 0);
3091 setsegment(&cpu_info_primary.ci_gdt[GNMITSS_SEL].sd,
3092 cpu_info_primary.ci_nmi_tss, sizeof(struct i386tss)-1,
3093 SDT_SYS386TSS, SEL_KPL, 0, 0);
3094
3095 /* exceptions */
3096 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3097 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3098 setgate(&idt[ 2], NULL, 0, SDT_SYSTASKGT, SEL_KPL, GNMITSS_SEL);
3099 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL);
3100 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL);
3101 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3102 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3103 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3104 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3105 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3106 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3107 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3108 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3109 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3110 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3111 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3112 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3113 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3114 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3115 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3116 for (i = 20; i < NRSVIDT; i++)
3117 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);
3118 for (i = NRSVIDT; i < NIDT; i++)
3119 unsetgate(&idt[i]);
3120 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL);
3121
3122 setregion(®ion, cpu_info_primary.ci_gdt, GDT_SIZE - 1);
3123 lgdt(®ion);
3124 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1);
3125 lidt(®ion);
3126
3127 /*
3128 * Initialize the I/O port and I/O mem extent maps.
3129 * Note: we don't have to check the return value since
3130 * creation of a fixed extent map will never fail (since
3131 * descriptor storage has already been allocated).
3132 *
3133 * N.B. The iomem extent manages _all_ physical addresses
3134 * on the machine. When the amount of RAM is found, the two
3135 * extents of RAM are allocated from the map (0 -> ISA hole
3136 * and end of ISA hole -> end of RAM).
3137 */
3138 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF,
3139 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage),
3140 EX_NOCOALESCE|EX_NOWAIT);
3141 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF,
3142 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage),
3143 EX_NOCOALESCE|EX_NOWAIT);
3144
3145 #if NISA > 0
3146 isa_defaultirq();
3147 #endif
3148
3149 /*
3150 * Attach the glass console early in case we need to display a panic.
3151 */
3152 cninit();
3153
3154 /*
3155 * Saving SSE registers won't work if the save area isn't
3156 * 16-byte aligned.
3157 */
3158 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf)
3159 panic("init386: pcb_savefpu not 16-byte aligned");
3160
3161 /* call pmap initialization to make new kernel address space */
3162 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE);
3163
3164 /*
3165 * Boot arguments are in a single page specified by /boot.
3166 *
3167 * We require the "new" vector form, as well as memory ranges
3168 * to be given in bytes rather than KB.
3169 */
3170 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) ==
3171 (BAPIV_VECTOR | BAPIV_BMEMMAP)) {
3172 if (bootargc > NBPG)
3173 panic("too many boot args");
3174
3175 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc,
3176 EX_NOWAIT))
3177 panic("cannot reserve /boot args memory");
3178
3179 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv,
3180 PROT_READ | PROT_WRITE,
3181 PROT_READ | PROT_WRITE | PMAP_WIRED);
3182
3183 bios_getopt();
3184
3185 } else
3186 panic("/boot too old: upgrade!");
3187
3188 #ifdef DIAGNOSTIC
3189 if (bios_memmap == NULL)
3190 panic("no BIOS memory map supplied");
3191 #endif
3192
3193 /*
3194 * account all the memory passed in the map from /boot
3195 * calculate avail_end and count the physmem.
3196 */
3197 avail_end = 0;
3198 physmem = 0;
3199 #ifdef DEBUG
3200 printf("memmap:");
3201 #endif
3202 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++)
3203 if (im->type == BIOS_MAP_FREE) {
3204 paddr_t a, e;
3205 #ifdef DEBUG
3206 printf(" %llx-%llx", im->addr, im->addr + im->size);
3207 #endif
3208
3209 if (im->addr >= 0x100000000ULL) {
3210 #ifdef DEBUG
3211 printf("-H");
3212 #endif
3213 continue;
3214 }
3215
3216 a = round_page(im->addr);
3217 if (im->addr + im->size <= 0xfffff000ULL)
3218 e = trunc_page(im->addr + im->size);
3219 else {
3220 #ifdef DEBUG
3221 printf("-T");
3222 #endif
3223 e = 0xfffff000;
3224 }
3225
3226 /* skip first 16 pages due to SMI corruption */
3227 if (a < 16 * NBPG)
3228 a = 16 * NBPG;
3229
3230 #ifdef MULTIPROCESSOR
3231 /* skip MP trampoline code page */
3232 if (a < MP_TRAMPOLINE + NBPG)
3233 a = MP_TRAMPOLINE + NBPG;
3234
3235 /* skip MP trampoline data page */
3236 if (a < MP_TRAMP_DATA + NBPG)
3237 a = MP_TRAMP_DATA + NBPG;
3238 #endif /* MULTIPROCESSOR */
3239
3240 #if NACPI > 0 && !defined(SMALL_KERNEL)
3241 /* skip ACPI resume trampoline code page */
3242 if (a < ACPI_TRAMPOLINE + NBPG)
3243 a = ACPI_TRAMPOLINE + NBPG;
3244
3245 /* skip ACPI resume trampoline data page */
3246 if (a < ACPI_TRAMP_DATA + NBPG)
3247 a = ACPI_TRAMP_DATA + NBPG;
3248 #endif /* ACPI */
3249
3250 #ifdef HIBERNATE
3251 /* skip hibernate reserved pages */
3252 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE)
3253 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE;
3254 #endif /* HIBERNATE */
3255
3256 /* skip shorter than page regions */
3257 if (a >= e || (e - a) < NBPG) {
3258 #ifdef DEBUG
3259 printf("-S");
3260 #endif
3261 continue;
3262 }
3263
3264 /*
3265 * XXX Some buggy ACPI BIOSes use memory that
3266 * they declare as free. Current worst offender
3267 * is Supermicro 5019D-FTN4. Typically the
3268 * affected memory areas are small blocks
3269 * between areas reserved for ACPI and other
3270 * BIOS goo. So skip areas smaller than 32 MB
3271 * above the 16 MB boundary (to avoid
3272 * affecting legacy stuff).
3273 */
3274 if (a > 16*1024*1024 && (e - a) < 32*1024*1024) {
3275 #ifdef DEBUG
3276 printf("-X");
3277 #endif
3278 continue;
3279 }
3280
3281 /* skip legacy IO region */
3282 if ((a > IOM_BEGIN && a < IOM_END) ||
3283 (e > IOM_BEGIN && e < IOM_END)) {
3284 #ifdef DEBUG
3285 printf("-I");
3286 #endif
3287 continue;
3288 }
3289
3290 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT))
3291 /* XXX What should we do? */
3292 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)"
3293 " FROM IOMEM EXTENT MAP!\n", a, e);
3294
3295 physmem += atop(e - a);
3296 dumpmem[i].start = atop(a);
3297 dumpmem[i].end = atop(e);
3298 i++;
3299 avail_end = max(avail_end, e);
3300 }
3301
3302 ndumpmem = i;
3303 avail_end -= round_page(MSGBUFSIZE);
3304
3305 #ifdef DEBUG
3306 printf(": %lx\n", avail_end);
3307 #endif
3308 if (physmem < atop(4 * 1024 * 1024)) {
3309 printf("\awarning: too little memory available;"
3310 "running in degraded mode\npress a key to confirm\n\n");
3311 cnpollc(1);
3312 cngetc();
3313 cnpollc(0);
3314 }
3315
3316 #ifdef DEBUG
3317 printf("physload: ");
3318 #endif
3319 kb = atop(KERNTEXTOFF - KERNBASE);
3320 if (kb > atop(IOM_END)) {
3321 paddr_t lim = atop(IOM_END);
3322 #ifdef DEBUG
3323 printf(" %lx-%x (<16M)", lim, kb);
3324 #endif
3325 uvm_page_physload(lim, kb, lim, kb, 0);
3326 }
3327
3328 for (i = 0; i < ndumpmem; i++) {
3329 paddr_t a, e;
3330
3331 a = dumpmem[i].start;
3332 e = dumpmem[i].end;
3333 if (a < atop(first_avail) && e > atop(first_avail))
3334 a = atop(first_avail);
3335 if (e > atop(avail_end))
3336 e = atop(avail_end);
3337
3338 if (a < e) {
3339 #ifdef DEBUG
3340 printf(" %lx-%lx", a, e);
3341 #endif
3342 uvm_page_physload(a, e, a, e, 0);
3343 }
3344 }
3345 #ifdef DEBUG
3346 printf("\n");
3347 #endif
3348
3349 tlbflush();
3350 #if 0
3351 #if NISADMA > 0
3352 /*
3353 * Some motherboards/BIOSes remap the 384K of RAM that would
3354 * normally be covered by the ISA hole to the end of memory
3355 * so that it can be used. However, on a 16M system, this
3356 * would cause bounce buffers to be allocated and used.
3357 * This is not desirable behaviour, as more than 384K of
3358 * bounce buffers might be allocated. As a work-around,
3359 * we round memory down to the nearest 1M boundary if
3360 * we're using any isadma devices and the remapped memory
3361 * is what puts us over 16M.
3362 */
3363 if (extmem > (15*1024) && extmem < (16*1024)) {
3364 printf("Warning: ignoring %dk of remapped memory\n",
3365 extmem - (15*1024));
3366 extmem = (15*1024);
3367 }
3368 #endif
3369 #endif
3370
3371 #ifdef DDB
3372 db_machine_init();
3373 ddb_init();
3374 if (boothowto & RB_KDB)
3375 db_enter();
3376 #endif
3377
3378 softintr_init();
3379 }
3380
3381 /*
3382 * consinit:
3383 * initialize the system console.
3384 */
3385 void
consinit(void)3386 consinit(void)
3387 {
3388 /* Already done in init386(). */
3389 }
3390
3391 void
cpu_reset(void)3392 cpu_reset(void)
3393 {
3394 struct region_descriptor region;
3395
3396 intr_disable();
3397
3398 if (cpuresetfn)
3399 (*cpuresetfn)();
3400
3401 /*
3402 * The keyboard controller has 4 random output pins, one of which is
3403 * connected to the RESET pin on the CPU in many PCs. We tell the
3404 * keyboard controller to pulse this line a couple of times.
3405 */
3406 outb(IO_KBD + KBCMDP, KBC_PULSE0);
3407 delay(100000);
3408 outb(IO_KBD + KBCMDP, KBC_PULSE0);
3409 delay(100000);
3410
3411 /*
3412 * Try to cause a triple fault and watchdog reset by setting the
3413 * IDT to point to nothing.
3414 */
3415 bzero((caddr_t)idt, sizeof(idt_region));
3416 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1);
3417 lidt(®ion);
3418 __asm volatile("divl %0,%1" : : "q" (0), "a" (0));
3419
3420 /*
3421 * Try to cause a triple fault and watchdog reset by unmapping the
3422 * entire address space.
3423 */
3424 bzero((caddr_t)PTD, NBPG);
3425 tlbflush();
3426
3427 for (;;)
3428 continue;
3429 /* NOTREACHED */
3430 }
3431
3432 void
cpu_initclocks(void)3433 cpu_initclocks(void)
3434 {
3435 (*initclock_func)(); /* lapic or i8254 */
3436 }
3437
3438 void
cpu_startclock(void)3439 cpu_startclock(void)
3440 {
3441 (*startclock_func)();
3442 }
3443
3444 void
need_resched(struct cpu_info * ci)3445 need_resched(struct cpu_info *ci)
3446 {
3447 ci->ci_want_resched = 1;
3448
3449 /* There's a risk we'll be called before the idle threads start */
3450 if (ci->ci_curproc) {
3451 aston(ci->ci_curproc);
3452 cpu_kick(ci);
3453 }
3454 }
3455
3456 /* Allocate an IDT vector slot within the given range.
3457 * XXX needs locking to avoid MP allocation races.
3458 */
3459
3460 int
idt_vec_alloc(int low,int high)3461 idt_vec_alloc(int low, int high)
3462 {
3463 int vec;
3464
3465 for (vec = low; vec <= high; vec++)
3466 if (idt[vec].gd_p == 0)
3467 return (vec);
3468 return (0);
3469 }
3470
3471 void
idt_vec_set(int vec,void (* function)(void))3472 idt_vec_set(int vec, void (*function)(void))
3473 {
3474 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL);
3475 }
3476
3477 void
idt_vec_free(int vec)3478 idt_vec_free(int vec)
3479 {
3480 unsetgate(&idt[vec]);
3481 }
3482
3483 const struct sysctl_bounded_args cpuctl_vars[] = {
3484 { CPU_LIDACTION, &lid_action, 0, 2 },
3485 { CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY },
3486 { CPU_OSFXSR, &i386_use_fxsave, SYSCTL_INT_READONLY },
3487 { CPU_SSE, &i386_has_sse, SYSCTL_INT_READONLY },
3488 { CPU_SSE2, &i386_has_sse2, SYSCTL_INT_READONLY },
3489 { CPU_XCRYPT, &i386_has_xcrypt, SYSCTL_INT_READONLY },
3490 };
3491
3492 /*
3493 * machine dependent system variables.
3494 */
3495 int
cpu_sysctl(int * name,u_int namelen,void * oldp,size_t * oldlenp,void * newp,size_t newlen,struct proc * p)3496 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,
3497 size_t newlen, struct proc *p)
3498 {
3499 dev_t dev;
3500
3501 switch (name[0]) {
3502 case CPU_CONSDEV:
3503 if (namelen != 1)
3504 return (ENOTDIR); /* overloaded */
3505
3506 if (cn_tab != NULL)
3507 dev = cn_tab->cn_dev;
3508 else
3509 dev = NODEV;
3510 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev));
3511 #if NBIOS > 0
3512 case CPU_BIOS:
3513 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp,
3514 newp, newlen, p);
3515 #endif
3516 case CPU_BLK2CHR:
3517 if (namelen != 2)
3518 return (ENOTDIR); /* overloaded */
3519 dev = blktochr((dev_t)name[1]);
3520 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev));
3521 case CPU_CHR2BLK:
3522 if (namelen != 2)
3523 return (ENOTDIR); /* overloaded */
3524 dev = chrtoblk((dev_t)name[1]);
3525 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev));
3526 case CPU_ALLOWAPERTURE:
3527 #ifdef APERTURE
3528 if (securelevel > 0)
3529 return (sysctl_int_lower(oldp, oldlenp, newp, newlen,
3530 &allowaperture));
3531 else
3532 return (sysctl_int(oldp, oldlenp, newp, newlen,
3533 &allowaperture));
3534 #else
3535 return (sysctl_rdint(oldp, oldlenp, newp, 0));
3536 #endif
3537 case CPU_CPUVENDOR:
3538 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor));
3539 case CPU_CPUFEATURE:
3540 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags));
3541 case CPU_KBDRESET:
3542 return (sysctl_securelevel_int(oldp, oldlenp, newp, newlen,
3543 &kbd_reset));
3544 #if NPCKBC > 0 && NUKBD > 0
3545 case CPU_FORCEUKBD:
3546 {
3547 int error;
3548
3549 if (forceukbd)
3550 return (sysctl_rdint(oldp, oldlenp, newp, forceukbd));
3551
3552 error = sysctl_int(oldp, oldlenp, newp, newlen, &forceukbd);
3553 if (forceukbd)
3554 pckbc_release_console();
3555 return (error);
3556 }
3557 #endif
3558 default:
3559 return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars),
3560 name, namelen, oldp, oldlenp, newp, newlen));
3561 }
3562 /* NOTREACHED */
3563 }
3564
3565 int
bus_space_map(bus_space_tag_t t,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)3566 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags,
3567 bus_space_handle_t *bshp)
3568 {
3569 int error;
3570 struct extent *ex;
3571
3572 /*
3573 * Pick the appropriate extent map.
3574 */
3575 if (t == I386_BUS_SPACE_IO) {
3576 ex = ioport_ex;
3577 if (flags & BUS_SPACE_MAP_LINEAR)
3578 return (EINVAL);
3579 } else if (t == I386_BUS_SPACE_MEM) {
3580 ex = iomem_ex;
3581 } else {
3582 panic("bus_space_map: bad bus space tag");
3583 }
3584
3585 /*
3586 * Before we go any further, let's make sure that this
3587 * region is available.
3588 */
3589 error = extent_alloc_region(ex, bpa, size,
3590 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
3591 if (error)
3592 return (error);
3593
3594 /*
3595 * For I/O space, that's all she wrote.
3596 */
3597 if (t == I386_BUS_SPACE_IO) {
3598 *bshp = bpa;
3599 return (0);
3600 }
3601
3602 if (IOM_BEGIN <= bpa && bpa <= IOM_END) {
3603 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa);
3604 return (0);
3605 }
3606
3607 /*
3608 * For memory space, map the bus physical address to
3609 * a kernel virtual address.
3610 */
3611 error = bus_mem_add_mapping(bpa, size, flags, bshp);
3612 if (error) {
3613 if (extent_free(ex, bpa, size, EX_NOWAIT |
3614 (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
3615 printf("bus_space_map: pa 0x%lx, size 0x%lx\n",
3616 bpa, size);
3617 printf("bus_space_map: can't free region\n");
3618 }
3619 }
3620
3621 return (error);
3622 }
3623
3624 int
_bus_space_map(bus_space_tag_t t,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)3625 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
3626 int flags, bus_space_handle_t *bshp)
3627 {
3628 /*
3629 * For I/O space, that's all she wrote.
3630 */
3631 if (t == I386_BUS_SPACE_IO) {
3632 *bshp = bpa;
3633 return (0);
3634 }
3635
3636 /*
3637 * For memory space, map the bus physical address to
3638 * a kernel virtual address.
3639 */
3640 return (bus_mem_add_mapping(bpa, size, flags, bshp));
3641 }
3642
3643 int
bus_space_alloc(bus_space_tag_t t,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t alignment,bus_size_t boundary,int flags,bus_addr_t * bpap,bus_space_handle_t * bshp)3644 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend,
3645 bus_size_t size, bus_size_t alignment, bus_size_t boundary,
3646 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp)
3647 {
3648 struct extent *ex;
3649 u_long bpa;
3650 int error;
3651
3652 /*
3653 * Pick the appropriate extent map.
3654 */
3655 if (t == I386_BUS_SPACE_IO) {
3656 ex = ioport_ex;
3657 } else if (t == I386_BUS_SPACE_MEM) {
3658 ex = iomem_ex;
3659 } else {
3660 panic("bus_space_alloc: bad bus space tag");
3661 }
3662
3663 /*
3664 * Sanity check the allocation against the extent's boundaries.
3665 */
3666 if (rstart < ex->ex_start || rend > ex->ex_end)
3667 panic("bus_space_alloc: bad region start/end");
3668
3669 /*
3670 * Do the requested allocation.
3671 */
3672 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0,
3673 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0),
3674 &bpa);
3675
3676 if (error)
3677 return (error);
3678
3679 /*
3680 * For I/O space, that's all she wrote.
3681 */
3682 if (t == I386_BUS_SPACE_IO) {
3683 *bshp = *bpap = bpa;
3684 return (0);
3685 }
3686
3687 /*
3688 * For memory space, map the bus physical address to
3689 * a kernel virtual address.
3690 */
3691 error = bus_mem_add_mapping(bpa, size, flags, bshp);
3692 if (error) {
3693 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT |
3694 (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
3695 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n",
3696 bpa, size);
3697 printf("bus_space_alloc: can't free region\n");
3698 }
3699 }
3700
3701 *bpap = bpa;
3702
3703 return (error);
3704 }
3705
3706 int
bus_mem_add_mapping(bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)3707 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags,
3708 bus_space_handle_t *bshp)
3709 {
3710 paddr_t pa, endpa;
3711 vaddr_t va;
3712 bus_size_t map_size;
3713 int pmap_flags = PMAP_NOCACHE;
3714
3715 pa = trunc_page(bpa);
3716 endpa = round_page(bpa + size);
3717
3718 #ifdef DIAGNOSTIC
3719 if (endpa <= pa && endpa != 0)
3720 panic("bus_mem_add_mapping: overflow");
3721 #endif
3722
3723 map_size = endpa - pa;
3724
3725 va = (vaddr_t)km_alloc(map_size, &kv_any, &kp_none, &kd_nowait);
3726 if (va == 0)
3727 return (ENOMEM);
3728
3729 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
3730
3731 if (flags & BUS_SPACE_MAP_CACHEABLE)
3732 pmap_flags = 0;
3733 else if (flags & BUS_SPACE_MAP_PREFETCHABLE)
3734 pmap_flags = PMAP_WC;
3735
3736 for (; map_size > 0;
3737 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE)
3738 pmap_kenter_pa(va, pa | pmap_flags,
3739 PROT_READ | PROT_WRITE);
3740 pmap_update(pmap_kernel());
3741
3742 return 0;
3743 }
3744
3745 void
bus_space_unmap(bus_space_tag_t t,bus_space_handle_t bsh,bus_size_t size)3746 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
3747 {
3748 struct extent *ex;
3749 u_long va, endva;
3750 bus_addr_t bpa;
3751
3752 /*
3753 * Find the correct extent and bus physical address.
3754 */
3755 if (t == I386_BUS_SPACE_IO) {
3756 ex = ioport_ex;
3757 bpa = bsh;
3758 } else if (t == I386_BUS_SPACE_MEM) {
3759 ex = iomem_ex;
3760 bpa = (bus_addr_t)ISA_PHYSADDR(bsh);
3761 if (IOM_BEGIN <= bpa && bpa <= IOM_END)
3762 goto ok;
3763
3764 va = trunc_page(bsh);
3765 endva = round_page(bsh + size);
3766
3767 #ifdef DIAGNOSTIC
3768 if (endva <= va)
3769 panic("bus_space_unmap: overflow");
3770 #endif
3771
3772 (void) pmap_extract(pmap_kernel(), va, &bpa);
3773 bpa += (bsh & PGOFSET);
3774
3775 pmap_kremove(va, endva - va);
3776 pmap_update(pmap_kernel());
3777
3778 /*
3779 * Free the kernel virtual mapping.
3780 */
3781 km_free((void *)va, endva - va, &kv_any, &kp_none);
3782 } else
3783 panic("bus_space_unmap: bad bus space tag");
3784
3785 ok:
3786 if (extent_free(ex, bpa, size,
3787 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
3788 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n",
3789 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size);
3790 printf("bus_space_unmap: can't free region\n");
3791 }
3792 }
3793
3794 void
_bus_space_unmap(bus_space_tag_t t,bus_space_handle_t bsh,bus_size_t size,bus_addr_t * adrp)3795 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size,
3796 bus_addr_t *adrp)
3797 {
3798 u_long va, endva;
3799 bus_addr_t bpa;
3800
3801 /*
3802 * Find the correct bus physical address.
3803 */
3804 if (t == I386_BUS_SPACE_IO) {
3805 bpa = bsh;
3806 } else if (t == I386_BUS_SPACE_MEM) {
3807 bpa = (bus_addr_t)ISA_PHYSADDR(bsh);
3808 if (IOM_BEGIN <= bpa && bpa <= IOM_END)
3809 goto ok;
3810
3811 va = trunc_page(bsh);
3812 endva = round_page(bsh + size);
3813
3814 #ifdef DIAGNOSTIC
3815 if (endva <= va)
3816 panic("_bus_space_unmap: overflow");
3817 #endif
3818
3819 (void) pmap_extract(pmap_kernel(), va, &bpa);
3820 bpa += (bsh & PGOFSET);
3821
3822 pmap_kremove(va, endva - va);
3823 pmap_update(pmap_kernel());
3824
3825 /*
3826 * Free the kernel virtual mapping.
3827 */
3828 km_free((void *)va, endva - va, &kv_any, &kp_none);
3829 } else
3830 panic("bus_space_unmap: bad bus space tag");
3831
3832 ok:
3833 if (adrp != NULL)
3834 *adrp = bpa;
3835 }
3836
3837 void
bus_space_free(bus_space_tag_t t,bus_space_handle_t bsh,bus_size_t size)3838 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
3839 {
3840
3841 /* bus_space_unmap() does all that we need to do. */
3842 bus_space_unmap(t, bsh, size);
3843 }
3844
3845 int
bus_space_subregion(bus_space_tag_t t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t size,bus_space_handle_t * nbshp)3846 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
3847 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
3848 {
3849 *nbshp = bsh + offset;
3850 return (0);
3851 }
3852
3853 paddr_t
bus_space_mmap(bus_space_tag_t t,bus_addr_t addr,off_t off,int prot,int flags)3854 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags)
3855 {
3856 /* Can't mmap I/O space. */
3857 if (t == I386_BUS_SPACE_IO)
3858 return (-1);
3859
3860 return (addr + off);
3861 }
3862
3863 #ifdef DIAGNOSTIC
3864 void
splassert_check(int wantipl,const char * func)3865 splassert_check(int wantipl, const char *func)
3866 {
3867 if (lapic_tpr < wantipl)
3868 splassert_fail(wantipl, lapic_tpr, func);
3869 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0)
3870 splassert_fail(-1, curcpu()->ci_idepth, func);
3871 }
3872 #endif
3873
3874 int
copyin32(const uint32_t * uaddr,uint32_t * kaddr)3875 copyin32(const uint32_t *uaddr, uint32_t *kaddr)
3876 {
3877 if ((vaddr_t)uaddr & 0x3)
3878 return EFAULT;
3879
3880 /* copyin(9) is atomic */
3881 return copyin(uaddr, kaddr, sizeof(uint32_t));
3882 }
3883
3884 /*
3885 * True if the system has any non-level interrupts which are shared
3886 * on the same pin.
3887 */
3888 int intr_shared_edge;
3889
3890 /*
3891 * Software interrupt registration
3892 *
3893 * We hand-code this to ensure that it's atomic.
3894 */
3895 void
softintr(int sir)3896 softintr(int sir)
3897 {
3898 struct cpu_info *ci = curcpu();
3899
3900 __asm volatile("orl %1, %0" :
3901 "=m" (ci->ci_ipending) : "ir" (1 << sir));
3902 }
3903
3904 /*
3905 * Raise current interrupt priority level, and return the old one.
3906 */
3907 int
splraise(int ncpl)3908 splraise(int ncpl)
3909 {
3910 int ocpl;
3911
3912 KASSERT(ncpl >= IPL_NONE);
3913
3914 _SPLRAISE(ocpl, ncpl);
3915 return (ocpl);
3916 }
3917
3918 /*
3919 * Restore an old interrupt priority level. If any thereby unmasked
3920 * interrupts are pending, call Xspllower() to process them.
3921 */
3922 void
splx(int ncpl)3923 splx(int ncpl)
3924 {
3925 _SPLX(ncpl);
3926 }
3927
3928 /*
3929 * Same as splx(), but we return the old value of spl, for the
3930 * benefit of some splsoftclock() callers.
3931 */
3932 int
spllower(int ncpl)3933 spllower(int ncpl)
3934 {
3935 int ocpl = lapic_tpr;
3936
3937 splx(ncpl);
3938 return (ocpl);
3939 }
3940
3941 int
intr_handler(struct intrframe * frame,struct intrhand * ih)3942 intr_handler(struct intrframe *frame, struct intrhand *ih)
3943 {
3944 int rc;
3945 #ifdef MULTIPROCESSOR
3946 int need_lock;
3947
3948 if (ih->ih_flags & IPL_MPSAFE)
3949 need_lock = 0;
3950 else
3951 need_lock = 1;
3952
3953 if (need_lock)
3954 __mp_lock(&kernel_lock);
3955 #endif
3956 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame);
3957 #ifdef MULTIPROCESSOR
3958 if (need_lock)
3959 __mp_unlock(&kernel_lock);
3960 #endif
3961 return rc;
3962 }
3963
3964 void
intr_barrier(void * ih)3965 intr_barrier(void *ih)
3966 {
3967 sched_barrier(NULL);
3968 }
3969
3970 #ifdef SUSPEND
3971
3972 void
intr_enable_wakeup(void)3973 intr_enable_wakeup(void)
3974 {
3975 }
3976
3977 void
intr_disable_wakeup(void)3978 intr_disable_wakeup(void)
3979 {
3980 }
3981
3982 #endif
3983
3984 unsigned int
cpu_rnd_messybits(void)3985 cpu_rnd_messybits(void)
3986 {
3987 struct timespec ts;
3988
3989 nanotime(&ts);
3990 return (ts.tv_nsec ^ (ts.tv_sec << 20));
3991 }
3992
3993 int i386_delay_quality;
3994
3995 void
delay_init(void (* fn)(int),int fn_quality)3996 delay_init(void(*fn)(int), int fn_quality)
3997 {
3998 if (fn_quality > i386_delay_quality) {
3999 delay_func = fn;
4000 i386_delay_quality = fn_quality;
4001 }
4002 }
4003
4004 void
delay_fini(void (* fn)(int))4005 delay_fini(void (*fn)(int))
4006 {
4007 if (delay_func == fn) {
4008 delay_func = i8254_delay;
4009 i386_delay_quality = 0;
4010 }
4011 }
4012